Solar cell, module and system

Abstract

The present disclosure is applicable to the field of photovoltaic technology, and provides a solar cell, a module and a system. The solar cell comprises: an edge busbar located at an edge position of a silicon substrate; and a connection line set comprising a connection conductor and a fine grid line, wherein the connection conductor forms a hollow slot, and the fine grid line is bridged across the hollow slot and passes through a passivation layer and is then in contact with a doped layer. The present disclosure can reduce the production cost of solar cells.

Description

Solar cells, modules and systems

[0001] This disclosure claims priority to Chinese Patent Application No. 202510291738.6, filed on March 12, 2025, entitled “A Solar Cell, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure pertains to the field of photovoltaic technology, and particularly relates to a solar cell, a solar module, and a photovoltaic system. Background Technology

[0003] Solar cells, as a highly efficient and clean energy conversion device, are widely used in various photovoltaic power generation systems. In traditional solar cell structures, main grid lines, fine grid lines, and pads are typically arranged on the cell surface to collect and transport current. The main grid lines extend along one side of the cell surface, while the fine grid lines are distributed perpendicular to the main grid lines, contacting the cell's doped layer to collect photogenerated carriers.

[0004] Typically, a coarser connecting grid is placed between the pad and the main grid. This coarse connecting grid causes partial shading of the cell surface, reducing the illuminated area and affecting photoelectric conversion efficiency. Secondly, because the connecting grid is thick, the contact area with the main grid lines is large, making it prone to slurry recombination at the contact point. This causes charge carriers to recombine before reaching the electrodes, reducing cell performance. Furthermore, the extensive use of fine grid slurry not only increases costs but may also introduce additional defects and losses due to uneven slurry distribution. Summary of the Invention

[0005] This disclosure provides a solar cell, a solar module, and a photovoltaic system, aiming to solve the problems of traditional installation methods affecting photoelectric conversion efficiency, easy recombination, and high production costs.

[0006] This disclosure is implemented as follows: a solar cell includes:

[0007] A silicon substrate, comprising a tunneling layer, a doped layer, and a passivation layer stacked sequentially;

[0008] An edge gate is located at the edge of a silicon substrate and extends along a first direction;

[0009] Edge pad points are set to correspond to the edge main grid.

[0010] The connection line group includes a connection conductor and a fine gate line. The connection conductor is located on the side of the passivation layer away from the doped layer. The connection conductor is used to connect the edge main gate and the edge Pad point. The connection conductor extends along a second direction, which intersects with the first direction.

[0011] The connecting conductor includes at least one hollow groove, with fine grid lines installed in the hollow groove, passing through the passivation layer and contacting the doped layer.

[0012] Optionally, at least one thin grid line may be installed at each cutout.

[0013] Optionally, the fine grid lines extend along a second direction.

[0014] Optionally, along the second direction, the total length of the fine grid lines is 10% to 90% of the total length of the connecting conductors.

[0015] Optionally, along the second direction, the total length of the fine grid lines is 50% to 90% of the total length of the connecting conductors.

[0016] Alternatively, the cutout extends along a second direction.

[0017] Optionally, the connecting conductor includes multiple perforated slots.

[0018] Optionally, along the second direction, multiple hollowed-out grooves are arranged along the same straight line.

[0019] Optionally, along the second direction, at least some of the openwork grooves are arranged in a staggered pattern.

[0020] Optionally, along the second direction, the distance between adjacent perforated slots is equal.

[0021] Optionally, along the second direction, the distance between at least some of the adjacent cutouts is unequal.

[0022] Optionally, the shape of the hollowed-out groove is at least one of the following: rectangular, circular, trapezoidal, triangular, fan-shaped, and elliptical.

[0023] Optionally, along the second direction, the fine grid lines are collinear.

[0024] Optionally, along the second direction, at least some of the fine grid lines are staggered.

[0025] Optionally, along the second direction, at least one fine grid line is located at the center of the cutout groove.

[0026] Optionally, along the second direction, at least one fine grid line is located at the edge of the cutout groove.

[0027] Optionally, the total area of ​​the hollowed-out groove accounts for 1% to 50% of the total area of ​​the connecting conductor.

[0028] Optionally, the width of the connecting conductor is 100–400 μm.

[0029] Optionally, the width of the connecting conductor is 200–300 μm.

[0030] Optionally, the edge main grid includes a connecting portion that contacts the connecting conductor and an extension portion extending along both ends of the connecting portion, wherein the width of the connecting conductor is 1 to 5 times the width of the connecting portion.

[0031] Optionally, the width of the connecting conductor is 1 to 3 times the width of the connecting portion.

[0032] Optionally, the edge main grid includes a connecting portion that contacts the connecting conductor and an extension portion extending along both ends of the connecting portion, wherein the cross-sectional area of ​​the connecting conductor is 1 to 5 times the cross-sectional area of ​​the connecting portion.

[0033] Optionally, the cross-sectional area of ​​the connecting conductor is 1 to 3 times the cross-sectional area of ​​the connecting part.

[0034] Optionally, a plurality of first fine gates and a plurality of second fine gates are arranged alternately along a first direction on the silicon substrate, and edge main gates and edge Pad points are respectively provided on opposite sides of the silicon substrate. The first fine gates are connected to the edge main gates and edge Pad points on one side, and the second fine gates are connected to the edge main gates and edge Pad points on the other side. The polarities of the first fine gates and the second fine gates are different.

[0035] Optionally, a first region and a second region are alternately arranged along a first direction on a silicon substrate. The tunneling layer includes a first tunneling layer and a second tunneling layer. The doping layer includes a first doping layer and a second doping layer. The passivation layer includes a first passivation layer and a second passivation layer. The first tunneling layer, the first doping layer, and the first passivation layer are stacked sequentially in the first region. The second tunneling layer, the second doping layer, and the second passivation layer are stacked sequentially in the second region. The polarities of the first doping layer and the second doping layer are different.

[0036] The first fine gate is located in the first region and is in ohmic contact with the first doped layer. The second fine gate is located in the second region and is in ohmic contact with the second doped layer.

[0037] Optionally, the connecting conductor is a copper conductor or an aluminum conductor, and the fine grid line is a silver fine grid line.

[0038] Optionally, the width of the connecting part is greater than the width of the extension part.

[0039] This disclosure also provides a battery assembly including the solar cell described above.

[0040] This disclosure also provides a photovoltaic system including the aforementioned battery module.

[0041] The beneficial effects achieved by this disclosure are that, by setting the edge main grid and edge pad points, and the connecting line group connecting the edge main grid and edge pad points, the collected current is converged and discharged. The connecting line group includes connecting conductors and fine grid lines. The fine grid lines are mounted on the hollow grooves formed by the connecting conductors. The fine grid lines are in contact with the doped layer, while the connecting conductors are not in physical contact with the doped layer. The fine grid lines collect the charge carriers generated by the doped layer, reducing charge carrier losses caused by the blocking of the connecting conductors. At the same time, the fine grid lines and connecting conductors only contact at both ends of the fine grid lines, resulting in a small contact area, which can reduce charge carrier recombination losses caused by paste recombination and save paste usage during manufacturing, thereby reducing the production cost of solar cells. Attached Figure Description

[0042] Figure 1 is a partial structural schematic diagram of the solar cell provided in this disclosure;

[0043] Figure 2 is a cross-sectional view of the solar cell provided in this disclosure along direction A.

[0044] Explanation of reference numerals in the attached figures: 100, solar cell; 110, silicon substrate; 111, silicon substrate; 112, tunneling layer; 113, doped layer; 114, passivation layer; 120, edge main grid; 121, connection portion; 122, extension portion; 130, connecting line group; 131, connecting conductor; 132, cutout groove; 133, fine grid line; 140, edge pad point; 150, first fine grid; 160, second fine grid. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0046] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “left”, “right”, “horizontal”, “top”, “bottom”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0048] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0049] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0050] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0051] This disclosure utilizes an edge main grid and edge pads, along with a connecting line group connecting the edge main grid and edge pads, to converge and guide the collected current. The connecting line group includes a connecting conductor and fine grid lines. The fine grid lines are mounted on a slot formed by the connecting conductor, and the fine grid lines are in contact with the doped layer, while the connecting conductor is not in physical contact with the doped layer. The fine grid lines collect the charge carriers generated by the doped layer, reducing charge carrier losses caused by the blocking effect of the connecting conductor. Furthermore, since the fine grid lines and connecting conductors only contact at both ends of the fine grid lines, the small contact area reduces charge carrier recombination losses due to paste recombination and saves on paste usage during manufacturing, thereby reducing the production cost of solar cells.

[0052] Example 1

[0053] As shown in Figures 1 and 2, this embodiment provides a solar cell 100, comprising:

[0054] The silicon substrate 110 includes a tunneling layer 112, a doped layer 113, and a passivation layer 114 stacked sequentially.

[0055] The edge gate 120 is located at the edge of the silicon substrate 110 and extends along a first direction;

[0056] Edge Pad point 140 is set to correspond to edge main grid 120;

[0057] The connection line group 130 includes a connection conductor 131 and a fine gate line 133. The connection conductor 131 is located on the side of the passivation layer 114 away from the doped layer 113. The connection conductor 131 is used to connect the edge main gate 120 and the edge Pad point 140. The connection conductor 131 extends along a second direction, which intersects with the first direction.

[0058] The connecting conductor 131 includes at least one hollow groove 132, and a fine grid line 133 is disposed in the hollow groove 132. The fine grid line 133 passes through the passivation layer 114 and contacts the doped layer 113.

[0059] The silicon substrate 110 is the foundation of the solar cell 100, and typically includes a silicon substrate 111 and various functional layers stacked on the silicon substrate 111. That is, the silicon substrate 110 is the solar cell 100 excluding the metallized electrode pattern. The functional layers include a tunneling layer 112, a doped layer 113, and a passivation layer 114 sequentially stacked on the silicon substrate 111. Specifically, the doped layer 113 may be disposed on the tunneling layer 112, and the passivation layer 114 may be disposed on the doped layer 113; alternatively, other functional layers may be disposed between the tunneling layer 112 and the doped layer 113, and the passivation layer 114 may be disposed on the doped layer 113; alternatively, the doped layer 113 may be disposed on the tunneling layer 112, and other functional layers may be disposed between the passivation layer 114 and the doped layer 113; alternatively, other functional layers may be disposed between the tunneling layer 112 and the doped layer 113, and also between the passivation layer 114 and the doped layer 113.

[0060] A tunneling layer 112 is disposed between the silicon substrate 111 and the doped layer 113, providing a transport channel between the doped layer 113 and the silicon substrate 111 through the tunneling effect. A passivation layer 114 is disposed on top of the doped layer 113. Commonly used materials include silicon dioxide (SiO2), silicon nitride (Si3N4), and aluminum oxide (Al2O3). It can bond with dangling bonds on the semiconductor surface, reducing the surface state density and thus improving the electrical properties of the semiconductor surface. Furthermore, the passivation layer 114 is typically disposed on the outermost layer of each functional layer, effectively blocking the diffusion of impurities (such as metal ions and water vapor) from the external environment, protecting the performance stability of the underlying structure. Simultaneously, the passivation layer 114 is often made of insulating material, which can isolate the doped layer 113 from other electrical regions or components, preventing current leakage and interference.

[0061] The doped layer includes P-type doped layer and N-type doped layer. The P-type doped layer and N-type doped layer can be disposed on one or both sides of the silicon substrate 111 to form a PN junction and generate a photovoltaic effect. When light shines on the solar cell 100, photons can excite electrons to jump from the valence band to the conduction band to form electron-hole pairs. These charge carriers are separated at the PN junction due to the electric field and generate current.

[0062] The edge main gate 120 is located at the edge of the silicon substrate 110, above the passivation layer 114, and extends along a first direction. The main function of the main gate is to converge and discharge the current collected from the fine gate (fine gate line 133 or other gate lines physically in contact with the doped layer). Therefore, the main gate needs good conductivity and sufficient cross-sectional area to carry a large current. Edge pad points 140 are correspondingly positioned to the edge main gate 120, located close to it. It is understood that the edge pad points 140 are close to the edge main gate 120; that is, the distance between the edge pad points 140 and the edge main gate 120 is small. When other pad points are provided on the solar cell 100, the distance between the edge pad point 140 and the edge main gate 120 is smaller than the distance between other pad points and the edge main gate 120. The edge pad points 140 are conductors used for connection and power output. The number of edge pad points 140 can be one or more, depending on the actual needs of the solar cell 100. When a main edge grid 120 is provided with multiple edge pad points 140, the multiple edge pad points 140 are arranged along the first extension direction.

[0063] The connecting line group 130 includes a composite structure composed of a connecting conductor 131 and a fine gate line 133. The connecting conductor 131 is disposed on the passivation layer 114, which isolates the connecting conductor 131 from the doped layer 113, preventing direct conduction between them. The connecting conductor 131 connects the edge main gate 120 and the edge Pad point 140. Since the connecting conductor 131, the edge main gate 120, and the edge Pad point 140 are all conductors, they are electrically connected. The connecting conductor 131 can guide the charge carriers (electrons or holes) collected at the edge main gate 120 to the edge Pad point 140, and then conduct them outward through the edge Pad point 140. For example, the edge Pad point 140 can be connected to a solder strip, through which the collected charge carriers can be conducted. The connecting conductor 131 extends along a second direction, which intersects with the first direction. This design reduces shading, ensures more light energy reaches the doped layer, and improves photoelectric conversion efficiency.

[0064] Specifically, the edge main gate 120 can extend along the longitudinal direction of the silicon substrate 110, and the connecting conductor 131 can extend along the transverse direction of the silicon substrate 110. That is, the first direction can be the longitudinal direction of the solar cell 100, and the second direction can be the transverse direction of the solar cell 100, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, for example, they can be the diagonal directions of the silicon substrate 110, and there is no specific limitation here.

[0065] The connecting conductor 131 includes a hollow groove 132. A fine grid line 133 is disposed in the hollow groove 132 of the connecting conductor 131. The two ends of the fine grid line 133 are respectively connected to the opposite two sides of the hollow groove 132, and pass through the passivation layer 114 to directly contact the doped layer 113. The two conductive media directly contact each other to form a conductive channel for collecting the charge carriers generated by the doped layer and reducing the charge carrier loss caused by the shielding of the connecting conductor 131. Specifically, the shape of the hollow groove 132 can be at least one of the following: rectangular, circular, trapezoidal, triangular, fan-shaped, and elliptical, and is not limited here.

[0066] At the contact point between the fine grid line 133 and the connecting conductor 131, charge carriers are captured and recombine, resulting in recombination losses. Since the fine grid line 133 only contacts the connecting conductor 131 at both ends, the small contact area reduces carrier recombination losses due to paste recombination. Furthermore, it saves on paste usage during manufacturing, thereby reducing the production cost of the solar cell 100.

[0067] In this embodiment, the collected current is gathered and discharged by setting an edge main grid 120 and an edge pad point 140, and a connecting line group 130 connecting the edge main grid 120 and the edge pad point 140. The connecting line group 130 includes a connecting conductor 131 and a fine grid line 133. The fine grid line 133 is mounted on the hollow groove 132 formed by the connecting conductor 131. The fine grid line 133 is in contact with the doped layer, while the connecting conductor 131 is not in contact with the doped layer. The fine grid line 133 collects the charge carriers generated by the doped layer, reducing the charge carrier loss caused by the shielding of the connecting conductor 131. At the same time, the fine grid line 133 and the connecting conductor 131 only contact at both ends of the fine grid line 133, resulting in a small contact area, which can reduce the charge carrier recombination loss caused by paste recombination and save paste usage during manufacturing, thereby reducing the production cost of the solar cell 100.

[0068] In one embodiment, at least one fine grid line 133 is installed at each cutout slot 132.

[0069] The number of fine grid lines 133 installed at a single slot 132 can be one or more. Using only one fine grid line 133 reduces the shading area and improves the photoelectric conversion efficiency of the battery. Using multiple fine grid lines 133 not only allows for better carrier collection but also serves as redundancy; if one fine grid line 133 breaks, the others can continue to collect current, resulting in better stability. When multiple fine grid lines are used, they can be arranged in parallel or at an angle; no limitation is made here.

[0070] In one embodiment, the fine grid lines 133 extend along a second direction.

[0071] The connecting conductor 131 extends along the second direction, and the fine grid lines 133 extend in the same direction as the connecting conductor 131. This arrangement helps to ensure uniform current transmission, reduce local resistance inside the battery, and improve overall current collection efficiency.

[0072] Example 2

[0073] In one embodiment, along the second direction, the total length of the fine grid line 133 is 10% to 90% of the total length of the connecting conductor 131.

[0074] The connecting conductor 131 extends along the second direction, and the total length of the connecting conductor 131 along the second direction refers to the length of the connecting conductor 131 between the edge main grid 120 and the edge Pad point 140. The total length of the fine grid line 133 along the second direction is that of the projected length of the fine grid line 133 in the second direction. It can be understood that when multiple fine grid lines 133 are provided, if the projections of multiple fine grid lines 133 overlap in the second direction, the length of the overlapping part is only calculated once.

[0075] The total length of the fine grid line 133 is 10% to 90% of the total length of the connecting conductor 131. For example, assuming the total length of the connecting conductor 131 is 10 mm, the total length of the fine grid line 133 can be 1 mm to 9 mm. This ensures that the fine grid line 133 can effectively transmit current without excessively obstructing the silicon substrate 110 and affecting the light absorption efficiency. By rationally designing the length of the fine grid line 133, damage caused by excessive material accumulation can be avoided, improving the long-term reliability of the battery.

[0076] In one embodiment, along the second direction, the total length of the fine grid line 133 is 50% to 90% of the total length of the connecting conductor 131.

[0077] The total length of the fine grid lines 133 along the second direction is 50% to 90% of the total length of the connecting conductor 131. For example, assuming the total length of the connecting conductor 131 is 10 mm, the total length of the fine grid lines 133 can be 5 mm to 9 mm. A higher proportion of fine grid line length 133 can maximize the carrier collection efficiency, improve the photoelectric conversion efficiency of the cell, and reduce the amount of paste used and lower the cost compared to full-length coverage.

[0078] Example 3

[0079] In one embodiment, the cutout 132 extends along a second direction.

[0080] The extension direction of the hollow groove 132 is consistent with the extension direction of the connecting conductor 131, which reduces the shading of the connecting conductor 131 on the silicon substrate 110, improves the light transmittance, and allows more light to pass through the hollow groove 132 to irradiate the silicon substrate 110, thereby improving the photoelectric conversion efficiency of the battery.

[0081] In one embodiment, the total area of ​​the hollowed-out groove 132 accounts for 1% to 50% of the total area of ​​the connecting conductor 131.

[0082] Understandably, in this embodiment, "area" refers to the area of ​​the side of the connecting conductor 131 facing away from the silicon substrate. Typically, the connecting conductor 131 is relatively thin. If the proportion of the cutout grooves 132 is too large, the portion of the connecting conductor 131 used for current transmission becomes smaller, which is detrimental to current transmission. The total area of ​​the cutout grooves 132 is the sum of the areas of all the cutout grooves, accounting for 1% to 50% of the total area of ​​the connecting conductor 131. This helps ensure that the connecting conductor 131 retains sufficient conductive portion for current transmission.

[0083] In one embodiment, the connecting conductor includes a plurality of cutouts 132.

[0084] Multiple slots 132 can further reduce the shading of the connecting conductor 131 on the silicon substrate 110, improve the light absorption efficiency of the cell, and at the same time reduce the use of connecting materials and reduce costs.

[0085] Specifically, multiple slots 132 can be arranged along the same straight line along the second direction, meaning that the center lines of the multiple slots 132 coincide along the second direction. Arranging the slots 132 along the same straight line ensures more uniform carrier collection and reduces the impact of local non-uniformity on battery performance. Furthermore, the straight-line arrangement of the slots 132 is easily achieved through processes such as screen printing, reducing manufacturing difficulty.

[0086] Alternatively, at least some of the perforated slots 132 can be staggered along the second direction, meaning that at least some of the perforated slots 132 are staggered along the centerline of the second direction. Specifically, some of the perforated slots 132 can be arranged along the same straight line, some can be staggered, or all of the perforated slots 132 can be staggered. The staggered arrangement of the perforated slots 132 can prevent the fine grid lines 133 from concentrating in a certain area, reduce the impact of local shading on the battery performance, better utilize light energy, and improve photovoltaic conversion efficiency.

[0087] In one embodiment, the distance between adjacent cutouts 132 is equal along the second direction.

[0088] If we take the position on any slot 132 closest to its adjacent slot 132 as the vertex, the distance between the vertices of two adjacent slots 132 is the distance between the two slots 132. The equal distance ensures that the slots 132 and the fine grid lines 133 are evenly distributed on the connecting conductor 131, improving the uniformity of carrier collection.

[0089] In one embodiment, along the second direction, the distance between at least partially adjacent cutouts 132 is unequal.

[0090] The distances between all adjacent slots 132 can be unequal. For example, with four slots 132, the distance between the first and second slots 132 is 50 μm, the distance between the second and third slots 132 is 60 μm, and the distance between the third and fourth slots 132 is 70 μm. Alternatively, the distances between some adjacent slots 132 can be equal, while the distances between some adjacent slots 132 can be unequal. For example, the distance between the first and second slots 132 is 50 μm, the distance between the second and third slots 132 is 50 μm, and the distance between the third and fourth slots 132 is 70 μm.

[0091] The unequal spacing design can optimize the distribution of fine grid lines 133 according to the light intensity and battery design requirements, reducing local shading.

[0092] In one embodiment, the fine gate lines 133 are collinear along the second direction.

[0093] When multiple slots 132 are formed on the connecting conductor 131, the fine grid lines 133 mounted on each slot 132 are distributed along the same straight line. Collinear arrangement can concentrate the collection of charge carriers, reduce the impact of dispersion on battery performance, and at the same time, the collinear arrangement of fine grid lines 133 can simplify the design and manufacturing process and improve production efficiency.

[0094] In one embodiment, the fine grid lines 133 are staggered along the second direction.

[0095] When multiple slots 132 are formed on the connecting conductor 131, at least some of the fine grid lines 133 mounted on each slot 132 are not distributed along the same straight line. Specifically, all the fine grid lines 133 may not be distributed along the same straight line, i.e., all the fine grid lines 133 are not collinear; or some of the fine grid lines 133 may be distributed along the same straight line, while others may not be distributed along the same straight line. For example, four slots 132 are provided, and one fine grid line 133 is mounted on each slot 132. Among these, three of the fine grid lines 133 are distributed along the same straight line, and the one fine grid line 133 has a certain distance or forms a certain angle with the three collinear fine grid lines 133.

[0096] In one embodiment, along the second direction, at least one fine grid line 133 is located at the center of the cutout groove 132.

[0097] That is, at least one fine grid line 133 is positioned at a location overlapping the center line of the slot 132. The fine grid line 133 in the central position is equidistant from the slot walls on both sides of the slot 132, ensuring uniform distribution of the fine grid line 133 within the slot and preventing localized overheating. The centrally positioned fine grid line 133 also provides an optimal contact point, reducing contact resistance and improving carrier transport efficiency.

[0098] In one embodiment, along the second direction, at least one fine grid line 133 is located at the edge of the cutout groove 132.

[0099] That is, at least one fine grid line 133 is positioned at a location that does not overlap with the center line of the slot 132, meaning the fine grid line 133 is offset from the center line of the slot 132. Specifically, it can be at a certain distance from the center line or at a certain angle. The fine grid line 133 at the edge can optimize the illumination area and reduce the impact of shading on battery performance.

[0100] Example 4

[0101] In one embodiment, the width of the connecting conductor 131 is 100–400 μm.

[0102] Since the connecting conductor 131 extends along the second direction, the width of the connecting conductor 131 refers to the distance between two opposite sides of the connecting conductor 131 perpendicular to the second extension direction.

[0103] A wider connecting conductor 131 provides a wider channel for charge carriers to pass through, resulting in lower resistance and facilitating carrier transport. However, a wider connecting conductor 131 also causes greater shading of the silicon substrate 110. Experiments have shown that a width of 100–400 μm for the connecting conductor 131 ensures good conductivity, reduces current transport losses, and does not significantly impact the photoelectric conversion efficiency of the solar cell 100.

[0104] Specifically, the width of the connecting conductor 131 can be 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 280μm, 300μm, 320μm, 340μm, 350μm, 370μm, 380μm, 385μm, 390μm, or 400μm, or other values ​​between 100 and 400μm, and is not limited here.

[0105] In one embodiment, the width of the connecting conductor 131 is 200–300 μm. Specifically, when the width of the connecting conductor 131 is between 200 and 300 μm, the conductivity and the shading of the silicon substrate 110 can be better balanced, improving the overall performance of the battery. While ensuring performance, excessive shading of the silicon substrate 110 can be avoided, which would affect the photoelectric conversion efficiency.

[0106] Example 5

[0107] In one embodiment, the edge main gate 120 includes a connecting portion 121 that contacts the connecting conductor 131 and an extension portion 122 extending along both ends of the connecting portion 121, wherein the width of the connecting conductor 131 is 1 to 5 times the width of the connecting portion 121.

[0108] Since the connecting conductor 131 extends along the second direction, the width of the connecting conductor 131 refers to the distance between two opposite sides of the connecting conductor 131 perpendicular to the second extension direction. Similarly, since the edge main gate 120 extends along the first direction, the width of the edge main gate 120 refers to the distance between two opposite sides of the edge main gate 120 perpendicular to the first extension direction.

[0109] The edge main grid 120 and the connecting conductor 131 contact each other at the connection portion 121 of the connecting conductor 131. At the connection portion 121, the connecting conductor 131 transfers the charge carriers collected at the edge pad point 140 to the edge main grid 120. A wider connecting conductor 131 can reduce resistance and facilitate the transport of charge carriers on the connecting conductor 131. At the same time, the width of the connection portion 121 is 0.2 to 1 times the width of the connecting conductor 131 to avoid the connection portion 121 being too narrow, which would prevent the charge carriers transferred from the connecting conductor 131 from passing through smoothly and affect the battery's transport efficiency.

[0110] The width of the connecting conductor 131 being 1 to 5 times the width of the connecting portion 121 can optimize current collection and reduce current loss. For example, the width of the connecting portion 121 is 100 μm, and the width of the connecting conductor 131 is 400 μm (4 times).

[0111] In one embodiment, the width of the connecting conductor 131 is 1 to 3 times the width of the connecting portion 121.

[0112] Further optimizing the width of the connecting conductor 131 to be within 1 to 3 times the width of the connecting portion 121 can further optimize conductivity and avoid a large difference in width between the connecting conductor 131 and the connecting portion 121, which would affect transmission efficiency.

[0113] For example, the width of the connecting part 121 is 150 μm, and the width of the connecting conductor 131 is 300 μm (twice).

[0114] Example 6

[0115] In one embodiment, the edge main grid 120 includes a connecting portion 121 that contacts the connecting conductor 131 and an extension portion 122 extending along both ends of the connecting portion 121, wherein the cross-sectional area of ​​the connecting conductor 131 is 1 to 5 times the cross-sectional area of ​​the connecting portion 121.

[0116] Since the connecting conductor 131 extends along the second direction, a cross-section of the connecting conductor 131 is taken perpendicular to the second extension direction. Meanwhile, the edge main gate 120 extends along the first direction, and a cross-section of the edge main gate 120 is taken perpendicular to the first extension direction.

[0117] The edge main grid 120 and the connecting conductor 131 are in contact at the connection portion 121 of the connecting conductor 131. At the connection portion 121, the connecting conductor 131 transfers the charge carriers collected at the edge pad point 140 to the edge main grid 120. The larger cross-sectional area of ​​the connecting conductor 131 can reduce resistance, which is beneficial to the transport of charge carriers on the connecting conductor 131. At the same time, the cross-sectional area of ​​the connecting portion 121 is 0.2 to 1 times the cross-sectional area of ​​the connecting conductor 131, so as to avoid the cross-section of the connecting portion 121 being too small, which would prevent the charge carriers transferred from the connecting conductor 131 from passing through smoothly and affecting the battery's transport efficiency.

[0118] Having a cross-sectional area of ​​the connecting conductor 131 that is 1 to 5 times the cross-sectional area of ​​the connecting portion 121 can optimize current collection and reduce current loss. For example, the cross-sectional area of ​​the connecting portion 121 is 100 μm, and the cross-sectional area of ​​the connecting conductor 131 is 400 μm (4 times).

[0119] In one embodiment, the cross-sectional area of ​​the connecting conductor 131 is 1 to 3 times the cross-sectional area of ​​the connecting portion 121.

[0120] Further optimizing the cross-sectional area of ​​the connecting conductor 131 to be within 1 to 3 times the cross-sectional area of ​​the connecting part 121 can further optimize conductivity and avoid a large difference in the cross-sectional areas of the connecting conductor 131 and the connecting part 121, which would affect the transmission efficiency.

[0121] For example, the cross-sectional area of ​​the connecting part 121 is 150 μm, and the cross-sectional area of ​​the connecting conductor 131 is 300 μm (twice).

[0122] Example 7

[0123] As shown in Figure 1, in one embodiment, a plurality of first fine gates 150 and a plurality of second fine gates 160 are disposed on a silicon substrate 110, which are alternately arranged along a first direction. An edge main gate 120 and an edge Pad point 140 are respectively disposed on opposite sides of the silicon substrate 110. The first fine gate 150 is connected to the edge main gate 120 and the edge Pad point 140 on one side, and the second fine gate 160 is connected to the edge main gate 120 and the edge Pad point 140 on the other side. The polarities of the first fine gate 150 and the second fine gate 160 are different.

[0124] Understandably, P-type and N-type regions are formed on the silicon substrate 110. These regions have different electrical characteristics, supporting the formation of the PN junction and the separation of charge carriers. The first fine gate 150 and the second fine gate 160 are respectively disposed in the two polarity regions. Specifically, the first fine gate 150 can be disposed in the P-type region and the second fine gate 160 in the N-type region, or the first fine gate 150 can be disposed in the N-type region and the second fine gate 160 in the P-type region.

[0125] The silicon substrate 110 has two opposite sides, namely a first side and a second side, and edge main gates 120 and edge pad points 140 corresponding to the edge main gates 120 are respectively provided on the two sides. Specifically, the first fine gate 150 and the second fine gate 160 can be connected to the edge pad points 140 through wires, and the wires used for connection are not in physical contact with the doped layer.

[0126] Taking a first fine gate 150 disposed in a P-type region and a second fine gate 160 disposed in an N-type region as an example: The first fine gate 150 collects holes generated in the P-type region. The first fine gate 150 is connected to the first side edge main gate 120 and the edge Pad point 140, transmitting the holes collected by the first fine gate 150 to the edge main gate 120 and connecting it to the load through the edge main gate 120. Specifically, part of the first fine gate 150 may be directly connected to the first side edge main gate 120, and part of the first fine gate 150 may be connected to the edge Pad point 140 and connected to the first side edge main gate 120 through the connecting line group 130. The second fine gate 160 collects electrons and holes generated in the N-type region. The second fine gate 160 is connected to the second side edge main gate 120 and the edge Pad point 140, transmitting the electrons collected by the second fine gate 160 to the edge main gate 120 and connecting it to the load through the edge main gate 120. Specifically, some of the second fine grids 160 may be directly connected to the edge main grid 120 on the second side, and some of the second fine grids 160 may be connected to the edge Pad point 140 and communicated with the edge main grid 120 on the second side through the connecting line group 130.

[0127] In one embodiment, a first region and a second region are alternately arranged along a first direction on a silicon substrate 110. A tunneling layer 112 includes a first tunneling layer and a second tunneling layer. A doped layer 113 includes a first doped layer and a second doped layer. A passivation layer 114 includes a first passivation layer and a second passivation layer. The first tunneling layer, the first doped layer, and the first passivation layer are stacked sequentially in the first region. The second tunneling layer, the second doped layer, and the second passivation layer are stacked sequentially in the second region. The polarities of the first doped layer and the second doped layer are different. A first fine gate 150 is located in the first region and is in ohmic contact with the first doped layer. A second fine gate 160 is located in the second region and is in ohmic contact with the second doped layer.

[0128] Specifically, the silicon substrate 110 includes a silicon substrate 111, a tunneling layer 112, a doped layer 113, and a passivation layer 114, with the doped layer 113 disposed on the silicon substrate 111. The tunneling layer 112 includes a first tunneling layer and a second tunneling layer, the doped layer 113 includes a first doped layer and a second doped layer, and the passivation layer 114 includes a first passivation layer and a second passivation layer. The first tunneling layer, the first doped layer, and the first passivation layer are sequentially stacked in a first region, and the second tunneling layer, the second doped layer, and the second passivation layer are disposed in a second region. The first region and the second region are alternately arranged along a first direction, that is, the first doped layer and the second doped layer are alternately arranged along the first direction on the silicon substrate 111. The polarities of the first doped layer and the second doped layer are different; the first doped layer can be a P-type doped layer and the second doped layer can be an N-type doped layer, or vice versa. The first polarity doped layer and the second polarity doped layer form regions with different electrical characteristics, supporting the formation of a PN junction and the separation of charge carriers.

[0129] The first fine gate 150 is located in the first region and is in ohmic contact with the first doped layer. That is, the first fine gate 150 passes through the first passivation layer and contacts the first doped layer, forming a conductive channel between them to collect the charge carriers generated in the first region. The second fine gate 160 is located in the second region and is in ohmic contact with the second doped layer. That is, the second fine gate 160 passes through the second passivation layer and contacts the first doped layer, forming a conductive channel between them to collect the charge carriers generated in the second region. Alternating between the first and second regions ensures the uniform distribution of the fine gate lines 133 on the silicon substrate 110, improving the uniformity of charge carrier collection.

[0130] Understandably, the first and second regions are arranged alternately, meaning they are both located on the same sheet of silicon substrate 110, typically on the back surface of the silicon substrate 110. The first fine gate 150 and the second fine gate 160 are respectively located corresponding to the first and second regions, thus they are located on the back surface of the silicon substrate 110. Since the light-facing surface of the silicon substrate 110 is not obstructed by the fine gates, the light absorption area can be maximized, shadow loss reduced, and the photoelectric conversion efficiency of the cell significantly improved.

[0131] Example 8

[0132] In one embodiment, the connecting conductor 131 is a copper conductor or an aluminum conductor, and the fine grid line 133 is a silver fine grid line.

[0133] For example, the connecting conductor 131 is a 250μm wide copper conductor, and the fine grid line 133 is a 50μm wide silver fine grid line. The connecting conductor 131 mainly serves to transport charge carriers. Copper and aluminum have good conductivity, which can reduce the resistance on the connecting conductor 131 and improve the current transmission efficiency. At the same time, copper and aluminum have low cost, reducing the overall manufacturing cost.

[0134] The fine grid lines 133 need to contact the doped layer, requiring not only excellent conductivity but also good contact performance. Silver fine grid lines possess excellent conductivity and contact performance, which can improve the reliability of the battery.

[0135] Different conductive materials are selected according to the different functions of the connecting conductor and the fine grid line 133, which saves the use of silver paste and reduces production costs.

[0136] Example 9

[0137] In one embodiment, the width of the connecting portion 121 is greater than the width of the extension portion 122.

[0138] The connecting portion 121 is used to connect with the connecting conductor 131 and receive the charge carriers transmitted by the connecting conductor 131; that is, the charge carriers transmitted by the connecting conductor 131 are collected in the connecting portion 121. A wider connecting portion 121 can optimize the collection of charge carriers and reduce losses during current transmission. The width of the extension portion 122 is smaller than the width of the connecting portion 121; a narrower extension portion 122 can reduce the amount of material used and lower costs.

[0139] Example 10

[0140] This embodiment provides a battery assembly, including the solar cell 100 in the above embodiment.

[0141] The battery module may include multiple solar cells 100. The multiple solar cells 100 in the battery module can be connected in series to form a battery string. The battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current charging output. For example, the connection between the individual cells can be achieved by welding the welding strips, or the connection between the individual battery strings can be achieved by busbars.

[0142] The battery module may also include a metal frame, a backsheet, photovoltaic glass, and an encapsulant film (not shown in the figures). The encapsulant film can be filled between the light-facing side of the solar cell 100 and the photovoltaic glass, the back-facing side and the backsheet, and adjacent cells. As a filler, it can be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulant film can be EVA film or POE film, and the specific choice can be made according to the actual situation. There are no restrictions here.

[0143] Photovoltaic glass can be applied to the encapsulating film on the light-facing side of the solar cell 100. This photovoltaic glass can be ultra-clear glass, possessing high light transmittance, high transparency, and superior physical, mechanical, and optical properties. For example, ultra-clear glass can achieve a light transmittance of over 92%, protecting the solar cell 100 while minimizing impact on its efficiency. Simultaneously, the encapsulating film bonds the photovoltaic glass and the solar cell 100 together, providing sealing, insulation, and waterproofing / moisture protection for the solar cell 100.

[0144] The backsheet can be attached to the film on the back side of the solar cell 100. The backsheet protects and supports the solar cell 100, providing reliable insulation, water resistance, and aging resistance. Multiple backsheet options are available, typically including tempered glass, acrylic glass, and aluminum alloy TPT composite film, etc. The specific choice depends on the specific circumstances and is not limited here. The backsheet, solar cell 100, film, and photovoltaic glass can be mounted on a metal frame. The metal frame serves as the main external support structure for the entire battery module, providing stable support and installation. For example, the battery module can be installed at the desired location using the metal frame.

[0145] The beneficial effects of the battery module in this embodiment are equivalent to those of the solar cell 100 described above, and will not be repeated here.

[0146] Example 10

[0147] An embodiment provides a photovoltaic module, including the battery module described in the above embodiment.

[0148] Photovoltaic systems can be applied in photovoltaic power plants, such as ground-mounted, rooftop, and floating power plants, as well as in equipment or devices that utilize solar energy to generate electricity, such as user solar power supplies, solar streetlights, solar cars, and solar buildings. Of course, it's understandable that the application scenarios of photovoltaic systems are not limited to these; that is, photovoltaic systems can be applied in all fields that require solar energy to generate electricity. Taking a photovoltaic power generation network as an example, a photovoltaic system can include photovoltaic arrays, combiner boxes, and inverters. A photovoltaic array can be a combination of multiple battery modules; for example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to combiner boxes, which collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into AC power required by the mains grid before being connected to the mains grid to achieve solar power supply.

[0149] The beneficial effects of the photovoltaic system in this embodiment are equivalent to the beneficial effects of the battery module described above, and will not be repeated here.

[0150] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A solar cell, wherein, include: A silicon substrate, comprising a tunneling layer, a doped layer, and a passivation layer stacked sequentially; An edge gate is located at the edge of the silicon substrate and extends along a first direction; The edge pad points are set corresponding to the edge main grid; A connection line group includes a connection conductor and a fine gate line. The connection conductor is located on the side of the passivation layer away from the doped layer. The connection conductor is used to connect the edge main gate and the edge Pad point. The connection conductor extends along a second direction, which intersects with the first direction. The connecting conductor includes at least one hollowed-out groove, the fine gate line is disposed in the hollowed-out groove, and the fine gate line passes through the passivation layer and contacts the doped layer.

2. The solar cell as described in claim 1, wherein, At least one fine grid line is installed at each of the said hollow slots.

3. The solar cell as described in claim 1, wherein, The fine grid lines extend along the second direction.

4. The solar cell as described in claim 1, wherein, Along the second direction, the total length of the fine grid lines is 10% to 90% of the total length of the connecting conductor.

5. The solar cell as described in claim 4, wherein, Along the second direction, the total length of the fine grid lines is 50% to 90% of the total length of the connecting conductor.

6. The solar cell as described in claim 1 or 2, wherein, The hollowed-out groove extends along the second direction.

7. The solar cell as claimed in claim 6, wherein, The connecting conductor includes a plurality of the hollowed-out slots.

8. The solar cell as claimed in claim 7, wherein, Along the second direction, the plurality of the hollowed-out grooves are arranged along the same straight line.

9. The solar cell as claimed in claim 7, wherein, Along the second direction, at least some of the hollowed-out grooves are arranged in a staggered pattern.

10. The solar cell according to any one of claims 7 to 9, wherein, Along the second direction, the distance between adjacent hollowed-out slots is equal.

11. The solar cell according to any one of claims 7 to 9, wherein, Along the second direction, the distances between at least some of the adjacent cutouts are unequal.

12. The solar cell as claimed in claim 2, wherein, The hollowed-out groove is at least one of the following shapes: rectangular, circular, trapezoidal, triangular, fan-shaped, and elliptical.

13. The solar cell of claim 7, wherein, Along the second direction, the fine grid lines are collinear.

14. The solar cell of claim 7, wherein, Along the second direction, at least some of the fine grid lines are staggered.

15. The solar cell of claim 7, wherein, Along the second direction, at least one of the fine grid lines is located at the center of the hollowed-out groove.

16. The solar cell of claim 7, wherein, Along the second direction, at least one of the fine grid lines is located at the edge of the hollowed-out groove.

17. The solar cell of claim 1, wherein, The total area of ​​the hollowed-out groove accounts for 1% to 50% of the total area of ​​the connecting conductor.

18. The solar cell as claimed in claim 1, wherein, The width of the connecting conductor is 100–400 μm.

19. The solar cell of claim 18, wherein, The width of the connecting conductor is 200–300 μm.

20. The solar cell of claim 1, wherein, The edge main grid includes a connecting portion that contacts the connecting conductor and an extension portion extending along both ends of the connecting portion, wherein the width of the connecting conductor is 1 to 5 times the width of the connecting portion.

21. The solar cell of claim 20, wherein, The width of the connecting conductor is 1 to 3 times the width of the connecting portion.

22. The solar cell of claim 1, wherein, The edge main grid includes a connecting portion that contacts the connecting conductor and an extension portion extending along both ends of the connecting portion, wherein the cross-sectional area of ​​the connecting conductor is 1 to 5 times the cross-sectional area of ​​the connecting portion.

23. The solar cell of claim 22, wherein, The cross-sectional area of ​​the connecting conductor is 1 to 3 times the cross-sectional area of ​​the connecting portion.

24. The solar cell as claimed in claim 1, wherein, The silicon substrate is provided with a plurality of first fine gates and a plurality of second fine gates arranged alternately along the first direction. The edge main gate and the edge Pad point are respectively provided on the two opposite edges of the silicon substrate. The first fine gate is connected to the edge main gate and the edge Pad point on one side, and the second fine gate is connected to the edge main gate and the edge Pad point on the other side. The polarity of the first fine gate and the second fine gate are different.

25. The solar cell of claim 24, wherein, The silicon substrate has a first region and a second region alternately arranged along the first direction. The tunneling layer includes a first tunneling layer and a second tunneling layer. The doping layer includes a first doping layer and a second doping layer. The passivation layer includes a first passivation layer and a second passivation layer. The first tunneling layer, the first doping layer, and the first passivation layer are stacked sequentially in the first region. The second tunneling layer, the second doping layer, and the second passivation layer are stacked sequentially in the second region. The polarities of the first doping layer and the second doping layer are opposite. The first fine gate is located in the first region and is in ohmic contact with the first doped layer. The second fine gate is located in the second region and is in ohmic contact with the second doped layer.

26. The solar cell as claimed in claim 1, wherein, The connecting conductor is a copper conductor or an aluminum conductor, and the fine grid line is a silver fine grid line.

27. The solar cell according to any one of claims 20 to 23, wherein, The width of the connecting part is greater than the width of the extension part.

28. A battery assembly, wherein, Includes the solar cell described in any one of claims 1 to 27.

29. A photovoltaic system, wherein, Includes the battery assembly as described in claim 28.

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