Unblocking control method and related apparatus

Abstract

An unblocking control method and a related apparatus. After performing a pulse-blocking operation on a power converter, if an unblocking condition exists, a pulse-blocking state of the power converter is released at an unblocking moment within a first time period. The first time period is a time period within which a switching transistor frequency of the power converter is equal to a specified switching transistor frequency after the pulse-blocking state is released, and the specified switching transistor frequency is greater than or equal to an original switching transistor frequency of the power converter and less than or equal to the maximum switching frequency that a switching transistor of the power converter can withstand.

Description

A method and related device for unsealing control

[0001] This application claims priority to Chinese Patent Application No. 202510126253.1, filed on January 24, 2025, entitled "An Unsealing Control Method and Related Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a method for controlling the unsealing of a device. Background Technology

[0003] In photovoltaic (PV) or solar-energy storage systems, power converters are equipped with overcurrent protection strategies. When the detected current exceeds a set protection threshold, a blocking event is triggered. After blocking, if the current does not exceed the set protection threshold, an unblocking event is triggered.

[0004] When a blocking or deblocking event is executed, the switching transistor will be forcibly turned off or on. If the blocking and deblocking events are executed multiple times, the switching frequency of the switching transistor will be too high. In severe cases, the thermal stress of the device will exceed the standard, causing the switching transistor to fail. Summary of the Invention

[0005] The following is an overview of the detailed description of this application. This overview is not intended to limit the scope of the claims. This disclosure provides an unsealing control method and related apparatus, as follows:

[0006] Firstly, this disclosure provides a method for lifting lockdown restrictions, including:

[0007] Perform the wave blocking action of the power converter;

[0008] In response to the unblocking condition of the power converter, the blocking state of the power converter is lifted at an unblocking moment within the first time period; the first time period is: the time period after the unblocking state is lifted, during which the switching frequency of the power converter is equal to the specified switching frequency, the specified switching frequency is greater than or equal to the original switching frequency of the power converter, and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand.

[0009] Optionally, the blocking state of the power converter is released at a certain unblocking moment within the first time period, including:

[0010] Determine a specific time for lifting the lockdown within the first time period;

[0011] The blocking state of the power converter is lifted at the time of unblocking.

[0012] Optionally, a time for lifting the lockdown within the first time period is determined, including:

[0013] Determine the first time period;

[0014] One moment in the first time period will be designated as the moment the lockdown is lifted.

[0015] Optionally, the switching frequency is specified as the original switching frequency, and a first time period is determined, including:

[0016] The time period after the power converter is de-encoded and the switching transistor is turned off is taken as the first time period.

[0017] Optionally, the first time period is determined, including:

[0018] Obtain the second time period; the second time period is the delayed unblocking period after the unblocking condition occurs.

[0019] The first time period is obtained by summing the time of the lifting of the lockdown and the time of the second time period.

[0020] Optionally, the original switching frequency is specified as n times the switching frequency, where n times the original switching frequency is less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand, and n is a positive integer greater than 1.

[0021] Determine a specific time for lifting the lockdown within the first time period, including:

[0022] When n is doubled, the earliest of the zero-crossing time and the peak time of the carrier signal of the switching transistor in the power converter is taken as a desealing time in the first time period; the zero-crossing time and the peak time are located after the desealing condition of the power converter.

[0023] Optionally, determining a time for lifting the lockdown within the first time period also includes:

[0024] When n is any value other than twice, the time of the zero-crossing point or the time of the peak point in the frequency multiplier of the carrier signal of the switching transistor in the power converter, or the earliest of the two times, is taken as an unsealing time in the first time period; the time of the zero-crossing point and the time of the peak point are located after the unsealing condition of the power converter.

[0025] Optionally, before using the zero-crossing point and peak point of the carrier signal of the switching transistor in the power converter as an unblocking point within the first time period, the unblocking control method further includes:

[0026] If the total number of switching cycles in the power converter is less than the threshold for the total number of switching cycles, the zero-crossing point and the peak point of the carrier signal of the switching transistor in the power converter are taken as a desealing point within the first time period.

[0027] Secondly, this disclosure discloses a power converter configured to perform the above-described desealing control method.

[0028] Thirdly, this disclosure discloses an optical energy storage system, including the power converter described above.

[0029] Optionally, the DC side of the power converter is connected to the photovoltaic modules and energy storage batteries, while the AC side of the power converter is connected to the power grid and / or the load.

[0030] Fourthly, this disclosure discloses a photovoltaic system including the aforementioned power converter.

[0031] This disclosure provides a deblocking control method and related apparatus. In this disclosure, after the power converter performs a blocking action, if a deblocking condition exists, the blocking state of the power converter is released at a deblocking moment within a first time period. The first time period is the time period during which the switching frequency of the power converter equals a specified switching frequency after the deblocking is executed. The specified switching frequency is greater than or equal to the original switching frequency of the power converter, and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand. Therefore, when the blocking state is released at a deblocking moment within the first time period, the switching frequency of the switching transistor is kept within the tolerable switching frequency range, avoiding excessive switching frequency and thus preventing switching transistor failure caused by excessive thermal stress.

[0032] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0033] Brief description of the attached figures

[0034] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 is a flowchart of an unsealing control method provided in an embodiment of this disclosure;

[0036] Figure 2 is a waveform diagram of an unsealing control method provided in an embodiment of this disclosure;

[0037] Figure 3 is a waveform diagram of another unsealing control method provided in an embodiment of this disclosure;

[0038] Figure 4 is a waveform diagram of another unsealing control method provided in an embodiment of this disclosure;

[0039] Figure 5 is a waveform diagram of another unsealing control method provided in an embodiment of this disclosure;

[0040] Figure 6 is a waveform diagram of the fifth unsealing control method provided in the embodiments of this disclosure;

[0041] Figure 7 is a waveform diagram of the sixth unsealing control method provided in the embodiments of this disclosure;

[0042] Figure 8 is a flowchart of another unsealing control method provided in an embodiment of this disclosure;

[0043] Figure 9 is a schematic diagram of a photovoltaic energy storage system provided in an embodiment of this disclosure. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0045] In photovoltaic (PV) or solar-energy storage systems, power converters are equipped with overcurrent protection strategies. When the detected current exceeds the set protection threshold, a blocking or shutdown event is triggered.

[0046] Specifically, current overcurrent protection strategies for power converters in photovoltaic or photovoltaic-storage systems can employ a dual protection design combining hardware and software. For hardware protection, the hardware circuitry sets up multiple current protection levels to perform wave-by-wave blocking or shutdown operations. In one embodiment, there are two levels. When the current reaches the level 1 protection point, a wave blocking event is triggered. At this time, the IGBT (Insulated-Gate Bipolar Transistor) / MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) switches stop transmitting current. When the current drops below the level 1 protection point, an unblocking event is triggered, releasing the wave blocking. If the current reaches the level 2 protection point, a shutdown event is triggered, and the equipment shuts down. For software protection, the software protection logic can also set multiple current protection levels. When the detected current exceeds the set protection threshold, a wave blocking or shutdown event is triggered.

[0047] After a wave blocking event is triggered, the switching transistor is forcibly turned off. When the current drops to the level 1 protection point, the switching transistor is forcibly turned on. Normally, the switching frequency of the device's switching transistor is a preset frequency (also called the original switching frequency), such as 16kHz (62.5µs). Therefore, within one switching cycle (62.5µs), the switching transistor performs one turn-on and one turn-off. However, if a wave blocking event is triggered, the hardware circuitry or software algorithm forcibly turns the switching transistor off or on. This breaks the preset switching frequency, and in severe cases, causes excessive thermal stress on the device, leading to switching transistor failure.

[0048] Therefore, this disclosure provides a deblocking control method and related apparatus. In this disclosure, after the power converter performs a blocking operation, if a deblocking condition exists, the blocking state of the power converter is lifted at a deblocking moment within a first time period. The first time period is the time period during which the switching frequency of the power converter equals a specified switching frequency after the deblocking is performed. The specified switching frequency is greater than or equal to the original switching frequency of the power converter, and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand. Therefore, when the blocking state is lifted at a deblocking moment within the first time period, the switching frequency of the switching transistor is kept within the tolerable switching frequency, avoiding a high switching frequency and thus preventing switching transistor failure caused by excessive thermal stress.

[0049] Based on the above, one embodiment of this disclosure provides a deblocking control method, the executing entity of which can be a power converter, which can be a power converter in a photovoltaic system or a photovoltaic-storage system. Referring to FIG1, the deblocking control method may include:

[0050] S11, Execute the blocking action of the power converter.

[0051] In practical scenarios, overcurrent protection strategies for power converters, whether hardware or software-based, trigger a blocking event when the current reaches a current threshold, such as the Level 1 protection point. At this point, the power converter performs a blocking action. During the blocking action, the switching transistors such as IGBTs / MOS transistors stop transmitting signals, causing the current value to decrease and ensuring equipment safety. In one blocking scenario, after the current reaches the Level 1 protection point, the power converter detects a wave-by-wave blocking signal, and the switching transistors immediately block the signal. The blocking sequence of the inner and outer transistors is considered. Taking a Type I NPC (Neutral Point Clamped) circuit as an example, the outer transistor can be blocked first, followed by the inner transistor.

[0052] S12. In response to the unblocking condition of the power converter, the blocking state of the power converter is released at one unblocking moment within the first time period.

[0053] In this embodiment, if the current does not drop below the Level 1 protection point, the power converter will not detect the deblocking signal and will maintain the blocked state. Once the current drops below the Level 1 protection point (i.e., the current value is less than the current threshold), the power converter detects the deblocking signal and enters the deblocking state. However, the deblocking operation is not performed immediately; instead, it is delayed. This delayed deblocking refers to a period of time after determining that the power converter is in the deblocking state before releasing the blocked state. The specific delay time can be configured accordingly. During the delayed deblocking period, the power converter remains in the blocked state.

[0054] In one embodiment, when delaying the lifting of restrictions, a lifting time can be selected. In this embodiment, the lifting time is a lifting time within a first time period.

[0055] The first time period is the period after the unblocking state is executed, during which the switching frequency of the power converter is equal to the specified switching frequency. The specified switching frequency is greater than or equal to the original switching frequency of the power converter, and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand.

[0056] Specifically, when delaying deblocking, a minimum time for wave-by-wave blocking can be set, preventing the switching transistor from continuing to operate shortly after its first action, thus avoiding frequent switching. For example, after the switching transistor is turned off, it can be restricted to not being turned on for 5µs to prevent the switching transistor from malfunctioning due to excessive switching frequency.

[0057] The implementation principle is shown in Figure 2. The horizontal axis of Figure 2 represents time T, and the vertical axis represents the level signal.

[0058] During normal output drive, the switching frequency is determined by a carrier signal, such as a PWM (Pulse Width Modulation) carrier signal (which can be a triangular carrier signal). The switching transistor can be either high-level or low-level turned on based on the actual configuration. In practice, the PWM carrier signal can be compared with a fixed comparison value CMP used for drive control. If the PWM carrier signal value is greater than the comparison value CMP, a high level is output; otherwise, a low level is output. Alternatively, if the PWM carrier signal value is less than the comparison value CMP, a high level is output; otherwise, a low level is output. In this embodiment, the high and low levels constitute the PWM drive signal, which is used to control the switching transistor to perform corresponding actions.

[0059] Taking the high-level conduction mode of the switching transistor as an example, during the output of the PWM drive signal in the above manner, if the actual current Iac is greater than the first-level protection point Ith, the switching transistor will immediately block the waveform. The PWM drive signal outputs a low level to achieve the waveform blocking operation. During the waveform blocking period, the PWM drive signal remains at a low level, and the power converter remains in a waveform blocking state. The switching transistor stops emitting waveforms until Iac is less than Ith, at which point the waveform blocking is released, the PWM drive signal is converted to a high level, and the switching transistor turns on. The specific waveform diagrams for this waveform blocking and deblocking of the PWM drive signal are shown in "Hardware Wave-by-Wave Signal" in Figure 2. In "Hardware Wave-by-Wave Signal," the PWM drive signal is low when controlling the switching transistor to block the waveform. When Iac is less than Ith, the waveform blocking is released. At this time, the PWM drive signal changes from the PWM drive waveform of "normal output drive (i.e., no waveform blocking and deblocking operation)" to the PWM drive waveform of "output drive signal after wave-by-wave (with waveform blocking and deblocking operation)".

[0060] Based on this, to avoid excessively rapid switching of the transistor, a minimum time for wave-by-wave blocking can be defined, and a delayed deblocking operation can be performed. Even if a deblocking signal is received within the minimum time for wave-by-wave blocking, the deblocking operation is not performed until the minimum time for wave-by-wave blocking is reached. Only then will the PWM drive signal be adjusted to a high level, and the deblocking operation will be performed. The PWM drive signal is adjusted from the PWM drive waveform of "normal output drive (i.e., no blocking or deblocking operation)" to the PWM drive waveform of "wave-by-wave signal considering delayed deblocking (blocking and deblocking operations exist, and deblocking is delayed)". The PWM drive signal waveforms for all cycles are shown in Figure 2 under "output drive considering delayed deblocking".

[0061] In Figure 2, T0 is the start time of a switching cycle, T1 is the moment when the actual current Iac is greater than the level 1 protection point Ith, T2 is the moment when the actual current Iac is less than the level 1 protection point Ith, T3 is the deblocking moment of the delayed deblocking, T4 is the moment when the PWM drive signal changes from high level to low level, and T5 is the end time of the switching cycle.

[0062] Although the above method limits the switching action by restricting the minimum time of wave-by-wave blocking, setting the minimum time only prevents the switching action from being too fast. When blocking and deblocking according to this minimum time, there are still a large number of switching actions within a single switching cycle. In severe cases, this can still lead to excessive thermal stress on the device and cause failure. As shown in Figure 2, considering the output drive signal after delayed deblocking, the PWM drive signal waveform contains two high levels and two low levels. If the switching transistor only supports one turn-off and one turn-on within one switching cycle, the high on / off frequency will still lead to switching transistor failure.

[0063] Therefore, in this embodiment of the disclosure, a specified switching frequency is set, which is greater than or equal to the original switching frequency of the power converter and less than or equal to the maximum switching frequency that the switching transistors in the power converter can withstand. Then, a first time period is determined after the unblocking state is executed, which makes the switching frequency of the power converter equal to the specified switching frequency. The unblocking operation is only performed at an unblocking moment within the first time period.

[0064] Specifically, analyzing a switching transistor over a single switching cycle reveals two main switching frequencies: a maximum switching frequency and a required switching frequency. The maximum switching frequency is the maximum number of operations that takes into account the heat generated during turn-on and turn-off losses, ensuring that thermal stress does not exceed limits. Each transistor can have its own maximum switching frequency set based on its actual thermal stress tolerance; these maximum switching frequencies can be the same or different for all transistors. The other switching frequency is determined based on performance requirements and can be called the required switching frequency. In real-world scenarios, during the transistor's blocking process, the current value decreases. The longer the blocking time, the greater the current decrease. Upon subsequent conduction, the current rise range is also larger. That is, with a longer blocking time, the fluctuations in current rise and fall are greater, leading to increased ripple and a potential decrease in current control performance due to blocking. If the switching transistor's thermal stress or temperature rise parameters still have a margin, and while ensuring transistor safety, the switching frequency during the wave-by-wave period can be increased based on short-term heat or other factors to avoid lower current control performance. This required switching frequency is the reasonable switching frequency set considering the transistor's performance requirements.

[0065] Therefore, in this embodiment, the minimum value between the maximum switching frequency and the required switching frequency of the switching transistor can be obtained, and this minimum value can be used as the specified switching frequency. In a real-world scenario, if the required switching frequency is less than the maximum switching frequency, it means that the thermal stress limit of the switching transistor will not be reached at the required switching frequency, and the switching transistor can be operated at the required switching frequency. If the required switching frequency is greater than the maximum switching frequency, it means that the thermal stress limit of the switching transistor will be reached at the required switching frequency, and in order to protect the switching transistor, only the maximum switching frequency is allowed to be used for switching.

[0066] In one implementation, if both the required switching frequency and the maximum switching frequency remain unchanged, then their minimum value also remains unchanged, and the specified switching frequency can be obtained by determining the minimum value only once. If at least one of the required switching frequency and the maximum switching frequency changes, then their minimum value will also change. In this case, when the frequency changes, the minimum value is determined once to obtain the specified switching frequency. If the two frequencies do not change subsequently, the determined specified switching frequency is used to determine the unsealing time.

[0067] In this embodiment, the minimum value between the maximum switching frequency and the required switching frequency is used to determine the unsealing time, which can simultaneously consider performance requirements and thermal stress requirements, and achieve performance requirements while ensuring the safety of the switching transistor.

[0068] In this embodiment, the specified switching frequency is greater than or equal to the original switching frequency of the power converter, and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand. That is, the specified switching frequency is at least the original switching frequency and at most the maximum switching frequency. Based on the specified switching frequency, a deblocking time is determined within the first time period, thereby releasing the blocking state of the power converter at the deblocking time.

[0069] In another implementation of this disclosure, the blocking state of the power converter is released at a deblocking moment within the first time period, including:

[0070] Determine an unblocking time within the first time period, and release the power converter from its blocking state at that time.

[0071] Specifically, in this embodiment of the present disclosure, a deblocking time within a first time period is first determined. Then, when the current time is the deblocking time, a wave blocking and deblocking operation is performed to control the switching transistor to deblock. After that, the power converter performs the wave transmission operation normally.

[0072] In this embodiment, after the power converter performs a blocking operation, if a blocking condition exists, the blocking state of the power converter is lifted at a blocking moment within a first time period. The first time period is the time period during which the switching frequency of the power converter is equal to a specified switching frequency after the blocking is lifted. The specified switching frequency is greater than or equal to the original switching frequency of the power converter and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand. Therefore, when the blocking state is lifted at a blocking moment within the first time period, the switching frequency of the switching transistor can be kept within the switching frequency that the switching transistor can withstand, avoiding a high switching frequency and thus avoiding switching transistor failure caused by excessive thermal stress of the device.

[0073] In the above embodiments, the power converter's blocking state is lifted at a specific unblocking moment within the first time period. There are two ways to determine the unblocking moment: one is to first determine the first time period and then determine the unblocking moment within that period; the other is to directly determine an unblocking moment within the first time period. These will be described separately below.

[0074] 1. The first implementation method.

[0075] Determine the first time period, and use a moment within the first time period as the time to lift the lockdown.

[0076] Specifically, the first time period is the period during which the switching frequency of the power converter equals the specified switching frequency after the unblocking state is executed. At any time within the first time period, the switching frequency of the power converter can be equal to the specified switching frequency. Therefore, after determining the first time period, any time within the first time period can be used as the unblocking time.

[0077] There are several ways to determine the first time period, which will be described in detail below. The following two embodiments will illustrate their specific implementations. However, the determination of the first time period in this disclosure can be achieved not only through these two embodiments, but also through other implementations within the scope of this disclosure.

[0078] First embodiment:

[0079] The determination of the first time period is related to the specified switching transistor frequency. Different specified switching transistor frequencies result in different determined first time periods. When the specified switching transistor frequency is the original switching transistor frequency, the determination of the first time period includes:

[0080] The time period after the power converter is de-encoded and the switching transistor is turned off is taken as the first time period.

[0081] Among them, the switching transistor turn-off time period is the switching transistor turn-off time period closest to the unsealing condition.

[0082] Specifically, if the original switching frequency is 16kHz (62.5us), then the switching transistor can only be turned on once and turned off once in one cycle.

[0083] Taking Figure 3 as an example, T0-T5 represents one switching cycle, during which only one turn-on and one turn-off are allowed. Analysis of the PWM drive signal during the T3-T5 time period (i.e., the waveform during the T3-T5 time period in normal output drive) shows that the PWM drive signal is low during this period, which controls the switch to turn off; therefore, the T3-T5 time period is the switch-off time period. If the de-sealment time is set within the T3-T5 time period, even if the switch is allowed to de-seal at this time, it will not turn on due to the low PWM signal. Analysis of the output waveform considering the delay reveals that within the entire preset frequency, there is only one turn-on and one turn-off, satisfying the frequency requirement of the specified switch frequency.

[0084] In the above implementation, within the time period T3-T5, T3 is the first moment when the PWM carrier signal and the comparison value are the same, and T5 is the second moment when the PWM carrier signal and the comparison value are the same. Any moment within the time period T3-T5 is the desealing moment in this embodiment. When the current moment is the desealing moment, the desealing operation is performed. At this time, since the PWM drive signal is low, the switch remains on until after moment T5, when the PWM drive signal becomes high, and the switch turns on.

[0085] In practical scenarios, the PWM carrier signal changes rapidly. Monitoring points other than the zero-crossing and peak of the PWM carrier signal results in low accuracy due to the rapid signal changes. However, monitoring the zero-crossing and peak (also called periodic points, specifically the highest point of the PWM carrier signal) yields relatively high accuracy. Therefore, in one implementation of this disclosure, to stabilize the switching frequency during wave-by-wave blocking, the deblocking action can be performed only at the time of the carrier's zero-crossing or peak. This ensures that the IGBT / MOS switching frequency does not exceed the set frequency, avoiding excessive thermal stress. The deblocking time includes the time of the zero-crossing or peak during the switching transistor's turn-off period, specifically, the wave blocking and deblocking operation is performed at the time of the zero-crossing or peak within the T3-T5 time period. Specifically, there are two implementation methods: deblocking at the zero-crossing time and deblocking at the peak time. The choice of method depends on the actual configuration.

[0086] Figure 3 is a schematic diagram of unsealing at the zero-crossing point. As can be seen from the bottom of Figure 3, when unsealing occurs at the first zero-crossing point after the unsealing condition, the PWM drive signal has only one high level and one low level within the T0-T5 cycle. At this time, the switching transistor will only turn on and off once, which meets the frequency requirements corresponding to the original switching transistor frequency.

[0087] The "wave-by-wave signal considering carrier unblocking" in Figure 3 refers to the schematic diagram of the PWM drive signal unblocking at the zero-crossing point of the carrier during this wave-blocking and unblocking operation. The PWM drive signals for all control cycles can be referred to in "output drive after wave-by-wave considering carrier". The remaining level signal diagrams in Figure 3 and the explanations of T0-T5 are as described above.

[0088] Figure 4 illustrates the unsealing process at the vertex moment. In Figure 4, when the comparison value is greater than the carrier value in the PWM carrier signal, the PWM drive signal is high; otherwise, it is low. When the unsealing condition of Iac being less than Ith is met, unsealing does not occur at this time. Instead, the unsealing operation is performed at the first vertex moment after the unsealing condition. As shown in the bottom diagram of Figure 4, during the unsealing at the vertex moment, within the cycle T0-T5, the PWM drive signal has only one high level and one low level. At this time, the switching transistor will only turn on and off once, satisfying the frequency requirement corresponding to the original switching transistor frequency.

[0089] The diagrams of the various level signals in Figure 4 and the explanations of T0-T5 are similar to those in Figure 3. Please refer to the corresponding explanations above.

[0090] In this embodiment, when using the PWM carrier signal for wave-by-wave deblocking control, the time of the zero-crossing point or the time of the peak is taken as the deblocking time. Deblocking can only be performed when the time of the zero-crossing point or the peak of the PWM carrier signal is detected, ensuring that the switching frequency of the switching transistor is the original switching frequency. After deblocking, normal operation is restored, so that there is only one turn-off and turn-on in one switching cycle, which meets the actual requirements of the switching frequency of the switching transistor.

[0091] Second embodiment:

[0092] The first time period is determined, including:

[0093] Obtain the second time period, which is the delayed reopening period after the reopening condition is met. Calculate the sum of the time when the reopening condition is met and the time of the second time period to obtain the first time period.

[0094] Specifically, the above embodiment determines the first time period by using the signal value of the PWM carrier signal. Alternatively, the first time period can also be determined using software timing.

[0095] When using software timing, the de-sealing delay time after the de-sealing condition corresponding to a specified switching frequency can be pre-configured. This de-sealing delay time is called the second time period. The second time period can be half a switching cycle, one or several switching cycles, or it can be a set value unrelated to the switching cycle. The de-sealing delay time can be, for example, 1 minute, 3 minutes, 5 minutes, etc., which can be configured according to the actual scenario. In this case, the second time period is decoupled from the PWM cycle.

[0096] Generally, as shown in Figure 3, when the turn-off period of the switching transistor is taken as the first time period, the switching frequency of the power converter can be made to be the original switching frequency. Therefore, when the deblocking control is implemented through software control, the first time period can also be the turn-off period of the switching transistor. In this case, the starting point of the second time period is the difference between the starting point of the first time period and the time when the deblocking condition occurs, and the ending point of the second time period is the difference between the ending point of the first time period and the time when the deblocking condition occurs.

[0097] In one embodiment, the two differences mentioned above can be obtained through a large number of experiments. Through experiments, the two differences corresponding to any time when the unsealing time is arbitrary can be determined, thereby obtaining the second time period.

[0098] After determining the second time period, add the start point of the second time period to the time when the lockdown is lifted to obtain the start point of the first time period. Add the end point of the second time period to the time when the lockdown is lifted to obtain the end point of the first time period, thus determining the first time period. Any time within the first time period is the time when the lockdown is lifted.

[0099] In the specific implementation, after the hardware triggers the blocking event, it directly latches the blocking signal and maintains the blocking signal. After there is a deblocking condition that satisfies Iac less than Ith, the software starts timing. When the timing reaches the deblocking time, the deblocking operation is performed to release the blocking state of the power converter.

[0100] If the specified switching frequency is greater than the original switching frequency, a corresponding second time period can be configured according to the requirements, thereby obtaining a first time period that makes the specified switching frequency greater than the original switching frequency, and the unsealing operation is performed at the unsealing time in the first time period.

[0101] In this embodiment, the unsealing time no longer depends on the PWM period, zero-crossing point, or vertex signal, but relies on software timing to control the unsealing time, which has greater flexibility and can realize wave-by-wave of different durations to meet actual frequency requirements.

[0102] 2. The second implementation method.

[0103] In this embodiment, instead of determining the first time period first and then determining the unsealing time within the first time period, we directly determine one unsealing time within the first time period. In this case, the first time period only includes one or more times.

[0104] In one scenario, when the specified switching frequency is n times the original switching frequency, and n times the original switching frequency is less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand, where n is a positive integer greater than 1, a method is adopted to directly determine a desealing time within the first time period. The above embodiment describes the process of achieving a switching frequency of the power converter equal to the original switching frequency, while this disclosure describes the process of achieving a switching frequency of the power converter equal to n times the original switching frequency. This disclosure also has several embodiments, which are described separately below.

[0105] First embodiment:

[0106] Determine a specific time for lifting the lockdown within the first time period, including:

[0107] When n is doubled, the earliest of the zero-crossing point and the peak point of the carrier signal of the switching transistor in the power converter is taken as the unsealing point in the first time period.

[0108] Among them, the time of the zero crossing and the time of the peak are located after the unsealing condition of the power converter.

[0109] In this embodiment, when n is doubled, the specified switching frequency is 32kHz (31.25us), meaning the switching transistor performs two turn-on cycles and two turn-off cycles within one switching cycle. In this case, since the desealing time is either the zero-crossing point or the period point, the switching transistor performs one turn-on cycle and one turn-off cycle within one switching cycle. Therefore, if desealing is possible at both the zero-crossing point and the peak point, it can be guaranteed that the switching transistor performs two turn-on cycles and two turn-off cycles within one switching cycle, satisfying the switching frequency requirement.

[0110] In practical implementation, the earliest of the zero-crossing time and the vertex time is taken as the unsealing time in the first time period. That is, whichever of the zero-crossing time and the vertex time arrives first, the unsealing operation is performed at that time. In practical implementation, after the occurrence of the unsealing condition, the earliest of the first zero-crossing time and the first vertex time is the unsealing time, as shown in Figure 5. After there is an unsealing condition that satisfies Iac less than Ith, the zero-crossing time occurs first, so the zero-crossing time, i.e., time T3, is used as the unsealing time. As can be seen from the bottom of Figure 5, when the unsealing operation can be performed at both the zero-crossing time and the vertex time, within the T0-T5 cycle, the PWM drive signal has two high levels and two low levels. At this time, the switching transistor will be turned on and off twice, which meets the frequency requirement corresponding to twice the original switching transistor frequency.

[0111] The diagrams of the various level signals in Figure 5 and the explanations of T0-T5 are similar to those in Figure 3. Please refer to the corresponding explanations above.

[0112] Furthermore, in this embodiment, the earliest of the zero-crossing point and the peak point is used as the unsealing time within the first time period, instead of any two points within a time period. This is because the PWM drive signal change requires waiting for the next comparison value to equalize with the PWM carrier signal, ensuring that the PWM drive signal turn-off time is necessarily later than the earliest zero-crossing point or peak point. Therefore, there is no possibility of premature unsealing before the zero-crossing point / peak point. Simultaneously, to ensure that the switching transistor can perform two turn-on and two turn-off operations within the period corresponding to twice the original switching transistor frequency, and unsealing before the next comparison value is loaded, only the zero-crossing point and the peak point can be used as the unsealing time.

[0113] If the switching frequency is controlled at twice the original switching frequency, the switching frequency will double, meaning the switching transistor will operate twice within one switching cycle. This increases the thermal stress on the switching transistor. To ensure effective operation, reducing the number of wave-by-wave cycles can reduce thermal stress. Therefore, in another implementation of this disclosure, when the total number of switching cycles in the power converter is less than the threshold for the total number of switching cycles, the earliest of the zero-crossing point and the peak point of the carrier signal of the switching transistor in the power converter is used as an unsealing point within the first time period.

[0114] The total number of interruptions can be the sum of all interruptions since the switch began operation. The threshold for the total number of interruptions is the maximum total number of interruptions the switch can withstand. If the total number of interruptions is not greater than the threshold, it means the switch can continue to perform interruption operations, and the unsealing operation can be performed at the unsealing point (i.e., the earliest of the zero-crossing time and the peak time). If it is greater than the threshold, it means the switch has reached its maximum wave-by-wave count. If the switch is unsealed further, there is a risk of switch failure due to thermal stress. In this case, unsealing is prohibited to ensure the switch's safety. A prompt message can then be output to allow maintenance personnel to determine whether the switch should continue operation or be replaced.

[0115] Second embodiment:

[0116] Determining a specific time for lifting the lockdown within the first time period also includes:

[0117] When n is any value other than twice, the time of the zero-crossing point or the time of the peak point in the frequency multiplier of the carrier signal of the switching transistor in the power converter, or the earliest of the two times, is taken as an unsealing time in the first time period; the time of the zero-crossing point and the time of the peak point are located after the unsealing condition of the power converter.

[0118] The above embodiment specifies a switching frequency of twice the original switching frequency. In addition, the specified switching frequency can also be three times, four times, five times, etc. When n times is any value other than twice, if only the earliest of the zero-crossing point and the periodic point is used as the unsealing time, only twice the original switching frequency can be achieved. If a higher switching frequency is required, a frequency multiplier signal of the carrier signal can be introduced.

[0119] The frequency multiplier signal of the carrier signal is also a triangular carrier signal, used for deblocking control. Specific examples can be found in Figures 6 and 7. The frequency of the multiplier signal is a specified multiple of the frequency of the PWM carrier signal. This specified multiple is an adjustable coefficient and can be an integer, such as 2, 3, 4, 5, etc., or a non-integer, such as 1.5, 2.3, etc., depending on the actual configuration. In Figures 6 and 7, the frequency of the multiplier signal is three times the frequency of the PWM carrier signal, i.e., a triplet carrier signal. In addition, it can also be implemented as a 2x, 4x, 5x, etc., depending on the specified switching transistor frequency. For example, if the specified switching transistor frequency is three times the original switching transistor frequency, the multiplier signal can be a triplet carrier signal. If the specified switching transistor frequency is four times the original switching transistor frequency, the multiplier signal can be a quadruple carrier signal.

[0120] When determining an unsealing time within the first time period based on the frequency multiplication signal, at least one of the zero-crossing point and the peak point of the frequency multiplication signal of the carrier signal of the switching transistor in the power converter can be used as the unsealing time within the first time period.

[0121] In one implementation, the time of the first zero-crossing point in the frequency-doubled signal after the occurrence of the unsealing condition is taken as the unsealing time, or the time of the first vertex in the frequency-doubled signal after the occurrence of the unsealing condition is taken as the unsealing time.

[0122] For example, if the specified switching frequency is three times the original switching frequency, and the multiplier signal is a third-multiplier carrier signal, using the zero-crossing point or the peak point as the deblocking time ensures that only three turn-on cycles and three turn-off cycles are allowed within one switching cycle. The same applies to other specified switching frequencies.

[0123] In one implementation, the earliest of the two times in the frequency-doubled signal—the time of the peak after the occurrence of the unsealing condition and the time of the zero-crossing point—is taken as the unsealing time.

[0124] For example, if the specified switching frequency is six times the original switching frequency, and the multiplier signal is a third-harmonic carrier signal, if both the zero-crossing point and the peak point are used as the deblocking time, using the earliest of the two times for the deblocking operation can ensure that only six turn-on operations and six turn-off operations are allowed within one switching cycle. The same applies to other specified switching frequencies.

[0125] For details on the implementation of the three methods in this embodiment, please refer to the corresponding descriptions above.

[0126] In Figure 6, the frequency-doubled signal is a triple-frequency carrier signal, which is set to be unsealed at the zero-crossing point. After there is a unsealing condition that satisfies Iac less than Ith, the unsealing operation is performed at the first zero-crossing point (as shown in Figure 6, the frequency-doubled carrier zero-crossing point). At this time, the PWM drive signal in the last figure of Figure 6 is the switching control signal that satisfies the specified switching frequency.

[0127] In Figure 7, the frequency multiplication signal is a triple frequency carrier signal, which is set to be desealed at the time of the vertex. After there is a desealing condition that satisfies Iac less than Ith, the first vertex time (as shown in the frequency multiplication carrier vertex in Figure 7) is desealed. At this time, the PWM drive signal in the last figure of Figure 7 is the switching control signal that satisfies the specified switching frequency.

[0128] The level signal diagrams in Figures 6 and 7, as well as the explanations of T0-T5, are similar to those in Figure 3. Please refer to the corresponding explanations above.

[0129] Furthermore, in this embodiment, only at least one of the zero-crossing point and the vertex is used as the unsealing time, rather than any arbitrary time within a time period. This is because the change in the PWM level signal requires waiting for the next comparison value to equalize with the PWM carrier signal. Since the frequency of the multiplier signal is higher than that of the PWM carrier signal, the change in the PWM level signal will inevitably be later than at least one of the earliest occurrences of the multiplier signal's zero-crossing point and vertex. Therefore, there is no possibility of unsealing before at least one of the zero-crossing point and the vertex. Simultaneously, to ensure that the switching transistor can perform multiple turn-on and multiple turn-off operations within the period corresponding to the multiplier signal, unsealing can be performed before the next comparison value is loaded. Therefore, only at least one of the zero-crossing point and the vertex time can be used as the unsealing time.

[0130] In this embodiment, the frequency multiplier of the PWM carrier signal is used to control the switching frequency of the switching transistor during wave-by-wave operation. This avoids the problem of rapid switching frequency changes caused by wave-by-wave blocking, meets the actual switching frequency requirements of the switching transistor, reduces the risk of excessive thermal stress, prevents switching transistor failure, and improves the reliability of continuous device operation. Furthermore, this disclosure also considers the performance-required switching frequency when setting the switching frequency of the switching transistor to meet current performance requirements.

[0131] In another implementation of this disclosure, the sealing and unsealing process is introduced by taking the time of zero crossing or the time of vertex as the unsealing time. The implementation process of other unsealing times is similar.

[0132] The first step is to immediately block the wave upon receiving the wave-by-wave blocking signal. Considering the blocking sequence of the inner and outer tubes, for example, in a type I NPC circuit, the outer tube can be blocked first and then the inner tube.

[0133] The second step involves maintaining the blocked state if no unblocking signal is detected. If an unblocking signal is detected, the state will not be immediately unblocked; proceed to the third step.

[0134] The third step is to unblock the system when a zero-crossing carrier signal or a periodic signal is detected, and then resume normal operation.

[0135] This disclosure also provides a power converter configured to perform the above-described deblocking control method.

[0136] This disclosure also provides a photovoltaic energy storage system, including the power converter described above.

[0137] In one implementation, the DC side of the power converter is connected to a photovoltaic module and an energy storage battery, and the AC side of the power converter is connected to at least one of a power grid and a load.

[0138] Referring to Figure 9, which is a schematic diagram of a photovoltaic-storage system, the system includes at least one photovoltaic module and at least one power converter (such as an inverter or a PCS (Power Conversion System, energy storage inverter)). The inverter or PCS is connected to the power grid and an optional load (such as a diesel generator). The device for implementing the above-described deblocking control method can be located within the power converter and includes electronic equipment capable of storing programs, variables, and supporting information interaction.

[0139] The photovoltaic modules on the DC side are connected to the DC side of the power converter via PV+ and PV-, and the energy storage batteries are connected to the DC side of the power converter via BAT+ and BAT-. The grid, load, and diesel generator connected to the AC side of the power converter are in an "AND" or "OR" relationship, meaning they can exist simultaneously or not simultaneously.

[0140] This disclosure also provides a photovoltaic system, including the power converter described above.

[0141] The difference between a photovoltaic (PV) system and a solar-storage system is that a PV system does not have a storage battery. The rest of the structure is the same as that of a solar-storage system, and the desealing control process is also the same.

[0142] This disclosure also provides a computer program product including computer-readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the unblocking control methods provided in this disclosure.

[0143] This disclosure also provides a computer-readable storage medium carrying one or more computer programs that, when executed by an electronic device, enable the electronic device to implement any of the unblocking control methods provided in this disclosure.

[0144] The various embodiments in this disclosure are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0145] The above description of the disclosed embodiments enables those skilled in the art to make or use this disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for lifting lockdown controls, comprising: Perform the wave blocking action of the power converter; In response to the unblocking condition of the power converter, the blocking state of the power converter is released at an unblocking moment within a first time period; the first time period is: the time period after the unblocking state is released, during which the switching frequency of the power converter is equal to a specified switching frequency, wherein the specified switching frequency is greater than or equal to the original switching frequency of the power converter and less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand.

2. The unseal control method according to claim 1, wherein Releasing the blocking state of the power converter at a certain unblocking moment within the first time period includes: Determine a specific time for lifting the lockdown within the first time period; The blocking state of the power converter is released at the unblocking time.

3. The unseal control method according to claim 2, wherein Determining a specific time for lifting the lockdown within the first time period includes: Determine the first time period; One moment in the first time period is taken as the unsealing moment.

4. The unsealing control method according to claim 3, wherein, The specified switching frequency is the original switching frequency, and determining the first time period includes: The time period after the power converter is de-encoded and the switching transistor is turned off is taken as the first time period.

5. The unsealing control method according to claim 3, wherein, Determining the first time period includes: Obtain the second time period; the second time period is the delayed unsealing period after the unsealing condition occurs; The first time period is obtained by summing the time of the unsealing operation and the time of the second time period.

6. The unsealing control method according to claim 2, wherein, The specified switching frequency is n times the original switching frequency, and the n times the original switching frequency is less than or equal to the maximum switching frequency that the switching transistor in the power converter can withstand, where n is a positive integer greater than 1. Determining a specific time for lifting the lockdown within the first time period includes: When n is doubled, the earliest of the zero-crossing point and the peak point of the carrier signal of the switching transistor in the power converter is taken as a desealing point within the first time period; the zero-crossing point and the peak point are located after the desealing condition of the power converter.

7. The unsealing control method according to claim 6, wherein, The method for determining a reopening time within a first time period further includes: When n is any value other than twice, one of the zero-crossing time and the vertex time in the frequency multiplier signal of the carrier signal of the switching transistor in the power converter, or the earliest of the zero-crossing time and the vertex time, is taken as an unsealing time in the first time period; the zero-crossing time and the vertex time are located after the unsealing condition of the power converter.

8. The unsealing control method according to claim 6 or 7, wherein, Before using the zero-crossing point and peak point of the carrier signal of the switching transistor in the power converter as an unblocking point within the first time period, the unblocking control method further includes: If the total number of switching cycles in the power converter is less than the threshold for the total number of switching cycles, the zero-crossing point and the peak point of the carrier signal of the switching transistor in the power converter are taken as a desealing point within the first time period.

9. A power converter configured to perform the desealing control method as described in any one of claims 1 to 8.

10. A photovoltaic energy storage system, comprising the power converter as described in claim 9.

11. The photovoltaic energy storage system according to claim 10, wherein, The DC side of the power converter is connected to the photovoltaic module and the energy storage battery, and the AC side of the power converter is connected to the power grid and / or the load.

12. A photovoltaic system comprising the power converter as described in claim 9.

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