Display panel, display module, and electronic device

Abstract

A display panel (10), a display module (100), and an electronic device (1000). The display panel (10) comprises pixel circuits (21) located in a display area, and first shift registers (111) and second shift registers (112) located in a bezel area. Each pixel circuit (21) comprises a data writing circuit (211), a driving circuit (212), and a compensation circuit (213), and transistors comprised in the data writing circuit (211) and the compensation circuit (213) are both metal oxide thin film transistors. The first shift registers (111) are electrically connected to the data writing circuits (211) of a row of pixel circuits (21). The first shift registers (111) are configured to provide a first scan signal to the connected data writing circuits (211). The data writing circuits (211) are configured to be turned on in response to the first scan signal. The second shift registers (112) are electrically connected to the compensation circuits (213) of at least one row of pixel circuits (21). The second shift registers (112) are configured to provide a second scan signal to the connected compensation circuits (213). The compensation circuits (213) are configured to be turned on in response to the second scan signal.

Description

Display panels, display modules, and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510106193.7, filed on January 22, 2025, entitled "Display Panel, Display Module and Electronic Device", and also claims priority to Chinese Patent Application No. 202510125337.3, filed on January 26, 2025, entitled "Display Panel, Display Module and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a display panel, display module and electronic device. Background Technology

[0003] The scan drive circuit is an important component of the display panel. The scan drive circuit may include cascaded multi-stage shift registers, which can be electrically connected to multiple traces in the display panel, such as gate lines, enable signal lines, or reset signal lines, to input scan signals to these traces. This enables the pixel circuits in the display panel to drive their electrically connected light-emitting devices to emit light, thereby allowing the display panel to display images.

[0004] However, the same pixel circuit usually needs to be connected to multiple shift registers, which not only easily increases the bezel size of the display panel, but also easily increases the power consumption of the display panel. Summary of the Invention

[0005] This application provides a display panel, a display module, and an electronic device to reduce the bezel size of the display panel and lower the power consumption of the display panel.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a display panel is provided, having a display area and a bezel area, the bezel area being located on at least two sides outside the display area. The display panel includes: multiple rows of pixel circuits located within the display area, and a first shift register and a second shift register located in the bezel area. Each row of pixel circuits includes a data writing circuit, a driving circuit, and a compensation circuit. The data writing circuit is electrically connected to the driving circuit and a data signal terminal, and the driving circuit is electrically connected to the compensation circuit. The transistors included in the data writing circuit and the compensation circuit are all metal-oxide-slim transistors. The first shift register is electrically connected to the data writing circuit of one row of pixel circuits. The first shift register is configured to provide a first scan signal to the data writing circuit of the pixel circuit connected to the first shift register. The data writing circuit is configured to be turned on in response to the first scan signal, transmitting a data signal from the data signal terminal to the compensation circuit. The second shift register is electrically connected to the compensation circuit of at least one row of pixel circuits. The second shift register is configured to provide a second scan signal to the compensation circuit of the pixel circuit connected to the second shift register. The compensation circuit is configured to be turned on in response to the second scan signal, transmitting a data signal to the driving circuit.

[0008] The display panel provided in some embodiments of this application, by setting a first shift register and a second shift register, makes the first shift register electrically connected to the data writing circuit located in the same row of pixel circuits, and makes the second shift register electrically connected to the compensation circuit located in at least one row of pixel circuits. Furthermore, the transistors included in both the data writing circuit and the compensation circuit are metal-oxide-semiconductor transistors. This approach has several advantages: firstly, it reduces leakage current by using the data writing circuit and the compensation circuit to maintain the potential of relevant nodes within the pixel circuits, thus reducing power consumption caused by leakage; secondly, it reduces the load on the first and second shift registers, allowing for more flexible control of the display panel for image display by utilizing their mutual cooperation; and thirdly, in the case of a small to medium-sized display panel, a single-sided driving method can be used to set the first shift register, thereby reducing the number of shift registers used to drive the pixel circuits, such as reducing the number of first shift registers used to drive the data writing circuits. Correspondingly, this reduces the number of gate driving circuits, thereby reducing power consumption caused by a large number of gate driving circuits, reducing the space occupied by the gate driving circuits, and reducing the bezel size of the display panel, facilitating a narrow bezel design.

[0009] In one possible design approach, the first shift register is located on one side outside the display area, and / or the second shift register is located on one side outside the display area. This increases the flexibility in setting the first and second shift registers, making it suitable for more types of display panels.

[0010] In one possible design approach, the aforementioned row of pixel circuits is electrically connected to a first shift register, and the aforementioned at least one row of pixel circuits is electrically connected to a second shift register. Along the row direction of the multiple rows of pixel circuits, the first and second shift registers are located on opposite sides outside the display area. In this case, the display panel is, for example, a small to medium-sized display panel. This arrangement, along the row direction of the multiple rows of pixel circuits, balances the number of gate drive circuits belonging to the shift registers on both sides of the display area, making the width of the bezel areas on both sides of the display area the same or approximately the same, and facilitating the routing of the bezel areas.

[0011] In one possible design approach, the aforementioned row of pixel circuits is electrically connected to two first shift registers, and the aforementioned at least one row of pixel circuits is electrically connected to two second shift registers. Along the row direction of the multi-row pixel circuits, the two first shift registers are located on opposite sides of the display area, and the two second shift registers are also located on opposite sides of the display area. In this case, the display panel is, for example, a large-size display panel. Using a dual-side driving method not only helps reduce the load on the first and second shift registers but also improves the display uniformity of the display panel.

[0012] In one possible design approach, the data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor. Both the first and third transistors are metal-oxide-slim (MOS) transistors. The control electrode of the first transistor is electrically connected to a first shift register, its first terminal is electrically connected to a data signal terminal, and its second terminal is electrically connected to the first terminal of the second transistor. The control electrode of the second transistor is electrically connected to the second terminal of the third transistor, and its second terminal is electrically connected to the first terminal of the third transistor. The control electrode of the third transistor is electrically connected to a second shift register. This design simplifies the structure of the data writing circuit, driving circuit, and compensation circuit, reducing the structural complexity and fabrication difficulty of the display panel.

[0013] In one possible design approach, the pixel circuit further includes a first reset circuit electrically connected to the driving circuit, the compensation circuit, and the first initial signal terminal. The transistor included in the first reset circuit is a metal-oxide-slim film transistor. A first shift register is also electrically connected to a first reset circuit of a row of pixel circuits. The first shift register is further configured to provide a first scan signal to the first reset circuit of each pixel circuit connected to the first shift register. The first reset circuit is configured to turn on in response to the first scan signal, transmitting a first initial signal from the first initial signal terminal to the driving circuit and the compensation circuit. The pixel circuits to which the first reset circuit connected to the same first shift register and the data writing circuit belong are located in different rows. This approach, on the one hand, helps reduce leakage current in the first reset circuit, maintaining the potential of the corresponding nodes within the pixel circuit; on the other hand, it further reduces the number of shift registers electrically connected to the pixel circuit, and correspondingly, further reduces the number of gate driving circuits electrically connected to the pixel circuit. This further reduces power consumption due to the large number of gate driving circuits, further reduces the space occupied by the gate driving circuits, and reduces the bezel size of the display panel, facilitating a narrow bezel design for the display panel.

[0014] In the first possible design approach, the pixel circuit to which the first reset circuit connected to the same first shift register belongs is located in the row preceding the pixel circuit to which the data write circuit connected to it belongs. That is, the same first shift register can provide the first scan signal for two adjacent rows of pixel circuits. This facilitates cooperation with other shift registers to drive the pixel circuits and also simplifies the design of the pixel circuit driving timing.

[0015] In one possible design approach, the first reset circuit includes a fourth transistor, which is a metal-oxide-slim thin-film transistor. The control electrode of the fourth transistor is electrically connected to the first shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the driving circuit and the compensation circuit. This simplifies the structure of the first reset circuit and reduces the structural complexity and fabrication difficulty of the display panel.

[0016] Secondly, a display panel is provided, comprising a display area and a bezel area, the bezel area being located on at least two sides outside the display area. The display panel further includes: multiple rows of pixel circuits located within the display area and a first shift register located in the bezel area. Each row of pixel circuits includes a data writing circuit, a driving circuit, and a compensation circuit. The data writing circuit is electrically connected to the driving circuit and a data signal terminal, and the driving circuit is electrically connected to the compensation circuit. Both the data writing circuit and the compensation circuit include metal-oxide-slim transistors. The first shift register is electrically connected to the data writing circuit and the compensation circuit of one row of pixel circuits. The first shift register is configured to provide a first scan signal to the data writing circuit and the compensation circuit of the pixel circuit connected to the first shift register. The data writing circuit and the compensation circuit are configured to be turned on in response to the first scan signal, transmitting a data signal from the data signal terminal to the driving circuit.

[0017] The display panel provided in some embodiments of this application sets the transistors included in the data writing circuit and the compensation circuit to metal-oxide transistors, and sets a first shift register so that the first shift register is electrically connected to the data writing circuit and the compensation circuit located in the same row of pixel circuits. This not only reduces leakage current through the data writing circuit and the compensation circuit, maintains the potential of relevant nodes inside the pixel circuit, and reduces power consumption caused by leakage current, but also reduces the number of shift registers electrically connected to the pixel circuit by sharing the first shift register. Correspondingly, it reduces the number of gate driving circuits. Thus, it can reduce the space occupied by the gate driving circuits while reducing the power consumption caused by a large number of gate driving circuits, and reduce the bezel size of the display panel, making it easier to realize a narrow bezel design of the display panel.

[0018] In a possible design in the second aspect, the data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor. Both the first and third transistors are metal-oxide-slim (MOS) transistors. The control electrode of the first transistor is electrically connected to a first shift register, its first terminal is electrically connected to a data signal terminal, and its second terminal is electrically connected to the first terminal of the second transistor. The control electrode of the second transistor is electrically connected to the second terminal of the third transistor, and its second terminal is electrically connected to the first terminal of the third transistor. The control electrode of the third transistor is electrically connected to the first shift register.

[0019] In a possible design approach in the second aspect, the pixel circuit further includes a first reset circuit electrically connected to the driving circuit, the compensation circuit, and a first initial signal terminal; the first reset circuit includes a metal-oxide-slim transistor. The display panel also includes a second shift register located in the bezel area, electrically connected to the first reset circuit of at least one row of pixel circuits; the second shift register is configured to provide a second scan signal to the first reset circuit of the pixel circuit connected to the second shift register; the first reset circuit is configured to turn on in response to the second scan signal, transmitting a first initial signal from the first initial signal terminal to the driving circuit and the compensation circuit. By electrically connecting the second shift register to the first reset circuit, the load on the second shift register is reduced, allowing for more flexible control of the display panel for image display.

[0020] In the second possible design approach, the first shift register is located on one side outside the display area, and / or the second shift register is located on one side outside the display area. This increases the flexibility in setting the first and second shift registers, making it suitable for more types of display panels.

[0021] In a second possible design, the aforementioned row of pixel circuits is electrically connected to a first shift register, and the aforementioned at least one row of pixel circuits is electrically connected to a second shift register. Along the row direction of the multi-row pixel circuits, the first and second shift registers are located on opposite sides outside the display area. In this case, the display panel is, for example, a small to medium-sized display panel. This arrangement, along the row direction of the multi-row pixel circuits, balances the number of gate drive circuits belonging to the shift registers on both sides of the display area, making the width of the bezel areas on both sides of the display area the same or approximately the same, and facilitating the routing of the bezel areas.

[0022] In a second possible design approach, the aforementioned row of pixel circuits is electrically connected to two first shift registers, and the aforementioned at least one row of pixel circuits is electrically connected to two second shift registers. Along the row direction of the multi-row pixel circuits, the two first shift registers are located on opposite sides of the display area, and the two second shift registers are also located on opposite sides of the display area. In this case, the display panel is, for example, a large-size display panel. Using a dual-side driving method not only helps reduce the load on the first and second shift registers but also improves the display uniformity of the display panel.

[0023] In a possible design in the second aspect, the first reset circuit includes a fourth transistor, which is a metal-oxide-slim thin-film transistor. The control electrode of the fourth transistor is electrically connected to the second shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the driving circuit and the compensation circuit. This simplifies the structure of the first reset circuit and reduces the structural complexity and manufacturing difficulty of the display panel.

[0024] In either the first or second possible design approach, the second transistor is a metal-oxide-slim thin-film transistor (MOST). This improves the crystallization uniformity of the active layer of the second transistor, thereby improving the uniformity of the transistor's characteristics. Alternatively, the second transistor is a low-temperature polycrystalline silicon (LTPS) thin-film transistor (LTPS). This allows the second transistor to possess higher electron mobility.

[0025] In one of the possible design embodiments of the first or second aspect, the display panel further includes a light-emitting device, a third shift register, and a fourth shift register, with the light-emitting device located within the display area and the third and fourth shift registers located outside the display area. The pixel circuit further includes a light-emitting control circuit, a second reset circuit, and a third reset circuit. The light-emitting control circuit is electrically connected to a first voltage signal terminal, a driving circuit, and the light-emitting device; the second reset circuit is electrically connected to a second initial signal terminal and the light-emitting device; and the third reset circuit is electrically connected to a third initial signal terminal and the driving circuit. The third shift register is electrically connected to the second and third reset circuits of at least one row of pixel circuits. The third shift register is configured to provide a third scan signal to the second and third reset circuits of the pixel circuits connected to the third shift register. The second reset circuit is configured to be turned on in response to the third scan signal, transmitting a second initial signal from the second initial signal terminal to the light-emitting device. The third reset circuit is configured to be turned on in response to the third scan signal, transmitting the third initial signal from the third initial signal terminal to the driving circuit. The fourth shift register is electrically connected to the light-emitting control circuit of at least one row of pixel circuits. The fourth shift register is configured to provide a light-emitting control circuit for the pixel circuit connected to the fourth scan signal. The light-emitting control circuit is configured to turn on in response to the fourth scan signal, connecting the path between the first voltage signal terminal and the light-emitting device.

[0026] By setting up a third reset circuit, the voltage difference between the output of the third reset circuit (e.g., the second or first node) and the third node can be adjusted using a third initial signal, thus biasing the driving circuit and improving the low frame rate flickering problem when the display panel shows a low-brightness image. By using the same third shift register to synchronously drive the second and third reset circuits of each pixel circuit in at least one row of pixel circuits, it is possible to avoid increasing the number of shift registers, thus avoiding increased power consumption and bezel size. Furthermore, by connecting the data writing circuit and the second reset circuit to different shift registers, the conduction status of the data writing circuit and the second reset circuit can be controlled separately. This allows for increasing the conduction frequency of the second reset circuit while meeting the control requirements of the data writing circuit, which is beneficial for achieving flicker-free frame rate switching within a higher frame rate range, such as 90Hz-120Hz.

[0027] In either the first or second possible design approach, the third shift register is located on one side outside the display area, and / or, the fourth shift register is located on one side outside the display area. This increases the flexibility in setting up the third and fourth shift registers, making it suitable for more types of display panels.

[0028] In one of the possible design embodiments of the first or second aspect, the aforementioned at least one row of pixel circuits is electrically connected to a third shift register and a fourth shift register. Along the row direction of the multi-row pixel circuits, the third and fourth shift registers are located on opposite sides outside the display area. This balances the number of shift registers and their associated gate drive circuits on both sides of the display area, ensuring that the width of the bezel areas on both sides of the display area is the same or approximately the same, and facilitating the routing of traces in the non-display area.

[0029] In either the first or second possible design approach, the aforementioned at least one row of pixel circuits is electrically connected to two third shift registers and two fourth shift registers. Along the row direction of the multi-row pixel circuits, the two third shift registers are located on opposite sides of the display area, and the two fourth shift registers are also located on opposite sides of the display area. This dual-side driving method is beneficial for improving the display uniformity of the display panel.

[0030] In one of the possible design embodiments of the first or second aspect, the light-emitting control circuit includes a fifth transistor and a sixth transistor, the second reset circuit includes a seventh transistor, and the third reset circuit includes an eighth transistor. The control electrode of the fifth transistor is electrically connected to a fourth shift register, the first electrode of the fifth transistor is electrically connected to a first voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to a driving circuit. The control electrode of the sixth transistor is electrically connected to the fourth shift register, the first electrode of the sixth transistor is electrically connected to the driving circuit, and the second electrode of the sixth transistor is electrically connected to the light-emitting device. The control electrode of the seventh transistor is electrically connected to a third shift register, the first electrode of the seventh transistor is electrically connected to a second initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the light-emitting device. The control electrode of the eighth transistor is electrically connected to the third shift register, the first electrode of the eighth transistor is electrically connected to a third initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the driving circuit. This simplifies the structure of the light-emitting control circuit, the second reset circuit, and the third reset circuit, reducing the structural complexity and manufacturing difficulty of the display panel.

[0031] In either the first or second possible design approach, the fifth, sixth, seventh, and eighth transistors are all low-temperature polycrystalline silicon thin-film transistors. This is beneficial for improving the electrical performance of the pixel circuit.

[0032] Thirdly, a display module is provided, comprising: a display panel as described in any embodiment of the first aspect, and a display driver. The display driver is electrically connected to the display panel.

[0033] Fourthly, an electronic device is provided, comprising: a display module as described in any embodiment of the third aspect, and a drive controller. The drive controller is coupled to the display module.

[0034] The technical effects of any of the design methods in the third and fourth aspects can be found in the technical effects of different design methods in the first or second aspects, and will not be repeated here. Attached Figure Description

[0035] Figure 1 is a structural diagram of an electronic device provided in an embodiment of this application;

[0036] Figure 2 is a partial structural diagram of an electronic device provided in an embodiment of this application;

[0037] Figure 3 is an architectural diagram of a gate driving circuit provided in an embodiment of this application;

[0038] Figure 4 is an equivalent circuit diagram of a sub-pixel provided in an embodiment of this application;

[0039] Figure 5 is a timing diagram provided in an embodiment of this application;

[0040] Figure 6 is a partial structural diagram of a display panel provided in an embodiment of this application;

[0041] Figure 7 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0042] Figure 8 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0043] Figure 9 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0044] Figure 10 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0045] Figure 11 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0046] Figure 12 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0047] Figure 13 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0048] Figure 14 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0049] Figure 15 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0050] Figure 16 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0051] Figure 17 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0052] Figure 18 is another timing diagram provided by an embodiment of this application;

[0053] Figure 19 is another timing diagram provided by an embodiment of this application;

[0054] Figure 20 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0055] Figure 21 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0056] Figure 22 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0057] Figure 23 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0058] Figure 24 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0059] Figure 25 is an equivalent circuit diagram of another sub-pixel provided in an embodiment of this application;

[0060] Figure 26 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0061] Figure 27 is a partial structural diagram of another display panel provided in an embodiment of this application;

[0062] Figure 28 is another timing diagram provided by an embodiment of this application. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0064] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. "At least one item" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items.

[0065] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0066] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "coupled" may indicate, for example, that two or more components have direct physical or electrical contact, or it may mean that two or more components do not have direct contact but still cooperate or interact with each other. The term "connected" should be interpreted broadly; for example, "connected" can mean directly linked or indirectly linked through an intermediate medium. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. Furthermore, the use of "based on" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0067] In this application embodiment, "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts used for description and clarification, and can vary accordingly depending on the orientation of the components in the accompanying drawings. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the illustrations do not reflect actual dimensional proportions. Therefore, variations in shape relative to the drawings are conceivable due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the areas shown in this application, but rather include shape deviations caused, for example, by manufacturing. For example, an etched area shown as rectangular would typically have a curved feature. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0068] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0069] In some embodiments of this application, the circuit structures provided, such as pixel circuits, utilize transistors that can be thin-film transistors (TFTs), metal-oxide-semiconductor (MOS) transistors, or other switching devices with similar characteristics. Furthermore, the first electrode of each transistor is one of the source and drain, and the second electrode is the other of the source and drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second electrodes of the transistors in some embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; or, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source. Additionally, the control electrode of a transistor refers, for example, to the gate electrode.

[0070] In some embodiments of the circuit structure provided in this application, such as in a pixel circuit, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0071] Some embodiments of this application provide an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products can be mobile phones, tablets, desktop computers, laptops, handheld computers, personal computers (PCs), netbooks, cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices, etc. Smart wearable devices can be, for example, smartwatches and smart bracelets. This application does not impose any special limitations on the specific type of this electronic device. Home electronics products can be smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances, such as soymilk makers and robot vacuum cleaners. In-vehicle electronics products can be in-vehicle navigation systems and in-vehicle DVDs. Financial terminal products can be ATMs and self-service terminals. This application does not impose any special limitations on the specific form of the above-mentioned electronic devices.

[0072] For ease of explanation, the following description uses a flat-screen mobile phone as an example, which should not be considered a specific limitation on the structural form of the electronic device. Figure 1 is a structural diagram of an electronic device provided in an embodiment of this application, and Figure 2 is a partial structural diagram of an electronic device provided in an embodiment of this application. Those skilled in the art will understand that the architecture of the electronic device shown in Figures 1 and 2 does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than those shown in Figures 1 and 2, or may combine some of the components shown in Figures 1 and 2, or may have a different component arrangement than those shown in Figures 1 and 2.

[0073] In some embodiments, as shown in FIG1, the electronic device 1000 mainly includes: a display module 100, a middle frame 200, a housing 300, and a cover plate 400.

[0074] The housing 300 is located on the backlight side of the display module 100. The mid-frame 200 is located between the display module 100 and the housing 300. The surface of the mid-frame 200 away from the display module 100 is used to mount internal components such as batteries, circuit boards, cameras, and antennas. This surface refers to the side of the mid-frame 200 facing the housing 300. The cover plate 400 is located on the side of the display module 100 away from the mid-frame 200. The cover plate 400 can be, for example, a cover glass, which may have a certain degree of toughness. The display module 100 has a light-emitting side capable of displaying images and a backlight side opposite to the light-emitting side. The mid-frame 200 is located on the backlight side of the display module 100, and the cover plate 400 is located on the light-emitting side of the display module 100.

[0075] In some examples, as shown in Figure 2, the electronic device 1000 also includes a drive controller 500, which is coupled to the display module 100, for example. The drive controller 500 can receive image signals RGB and control signals CTRL, and output image data signals DATA that match the interface specifications of the display module 100 according to the image signals RGB. The drive controller 500 can also output data control signals DCS. The drive controller 500 may include, for example, a system-on-chip (SOC).

[0076] The aforementioned display module 100 includes, for example, a display panel 10 and a display driver 20. The display driver 20 can be coupled to a drive controller 500, receive signals output by the drive controller 500, and provide display signals to the display panel 10. Of course, the display module 100 may also include structures such as flexible circuit boards.

[0077] For example, the display driver 20 receives a data control signal DCS and an image data signal DATA from the driver controller 500. The display driver 20 converts the image data signal DATA into a data signal and outputs the data signal to multiple data signal lines DL in the display panel 10. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA. The display driver 20 can also output scan control signals SCS required for display to the display panel 10, such as a clock signal CLK, an initial input signal STV, a reset signal RST, etc. The display driver 20 may include, for example, a display driver integrated circuit (DDIC).

[0078] In some examples, the display panel 10 described above can be a self-emissive display panel, which has advantages such as light weight, thinness, and high contrast. Optionally, the display panel 10 can be a self-emissive display panel such as an organic light-emitting diode (OLED) display panel, an active-matrix organic light-emitting diode (AMOLED) display panel, a mini organic light-emitting diode (Mini-OLED) display panel, a micro light-emitting diode (Micro-LED) display panel, a micro organic light-emitting diode (Micro-OLED) display panel, or a quantum dot light-emitting diode (QLED) display panel. In this case, the display panel 10 can be a rigid display panel or a flexible display panel.

[0079] For any of the above-described display panels 10, the display panel 10 has a display area (AA) and a border area BB located around the display area AA. The display area AA is used to display images. As shown in FIG2, the display panel 10 includes a plurality of sub-pixels P disposed within the display area AA, and a scan driving circuit 1 disposed within the border area BB. Correspondingly, the scan driving circuit 1 is disposed outside the display area AA.

[0080] The aforementioned multiple sub-pixels P can receive data signals provided by the display driver 20. In some embodiments of this application, the multiple sub-pixels P are illustrated by arranging them in a matrix form. Sub-pixels P arranged in a row along the row direction X are called sub-pixels in the same row, and sub-pixels P arranged in a row along the column direction Y are called sub-pixels in the same column.

[0081] The scan driving circuit 1 described above can receive the scan control signal SCS provided by the display driver 20. This scan driving circuit 1 includes, for example, multiple array substrate gate driver circuits (GOA) 11. Hereinafter, the array substrate gate driver circuit 11 will be simply referred to as the gate driver circuit 11. Each gate driver circuit 11 in the scan driving circuit 1 employs a technology that integrates the row scanning circuit of a flat panel display (FPD) into the panel design, achieving narrow bezels, reducing the cost of the display panel 10, and eliminating the need for a gate driver chip.

[0082] Figure 3 is an architectural diagram of a gate driving circuit provided in an embodiment of this application.

[0083] In some embodiments, as shown in FIG3, the gate driving circuit 11 includes a plurality of cascaded shift registers (SR), namely shift registers SR(1), SR(2), SR(3), SR(4)...SR(n). Wherein, n is a positive integer.

[0084] For example, the signal input terminal InP of the first-stage shift register SR(1) is electrically connected to the start signal terminal STV to receive the scan start signal or the scan stop start signal. Except for the first-stage shift register SR(1), the signal input terminal InP of each shift register is electrically connected to the signal output terminal OutP of its preceding shift register; for example, the signal input terminal InP of shift register SR(3) is electrically connected to the signal output terminal OutP of shift register SR(2). Except for the last-stage shift register SR(n), the reset signal terminal of each shift register is electrically connected to the signal output terminal OutP of its next-stage shift register; for example, the reset signal terminal of shift register SR(3) is electrically connected to the signal output terminal OutP of shift register SR(4). The reset signal terminal of the last-stage shift register SR(n) is electrically connected to the start signal terminal STV.

[0085] When the scan enable signal is input at the start signal terminal STV, the first-stage shift register SR(1) of the gate drive circuit 11 starts working, and subsequently, the multi-stage shift registers start working one after another. The electrical signal received at the signal input terminal InP of a certain stage shift register is the electrical signal output at the signal output terminal OutP of the previous stage shift register. When there is no trigger at the signal input terminal InP, the internal reset function of the circuit will reset the circuit output to a certain default state, thereby realizing the transmission of the turn-on / turn-off signal to the sub-pixel P row by row, and turning on / off certain transistors in the sub-pixel P in turn.

[0086] The signal output terminal OutP of each shift register can be electrically connected to one, two, four or more rows of sub-pixels P, and this application embodiment does not limit this.

[0087] As exemplified in Figure 3, the gate drive circuit 11 also includes multiple clock signal lines and power supply voltage signal lines. Each shift register is electrically connected to the aforementioned multiple clock signal lines and power supply voltage signal lines to receive the corresponding clock signals and power supply voltage signals.

[0088] It is understandable that the signal output terminal OutP of the shift register of different types of gate drive circuits 11 can output different types of scan signals to the corresponding sub-pixels P. For details on these various types of scan signals, please refer to the relevant explanations below; they will not be repeated here.

[0089] In some embodiments, a sub-pixel P includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit. The light-emitting device is, for example, an OLED. The pixel circuit generates a driving signal and transmits the driving signal to the light-emitting device electrically connected to it, driving the light-emitting device to emit light. The light emitted by the light-emitting devices of multiple sub-pixels P cooperates to enable the electronic device 1000 to display an image.

[0090] The aforementioned pixel circuit typically includes multiple transistors, such as a driving transistor. These transistors are, for example, low-temperature polysilicon (LTPS) thin-film transistors, and the corresponding pixel circuit is an LTPS pixel circuit. However, due to leakage problems in LTPS pixel circuits, the voltage at the control electrode of the driving transistor is difficult to maintain for a long time. This leads to severe screen flickering during low-frequency display, making it difficult to achieve low frame rate applications, such as 1Hz or 10Hz.

[0091] To address this issue, the industry developed low-temperature polycrystalline oxide (LTPO) technology. LTPO technology combines the high mobility of LTPS thin-film transistors with the low leakage current of indium gallium zinc oxide (IGZO) thin-film transistors. This allows for both high screen brightness and high frame rate display, and low frame rate display when the SoC is not sending images or is sending low frame rate images. This achieves relatively smooth high frame rate display while reducing power consumption when high frame rate is not needed, i.e., low frame rate display.

[0092] Figure 4 shows an equivalent circuit diagram of a sub-pixel, and Figure 5 is a timing diagram. This timing diagram can be applied to sub-pixels with various structures. This embodiment of the application uses the timing diagram applied to the sub-pixel shown in Figure 4 as an example for illustration. In the sub-pixel shown in Figure 4, the pixel circuit is an LTPO pixel circuit.

[0093] In some embodiments, as shown in FIG4, the pixel circuit 21 in sub-pixel P is electrically connected to the light-emitting device 22. The pixel circuit 21 may include a data writing circuit 211, a driving circuit 212, a compensation circuit 213, a first reset circuit 214, a light-emitting control circuit 215, an energy storage sub-circuit 216, and a second reset circuit 217.

[0094] For example, the data writing circuit 211 includes a first transistor T1, the driving circuit 212 includes a second transistor T2, the compensation circuit 213 includes a third transistor T3, the first reset circuit 214 includes a fourth transistor T4, the light-emitting control circuit 215 includes a fifth transistor T5 and a sixth transistor T6, the energy storage sub-circuit 216 includes a storage capacitor Cst, and the second reset circuit 217 includes a seventh transistor T7.

[0095] Referring again to Figure 4, the first transistor T1 and the second transistor T2 are electrically connected, and their junction point is, for example, the first node N1. The second transistor T2 and the third transistor T3 are electrically connected, and their junction point is, for example, the second node N2 and the third node N3. Specifically, the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal SC1, the first electrode of the first transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the third node N3, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the second scan signal terminal SC2, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The first electrode of the storage capacitor Cst is electrically connected to the third node N3, and the second electrode of the storage capacitor Cst is electrically connected to the first voltage signal terminal ELVDD.

[0096] The control electrode of the fourth transistor T4 is electrically connected to the third scan signal terminal SC3, the first electrode of the fourth transistor T4 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the fourth scan signal terminal SC4, the first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1. The control electrode of the sixth transistor T6 is electrically connected to the fourth scan signal terminal SC4, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device 22, and the cathode of the light-emitting device 22 is electrically connected to the second voltage signal terminal ELVSS. The point where the electrical connections of the sixth transistor T6 and the light-emitting device 22 converge is, for example, the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the fifth scan signal terminal SC5, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0097] Optionally, the third transistor T3 and the fourth transistor T4 are both metal-oxide-slim transistors, such as IGZO thin-film transistors. Further, both are N-type transistors and can be turned on in response to a high-level electrical signal. The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all LTPS thin-film transistors. Further, all five are P-type transistors and can be turned on in response to a low-level electrical signal.

[0098] The following uses pixel circuit 21 in the nth row of sub-pixels P as an example, where n is a positive integer. The working process of pixel circuit 21 is illustrated in Figures 4 and 5. In Figure 5, SC1(n) represents the first scan signal received by each pixel circuit 21 in the nth row of sub-pixels P, SC1(n+1) represents the first scan signal received by each pixel circuit 21 in the (n+1)th row of sub-pixels P, SC2(n) represents the second scan signal received by each pixel circuit 21 in the nth row of sub-pixels P, SC3(n) represents the third scan signal received by each pixel circuit 21 in the nth row of sub-pixels P, SC4(n) represents the fourth scan signal received by each pixel circuit 21 in the nth row of sub-pixels P, and SC5(n) represents the fifth scan signal received by each pixel circuit 21 in the nth row of sub-pixels P.

[0099] As shown in Figure 5, the working process of the pixel circuit 21 includes: a non-light-emitting stage S1 and a light-emitting stage S2. The non-light-emitting stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3.

[0100] During the non-light-emitting phase S1, the level of the fourth scan signal is high. The fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0101] During the first reset phase t1 of the non-light-emitting phase S1, both the second and third scan signals are at high levels. The third transistor T3 and the fourth transistor T4 are both turned on. The first initial signal from the first initial signal terminal Vinit1 is transmitted sequentially through the fourth transistor T4, the second node N2, and the third transistor T3 to the third node N3, resetting the third node N3.

[0102] During the data writing and compensation phase t2 of the non-light-emitting phase S1, the second scan signal is at a high level, and the first scan signal is at a low level. Both the third transistor T3 and the first transistor T1 are turned on. The data signal from the data signal terminal Data is sequentially transmitted through the first transistor T1, the first node N1, the second transistor T2, the second node N2, and the third transistor T3 to the third node N3, realizing the writing of the data signal and compensation for the threshold voltage of the second transistor T2. During this period, the storage capacitor Cst is also charged to maintain the potential of the third node N3.

[0103] During the second reset phase t3 of the non-light-emitting phase S1, the level of the fifth scan signal is low. The seventh transistor T7 is turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 through the seventh transistor T7 to reset the fourth node N4, which is also to reset the anode of the light-emitting device 22.

[0104] During the light-emitting stage S2, the level of the fourth scan signal is low, and the fifth transistor T5 and the sixth transistor T6 are turned on, connecting the path between the first voltage signal terminal ELVDD and the light-emitting device 22. The driving signal generated based on the data signal and the first voltage signal from the first voltage signal terminal ELVDD is transmitted to the light-emitting device 22 to drive the light-emitting device 22 to emit light.

[0105] In some embodiments, to optimize power consumption and achieve a set of frame rates compatible with 1Hz, 10Hz, 30Hz, 60Hz, and 120Hz, the aforementioned driving circuit 1 includes, for example, five types of gate driving circuits 11. These five types of gate driving circuits 11 are, for example, a first gate driving circuit 11a, a second gate driving circuit 11b, a third gate driving circuit 11c, a fourth gate driving circuit 11d, and a fifth gate driving circuit 11e.

[0106] In some examples, as shown in Figure 6, for small to medium-sized display panels, the number of first gate driving circuits 11a is, for example, two, and the number of second gate driving circuits 11b, third gate driving circuit 11c, fourth gate driving circuit 11d, and fifth gate driving circuit 11e is, for example, one each. For example, along the row direction X of the multi-row sub-pixels P, three gate driving circuits 11 are provided on each side outside the display area AA.

[0107] In this embodiment, two adjacent sub-pixels P represent two adjacent rows of sub-pixels P.

[0108] Referring to Figures 4 and 6, along the row direction X of the multi-row sub-pixels P, the two first gate driving circuits 11a are located, for example, on both sides outside the display area AA, i.e., on the left and right sides, employing a bilateral driving method, which can also be called dual-side driving. In each first gate driving circuit 11a, a first shift register GP-GOA is electrically connected, for example, to each pixel circuit 21 in a row of sub-pixels P via a first scan signal terminal SC1, to provide a first scan signal to the corresponding pixel circuit 21.

[0109] Along the row direction X of the multi-row sub-pixels P, the second gate driving circuit 11b is located, for example, on one side outside the display area AA, such as the right side, using a single-sided driving method, also known as single-sided driving. In each of the second gate driving circuits 11b, a second shift register GN-GOA is electrically connected, for example, to each pixel circuit 21 in the two rows of sub-pixels P via a second scan signal terminal SC2, so as to provide a second scan signal to the corresponding pixel circuit 21.

[0110] Along the row direction X of the multi-row sub-pixels P, the third gate driving circuit 11c is located, for example, on one side outside the display area AA, such as the left side, and adopts a single-sided driving method. Among them, a third shift register Rst-NGOA in each third gate driving circuit 11c is electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the third scan signal terminal SC3, so as to provide a third scan signal to the corresponding pixel circuit 21.

[0111] Along the row direction X of the multi-row sub-pixels P, the fourth gate driving circuit 11d is located, for example, on one side outside the display area AA, such as the left side, and adopts a single-sided driving method. Among them, a fourth shift register EM-GOA in each fourth gate driving circuit 11d is electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the fourth scan signal terminal SC4, so as to provide the fourth scan signal to the corresponding pixel circuit 21.

[0112] Along the row direction X of the multi-row sub-pixels P, the fifth gate driving circuit 11e is located, for example, on one side outside the display area AA, such as the right side, and adopts a single-sided driving method. Among them, a fifth shift register Rst-PGOA in each fifth gate driving circuit 11e is electrically connected to each pixel circuit 21 in the two rows of sub-pixels P through the fifth scan signal terminal SC5, so as to provide the fifth scan signal to the corresponding pixel circuit 21.

[0113] In other words, each two rows of sub-pixels P require eight shift registers to drive them.

[0114] Referring to Figures 5 and 6, during the image display process, the nth row sub-pixel P and the (n+1)th row sub-pixel P synchronously execute the first reset stage t1; then, the data writing and compensation stage t2 is executed in a time-division manner, writing the data signal line by line and compensating the threshold voltage; after that, the second reset stage t3 and the light emission stage S2 are executed synchronously.

[0115] In other examples, as shown in Figure 7, for large-size display panels, the number of the first gate driving circuit 11a, the second gate driving circuit 11b, the third gate driving circuit 11c, the fourth gate driving circuit 11d, and the fifth gate driving circuit 11e is, for example, two each. For instance, along the row direction X of the multi-row sub-pixels P, on each side outside the display area AA, there is one first gate driving circuit 11a, one second gate driving circuit 11b, one third gate driving circuit 11c, one fourth gate driving circuit 11d, and one fifth gate driving circuit 11e. Each gate driving circuit 11 employs a bilateral driving method.

[0116] The correspondence between the shift register and the sub-pixel P in each gate drive circuit 11 shown in Figure 7 is the same as that shown in Figure 6. Please refer to the relevant explanation above, which will not be repeated here.

[0117] In other words, each pair of sub-pixels P requires twelve shift registers to drive it.

[0118] For the two types of display panels mentioned above, although this configuration can achieve better display effects and power consumption benefits, the additional gate drive circuits 11 or shift registers will bring additional power consumption, hindering further reduction in power consumption; moreover, the five types of gate drive circuits 11 mentioned above will occupy a large space, resulting in a larger bezel size for the display panel, making it difficult to achieve a narrow bezel design.

[0119] Figure 8 also shows an equivalent circuit diagram of a sub-pixel, in which the pixel circuit is an LTPO pixel circuit.

[0120] In some embodiments, as shown in FIG8, the pixel circuit 21 in sub-pixel P is electrically connected to the light-emitting device 22. The pixel circuit 21 may include a data writing circuit 211, a driving circuit 212, a compensation circuit 213, a first reset circuit 214, a light-emitting control circuit 215, an energy storage sub-circuit 216, and a second reset circuit 217.

[0121] For example, in Figure 8, the structure and connection relationship of the data writing circuit 211, driving circuit 212, compensation circuit 213, light emission control circuit 215, energy storage sub-circuit 216 and second reset circuit 217 can be referred to Figure 4, and the relevant description of Figure 4 above can be referred to, and will not be repeated here.

[0122] The first reset circuit 214 in pixel circuit 21 can also adopt other connection methods. For example, as shown in Figure 8, the second terminal of the fourth transistor T4 in the first reset circuit 214 is electrically connected to the third node N3, and the control terminal of the fourth transistor T4 is electrically connected to the second scan signal terminal SC2(n-5); the control terminal of the seventh transistor T7 in the second reset circuit 217 is electrically connected to the first scan signal terminal SC1(n+1). Here, n≥5, and n is an integer.

[0123] In some embodiments, to optimize power consumption and achieve a set of frame rates compatible with 1Hz, 10Hz, 30Hz, 60Hz, and 120Hz, the driving circuit 1 includes, for example, three types of gate driving circuits 11. These three types of gate driving circuits 11 are, for example, a first gate driving circuit 11a, a second gate driving circuit 11b, and a fourth gate driving circuit 11d.

[0124] In some examples, as shown in Figure 9, for small to medium-sized display panels, the number of the first gate driving circuit 11a, the second gate driving circuit 11b, and the fourth gate driving circuit 11d is, for example, two. Along the row direction X of the multi-row sub-pixels P, each side outside the display area AA is provided with one first gate driving circuit 11a, one second gate driving circuit 11b, and one fourth gate driving circuit 11d.

[0125] Referring again to Figure 9, the first gate driving circuit 11a, the second gate driving circuit 11b, and the fourth gate driving circuit 11d all adopt a dual-side driving method.

[0126] Referring to Figures 8 and 9, a first shift register GP-GOA in each first gate driving circuit 11a is electrically connected, for example, to the data writing circuit 211 of each pixel circuit 21 in the nth row sub-pixel P via the first scan signal terminal SC1(n), and to the second reset circuit 217 of each pixel circuit 21 in the (n+1)th row sub-pixel P via the first scan signal terminal SC1(n+1), so as to provide a first scan signal for the corresponding pixel circuit 21. A second shift register GN-GOA in each second gate driving circuit 11b is electrically connected, for example, to the compensation circuit 213 of each pixel circuit 21 in the nth row sub-pixel P via the second scan signal terminal SC2(n), and to the first reset circuit 214 of each pixel circuit 21 in the (n-5)th row sub-pixel P via the second scan signal terminal SC2(n-5), so as to provide a second scan signal for the corresponding pixel circuit 21. Here, the second shift register GN-GOA can also be electrically connected to the nth row sub-pixel P, and to the other rows of sub-pixels P except for the (n-5)th row. One of the fourth shift registers EM-GOA in each fourth gate drive circuit 11d is electrically connected, for example, to each pixel circuit 21 in the two rows of sub-pixels P via the fourth scan signal terminal SC4, to provide a fourth scan signal to the corresponding pixel circuit 21. Each two rows of sub-pixels P are driven using eight shift registers.

[0127] For the aforementioned display panel, although this configuration can achieve better display effects and power consumption benefits, the additional gate drive circuits 11 or shift registers will bring additional power consumption, hindering further reduction in power consumption; moreover, the three types of gate drive circuits 11 mentioned above will occupy a large space, resulting in a larger bezel size for the display panel, making it difficult to achieve a narrow bezel design.

[0128] Based on this, some embodiments of this application provide a display panel that can be applied to the aforementioned display module or electronic device. Optionally, this display panel can be the display panel shown in FIG2. The display panel improves the structure of the pixel circuit 21, and correspondingly improves the arrangement between the pixel circuit 21 and its electrically connected shift register or gate drive circuit. FIG10, FIG12, and FIG15 respectively illustrate an equivalent circuit diagram of a sub-pixel, and FIG11, FIG13, FIG14, FIG16, and FIG17 respectively illustrate a partial structural diagram of a display panel.

[0129] In some embodiments, as shown in FIG2, the display panel 10 may include a plurality of sub-pixels P, which are located within the display area AA, for example, arranged in an array. Specifically, the plurality of sub-pixels P are arranged in multiple rows and columns, with each row of sub-pixels P including a plurality of sub-pixels P spaced apart along the row direction X, and each column of sub-pixels P including a plurality of sub-pixels P spaced apart along the column direction Y. Of course, the arrangement of the plurality of sub-pixels P is not limited to this.

[0130] In some examples, as shown in Figures 10, 12, and 15, each sub-pixel P includes a connected pixel circuit 21 and a light-emitting device 22. The pixel circuit 21 includes a data writing circuit 211, a driving circuit 212, and a compensation circuit 213. The data writing circuit 211 is electrically connected to the data signal terminal Data and the driving circuit 212, with the junction of these two electrical connections, for example, at a first node N1. The driving circuit 212 is also electrically connected to the compensation circuit 213, with the junction of these two electrical connections, for example, at a second node N2 and a third node N3. For example, the data signal from the data signal terminal Data can be transmitted sequentially through the data writing circuit 211, the first node N1, the driving circuit 212, the second node N2, and the compensation circuit 213 to the third node N3.

[0131] For example, the transistors included in the data writing circuit 211 and the compensation circuit 213 are all metal-oxide-slim transistors (MOSTs). Correspondingly, the transistors included in the data writing circuit 211 and the compensation circuit 213 are all N-type transistors. The active layer material of the MOSTs includes, but is not limited to, metal oxides such as 1GZO. This reduces leakage current in the data writing circuit 211, facilitating the maintenance of the potential of the first node N1 and reducing power consumption. Furthermore, it reduces leakage current in the compensation circuit 213, facilitating the maintenance of the potential of the third node N3.

[0132] In some examples, as shown in Figures 11 and 13, the display panel 10 may further include a first shift register 111, which is located outside the display area AA, that is, within the bezel area BB. The number of first shift registers 111 may be multiple, with multiple first shift registers 111 located on the same side of the display area AA cascaded sequentially to form a first gate driving circuit 11a. This first gate driving circuit 11a is located in the bezel area BB.

[0133] Each first shift register 111 is electrically connected, for example, to the data writing circuit 211 of each pixel circuit 21 in a row of pixel circuits 21. Furthermore, the first shift register 111 is configured to provide a first scan signal to the data writing circuit 211 of the pixel circuit 21 to which the first shift register 111 is connected. This helps reduce the load on each first shift register 111 and allows for more flexible control of the display panel 10 for image display.

[0134] For example, the first shift register 111 and the data writing circuits 211 of each pixel circuit 21 in the aforementioned row of pixel circuits 21 can be electrically connected via the first scan signal terminal SC1. Each data writing circuit 211 can receive a first scan signal via the first scan signal terminal SC1. The data writing circuit 211 is configured to turn on in response to the first scan signal, transmitting the data signal from the data signal terminal Data to the compensation circuit 213. Specifically, the data signal can be transmitted sequentially through the data writing circuit 211, the first node N1, and the driving circuit 212 to the compensation circuit 213 or the second node N2.

[0135] In some examples, as shown in Figures 11 and 13, the display panel 10 may further include a second shift register 112 located outside the display area AA, that is, within the border area BB. The number of second shift registers 112 may be multiple, with multiple second shift registers 112 located on the same side of the display area AA cascaded sequentially to form a second gate driving circuit 11b. The second gate driving circuit 11b is located in the border area BB.

[0136] Each second shift register 112 is electrically connected, for example, to the compensation circuit 213 of each pixel circuit 21 in at least one row of pixel circuits 21. Further, the second shift register 112 is configured to provide a second scan signal to the compensation circuit 213 of the pixel circuit 21 to which the second shift register 112 is connected. For example, each second shift register 112 can be electrically connected to the compensation circuit 213 of each pixel circuit 21 in one row of pixel circuits 21. This helps reduce the load on each second shift register 112 and allows for more flexible control of the display panel 10 for image display. As shown in FIG13, each second shift register 112 can be electrically connected to the compensation circuit 213 of each pixel circuit 21 in two rows of pixel circuits 21. This helps reduce the number of second shift registers 112 and simplifies the structure of the second gate drive circuit 11b and the display panel 10. Here, the number of rows of pixel circuits 21 to which the second shift register 112 is connected can be selected and set according to actual needs.

[0137] For example, the second shift register 112 and the compensation circuit 213 of each pixel circuit 21 in at least one row of pixel circuits 21 can be electrically connected via the second scan signal terminal SC2. Each compensation circuit 213 can receive a second scan signal via the second scan signal terminal SC2. The compensation circuit 213 is configured to turn on in response to the second scan signal and transmit the data signal to the drive circuit 212 or the third node N3.

[0138] It is understandable that, since the transistors included in the data writing circuit 211 and the compensation circuit 213 are all metal oxide thin film transistors, in small and medium-sized display panels, both the first shift register 111 and the second shift register 112 can be set up using a single-sided driving method.

[0139] Taking the second shift register 112 as an example, which is electrically connected to the two adjacent rows of pixel circuits 21.

[0140] For example, as shown in Figures 13 and 16, when the display panel 10 is a small to medium-sized display panel, one row of pixel circuits 21 can be electrically connected to a first shift register 111, and the two adjacent rows of pixel circuits 21 can be electrically connected to a second shift register 112.

[0141] In this case, adjacent rows of pixel circuits 21 are electrically connected, for example, to two first shift registers 111 and one second shift register 112. However, in the embodiment shown in FIG6, adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA and one second shift register GN-GOA. This means that, compared to FIG6, in this embodiment, the number of shift registers used to drive the data writing circuit 211 and compensation circuit 213 in the pixel circuit 21 is reduced by two, and correspondingly, the number of gate driving circuits used to drive the data writing circuit 211 and compensation circuit 213 in the pixel circuit 21 is reduced by one.

[0142] Furthermore, as shown in Figures 14 and 17, when the display panel 10 is a large-sized display panel, one row of pixel circuits 21 can be electrically connected to two first shift registers 111, and the two adjacent rows of pixel circuits 21 can be electrically connected to two second shift registers 112.

[0143] In this case, adjacent rows of pixel circuits 21 are electrically connected, for example, to four first shift registers 111 and two second shift registers 112. In the embodiment shown in FIG. 7, adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA and two second shift registers GN-GOA. That is, in the embodiments of this application, the number of shift registers and gate drive circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 remains unchanged and is not increased.

[0144] Therefore, the display panel 10 provided in some embodiments of this application, by setting a first shift register 111 and a second shift register 112, such that the first shift register 111 is electrically connected to the data writing circuit 211 in each pixel circuit 21 located in the same row, and the second shift register 112 is electrically connected to the compensation circuit 213 in each pixel circuit 21 located in at least one row, and the transistors included in the data writing circuit 211 and the compensation circuit 213 are set as metal-oxide transistors, in this way, on the one hand, leakage current can be reduced by the data writing circuit 211 and the compensation circuit 213, the potential of the relevant nodes inside the pixel circuit 21 can be maintained, and the power consumption caused by leakage current can be reduced; on the other hand, it is beneficial to reduce the first shift register 111 and the second shift register 212. The load of the device 112 can be controlled more flexibly by the cooperation of the first shift register 111 and the second shift register 112. Furthermore, when the display panel 10 is a small to medium-sized display panel, the first shift register 111 can be set in a single-sided driving manner, thereby reducing the number of shift registers used to drive the pixel circuit 21. For example, the number of first shift registers 111 used to drive the data writing circuit 211 can be reduced. Correspondingly, the number of gate driving circuits can be reduced. This can reduce the power consumption caused by a large number of gate driving circuits, reduce the space occupied by the gate driving circuits, reduce the bezel size of the display panel 10, and facilitate the narrow bezel design of the display panel 10.

[0145] In some embodiments, at least one of the first shift register 111 and the second shift register 112 is located on one side outside the display area AA. Alternatively, the first shift register 111 may be located on one side outside the display area AA, and / or the second shift register 112 may be located on one side outside the display area AA.

[0146] Optionally, the first shift register 111 is located on one side outside the display area AA, such as the left side, right side, top side, or bottom side in Figure 13, and the second shift register 112 is located on one side outside the display area AA, such as the right side, left side, top side, or bottom side in Figure 13. Alternatively, the first shift register 111 is located on both sides outside the display area AA, such as the left and right sides in Figure 14, and the second shift register 112 is located on both sides outside the display area AA, such as the left and right sides in Figure 14.

[0147] This increases the flexibility of setting the first shift register 111 and the second shift register 112, making it suitable for more types of display panels 10.

[0148] In some embodiments, as shown in Figures 13 and 16, when the display panel 10 is a small to medium-sized display panel, a row of pixel circuits 21 can be electrically connected to a first shift register 111. This first shift register 111 is located on one side outside the display area AA, and it is configured with single-sided driving. Furthermore, at least one row of pixel circuits 21 can be electrically connected to a second shift register 112. This second shift register 112 is located on one side outside the display area AA, and it is configured with single-sided driving.

[0149] In some examples, along the row direction X of the multi-row pixel circuit 21, the aforementioned first shift register 111 and second shift register 112 are located on both sides outside the display area AA, i.e., the left and right sides, respectively. Correspondingly, a first gate driving circuit 11a including the first shift register 111 is provided on one side of the multi-row pixel circuit P, and a second gate driving circuit 11b including the second shift register 112 is provided on the other side.

[0150] Optionally, in Figures 13 and 16, two adjacent rows of pixel circuits 21 are electrically connected to a second shift register 112. The second shift register 112 is located on the right side of Figures 13 and 16. The two first shift registers 111 connected to these two adjacent rows of pixel circuits 21 are arranged along the column direction Y, and these two first shift registers 111 are located on the left side as shown in Figures 13 and 16. For example, along the row direction X, the size of the space occupied by these two first shift registers 111 is the same as or approximately the same as the size of the space occupied by the second shift register 112.

[0151] In this way, along the row direction X of the multi-row pixel circuit 21, the number of gate drive circuits belonging to the shift registers on both sides of the display area AA can be balanced, so that the width of the border area BB on both sides of the display area AA is the same or approximately the same, and it is beneficial to the routing of the border area BB.

[0152] In other embodiments, as shown in Figures 14 and 17, when the display panel 10 is a large-sized display panel, one row of pixel circuits 21 can be electrically connected to two first shift registers 111, and at least one row of pixel circuits 21 is electrically connected to two second shift registers 112. Along the row direction X of the multiple rows of pixel circuits 21, the two first shift registers 111 are located on both sides outside the display area AA, and the two second shift registers 112 are located on both sides outside the display area AA. Correspondingly, each side outside the display area AA is provided with a first gate driving circuit 11a including the first shift register 111 and a second gate driving circuit 11b including the second shift register 112.

[0153] This helps reduce the load on the first shift register 111 and the second shift register 112, and allows for more flexible control of the display panel 10 for screen display.

[0154] In some examples, continuing to refer to Figure 14, the second shift register 112 is farther away from the display area AA than the first shift register 111 located on the same side. That is, of the first shift register 111 and the second shift register 112 located on the same side of the display area AA, the first shift register 111 is closer to the display area AA. Correspondingly, the two first gate drive circuits 11a are located between the two second gate drive circuits 11b.

[0155] Since each first shift register 111 is electrically connected to one row of pixel circuits 21, and each second shift register 112 is electrically connected to one or more rows of pixel circuits 21, the wiring between the first gate driving circuit 11a and the multi-row pixel circuits 21 may be more numerous and complex than that between the second gate driving circuit 11b. This arrangement optimizes the wiring space of the display panel 10, reduces the winding between the first gate driving circuit 11a and the multi-row pixel circuits 21, lowers wiring difficulty, and improves the yield of the display panel 10. Furthermore, the dual-side driving method helps improve the display uniformity of the display panel 10.

[0156] Of course, as shown in Figure 17, the positions of the first shift register 111 and the second shift register 112 located on the same side can be interchanged.

[0157] The structures of the data writing circuit 211, driving circuit 212, and compensation circuit 213 described above include various types. The structures of the data writing circuit 211, driving circuit 212, and compensation circuit 213 are illustrated below with reference to the accompanying drawings, but the structures of the data writing circuit 211, driving circuit 212, and compensation circuit 213 are not limited to these.

[0158] In some examples, as shown in Figures 10, 12, and 15, the data writing circuit 211 includes a first transistor T1, the driving circuit 212 includes a second transistor T2, and the compensation circuit 213 includes a third transistor T3. Both the first transistor T1 and the third transistor T3 are metal-oxide-slim transistors.

[0159] The control electrode of the first transistor T1 is electrically connected to the first shift register 111, the first electrode of the first transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, i.e., the first node N1.

[0160] For example, when the level of the first scan signal transmitted from the first shift register 111 to the first transistor T1 through the first scan signal terminal SC1 is high, the first transistor T1 can be turned on under the control of the first scan signal to receive and transmit data signals to the first node N1.

[0161] The control electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, i.e., the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3, i.e., the second node N2.

[0162] For example, when the potential of the third node N3 is an effective potential, the second transistor T2 can be turned on under the control of the potential of the third node N3, transmitting the electrical signal, such as a data signal, from the first node N1 to the second node N2. Here, the effective potential of the third node N3 is, for example, a low level.

[0163] The control electrode of the third transistor T3 is electrically connected to the second shift register 112.

[0164] For example, when the level of the second scan signal transmitted from the second shift register 112 to the third transistor T3 through the second scan signal terminal SC2 is high, the third transistor T3 can be turned on under the control of the second scan signal to transmit the electrical signal, such as the data signal, at the second node N2 to the third node N3.

[0165] The above configuration helps to simplify the structure of the data writing circuit 211, the driving circuit 212 and the compensation circuit 213, and reduces the structural complexity and manufacturing difficulty of the display panel 10.

[0166] For example, the second transistor T2 can be a metal oxide thin film transistor, or the second transistor T2 can be a low-temperature polycrystalline silicon thin film transistor.

[0167] In the case where the second transistor T2 is a low-temperature polycrystalline silicon thin-film transistor, it can achieve a higher electron mobility. In the case where the second transistor T2 is a metal-oxide-semiconductor thin-film transistor, the crystallization uniformity of the active layer of the second transistor T2 can be improved, thereby enhancing the uniformity of the characteristics of the second transistor T2.

[0168] In some embodiments, as shown in Figures 10 and 12, the pixel circuit 21 may further include a first reset circuit 214. The first reset circuit 214 is electrically connected to the driving circuit 212, the compensation circuit 213, and the first initial signal terminal Vinit1. Specifically, the first reset circuit 214 is electrically connected to the second node N2, which is the junction point of the electrical connections of the driving circuit 212 and the compensation circuit 213.

[0169] For example, the transistor included in the first reset circuit 214 is a metal-oxide-slim thin-film transistor. Accordingly, the transistor included in the first reset circuit 214 is an N-type transistor. This reduces leakage current in the first reset circuit 214, making it easier to maintain the potential of the second node N2.

[0170] In some examples, since the transistors included in the first reset circuit 214 and the data writing circuit 211 are both metal-oxide-slim transistors, both of which can be turned on under the control of a high-level electrical signal, the first scan signal received by the data writing circuit 211 can be multiplexed to the first reset circuit 214. As shown in Figures 13 and 14, the first shift register 111 included in the display panel 10 is also electrically connected to the first reset circuit 214 of each pixel circuit 21 in a row of pixel circuits 21. Furthermore, the first shift register 111 is also configured to provide the first scan signal to the first reset circuit 214 of the pixel circuit 21 connected to the first shift register 111. This helps to reduce the load on each first shift register 111 and allows for more flexible control of the display panel 10 for image display.

[0171] For example, the first shift register 111 and the first reset circuit 214 of each pixel circuit 21 in the aforementioned row of pixel circuits 21 can be electrically connected via the first scan signal terminal SC1. Each first reset circuit 214 can receive a first scan signal via the first scan signal terminal SC1. The first reset circuit 214 is configured to turn on in response to the first scan signal, transmitting the first initial signal from the first initial signal terminal Vinit1 to the drive circuit 212 and the compensation circuit 213, specifically the second node N2 and the third node N3.

[0172] For example, the pixel circuits 21 to which the first reset circuit 214 and the data writing circuit 211 connected to the same first shift register 111 belong are located in different rows. That is, the same first shift register 111 is not simultaneously electrically connected to the first reset circuit 214 and the data writing circuit 211 of the same pixel circuit 21. For example, referring to Figures 10, 12, 13 and 14, the same first shift register 111 is electrically connected to the data writing circuits 211 of each pixel circuit 21 in the nth row of pixel circuits 21 through the first scan signal terminal SC1(n), and is electrically connected to the first reset circuits 214 of each pixel circuit 21 in the nith row of pixel circuits 21 through the first scan signal terminal SC1(ni).

[0173] Optionally, when i=1, the same first shift register 111 is electrically connected to the data writing circuit 211 of each pixel circuit 21 in the nth row of pixel circuits 21 via the first scan signal terminal SC1(n), and electrically connected to the first reset circuit 214 of each pixel circuit 21 in the (n-1)th row of pixel circuits 21 via the first scan signal terminal SC1(n-1). Correspondingly, the pixel circuit 21 to which the first reset circuit 214 connected to the same first shift register 111 belongs is located in the row preceding the pixel circuit 21 to which the data writing circuit 211 connected to it belongs. That is, the same first shift register 111 provides the first scan signal for two adjacent rows of pixel circuits 21. This facilitates cooperation with other shift registers to drive the pixel circuits 21, and also simplifies the design of the driving timing for the pixel circuits 21.

[0174] Of course, in addition to the first shift register 111 being electrically connected to the data writing circuit 211 of each pixel circuit 21 in the nth row pixel circuit 21, it can also be electrically connected to the first reset circuit 214 of each pixel circuit 21 in the (n-3)th or (n-5)th row pixel circuit 21. This embodiment is not limited to this and can be selected and configured according to actual needs. Where n and i are both integers, n≠i, i≠0, and n>1.

[0175] Taking the above-mentioned second shift register 112 as an example, which is electrically connected to the two adjacent rows of pixel circuits 21.

[0176] For example, as shown in FIG13, when the display panel 10 is a small to medium-sized display panel, adjacent rows of pixel circuits 21 are electrically connected to, for example, two first shift registers 111 and one second shift register 112. Analogous to FIG6, adjacent rows of pixel circuits 21 can also be considered to be electrically connected to one second shift register GN-GOA and two third shift registers Rst-NGOA. However, in the embodiment shown in FIG6, adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA, one second shift register GN-GOA, and one third shift register Rst-NGOA. This means that, compared with Figure 6, in this embodiment of the application, the four first shift registers GP-GOA electrically connected to the data writing circuit 211 are omitted, the number of shift registers used to drive the data writing circuit 211, compensation circuit 213 and first reset circuit 214 in the pixel circuit 21 is reduced by three, and correspondingly, the number of gate driving circuits used to drive the data writing circuit 211, compensation circuit 213 and first reset circuit 214 in the pixel circuit 21 is reduced by two.

[0177] For example, as shown in FIG14, when the display panel 10 is a large-sized display panel, adjacent rows of pixel circuits 21 are electrically connected to, for example, four first shift registers 111 and two second shift registers 112. Analogous to FIG7, adjacent rows of pixel circuits 21 can also be considered electrically connected to two second shift registers GN-GOA and two third shift registers Rst-NGOA. In the embodiment shown in FIG7, adjacent rows of pixel circuits 21 are electrically connected to four first shift registers GP-GOA, two second shift registers GN-GOA, and two third shift registers Rst-NGOA. That is, in this embodiment, the number of shift registers used to drive the data writing circuit 211, compensation circuit 213, and first reset circuit 214 in the pixel circuit 21 is reduced by two; correspondingly, the number of gate driving circuits used to drive the data writing circuit 211, compensation circuit 213, and first reset circuit 214 in the pixel circuit 21 is reduced by two.

[0178] Therefore, the first reset circuit 214 and the first shift register 111 are configured in the above manner. On the one hand, this helps to reduce the leakage current of the first reset circuit 214 and maintain the potential of the corresponding node in the pixel circuit 21. On the other hand, regardless of whether the display panel 10 is a large-size display panel or a medium-size display panel, the number of shift registers electrically connected to the pixel circuit 21 can be further reduced. Correspondingly, the number of gate driving circuits electrically connected to the pixel circuit 21 can be further reduced. This can further reduce the power consumption caused by the large number of gate driving circuits, further reduce the space occupied by the gate driving circuits, reduce the bezel size of the display panel 10, and facilitate the narrow bezel design of the display panel 10.

[0179] In some examples, as shown in Figures 10 and 12, the first reset circuit 214 described above includes, for example, a fourth transistor T4, which is a metal-oxide-slim film transistor.

[0180] Specifically, the control terminal of the fourth transistor T4 is electrically connected to the first shift register 111, the first terminal of the fourth transistor T4 is electrically connected to the first initial signal terminal Vinit1, and the second terminal of the fourth transistor T4 is electrically connected to the driving circuit 212 and the compensation circuit 213. Correspondingly, the second terminal of the fourth transistor T4 is electrically connected to the second node N2.

[0181] For example, when the level of the first scan signal transmitted from the first shift register 111 to the fourth transistor T4 via the first scan signal terminal SC1(n-1) is high, the fourth transistor T4 can be turned on under the control of the first scan signal to receive and transmit the first initial signal to the second node N2. The first initial signal can also be transmitted to the third node N3 via the compensation circuit 213 to reset the third node N3.

[0182] The above configuration helps to simplify the structure of the first reset circuit 214 and reduce the structural complexity and manufacturing difficulty of the display panel 10.

[0183] It is understood that the display panel 10 and pixel circuit 21 may also include other circuit structures, which will be illustrated below with reference to the accompanying drawings.

[0184] In some embodiments, as shown in Figures 10 and 12, the pixel circuit 21 may further include: a light-emitting control circuit 215, an energy storage sub-circuit 216, and a second reset circuit 217. The light-emitting control circuit 215 is electrically connected to the first voltage signal terminal ELVDD, the driving circuit 212, and the light-emitting device 22. The point where the light-emitting control circuit 215 and the light-emitting device 22 are electrically connected is, for example, the fourth node N4. The energy storage sub-circuit 216 is electrically connected to the first voltage signal terminal ELVDD and the third node N3, and is used to maintain the potential of the third node N3. The second reset circuit 217 is electrically connected to the second initial signal terminal Vinit2 and the light-emitting device 22; specifically, the second reset circuit 217 is electrically connected to the second initial signal terminal Vinit2 and the fourth node N4.

[0185] In this case, as shown in Figures 11, 13, and 14, the display panel 10 may further include a third shift register 113 and a fourth shift register 114 located outside the display area AA. For example, there may be multiple third shift registers 113, with multiple third shift registers 113 located on the same side of the display area AA cascaded sequentially to form a third gate drive circuit 11c. For example, there may be multiple fourth shift registers 114, with multiple fourth shift registers 114 located on the same side of the display area AA cascaded sequentially to form a fourth gate drive circuit 11d. Both the third gate drive circuit 11c and the fourth gate drive circuit 11d are located in the border area BB.

[0186] Referring again to Figures 13 and 14, each third shift register 113 is electrically connected, for example, to the second reset circuit 217 of each pixel circuit 21 in at least one row of pixel circuits 21. Further, the third shift register 113 is configured to provide a third scan signal to the second reset circuit 217 of the pixel circuit 21 to which the third shift register 113 is connected. For example, each third shift register 113 can be electrically connected to the second reset circuit 217 of each pixel circuit 21 in one row of pixel circuits 21. This helps reduce the load on each third shift register 113 and allows for more flexible control of the display panel 10 for image display. As shown in Figures 13 and 14, each third shift register 113 can be electrically connected to the second reset circuit 217 of each pixel circuit 21 in two rows of pixel circuits 21. This helps reduce the number of third shift registers 113 and simplifies the structure of the third gate drive circuit 11c and the display panel 10. Here, the number of rows of pixel circuits 21 to which the third shift register 113 is connected can be selected and set according to actual needs.

[0187] For example, the third shift register 113 and the second reset circuit 217 of each pixel circuit 21 in at least one row of pixel circuits 21 can be electrically connected via the third scan signal terminal SC3. Each second reset circuit 217 can receive a third scan signal via the third scan signal terminal SC3. The second reset circuit 217 is configured to turn on in response to the third scan signal, transmitting a second initial signal from the second initial signal terminal Vinit2 to the light-emitting device 22.

[0188] Referring again to Figures 13 and 14, each fourth shift register 114 is electrically connected, for example, to the light-emitting control circuit 215 of each pixel circuit 21 in at least one row of pixel circuits 21. Further, the fourth shift register 114 is configured to provide a fourth scan signal to the light-emitting control circuit 215 of the pixel circuit connected to the fourth shift register 114. For example, each fourth shift register 114 can be electrically connected to the light-emitting control circuit 215 of each pixel circuit 21 in one row of pixel circuits 21. This helps reduce the load on each fourth shift register 114 and allows for more flexible control of the display panel 10 for image display. As shown in Figures 13 and 14, each fourth shift register 114 can be electrically connected to the light-emitting control circuit 215 of each pixel circuit 21 in two rows of pixel circuits 21. This helps reduce the number of fourth shift registers 114 and simplifies the structure of the fourth gate drive circuit 11d and the display panel 10. Here, the number of rows of pixel circuits 21 connected to the fourth shift register 114 can be selected and set according to actual needs.

[0189] For example, the fourth shift register 114 and the light-emitting control circuit 215 of each pixel circuit 21 in at least one row of pixel circuits 21 can be electrically connected via the fourth scan signal terminal SC4. Each light-emitting control circuit 215 can receive a fourth scan signal via the fourth scan signal terminal SC4. The light-emitting control circuit 215 is configured to turn on in response to the fourth scan signal, connecting the path between the first voltage signal terminal ELVDD and the light-emitting device 22.

[0190] Here, the data writing circuit 211 and the second reset circuit 217 are connected to different shift registers, so that the conduction status of the data writing circuit 211 and the second reset circuit 217 can be controlled separately. This allows the conduction frequency of the second reset circuit 217 to be increased while meeting the control requirements of the data writing circuit 211, which is beneficial for achieving flicker-free frame rate switching in a higher frame rate range, such as 90Hz-120Hz.

[0191] It is understood that, in some embodiments, as shown in FIG10, the pixel circuit 21 may be composed of the aforementioned data writing circuit 211, driving circuit 212, compensation circuit 213, first reset circuit 214, light emission control circuit 215, energy storage sub-circuit 216, and second reset circuit 217.

[0192] In other embodiments, the pixel circuit 21 may also be composed of other circuits. For example, as shown in FIG15, the pixel circuit 21 may be composed of the aforementioned data writing circuit 211, driving circuit 212, compensation circuit 213, light emission control circuit 215, energy storage sub-circuit 216, second reset circuit 217, and third reset circuit 218. As also shown in FIG12, the pixel circuit 21 may be composed of the aforementioned data writing circuit 211, driving circuit 212, compensation circuit 213, first reset circuit 214, light emission control circuit 215, energy storage sub-circuit 216, second reset circuit 217, and third reset circuit 218.

[0193] The third reset circuit 218 is illustrated below with reference to the accompanying drawings. In some examples, as shown in Figures 12 and 15, the third reset circuit 218 is electrically connected to the third initial signal terminal Vinit3 and the drive circuit 212. Specifically, the third reset circuit 218 is electrically connected to the third initial signal terminal Vinit3 and the second node N2.

[0194] Optionally, the third reset circuit 218 may also be electrically connected to the aforementioned third shift register 113.

[0195] Referring to Figures 12 and 13, each third shift register 113 is electrically connected, for example, to the third reset circuit 218 of each pixel circuit 21 in at least one row of pixel circuits 21. Further, the third shift register 113 is configured to provide a third scan signal to the third reset circuit 218 of the pixel circuit 21 to which the third shift register 113 is connected.

[0196] For example, the third shift register 113 and the third reset circuit 218 of each pixel circuit 21 in at least one row of pixel circuits 21 can be electrically connected via the third scan signal terminal SC3. Each third reset circuit 218 can receive a third scan signal via the third scan signal terminal SC3. The third reset circuit 218 is configured to turn on in response to the third scan signal, transmitting the third initial signal from the third initial signal terminal Vinit3 to the drive circuit 212 and the compensation circuit 213. Of course, the third reset circuit 218 can also be electrically connected to the third initial signal terminal Vinit3 and the first node N1, and can transmit the third initial signal to the first node N1; this embodiment of the application does not limit this.

[0197] Here, when the pixel circuit 21 includes both a second reset circuit 217 and a third reset circuit 218, each third shift register 113 is electrically connected to both the second reset circuit 217 and the third reset circuit 218 in the same pixel circuit 21.

[0198] By setting up a third reset circuit 218, the voltage difference between the output of the third reset circuit 218 and the third node N3 can be adjusted using a third initial signal. The output of the third reset circuit 218 is, for example, the second node N2, which puts the driving circuit 212 in a biased state, thus improving the problem of low frame rate flicker when the display panel 10 displays a low-brightness image. In addition, by using the same third shift register 113 to synchronously drive the second reset circuit 217 and the third reset circuit 218 of each pixel circuit 21 in at least one row of pixel circuits 21, it is possible to avoid increasing the number of shift registers and avoid increasing power consumption and bezel size.

[0199] The relative positional relationships between the aforementioned third shift register 113, fourth shift register 114, pixel circuit 21, first shift register 111, and second shift register 112 can be varied and can be selected and set according to actual needs. A schematic explanation is provided below with reference to the accompanying drawings.

[0200] In some embodiments, as shown in Figures 13, 14, 16, and 17, at least one of the third shift register 113 and the fourth shift register 114 is located on one side outside the display area AA. Alternatively, the third shift register 113 may be located on one side outside the display area AA, and / or the fourth shift register 114 may be located on one side outside the display area AA.

[0201] Optionally, the third shift register 113 is located on one side outside the display area AA, such as the left side, right side, top side, or bottom side in Figure 13, and the fourth shift register 114 is located on one side outside the display area, such as the right side, left side, top side, or bottom side in Figure 13. Alternatively, the third shift register 113 is located on both sides outside the display area AA, such as the left and right sides in Figure 14, and the fourth shift register 114 is located on both sides outside the display area AA, such as the left and right sides in Figure 14.

[0202] For example, the aforementioned at least one row of pixel circuits 21 can be electrically connected to a third shift register 113, which is located on one side outside the display area AA. The third shift register 113 is driven on one side. Correspondingly, the multi-row pixel circuit P in the display panel 10 is electrically connected to a third gate driving circuit 11c, which is located on one side outside the display area AA. Alternatively, the aforementioned at least one row of pixel circuits 21 can also be electrically connected to two third shift registers 113, which are located on opposite sides outside the display area AA. The third shift registers 113 are driven on both sides. Correspondingly, the multi-row pixel circuit P in the display panel 10 is electrically connected to two third gate driving circuits 11c, which are located on opposite sides outside the display area AA.

[0203] For example, the aforementioned at least one row of pixel circuits 21 can be electrically connected to a fourth shift register 114, which is located on one side outside the display area AA. The fourth shift register 114 is driven on one side. Correspondingly, the multi-row pixel circuit P in the display panel 10 is electrically connected to a fourth gate driving circuit 11d, which is located on one side outside the display area AA. Alternatively, the aforementioned at least one row of pixel circuits 21 can also be electrically connected to two fourth shift registers 114, which are located on opposite sides outside the display area AA. The fourth shift registers 114 are driven on both sides. Correspondingly, the multi-row pixel circuit P in the display panel 10 is electrically connected to two fourth gate driving circuits 11d, which are located on opposite sides outside the display area AA.

[0204] When the third shift register 113 and / or the fourth shift register 114 are located on one side outside the display area AA, it is beneficial to reduce the number of gate drive circuits in the display panel 10, thereby reducing the power consumption and bezel size of the display panel 10. When the third shift register 113 and / or the fourth shift register 114 are located on both sides outside the display area AA, it is beneficial to reduce the load on the corresponding gate drive circuits.

[0205] In some examples, the display panel 10 is, for example, a small to medium-sized display panel. As shown in Figures 13 and 16, the aforementioned at least one row of pixel circuits 21 can be electrically connected to a third shift register 113 and a fourth shift register 114. Along the row direction X of the multi-row pixel circuits 21, the third shift register 113 and the fourth shift register 114 are located on both sides outside the display area AA, respectively.

[0206] Referring again to Figures 13 and 16, correspondingly, along the row direction X of the multi-row pixel circuit 21, the third gate driving circuit 11c and the fourth gate driving circuit 11d are located on both sides outside the display area AA, respectively.

[0207] In this way, along the row direction X of the multi-row pixel circuit 21, the number of shift registers and their respective gate drive circuits on both sides of the display area AA can be balanced, so that the width of the partial border area BB on both sides of the display area AA is the same or approximately the same, and it is beneficial to the wiring arrangement in the border area BB.

[0208] Further, as shown in Figures 13 and 16, along the row direction X of the multi-row pixel circuit 21, the third shift register 113 is located, for example, on one side outside the display area AA, along with the second shift register 112, and the fourth shift register 114 is located, for example, on the other side outside the display area AA, along with the first shift register 111. Specifically, the third shift register 113 is further away from the pixel circuit 21 than the second shift register 112 located on the same side. And / or, the fourth shift register 114 is further away from the pixel circuit 21 than the first shift register 111 located on the same side. That is, when the third shift register 113 and the second shift register 112 are located on the same side outside the display area AA, the third shift register 113 is located on the side of the second shift register 112 that is further away from the display area AA. When the fourth shift register 114 and the first shift register 111 are located on the same side outside the display area AA, the fourth shift register 114 is located on the side of the first shift register 111 that is further away from the display area AA.

[0209] This helps to reduce the voltage drop generated during the transmission of the first scan signal output by the first shift register 111 and the second scan signal output by the second shift register 112 to the pixel circuit 21, so that the data writing circuit 211 and the compensation circuit 213 can be fully turned on in the corresponding working stages, thereby improving the speed of data signal writing to the display panel 10 and improving the accuracy of the data voltage written to the third node N3.

[0210] Of course, the positions of the third shift register 113 and the fourth shift register 114 can be interchanged, and this application embodiment does not limit this.

[0211] In other examples, the display panel 10 may be a large-sized display panel. As shown in Figures 14 and 17, the aforementioned at least one row of pixel circuits 21 can be electrically connected to two third shift registers 113 and two fourth shift registers 114. Along the row direction X of the multi-row pixel circuits 21, the two third shift registers 113 are located on both sides outside the display area AA, and the two fourth shift registers 114 are located on both sides outside the display area AA. Both the third shift registers 113 and the fourth shift registers 114 are configured using a bilateral driving method.

[0212] Referring again to Figures 14 and 17, the fourth shift register 114 is further away from the display area AA than the third shift register 113, which is located on the same side. That is, of the third shift register 113 and the fourth shift register 114, which are located on the same side, the fourth shift register 114 is located on the side of the third shift register that is further away from the display area AA.

[0213] Of course, the positions of the third shift register 113 and the fourth shift register 114 located on the same side can be interchanged, and this application embodiment does not limit this.

[0214] Here, comparing Figures 13 and 6, or Figures 16 and 6, when the display panel 10 is a small to medium-sized display panel, the number of shift registers connected to every two rows of pixel circuits 21 is reduced, for example, from eight to five. Comparing Figures 14 and 7, or Figures 17 and 7, when the display panel 10 is a large-sized display panel, the number of shift registers connected to every two rows of pixel circuits 21 is reduced, for example, from twelve to ten. Testing shows that the bezel size gain of the display panel 10 is greater than or equal to 150 μm, and the power consumption gain is greater than or equal to 20 mW.

[0215] The structures of the above-mentioned light-emitting control circuit 215, energy storage sub-circuit 216, second reset circuit 217, and third reset circuit 218 include various types. The structures of the light-emitting control circuit 215, energy storage sub-circuit 216, second reset circuit 217, and third reset circuit 218 are illustrated below with reference to the accompanying drawings. However, the structures of the light-emitting control circuit 215, energy storage sub-circuit 216, second reset circuit 217, and third reset circuit 218 are not limited to these.

[0216] In some examples, as shown in Figures 12 and 15, the light-emitting control circuit 215 includes a fifth transistor T5 and a sixth transistor T6, the energy storage sub-circuit 216 includes a storage capacitor Cst, the second reset circuit 217 includes a seventh transistor T7, and the third reset circuit 218 includes an eighth transistor T8.

[0217] The control electrode of the fifth transistor T5 is electrically connected to the fourth shift register 114, the first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal ELVDD, and the second electrode of the fifth transistor T5 is electrically connected to the driving circuit 212. Specifically, the second electrode of the fifth transistor T5 is electrically connected to the first node N1. The control electrode of the sixth transistor T6 is electrically connected to the fourth shift register 114, the first electrode of the sixth transistor T6 is electrically connected to the driving circuit 212, and the second electrode of the sixth transistor T6 is electrically connected to the light-emitting device 22. Specifically, the first electrode of the sixth transistor T6 is electrically connected to the second node N2.

[0218] For example, when the fourth scan signal transmitted from the fourth shift register 114 to the fifth transistor T5 and the sixth transistor T6 via the fourth scan signal terminal SC4 is at an effective operating level, the fifth transistor T5 and the sixth transistor T6 can be turned on under the control of the fourth scan signal, connecting the path between the first voltage signal terminal ELVDD and the light-emitting device 22. The effective operating circuit here is, for example, at a low level.

[0219] One end of the aforementioned storage capacitor Cst is electrically connected to the first voltage signal terminal ELVDD, and the other end is electrically connected to the third node N3. The storage capacitor Cst is used to maintain the potential of the third node N3.

[0220] The control electrode of the seventh transistor T7 is electrically connected to the third shift register 113, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the light-emitting device 22.

[0221] For example, when the third scan signal transmitted from the third shift register 113 to the seventh transistor T7 via the third scan signal terminal SC3 is at an effective operating level, the seventh transistor T7 can be turned on under the control of the third scan signal, receiving and transmitting the second initial signal to the fourth node N4 to reset the anode of the light-emitting device 22. The effective operating circuit here is, for example, at a low level.

[0222] The control terminal of the aforementioned eighth transistor T8 is electrically connected to the third shift register 113, the first terminal of the eighth transistor T8 is electrically connected to the third initial signal terminal Vinit3, and the second terminal of the eighth transistor T8 is electrically connected to the drive circuit 212. Specifically, the second terminal of the eighth transistor T8 is electrically connected to either the second node N2 or the first node N1.

[0223] For example, when the third scan signal transmitted from the third shift register 113 to the eighth transistor T8 via the third scan signal terminal SC3 is at a valid operating level, the eighth transistor T8 can be turned on under the control of the third scan signal to receive and transmit the third initial signal to the second node N2 or the first node N1. The valid operating level here is, for example, low.

[0224] The above configuration helps to simplify the structure of the light-emitting control circuit 215, the energy storage sub-circuit 216, the second reset circuit 217 and the third reset circuit 218, and reduces the structural complexity and manufacturing difficulty of the display panel 10.

[0225] The types of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 mentioned above include various types, and can be selected and set according to actual needs.

[0226] Optionally, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all low-temperature polycrystalline silicon thin-film transistors. This allows the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 to all have high electron mobility, improving the electrical performance of the pixel circuit 21. Of course, the seventh transistor T7 and the eighth transistor T8 can also be metal-oxide-semiconductor thin-film transistors.

[0227] It is understood that during the display process of the display panel 10, at least two refresh rate frames can be included. For example, the display panel 10 can include a first refresh rate and a second refresh rate, and the first refresh rate is greater than the second refresh rate. At the first refresh rate, a frame may only include a refresh frame period, while at the second refresh rate, a frame may include a refresh frame period and a hold frame period. The display panel 10 can include multiple refresh rate frames, and the relationship between different refresh rate frames can be controlled by adjusting the duration of the hold frame period. This application embodiment does not specifically limit this.

[0228] For example, the display panel 10 includes a first refresh rate. Figure 18 illustrates a timing diagram that can be applied to sub-pixels with various structures. This embodiment of the application uses the timing diagram applied to the sub-pixels shown in Figure 12 as an example for explanation. Below, taking the nth row pixel circuit 21 as an example (n is a positive integer), the operation of the pixel circuit 21 will be schematically explained in conjunction with Figures 18 and 12. In Figure 18, SC1(n-1) represents the first scan signal received by the data writing circuit 211 of the (n-1)th row pixel circuit 21, SC1(n) represents the first scan signal received by the data writing circuit 211 of the nth row pixel circuit 21, SC1(n+1) represents the first scan signal received by the data writing circuit 211 of the (n+1)th row pixel circuit 21, SC2(n) represents the second scan signal received by the compensation circuit 213 of the nth row pixel circuit 21, SC3(n) represents the third scan signal received by the second reset circuit 217 of the nth row pixel circuit 21, and SC4(n) represents the fourth scan signal received by the light emission control circuit 215 of the nth row pixel circuit 21.

[0229] As shown in Figure 18, the working process of the pixel circuit 21 includes: a non-light-emitting stage S1 and a light-emitting stage S2. The non-light-emitting stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3.

[0230] During the non-light-emitting phase S1, the level of the fourth scan signal is high. The fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0231] During the first reset stage t1 of the non-light-emitting stage S1, the level of the second scan signal transmitted to the nth row pixel circuit 21 is high, and the level of the first scan signal transmitted to the (n-1)th row pixel circuit 21 is synchronously transmitted to the first reset circuit 214 of the nth row pixel circuit 21, and the level is high. The third transistor T3 and the fourth transistor T4 are both turned on, and the first initial signal from the first initial signal terminal Vinit1 is transmitted sequentially through the fourth transistor T4, the second node N2, and the third transistor T3 to the third node N3, resetting the third node N3.

[0232] For information on data writing in the non-light-emitting stage S1 and compensation stage t2, please refer to the relevant explanations above, which will not be repeated here.

[0233] During the second reset phase t3 of the non-light-emitting phase S1, the level of the third scan signal is low. Both the seventh transistor T7 and the eighth transistor T8 are turned on. The second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 via the seventh transistor T7, resetting the fourth node N4, which is the anode of the light-emitting device 22. The third initial signal from the third initial signal terminal Vinit3 is transmitted to the second node N2 via the eighth transistor T8, resetting the second node N2. Furthermore, the third initial signal is also used to adjust the voltage difference between the third node N3 and the second node N2, mitigating or offsetting the threshold voltage drift of the second transistor T2, adjusting the bias state of the second transistor T2, and improving the display uniformity of the display panel 10.

[0234] For information on the light-emitting stage S2, please refer to the relevant explanation above; it will not be repeated here.

[0235] As shown in the timing diagram in Figure 18, during the conduction of the third transistor T3 of the nth row pixel circuit 21, the first transistors T1 of the (n-1), nth, and n+1th row pixel circuits 21 can all be turned on for data writing and threshold voltage compensation. Correspondingly, each second shift register 112 can be electrically connected to the third transistor T3 of all three rows of pixel circuits 21, i.e., the compensation circuit 213.

[0236] For example, the display panel 10 includes a first refresh rate and a second refresh rate. Figure 19 also illustrates a timing diagram corresponding to the sub-pixels shown in Figure 15. Below, taking the nth row pixel circuit 21 as an example, where n is a positive integer, the operation of the pixel circuit 21 is illustrated in conjunction with Figures 19 and 15. In Figure 19, SC1(n) represents the first scan signal received by the nth row pixel circuit 21, SC1(n+1) represents the first scan signal received by the (n+1)th row pixel circuit 21, SC2(n) represents the second scan signal received by the nth row pixel circuit 21, SC3(n) represents the third scan signal received by the nth row pixel circuit 21, SC4(n) represents the fourth scan signal received by the nth row pixel circuit 21, and Vinit3 represents the third initial signal received by the nth row pixel circuit 21.

[0237] As shown in Figure 19, the operation of the pixel circuit 21 includes a refresh frame period and a hold frame period. During the refresh frame period, the pixel circuit 21 operates in a non-light-emitting phase S1 and a light-emitting phase S2. The non-light-emitting phase S1 includes a first reset phase t1, a data writing and compensation phase t2, and a second reset phase t3. During the hold frame period, the pixel circuit 21 operates in a bias phase TK.

[0238] During the non-light-emitting phase S1, the level of the fourth scan signal is high. The fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0239] During the first reset phase t1 of the non-light-emitting phase S1, the level of the second scan signal is high, and the level of the third scan signal is low. Both the third transistor T3 and the eighth transistor T8 are turned on. The third initial signal from the third initial signal terminal Vinit3 is transmitted sequentially through the eighth transistor T8, the second node N2, and the third transistor T3 to the third node N3, resetting the third node N3. The seventh transistor T7 is turned on, and the second initial signal from the second initial signal terminal Vinit2 is transmitted through the seventh transistor T7 to the fourth node N3, resetting the anode of the light-emitting device 22.

[0240] For information on data writing in the non-light-emitting stage S1 and compensation stage t2, please refer to the relevant explanations above, which will not be repeated here.

[0241] During the second reset phase t3 of the non-light-emitting phase S1, the level of the third scan signal is low. Both the seventh transistor T7 and the eighth transistor T8 are turned on. The second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 via the seventh transistor T7, resetting the fourth node N4, which is the anode of the light-emitting device 22. The third initial signal from the third initial signal terminal Vinit3 is transmitted to the second node N2 via the eighth transistor T8, resetting the second node N2. Furthermore, the third initial signal is also used to adjust the voltage difference between the third node N3 and the second node N2, alleviating or offsetting the threshold voltage drift of the second transistor T2, adjusting the bias state of the second transistor T2, improving the problem of low frame rate flicker under low brightness, and improving the display uniformity of the display panel 10. In this example, the third initial signal is, for example, a frequency conversion voltage signal, and the voltage value of the third initial signal in the second reset phase t3 is greater than its voltage value in the first reset phase t1. Furthermore, the voltage value of the third initial signal in the first reset phase t1 is, for example, the same as the voltage value of the first initial signal in the first reset phase t1 shown in FIG18; the voltage value of the third initial signal in the second reset phase t3 is, for example, the same as the voltage value of the third initial signal in the second reset phase t3 shown in FIG18.

[0242] For information on the light-emitting stage S2, please refer to the relevant explanation above; it will not be repeated here.

[0243] During the bias phase TK, the control electrode of the second transistor T2, i.e., the third node N3, maintains the potential from the previous phase, such as the potential after data writing and threshold voltage compensation. The eighth transistor T8 is turned on, and the third initial signal with a higher voltage value is transmitted to the second node N2 through the eighth transistor T8, causing the second transistor T2 to be in a biased state.

[0244] As shown in the timing diagram in Figure 19, during the conduction of the third transistor T3 of the nth row pixel circuit 21, the first transistor T1 of both the nth and (n+1)th row pixel circuits 21 can be turned on for data writing and threshold voltage compensation. Correspondingly, each second shift register 112 can be electrically connected to the third transistor T3 of both rows of pixel circuits 21, i.e., the compensation circuit 213.

[0245] Some embodiments of this application also provide a display panel, the structure and arrangement of which include a plurality of pixel circuits are, for example, the same as the structure and arrangement of the plurality of pixel circuits 21 in the display panel provided in the above embodiments, as detailed in the relevant descriptions above, and will not be repeated here. The difference between this display panel and the display panel provided in the above embodiments lies, for example, in the arrangement of the partial circuit structure of the pixel circuit with the shift register. The differences will be illustrated below with reference to the accompanying drawings.

[0246] Figures 20, 21, 22, and 25 illustrate equivalent circuit diagrams of a sub-pixel, while Figures 23, 24, 26, and 27 illustrate partial structural diagrams of a display panel. Referring to Figures 20-27, the data writing circuit 211 and compensation circuit 213 in the same pixel circuit 21 are electrically connected to the first shift register 111 and the second shift register 112, respectively. In the structures shown in Figures 23, 24, 26, and 27, the first shift register 111 is electrically connected to the data writing circuit 211 and compensation circuit 213 of each pixel circuit 21 in a row of pixel circuits 21. That is, the data writing circuit 211 and compensation circuit 213 in the same pixel circuit 21 are all electrically connected to the first shift register 111. For example, the first shift register 111 is configured to provide a first scan signal to the data writing circuit 211 and compensation circuit 213 of the pixel circuit 21 connected to the first shift register 111.

[0247] That is, the data writing circuit 211 and the compensation circuit 213 in the same pixel circuit 21 can both be electrically connected to the first scan signal terminal SC1 and receive the first scan signal from the same first shift register 111. The data writing circuit 211 and the compensation circuit 213 are configured to be turned on in response to the first scan signal and transmit the data signal from the data signal terminal Data to the driving circuit 212.

[0248] It is understandable that, since the transistors included in the data writing circuit 211 and the compensation circuit 213 are all metal oxide thin film transistors, the first shift register 111 can be set in a single-sided driving manner in small and medium-sized display panels.

[0249] For example, the display panel 10 may be a small to medium-sized display panel. As shown in Figures 23 and 26, a row pixel circuit 21 may be electrically connected to a first shift register 111, which is located on the side outside the display area AA. Correspondingly, the data writing circuit 211 and the compensation circuit 213 in the multi-row pixel circuit P of the display panel 10 are electrically connected to a first gate driving circuit 11a, which is located on the side outside the display area AA.

[0250] In the embodiment shown in Figure 6, the data writing circuit 211 of each row of pixel circuits 21 is electrically connected to two first shift registers GP-GOA, and the compensation circuit 213 of every two rows of pixel circuits 21 is electrically connected to one second shift register GN-GOA. This means that, compared with Figure 6, in this embodiment of the application, the number of shift registers electrically connected to the data writing circuit 211 and the compensation circuit 213 of every two rows of pixel circuits 21 is reduced by three, and correspondingly, the number of gate driving circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by two.

[0251] Furthermore, in the embodiment shown in FIG9, the data writing circuit 211 of each row of pixel circuit 21 is electrically connected to two first shift registers GP-GOA, and the compensation circuit 213 of every two rows of pixel circuit 21 is electrically connected to two second shift registers GN-GOA. This means that, compared with FIG9, in the embodiment of this application, the number of shift registers electrically connected to the data writing circuit 211 and the compensation circuit 213 of every two rows of pixel circuit 21 is reduced by four, and correspondingly, the number of gate driving circuits used to drive the data writing circuit 211 and the compensation circuit 213 in the pixel circuit 21 is reduced by three.

[0252] For example, the display panel 10 may be a large-sized display panel. As shown in Figures 24 and 27, a row pixel circuit 21 may also be electrically connected to two first shift registers 111, which are located on both sides outside the display area AA. Correspondingly, the multi-row pixel circuit P in the display panel 10 is electrically connected to two first gate driving circuits 11a, which are also located on both sides outside the display area AA.

[0253] In the embodiment shown in Figure 7, the data writing circuit 211 of each row of pixel circuits 21 is electrically connected to two first shift registers GP-GOA, and the compensation circuit 213 of every two rows of pixel circuits 21 is electrically connected to two second shift registers GN-GOA. This means that, compared with Figure 7, in this embodiment, the number of shift registers electrically connected to the data writing circuit 211 and compensation circuit 213 of every two rows of pixel circuits 21 is reduced by two, and correspondingly, the number of gate driving circuits used to drive the data writing circuit 211 and compensation circuit 213 in the pixel circuit 21 is reduced by two.

[0254] Therefore, the display panel 10 provided in some embodiments of this application sets the transistors included in the data writing circuit 211 and the compensation circuit 213 to metal-oxide transistors, and sets a first shift register 111 so that the first shift register 111 is electrically connected to the data writing circuit 211 and the compensation circuit 213 in each pixel circuit 21 located in the same row. In this way, leakage current can be reduced by the data writing circuit 211 and the compensation circuit 213, the potential of the relevant nodes inside the pixel circuit 21 can be maintained, and the power consumption caused by leakage current can be reduced. Furthermore, by sharing the first shift register 111, the number of shift registers electrically connected to the pixel circuit 21 can be reduced, and the number of gate driving circuits can be reduced accordingly. Thus, while reducing the power consumption caused by a large number of gate driving circuits, the space occupied by the gate driving circuits can be reduced, the bezel size of the display panel 10 can be reduced, and the narrow bezel design of the display panel 10 can be easily realized.

[0255] In some embodiments, as shown in Figures 20-22, when the pixel circuit 21 includes a first reset circuit 214, the first reset circuit 214 and data writing circuit 211 of the pixel circuits 21 located in different rows are electrically connected to the first shift register 111. In the structures shown in Figures 23 and 24, the display panel 10 further includes a second shift register 112 located outside the display area AA, i.e., located in the border area BB. This second shift register 112 is electrically connected to the first reset circuit 214 of each pixel circuit 21 in at least one row of pixel circuits 21. Accordingly, the first reset circuit 214 and data writing circuit 211 of the pixel circuits 21 located in different rows are electrically connected to different shift registers.

[0256] Furthermore, the second shift register 112 is configured to provide the second scan signal to the first reset circuit 214 of the pixel circuit 21 connected to the second shift register 112. The first reset circuit 214 is configured to be turned on in response to the second scan signal, transmitting the first initial signal from the first initial signal terminal Vinit1 to the drive circuit 212 and the compensation circuit 213.

[0257] By electrically connecting the second shift register 112 to the first reset circuit 214, the load on the second shift register 112 can be reduced, allowing for more flexible control of the display panel 10 for screen display.

[0258] In this example, the connection relationship between the first reset circuit 214, the drive circuit 212, and the compensation circuit 213 can be varied and can be selected and set according to actual needs.

[0259] For example, as shown in Figure 22, the first reset circuit 214 is electrically connected to the second node N2. Correspondingly, the second terminal of the fourth transistor T4 included in the first reset circuit 214 is electrically connected to the second node N2. At this time, after the first reset circuit 214 is turned on in response to the second scan signal, the first initial signal is transmitted to the second node N2 and can be transmitted to the third node N3 via the compensation circuit 213 to reset the third node N3.

[0260] As shown in Figures 20 and 21, the first reset circuit 214 is electrically connected to the third node N3. Correspondingly, the second terminal of the fourth transistor T4 included in the first reset circuit 214 is electrically connected to the third node N3. At this time, after the first reset circuit 214 is turned on in response to the second scan signal, the first initial signal is transmitted to the third node N3 to reset it.

[0261] For example, as shown in Figures 20-22, when the data writing circuit 211 includes a first transistor T1, the driving circuit 212 includes a second transistor T2, and the compensation circuit 213 includes a third transistor T3, the connection method between the first transistor T1, the second transistor T2, and the third transistor T3 differs from some of the above embodiments in that the control terminals of both the first transistor T1 and the third transistor T3 are electrically connected to the first shift register 111. When the first reset circuit 214 includes a fourth transistor T4, the connection method of the fourth transistor T4 differs from some of the above embodiments in that the control terminal of the fourth transistor T4 is electrically connected to the second shift register 112. Other details can be found in the relevant descriptions above and will not be repeated here.

[0262] In some examples, as shown in Figures 23 and 24, the second shift register 112 is located on one side outside the display area AA.

[0263] For example, as shown in Figure 23, at least one row of pixel circuits 21 can be electrically connected to a second shift register 112, which can be located on one side outside the display area AA along the row direction X of the multi-row pixel circuits 21. Correspondingly, the first reset circuit 214 in the multi-row pixel circuit P in the display panel 10 is electrically connected to a second gate driving circuit 11b, which is located on one side outside the display area AA.

[0264] At this time, the second shift register 112 is set in a single-sided driving manner, and the display panel 10 is, for example, a small to medium-sized display panel.

[0265] This helps reduce the load on the second shift register 112 and allows for more flexible control of the display panel 10 for screen display.

[0266] For example, as shown in Figure 24, at least one row of pixel circuits 21 can be electrically connected to two second shift registers 112. Along the row direction X of the multi-row pixel circuits 21, the two second shift registers 112 are located on both sides outside the display area AA. Correspondingly, the multi-row pixel circuit P in the display panel 10 is electrically connected to two second gate driving circuits 11b, and the two second gate driving circuits 11b are located on both sides outside the display area AA.

[0267] At this time, the second shift register 112 is set in a dual-sided driving manner, and the display panel 10 is, for example, a large-size display panel.

[0268] This helps to reduce the voltage drop generated by the second scan signal output by the second shift register 112 during transmission to the pixel circuit 21, so that the first reset circuit 214 can be fully turned on in the corresponding working stage, thereby improving the writing speed of the first initial signal.

[0269] In some embodiments, as shown in FIG23, when the display panel 10 is a small to medium-sized display panel, a row of pixel circuits 21 can be electrically connected to a first shift register 111, and at least one row of pixel circuits 21 can be electrically connected to a second shift register 112. Along the row direction X of the multiple rows of pixel circuits 21, the first shift register 111 and the second shift register 112 are located on opposite sides outside the display area AA. Specifically, please refer to the description above regarding the relative positions of the first shift register 111, the second shift register 112, and the pixel circuits 21; this will not be repeated here.

[0270] In other embodiments, as shown in FIG24, when the display panel 10 is a large-sized display panel, a row of pixel circuits 21 can be electrically connected to two first shift registers 111, and at least one row of pixel circuits 21 is electrically connected to two second shift registers 112. Along the row direction X of the multiple rows of pixel circuits 21, the two first shift registers 111 are located on both sides outside the display area AA, and the two second shift registers 112 are located on both sides outside the display area AA. Correspondingly, each side outside the display area AA is provided with a first gate driving circuit 11a including the first shift register 111 and a second gate driving circuit 11b including the second shift register 112.

[0271] For example, continuing to refer to Figure 24, the second shift register 112 is closer to the display area AA than the first shift register 111 located on the same side. That is, between the first shift register 111 and the second shift register 112 located on the same side of the multi-row pixel circuit P, the first shift register 111 is farther away from the display area AA. Correspondingly, the two second gate drive circuits 11b are located between the two first gate drive circuits 11a.

[0272] In this way, along the row direction X of the multi-row pixel circuit 21, it is beneficial to balance the number of shift registers and gate drive circuits on both sides of the display area AA, so that the border size on both sides of the display area AA is approximately equal.

[0273] In some embodiments, referring to Figures 21-24, when the pixel circuit 21 further includes a light-emitting control circuit 215, a second reset circuit 217, and a third reset circuit 218, and also includes a first reset circuit 214, the display panel 10 further includes a third shift register 113 and a fourth shift register 114. The connection relationship and relative position relationship between the third shift register 113 and the fourth shift register 114 and the pixel circuit 21 are the same as those shown in some embodiments above, for example, Figure 12. As shown in Figure 25, when the display panel 10 includes the light-emitting control circuit 215, the second reset circuit 217, and the third reset circuit 218, but does not include the first reset circuit 214, as shown in Figures 26 and 27, the display panel 10 further includes a third shift register 113 and a fourth shift register 114. The connection relationship and relative position relationship between the third shift register 113 and the fourth shift register 114 and the pixel circuit 21 are the same as those shown in some embodiments above, for example, Figure 15. For details, please refer to the above description; further details will not be repeated here.

[0274] Specifically, for the third reset circuit 218, as shown in Figure 21, the third reset circuit 218 can be electrically connected to the first node N1, and correspondingly, the second terminal of the eighth transistor T8 in the third reset circuit 218 is electrically connected to the first node N1. Alternatively, as shown in Figures 22 and 25, the third reset circuit 218 can be electrically connected to the second node N2, and correspondingly, the second terminal of the eighth transistor T8 in the third reset circuit 218 is electrically connected to the second node N2.

[0275] Figure 28 illustrates a timing diagram that can be applied to sub-pixels with various structures. This embodiment uses the application of this timing diagram to the sub-pixels shown in Figure 20 as an example for explanation. Below, taking the nth row pixel circuit 21 as an example (n is a positive integer), the operation of pixel circuit 21 is illustrated in conjunction with Figures 28 and 20. In Figure 28, SC1(n) represents the first scan signal received by the nth row pixel circuit 21, SC1(n+1) represents the first scan signal received by the (n+1)th row pixel circuit 21, SC2(n) represents the second scan signal received by the nth row pixel circuit 21, SC3(n) represents the third scan signal received by the nth row pixel circuit 21, and SC4(n) represents the fourth scan signal received by the nth row pixel circuit 21.

[0276] As shown in Figure 28, the working process of the pixel circuit 21 includes: a non-light-emitting stage S1 and a light-emitting stage S2. The non-light-emitting stage S1 includes a first reset stage t1, a data writing and compensation stage t2, and a second reset stage t3.

[0277] During the non-light-emitting phase S1, the level of the fourth scan signal is high. The fifth transistor T5 and the sixth transistor T6 are in the off state, and the light-emitting device 22 does not emit light.

[0278] During the first reset phase t1 of the non-light-emitting phase S1, the level of the second scan signal is high. All fourth transistors T4 are turned on, and the first initial signal from the first initial signal terminal Vinit1 is transmitted to the first node N1 via the fourth transistor T4 to reset the first node N1.

[0279] During the data writing and compensation phase t2 of the non-light-emitting phase S1, the level of the first scan signal is high. Both the first transistor T1 and the third transistor T3 are turned on. The data signal from the data signal terminal Data is sequentially transmitted through the first transistor T1, the first node N1, the second transistor T2, the second node N2, and the third transistor T3 to the third node N3, realizing the writing of the data signal and compensation for the threshold voltage of the second transistor T2. During this period, the storage capacitor Cst is also charged to maintain the potential of the third node N3.

[0280] During the second reset phase t3 of the non-light-emitting phase S1, the level of the third scan signal is low. Both the seventh transistor T7 and the eighth transistor T8 are turned on. The second initial signal from the second initial signal terminal Vinit2 is transmitted to the fourth node N4 via the seventh transistor T7, resetting the fourth node N4, which is the anode of the light-emitting device 22. The third initial signal from the third initial signal terminal Vinit3 is transmitted to the first node N1 via the eighth transistor T8, resetting the first node N1. Furthermore, the third initial signal is also used to adjust the voltage difference between the third node N3 and the first node N1, mitigating or offsetting the threshold voltage drift of the second transistor T2, adjusting the bias state of the second transistor T2, and improving the display uniformity of the display panel 10.

[0281] For information on the light-emitting stage S2, please refer to the relevant explanation above; it will not be repeated here.

[0282] Based on the timing diagram shown in Figure 28, it can be seen that before the seventh transistor T7 and the eighth transistor T8 of the nth row pixel circuit 21 are turned on, the first transistor T1 and the third transistor T3 of the nth row pixel circuit 21, and the first transistor T1 and the third transistor T3 of the (n+1)th row pixel circuit 21 are turned on in a time-division manner to perform data writing and threshold voltage compensation. Accordingly, each third shift register 113 can be electrically connected to the seventh transistor T7 and the eighth transistor T8 of the two rows of pixel circuits 21, that is, the second reset circuit 217 and the third reset circuit 218.

[0283] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a border area, the border area being located on at least two sides outside the display area; the display panel includes: A multi-row pixel circuit is located within the display area; each row pixel circuit includes a data writing circuit, a driving circuit, and a compensation circuit. The data writing circuit is electrically connected to the driving circuit and a data signal terminal, and the driving circuit is electrically connected to the compensation circuit. The transistors included in the data writing circuit and the compensation circuit are all metal-oxide-slim thin-film transistors. A first shift register is located in the border area; the first shift register is electrically connected to the data writing circuit of a row of pixel circuits; the first shift register is configured to provide a first scan signal to the data writing circuit of the pixel circuit connected to the first shift register; the data writing circuit is configured to be turned on in response to the first scan signal, and transmit the data signal from the data signal terminal to the compensation circuit; A second shift register is located in the border area; the second shift register is electrically connected to a compensation circuit of at least one row of pixel circuits; the second shift register is configured to provide a second scan signal to the compensation circuit of the pixel circuit connected to the second shift register; the compensation circuit is configured to be turned on in response to the second scan signal to transmit the data signal to the driving circuit.

2. The display panel according to claim 1, characterized in that, The first shift register is located on one side outside the display area, and / or the second shift register is located on one side outside the display area.

3. The display panel according to claim 2, characterized in that, A row of pixel circuits is electrically connected to a first shift register, and a second shift register is electrically connected to at least one row of pixel circuits; Along the row direction of the multi-row pixel circuit, the first shift register and the second shift register are located on both sides outside the display area.

4. The display panel according to claim 2, characterized in that, One row of pixel circuits is electrically connected to two of the first shift registers, and at least one row of pixel circuits is electrically connected to two of the second shift registers; Along the row direction of the multi-row pixel circuit, the two first shift registers are located on both sides outside the display area, and the two second shift registers are located on both sides outside the display area.

5. The display panel according to any one of claims 1-4, characterized in that, The data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor; both the first transistor and the third transistor are metal oxide thin-film transistors. The control electrode of the first transistor is electrically connected to the first shift register, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; The control electrode of the third transistor is electrically connected to the second shift register.

6. The display panel according to any one of claims 1-5, characterized in that, The pixel circuit further includes a first reset circuit, which is electrically connected to the driving circuit, the compensation circuit, and the first initial signal terminal; the transistor included in the first reset circuit is a metal oxide thin film transistor. The first shift register is also electrically connected to a first reset circuit of a row of pixel circuits; the first shift register is also configured to provide the first scan signal to the first reset circuit of the pixel circuit connected to the first shift register; the first reset circuit is configured to be turned on in response to the first scan signal, and to transmit the first initial signal from the first initial signal terminal to the driving circuit and the compensation circuit; The pixel circuits to which the first reset circuit and the data writing circuit connected to the same first shift register belong are located in different rows.

7. The display panel according to claim 6, characterized in that, The pixel circuit to which the first reset circuit connected to the same first shift register belongs is located in the row preceding the pixel circuit to which the data write circuit to which it belongs.

8. The display panel according to claim 6 or 7, characterized in that, The first reset circuit includes a fourth transistor, which is the metal oxide thin-film transistor; The control electrode of the fourth transistor is electrically connected to the first shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the driving circuit and the compensation circuit.

9. A display panel, characterized in that, The display panel includes a display area and a border area, the border area being located on at least two sides outside the display area; the display panel includes: A multi-row pixel circuit is located within the display area; a row pixel circuit includes a data writing circuit, a driving circuit, and a compensation circuit. The data writing circuit is electrically connected to the driving circuit and a data signal terminal, and the driving circuit is electrically connected to the compensation circuit. The transistors included in the data writing circuit and the compensation circuit are all metal-oxide-slim thin-film transistors. A first shift register is located in the border area; the first shift register is electrically connected to a data writing circuit and a compensation circuit of a row of pixel circuits; the first shift register is configured to provide a first scan signal to the data writing circuit and the compensation circuit of the pixel circuit connected to the first shift register; the data writing circuit and the compensation circuit are configured to be turned on in response to the first scan signal, and transmit the data signal from the data signal terminal to the driving circuit.

10. The display panel according to claim 9, characterized in that, The data writing circuit includes a first transistor, the driving circuit includes a second transistor, and the compensation circuit includes a third transistor; both the first transistor and the third transistor are metal oxide thin-film transistors. The control electrode of the first transistor is electrically connected to the first shift register, the first electrode of the first transistor is electrically connected to the data signal terminal, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor. The control electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the third transistor; The control electrode of the third transistor is electrically connected to the first shift register.

11. The display panel according to claim 9 or 10, characterized in that, The pixel circuit further includes a first reset circuit, which is electrically connected to the driving circuit, the compensation circuit, and the first initial signal terminal; the transistor included in the first reset circuit is a metal oxide thin film transistor. The display panel further includes a second shift register located in the bezel area, the second shift register being electrically connected to a first reset circuit of at least one row of pixel circuits; the second shift register is configured to provide a second scan signal to the first reset circuit of the pixel circuit connected to the second shift register; the first reset circuit is configured to be turned on in response to the second scan signal, transmitting a first initial signal from the first initial signal terminal to the driving circuit and the compensation circuit.

12. The display panel according to claim 11, characterized in that, The first shift register is located on one side outside the display area, and / or the second shift register is located on one side outside the display area.

13. The display panel according to claim 12, characterized in that, A row of pixel circuits is electrically connected to a first shift register, and a second shift register is electrically connected to at least one row of pixel circuits; Along the row direction of the multi-row pixel circuit, the first shift register and the second shift register are located on both sides outside the display area.

14. The display panel according to claim 12, characterized in that, One row of pixel circuits is electrically connected to two of the first shift registers, and at least one row of pixel circuits is electrically connected to two of the second shift registers; Along the row direction of the multi-row pixel circuit, the two first shift registers are located on both sides outside the display area, and the two second shift registers are located on both sides outside the display area.

15. The display panel according to any one of claims 11-14, characterized in that, The first reset circuit includes a fourth transistor, which is the metal oxide thin-film transistor; The control electrode of the fourth transistor is electrically connected to the second shift register, the first electrode of the fourth transistor is electrically connected to the first initial signal terminal, and the second electrode of the fourth transistor is electrically connected to the driving circuit and the compensation circuit.

16. The display panel according to any one of claims 1-15, characterized in that, The second transistor is either a metal oxide thin-film transistor or a low-temperature polycrystalline silicon thin-film transistor.

17. The display panel according to any one of claims 1-16, characterized in that, The display panel further includes a light-emitting device, a third shift register, and a fourth shift register. The light-emitting device is located within the display area, and the third and fourth shift registers are located outside the display area. The pixel circuit further includes a light-emitting control circuit, a second reset circuit, and a third reset circuit. The light-emitting control circuit is electrically connected to the first voltage signal terminal, the driving circuit, and the light-emitting device; the second reset circuit is electrically connected to the second initial signal terminal and the light-emitting device; and the third reset circuit is electrically connected to the third initial signal terminal and the driving circuit. The third shift register is electrically connected to a second reset circuit and a third reset circuit of at least one row of pixel circuits; the third shift register is configured to provide a third scan signal to the second reset circuit and the third reset circuit of the pixel circuit connected to the third shift register; the second reset circuit is configured to be turned on in response to the third scan signal, and transmit a second initial signal from the second initial signal terminal to the light-emitting device; The third reset circuit is configured to be turned on in response to the third scan signal, and to transmit the third initial signal from the third initial signal terminal to the drive circuit; The fourth shift register is electrically connected to the light-emitting control circuit of at least one row of pixel circuits; the fourth shift register is configured to provide a fourth scan signal to the light-emitting control circuit of the pixel circuit connected to the fourth shift register; the light-emitting control circuit is configured to be turned on in response to the fourth scan signal, connecting the path between the first voltage signal terminal and the light-emitting device.

18. The display panel according to claim 17, characterized in that, The third shift register is located on one side outside the display area, and / or the fourth shift register is located on one side outside the display area.

19. The display panel according to claim 18, characterized in that, At least one row of pixel circuitry is electrically connected to one of the third shift registers and one of the fourth shift registers; Along the row direction of the multi-row pixel circuit, the third shift register and the fourth shift register are located on both sides outside the display area.

20. The display panel according to claim 18, characterized in that, At least one row of pixel circuitry is electrically connected to two of the third shift registers and two of the fourth shift registers; Along the row direction of the multi-row pixel circuit, the two third shift registers are located on both sides outside the display area, and the two fourth shift registers are located on both sides outside the display area.

21. The display panel according to any one of claims 17-20, characterized in that, The light-emitting control circuit includes a fifth transistor and a sixth transistor, the second reset circuit includes a seventh transistor, and the third reset circuit includes an eighth transistor; The control electrode of the fifth transistor is electrically connected to the fourth shift register, the first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fifth transistor is electrically connected to the driving circuit. The control electrode of the sixth transistor is electrically connected to the fourth shift register, the first electrode of the sixth transistor is electrically connected to the driving circuit, and the second electrode of the sixth transistor is electrically connected to the light-emitting device. The control electrode of the seventh transistor is electrically connected to the third shift register, the first electrode of the seventh transistor is electrically connected to the second initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the light-emitting device. The control electrode of the eighth transistor is electrically connected to the third shift register, the first electrode of the eighth transistor is electrically connected to the third initial signal terminal, and the second electrode of the eighth transistor is electrically connected to the driving circuit.

22. The display panel according to claim 21, characterized in that, The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all low-temperature polycrystalline silicon thin-film transistors.

23. A display module, characterized in that, The display module includes: The display panel as described in any one of claims 1-22; The display driver is electrically connected to the display panel.

24. An electronic device, characterized in that, The electronic device includes: The display module as described in claim 23; A drive controller is coupled to the display module.

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