Phase-locked loop, radio frequency circuit, and terminal device

Abstract

A phase-locked loop, a radio frequency circuit, and a terminal device, which relate to the technical field of radio frequencies, and are used for improving linearity of frequency-modulated signals output by phase-locked loops. The phase-locked loop comprises a phase detector, an oscillator, a processing unit, and a logic unit, wherein the oscillator outputs a frequency-modulated signal to the phase detector according to a frequency adjustment signal output by the logic unit; the phase detector determines a phase error between the frequency-modulated signal and a reference signal, and outputs same to the processing unit and the logic unit; the processing unit determines a boundary frequency and a frequency modulation slope of each frequency modulation band according to the phase error, the frequency adjustment signal, and a frequency control signal, and outputs same to the logic unit; and the logic unit performs a logic operation on the phase error and the boundary frequency and the frequency modulation slope of each frequency modulation band to obtain a frequency adjustment signal and output same to the oscillator. Calibrating a frequency adjustment signal by means of a processing unit and a logic unit improves frequency adjustment signal accuracy, thereby improving linearity of frequency-modulated signals generated on the basis of frequency adjustment signals.

Description

A phase-locked loop, radio frequency circuit and terminal device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510114977.4, filed on January 23, 2025, with the invention title “A Phase-Locked Loop, Radio Frequency Circuit and Terminal Equipment”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of radio frequency technology, and in particular to a phase-locked loop, radio frequency circuit and terminal equipment. Background Technology

[0004] A phase-locked loop (PLL) is a negative feedback control element that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator (VCO) to generate a target frequency. Currently, it is mainly used in mobile terminal transmitters to generate fixed-frequency or swept-frequency signals, offering advantages such as low power consumption and low cost.

[0005] However, existing phase-locked loops (PLLs) suffer from nonlinearity in their frequency modulation (FM) signals. As shown in Figure 1, the ideal FM signal L1 is a signal whose frequency is linear with time. However, the FM signal L2 actually output by the PLL cannot satisfy this linear relationship. This nonlinearity leads to a large frequency difference between the actual FM signal output by the PLL and the desired FM signal, affecting the accuracy of subsequent circuit operations.

[0006] Therefore, how to improve the linearity of the frequency modulation signal output by the phase-locked loop is a technical problem that urgently needs to be solved in the circuit design of the phase-locked loop. Summary of the Invention

[0007] This application provides a phase-locked loop, a radio frequency circuit, and a terminal device to improve the linearity of the frequency modulation signal output by the phase-locked loop.

[0008] In a first aspect, this application provides a phase-locked loop, including a phase detector, an oscillator, a processing unit, and a logic unit. The first input terminal of the phase detector is used to receive a reference signal, the second input terminal of the phase detector is coupled to the output terminal of the oscillator, the output terminal of the phase detector is coupled to the first input terminal of the logic unit and the first input terminal of the processing unit, the second input terminal of the logic unit is coupled to the output terminal of the processing unit, the output terminal of the logic unit is coupled to the second input terminal of the processing unit and the input terminal of the oscillator, and the third input terminal of the processing unit is used to receive a frequency control signal. When the phase-locked loop (PLL) is working, the oscillator outputs a frequency modulation (FM) signal based on the frequency adjustment signal output by the logic unit, allowing the FM signal to enter the PLL and processing unit. The phase detector determines the phase error between the FM signal output by the oscillator and the reference signal, and outputs the phase error to the processing unit and the logic unit. The processing unit determines the boundary frequency and modulation slope of each FM band in the FM signal based on the phase error output by the phase detector, the frequency adjustment signal output by the oscillator, and the frequency control signal, and outputs this information to the logic unit. The logic unit performs logical operations on the phase error output by the phase detector and the boundary frequencies and modulation slopes of each FM band in the FM signal output by the processing unit to obtain the frequency adjustment signal, which is then output to the oscillator.

[0009] Based on the above structure, by setting up a processing unit and a logic unit in the phase-locked loop (PLL), a negative feedback circuit is essentially established. The frequency adjustment signal calculated by the PLL is used to drive the oscillator to output a frequency modulation signal, and also output to the processing unit and logic unit for negative feedback adjustment to calibrate the previous frequency adjustment signal. Thus, the PLL structure provided in this application can improve the linearity of the output frequency modulation signal. In one embodiment, even if the previous frequency adjustment signal is inaccurate, causing the frequency modulation signal output by the oscillator to be nonlinear, a more accurate frequency adjustment signal can be calibrated based on the negative feedback circuit. This more accurate frequency adjustment signal can then drive the oscillator to output a frequency modulation signal with better linearity.

[0010] In one possible design, the frequency adjustment signal includes a fine-tuning control signal, which contains fine-tuning control words for each position between the start and end positions of each frequency modulation band. Based on the fine-tuning control words for each position, after receiving the frequency control signal and the frequency adjustment signal, if the processing unit detects that the first fine-tuning control word at the first position reaches a first threshold during the frequency rise segment of the frequency control signal, it records the first position and the first fine-tuning control word, and outputs the first position and the first fine-tuning control word to the logic unit.

[0011] Here, the first threshold can be set to a relative value, such as the maximum value among all the first fine-tuning control words within a frequency band. Alternatively, it can be set to the maximum value that the first fine-tuning control word can take, or a value near the maximum value, such as 80%, 70%, 60%, 65%, 90%, etc., of the maximum value. Or, it can be set to other values ​​without limitation.

[0012] In the above design, the first position can be considered as the position where the frequency overlap problem exists. By recording the first fine-tuning control word at the first position, the first fine-tuning control word can be used to correct the original fine-tuning control word at the first position, so that the frequency points of the positions before and after the first position are aligned at the first position, thus solving the frequency overlap problem at the first position.

[0013] In one example of the above design, the first position is located in the overlapping area of ​​adjacent FM bands.

[0014] Based on the above example, the overlapping area of ​​adjacent FM bands is the most common location for frequency overlap. By selecting the first position within the overlapping area of ​​adjacent FM bands and recording the first position and the corresponding first fine-tuning control word, the recorded first fine-tuning control word can be used to correct the fine-tuning control word of the overlapping area and compensate for the frequency overlap nonlinearity that occurs in the overlapping area.

[0015] In one example of the above design, the overlapping regions of adjacent frequency bands use the recorded first fine-tuning control word, while the non-overlapping regions still use the original fine-tuning control word.

[0016] Based on the above examples, it can both compensate for the frequency overlap nonlinearity in the overlapping region and retain the original fine-tuning control word as much as possible, avoiding additional workload, improving the correction speed of the fine-tuning control word, and reducing the frequency modulation delay introduced by adding negative feedback circuit.

[0017] In one example of the above design, the overlapping area of ​​adjacent FM bands is recorded only once for the first position.

[0018] Based on the above example, it can be ensured that there is only one recorded first fine-tuning control word in the overlapping area of ​​adjacent FM bands. Therefore, adjacent FM bands have the same frequency point in the overlapping area, and their boundaries can be aligned with each other.

[0019] In one example of the above design, the frequency control signal includes frequency control words at various positions. While recording the first position and the corresponding first fine-tuning control word, the processing unit can also record the first frequency control word corresponding to the first position. Based on the recorded first frequency control word, if the second frequency control word at the second position is detected to be the same as the recorded first frequency control word during the frequency drop segment of the frequency control signal, the second position and the corresponding second fine-tuning control word are recorded, and the second position and the second fine-tuning control word are output to the logic unit.

[0020] Based on the above example, the first fine-tuning control word recorded in the overlapping area of ​​the rising frequency segment can be directly mirrored to the overlapping area of ​​the falling frequency segment. This ensures that the overlapping area of ​​the falling frequency segment has the same second fine-tuning control word as the first fine-tuning control word, and also ensures that the rising and falling frequency segments in a sweep waveform are symmetrical. Based on the symmetrical sweep waveform, a regular sweep curve can be fitted more quickly.

[0021] In one example of the above design, the processing unit includes a first recorder. The input of the first recorder is used to receive a frequency control signal and a fine-tuning control signal. The output of the first recorder is coupled to the second input of the logic unit. The first recorder is used to record and output the first position and the first fine-tuning control word when the first position reaches a first threshold during the rising frequency segment of the frequency control signal.

[0022] Based on the above example, the recording operation of the rising frequency segment can be achieved by using a recorder. The recorder has a simple structure, low cost, and is relatively easy to obtain, which can reduce the design difficulty of the phase-locked loop.

[0023] In a further possible example, the processing unit further includes a second recorder coupled between the output of the first recorder and the second input of the logic unit. The second recorder is used to record the second position and the second fine-tuning control word when it detects that the second fine-tuning control word of the second position is the same as the first fine-tuning control word during the frequency drop segment of the frequency control signal, and output the first position, the second position, the first fine-tuning control word and the second fine-tuning control word to the logic unit.

[0024] Based on the above example, another recorder can be used to mirror the control word for the frequency drop-off segment, reducing the design difficulty of the phase-locked loop.

[0025] In one example of the above design, the phase-locked loop also includes a delay circuit coupled between the output of the logic unit and the second input of the processing unit. The delay circuit is used to delay the fine-tuning control signal output by the logic unit and send it to the processing unit.

[0026] Based on the above example, a delay circuit can be used to delay the fine-tuning control word fed back from the logic unit by one beat, thereby distinguishing the fine-tuning control word currently being recorded by the processing unit from the fine-tuning control word fed back. This prevents the fine-tuning control word fed back from affecting the calibration operation of the current fine-tuning control word, maintaining the accuracy of the fine-tuning control word calibration. Based on the accurate fine-tuning control word, the oscillator can also be driven to output a more accurate frequency modulation signal.

[0027] In one possible design, the frequency adjustment signal includes a coarse adjustment control signal, which includes a coarse adjustment control word corresponding to each frequency modulation band. Based on the coarse adjustment control word corresponding to each frequency modulation band, the processing unit can obtain the frequency modulation slope of the frequency modulation band indicated by each coarse adjustment control word by fitting the phase error, and then accumulate the frequency modulation slopes of multiple frequency modulation bands to obtain the target frequency modulation slope, and output it to the logic unit.

[0028] Based on the above design, by fitting the frequency modulation curve within each frequency modulation band to a straight line and then accumulating the slopes of the straight lines within each frequency modulation band over time, the slopes of each frequency modulation band can be made consistent. Consistent frequency modulation slopes lead to consistent frequency modulation gains, thus solving the problem of frequency modulation gain nonlinearity in existing phase-locked loops. Furthermore, since the segmentation of the frequency modulation slope is based on the coarse adjustment control word rather than the frequency control word, the boundaries of each segment in the frequency modulation gain nonlinearity compensation stage can be naturally aligned with the boundaries of the frequency modulation bands used in the frequency overlap nonlinearity compensation stage. After the information from the two compensation stages is superimposed, a frequency modulation signal conforming to a linear relationship can be obtained.

[0029] In one example of the above design, the processing unit includes a slope calibrator and an accumulator. The input of the slope calibrator is coupled to the output of the phase detector, the output of the slope calibrator is coupled to the input of the accumulator, and the output of the accumulator is coupled to the second input of the logic unit. The slope calibrator is used to fit the FM slope of each FM band indicated by the coarse adjustment control word based on the phase error and output it to the accumulator. The accumulator is used to accumulate the FM slopes of multiple FM bands to obtain the target FM slope and output it to the logic unit.

[0030] Based on the above design, compensation for frequency modulation gain nonlinearity can be achieved through a slope calibrator and an accumulator. The slope calibrator and accumulator have simple structures and low costs, which can reduce the design difficulty.

[0031] In one possible design, the logic unit is an adder. The processing logic of an adder is simple and easy to implement.

[0032] In one possible design, the phase-locked loop (PLL) also includes a frequency divider. The first input of the frequency divider receives a frequency control signal, the second input is coupled to the output of the oscillator, and the output is coupled to the second input of the phase detector. After receiving the frequency control signal and the frequency modulation signal output by the oscillator, the frequency divider divides the frequency of the frequency modulation signal output by the oscillator to a reference frequency according to the frequency control signal, and sends the divided frequency modulation signal to the phase detector. The reference frequency is the frequency of a reference signal.

[0033] Based on the above design, the frequency of the frequency modulation signal can be pulled down to the frequency of the reference signal by the constantly changing sweep frequency in the frequency control signal, so as to meet the requirements of continuous frequency sweep while providing the same clock reference for the phase comparison of the phase-locked loop.

[0034] In one possible design, the phase-locked loop also includes a filter coupled between the output of the phase detector and the first input of the logic unit, which is used to perform low-pass filtering on the phase error of the phase detector output before outputting it to the logic unit.

[0035] Based on the above design, noise and interference signals in the phase error can be filtered out by a low-pass filter, thereby improving signal quality.

[0036] In a second aspect, this application provides a radio frequency circuit including a phase-locked loop as described in the first aspect or any of the designs or examples of the first aspect above.

[0037] In one possible design, the RF circuit also includes a waveform generator, the output of which is coupled to the input of the phase-locked loop (PLL), and the first output of the PLL is coupled to the transmitter of the RF circuit. The waveform generator generates a frequency control signal and outputs it to the PLL. The PLL generates and outputs a frequency-modulated signal based on the reference signal and the frequency control signal, and this frequency-modulated signal is emitted outside the RF circuit through its transmitter.

[0038] Based on the above design, a voltage waveform signal can be generated by a waveform generator, and then converted into a frequency waveform signal, i.e., a radio frequency signal, in the phase-locked loop, thus realizing the conversion and output of voltage signal to radio frequency signal.

[0039] In one possible design, the radio frequency circuit also includes a power amplifier coupled between the first output of the phase-locked loop and the transmitter, which is used to amplify the frequency-modulated signal output by the phase-locked loop before outputting it.

[0040] Based on the above design, the power of the output signal can be increased by a power amplifier to enable the output signal to be transmitted to a farther location, meeting the requirements of long-distance transmission. For example, if applied in the field of detection, the output signal can detect targets at a greater distance, improving ranging capabilities.

[0041] In one possible design, the RF circuit also includes a mixer coupled between the receiver of the RF circuit and the second output of the phase-locked loop. The phase-locked loop is also used to output the local oscillator signal to the mixer, which is used to mix the echo signal from the receiver with the local oscillator signal to obtain an intermediate frequency signal.

[0042] Based on the above design, both the local oscillator signal and the frequency modulation (FM) signal originate from the phase-locked loop (PLL). These two signals share similar characteristics; therefore, the local oscillator signal can be used as a reference to extract and analyze the effective components of the echo signal to determine the information carried by the echo signal. For example, when the mixer performs mixing, only the portion of the echo signal with the same frequency as the local oscillator signal can be mixed, while the portion with different frequencies is ignored. This reduces noise interference, improves the accuracy of the intermediate frequency (IF) signal, and allows the IF signal to carry the phase difference information between the FM signal and the echo signal, which can be used to analyze the transmission characteristics of the FM signal outside the RF circuit.

[0043] In further possible designs, the RF circuit also includes a low-noise amplifier coupled between the receiver and the mixer of the RF circuit, which is used to amplify the echo signal received by the receiver with low noise before outputting it.

[0044] Based on the above design, the effective components in the received signal can be amplified by a low-noise amplifier, while reducing the introduction of self-noise and external noise, thereby improving the signal-to-noise ratio and reception quality of the received signal, and thus improving the quality of the intermediate frequency signal.

[0045] Thirdly, this application provides a terminal device that includes a phase-locked loop as described in the first aspect or any of the designs or examples of the first aspect, or includes a radio frequency circuit as described in the second aspect or any of the designs of the second aspect.

[0046] In one possible design, the terminal device is a detection device used to measure the distance and / or velocity of a target outside the terminal device.

[0047] In one possible design, the terminal device is a sensor, such as a radar sensor, a perception sensor, a millimeter-wave sensor, or an artificial intelligence sensor.

[0048] Optionally, sensors can be applied to various fields. For example, they can be used in smart homes to detect the status of users in a primary space, which assists smart home devices in achieving whole-house intelligent control of that space. They can also be used in medical assistance to detect the vital signs of users undergoing surgery and promptly alert medical personnel when abnormalities occur. Furthermore, they can be used in cockpits to identify abandoned living beings or to recognize operations performed by the driver and co-pilot. And so on, to name just a few.

[0049] The technical effects that can be achieved by the design of the second or third aspect mentioned above can be referred to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0050] Figure 1 illustrates a schematic diagram of the comparison curves between an ideal frequency modulation signal and an actual frequency modulation signal;

[0051] Figure 2a illustrates a possible application scenario applicable to this application;

[0052] Figure 2b illustrates another possible application scenario to which this application applies;

[0053] Figure 2c illustrates another possible application scenario to which this application applies;

[0054] Figure 3a illustrates a schematic diagram of a mainstream digital phase-locked loop.

[0055] Figure 3b illustrates a schematic diagram of a digital phase-locked loop employing a coarse-fine adjustment scheme in the prior art.

[0056] Figure 3c illustrates, for example, a schematic diagram of the frequency overlap nonlinearity and frequency modulation slope nonlinearity present in a digital phase-locked loop in the prior art;

[0057] Figure 4 illustrates a schematic diagram of a phase-locked loop provided in this application;

[0058] Figure 5 illustrates an exemplary structural diagram of another phase-locked loop provided in this application;

[0059] Figure 6a illustrates a schematic diagram of a frequency modulation control signal provided in this application;

[0060] Figure 6b illustrates a schematic diagram of another frequency modulation control signal provided in this application;

[0061] Figure 6c illustrates a schematic diagram of yet another frequency modulation control signal provided in this application;

[0062] Figure 7 illustrates, exemplarily, a flowchart of frequency overlap compensation and frequency modulation gain compensation provided in this application;

[0063] Figure 8 is an exemplary schematic diagram showing the presentation of various signals in a phase-locked loop provided by the prior art;

[0064] Figure 9 exemplarily illustrates a comparison diagram of frequency modulation curves before and after compensation provided in this application;

[0065] Figure 10 illustrates a schematic diagram of the structure of a processing unit provided in this application;

[0066] Figure 11a exemplarily shows the frequency modulation bandwidth curve and frequency difference curve of a phase-locked loop provided in this application at a sweep rate of 26MHz / μs;

[0067] Figure 11b exemplarily illustrates the frequency modulation bandwidth curve and frequency difference curve of a phase-locked loop provided in this application at a sweep rate of 106MHz / μs;

[0068] Figure 12 illustrates a schematic diagram of another phase-locked loop provided in this application;

[0069] Figure 13 illustrates a detailed circuit structure diagram of a phase-locked loop provided in this application;

[0070] Figure 14 illustrates a schematic diagram of the structure of a radio frequency circuit provided in this application;

[0071] Figure 15 illustrates a schematic diagram of the structure of a terminal device provided in this application. Detailed Implementation

[0072] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0073] The following provides explanations for some of the terms used in this application. It should be noted that these explanations are for the convenience of those skilled in the art and do not constitute a limitation on the scope of protection claimed in this application.

[0074] I. Frequency mixing.

[0075] Frequency mixing, also known as coherent demodulation, refers to the process of subtracting the frequency and phase of two signals.

[0076] In frequency-modulated continuous wave (FM) radar, the detection signal is typically a linear frequency-modulated (LFM) signal. After this LFM signal interacts with the target object, the reflected echo signal (i.e., the received signal) also exhibits the same frequency variation characteristics. However, depending on the target distance, the echo signal will have a certain phase and frequency difference relative to the detection signal. Therefore, after receiving the echo signal, the echo signal and the detection signal can be mixed; that is, the frequency and phase difference between the detection signal and the echo signal is calculated to obtain a low-frequency beat signal, also known as a beat frequency signal or intermediate frequency (IF) signal. The IF signal contains information about the frequency difference between the two signals, which is related to the target distance. For example, in a static state, the absolute value of the frequency difference is proportional to the target distance. In a dynamic state, the IF signal also contains information about the Doppler effect caused by target movement; based on this Doppler effect information, the target's velocity can be calculated.

[0077] II. Fast Fourier Transform (FFT).

[0078] The Faster Interpreter (FFT) is commonly used in frequency domain filtering and spectral analysis. It decomposes a signal into a superposition of several sine waves, thus transforming the signal from the time domain to the frequency domain. Since the frequency domain has fewer dimensions than the time domain, it can be considered that FFT processing can compress the data volume. Furthermore, based on the FFT-processed data, target measurements can be performed, such as determining the distance and / or velocity of a target.

[0079] III. Phase-locked loop convergence.

[0080] A phase-locked loop (PLL) is a device that locks its output frequency-modulated (FM) signal to a reference signal. When the FM signal output by the PLL gradually converges to the ideal FM curve, for example, when the frequency error between the output FM signal and the ideal FM curve is zero, the PLL can be considered to have reached convergence.

[0081] The preceding text introduced some of the terms used in this application. The following text introduces the possible application scenarios of this application.

[0082] The phase-locked loop provided in this application can be integrated into sensors or chips, such as millimeter-wave sensors, radar sensors, sensing radar chips, artificial intelligence (AI) super-sensing sensors, AI-assisted health and wellness sensors, etc. Alternatively, it can be integrated into other modules or units besides sensors and chips, without limitation.

[0083] Taking the integrated sensing radar chip as an example, this sensing radar chip can be applied to various types of terminal devices, including but not limited to: smart terminals (mobile phones, foldable screen phones, computers, laptops, tablets, PDAs, desktops, headphones, speakers, wearable devices, in-vehicle devices, virtual reality devices, augmented reality devices, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), etc.), robots, surveying equipment, drones, routers, smart home devices (such as LCD TVs, home robots, robot vacuum cleaners, smart lamps, audio systems, smart lighting systems, electrical control systems, home background music systems, home theater systems, intercom systems, or video surveillance, etc.), smart manufacturing equipment (such as industrial equipment), smart transportation equipment (such as AGVs, unmanned transport vehicles, or trucks, etc.), medical equipment, in-vehicle devices (such as unmanned vehicles, smart cars, electric vehicles, or digital cars, etc.), or other means of transportation (ships, airplanes, trains, subways, maglev trains, submarines, spacecraft, or fighter jets, etc.).

[0084] For example, in one possible application scenario, the sensing radar chip can be integrated into home appliances to achieve whole-house intelligence, as shown in Figure 2a. This home appliance can be mounted on the ceiling to sense user activity within a room and execute corresponding home controls. For instance, it can automatically turn on relevant smart devices in a room when it senses a user entering or showing a tendency to enter, and automatically turn off relevant smart devices when it senses a user leaving, achieving the effect of devices turning on when someone is present and off when they leave. Another example is monitoring user posture; if a user is detected to have fallen or fainted, a notification message is sent to a pre-configured user terminal, or an emergency call is made, to provide home care and monitoring for vulnerable groups such as elderly people living alone or young children, preventing accidents. Yet another example is installing it in the bedroom to record the user's breathing rate, sleep duration, and number of awakenings during sleep, enabling home health monitoring without the user's awareness. Alternatively, it can perform other smart home controls, which will not be listed here.

[0085] In another possible application scenario, the phase-locked loop (PLL) can be integrated into an in-vehicle device, as shown in Figure 2b. In one example, this in-vehicle device can be installed at the front of the vehicle, covering most of the cabin area, to implement a liveness detection function. For example, after the vehicle is turned off, with all doors closed, windows closed, and locks engaged, the in-vehicle device can capture information about the in-vehicle environment, especially the rear seat environment. If it detects a child or pet left behind in the vehicle, it can flash lights, honk the horn, or even make a phone call to the owner. Alternatively, in another example, it can also be used to recognize operations performed by the driver and passenger. For example, after the vehicle is started, the in-vehicle device recognizes the front seat environment. When it detects that the driver is clicking the in-vehicle central control screen, it displays the corresponding interface on the driver's side half of the screen, while if the passenger is clicking the screen, it displays the corresponding interface on the passenger's side half of the screen, making it easier for the user to operate the interface. Alternatively, in another example, gesture recognition could be used to achieve intelligent vehicle control. For instance, detecting a user snapping their fingers could start the vehicle, or detecting a user waving their hand could play music. Other in-vehicle intelligent controls are also possible, but these will not be listed here.

[0086] In another possible application scenario, phase-locked loops (PLLs) can be integrated into medical devices, such as those in operating rooms, wards, or treatment rooms. Taking operating room equipment as an example (see Figure 2c), during surgery, the medical device continuously scans the patient's vital signs. If abnormal vital signs are detected, such as rapid or slow breathing, an alert can be sent to the doctor, enabling timely response to the emergency and protecting the patient's life.

[0087] It should be understood that the various possible application scenarios given above are merely examples. The phase-locked loop provided in this application can also be applied to other possible scenarios, and is not limited to those exemplified above. For example, it can also be integrated into a roadside unit (RSU) as a roadside detection device to detect whether a traffic accident has occurred on the road segment. Another example is its integration into a swimming pool to detect whether a child or adult is trapped inside. Furthermore, it can be applied to smartphones, smart manufacturing equipment, industrial equipment, and robots, among others.

[0088] It should be noted that the application scenarios described in this application are for the purpose of more clearly illustrating the technical solutions of this application, and do not constitute a limitation on the technical solutions provided in this application.

[0089] Among various sensing radar chips, millimeter-wave radar has attracted widespread attention due to its all-weather, low-cost, and high-precision characteristics, and has been continuously applied in fields such as autonomous driving, smart terminals, and industrial production in recent years.

[0090] Frequency-modulated continuous wave (FMCW) is a ranging method for millimeter-wave radar. Its principle involves emitting a continuously varying frequency signal and measuring the difference between the transmitted and received signals (the intermediate frequency, or IF signal). Based on the correlation between the IF signal, the sweep bandwidth, and the period, the distance to the target is calculated. The range resolution of FMCW radar is inversely proportional to the sweep bandwidth; therefore, a wide sweep range can achieve high range resolution.

[0091] Furthermore, considering the system signal-to-noise ratio requirements, a short sweep period and low phase noise will reduce mutual interference between various intermediate frequency signals in multi-target situations, achieving excellent ranging performance. Generally, FMCW radar transmitters require the root mean square frequency difference of the continuous frequency modulated wave to be within 1‰ of the sweep bandwidth, which places high demands on the frequency synthesizer.

[0092] To meet the frequency sweeping requirements of FMCW radar, phase-locked loops (PLLs) are commonly used to generate the frequency-modulated (FM) signal, also known as the frequency sweep signal. There are two main types of PLLs: digital PLLs and analog PLLs. Compared to analog PLLs, digital PLLs offer superior process iteration and interference immunity. Furthermore, their digital architecture allows for the use of complex signal processing algorithms to compensate for various non-ideal factors in the circuit, such as the nonlinearity of the voltage-controlled oscillator (VCO). Therefore, digital PLLs have a wider range of applications than analog PLLs.

[0093] Please refer to Figure 3a, which shows a schematic diagram of a mainstream digital phase-locked loop. This phase-locked loop includes a phase frequency detector (PFD), a loop filter (LF), a voltage-controlled oscillator (VCO), and a multi-modulus divider (MMD), and their connections are shown in Figure 3a.

[0094] When the phase-locked loop is working, the voltage-controlled oscillator outputs a frequency modulation signal θ. out The frequency modulation signal θ out The output signal of the phase-locked loop (PLL) is also fed back to the multi-mode divider. The multi-mode divider receives the frequency control signal θ from the previous stage circuit element of the PLL. in According to the frequency control signal θ in The frequency modulation signal θ out The frequency of the modulated signal is divided to the frequency of the reference signal Ref and then output to the frequency and phase detector. The divided frequency-modulated signal is compared with the reference signal Ref in the frequency and phase detector to obtain the phase error ERR, which is then output to the loop filter. Noise and interference components in the phase error ERR are filtered out by the low-pass loop filter, forming the control voltage of the voltage-controlled oscillator, called the frequency adjustment signal TE. The frequency adjustment signal TE acts on the voltage-controlled oscillator and is mainly responsible for adjusting the frequency of the output frequency-modulated signal θ. out The oscillation frequency is pulled towards the frequency control signal θ in The frequency of the frequency modulation signal θ is then divided by a multi-mode frequency divider. out The feedback is sent to the frequency and phase detector, initiating a new round of frequency locking.

[0095] Typically, the frequency control signal θ inThe frequency of the frequency sweep is constantly changing. To meet the ranging accuracy requirements of FMCW radar, a wide frequency sweep range is needed. Therefore, the tuning range of the voltage-controlled oscillator (VCO) also needs to be set relatively wide. In a common approach, the VCO uses a switched capacitor array encoded with an equally weighted thermometer to achieve the tuning function, as shown in Figure 3b. It should be noted that Figure 3b uses a switched capacitor array including a 6-dimensional coarse-tuning capacitor array (6D-Fine Bank) and a 6-dimensional fine-tuning capacitor array (6D-Coarse Bank) as an example. However, the coarse-tuning and fine-tuning capacitor arrays in actual VCOs are not limited to 6D; they can also be 5D, 4D, 3D, 2D, or 7D, 8D, 9D, 10D, etc. This application only uses a 6D capacitor array as an example for introduction.

[0096] Based on the architecture shown in Figure 3b, the frequency control signal θ in After being input to the multi-mode divider, the multi-mode divider controls the frequency according to the frequency control signal θ. in The constantly changing frequency alters the division ratio, and the altered division ratio is used to modulate the frequency signal θ output by the voltage-controlled oscillator. out Frequency division is performed so that the frequency of the divided signal participating in phase-locked loop changes continuously, satisfying the requirement of continuous frequency sweep. Frequency control signal θ in The frequency control word (FCW) is included. The FCW has an integer part and a fractional part. The integer part is processed by a frequency and phase detector and a loop filter to generate a coarse tune word (TW_F), while the fractional part is used to generate a fine tune word (TW_C). Both control words, TW_F and TW_C, are output to the voltage-controlled oscillator (VCO). The VCO adjusts the switching of the 6-dimensional coarse tune capacitor array according to the coarse tune control word TE_F, and adjusts the switching of the 6-dimensional fine tune capacitor array according to the fine tune control word TE_C. By coordinating the coarse and fine tune capacitor arrays, a continuous frequency modulation signal θ is generated. out And output. Among them, the coarse tuning capacitor array can ensure a sufficiently wide tuning range, while the fine tuning capacitor array can ensure a sufficiently fine tuning resolution.

[0097] However, in actual production and use, due to manufacturing errors or changes in the circuit environment (such as temperature or voltage variations), components in the phase-locked loop (PLL) may malfunction or experience functional mismatch, a problem often referred to as PLL layout mismatch. In this case, the frequency modulation signal θ output by the voltage-controlled oscillator (VCO) will... out There may be some error between the frequency of the frequency modulation signal θ and the originally expected output frequency. To ensure the frequency modulation signal θ... outIt is a continuous frequency modulation without frequency interruption. In existing voltage-controlled oscillators (VCOs), the tuning curves combining coarse and fine tuning exhibit frequency overlap between each fine tuning band, as shown in Figure 3c(A). This frequency overlap causes the frequency modulation signal θ output by the VCO to... out The frequency sweep waveform exhibits nonlinearity, which severely affects the ranging accuracy of the FMCW radar.

[0098] Besides frequency overlap nonlinearity, existing voltage-controlled oscillators (VCOs) also suffer from tuning gain nonlinearity. Specifically, as shown in Figure 3c(A), each fine-tuning band initially presents as a curve, which does not meet the requirements of linear frequency modulation. Therefore, to achieve linear frequency modulation, the curve of each fine-tuning band needs to be fitted into a straight line, as shown in Figure 3c(B). However, the slopes of the straight lines fitted in this way are all different, meaning the slopes of the frequencies are different. Different slopes result in different tuning gains, thus causing tuning gain nonlinearity in each fine-tuning band, which also needs to be compensated for.

[0099] In addition, in order to adapt to the frequency hopping anti-interference requirements in automotive radar applications and the multi-mode radar frame requirements in IoT applications, the convergence time of the phase-locked loop should be as small as possible. However, the convergence time of existing phase-locked loops is mostly above 100 frequency sweep cycles, which cannot meet the requirement of minimizing the convergence time in the current scenario.

[0100] Based on this, an adaptive digital predistortion algorithm needs to be designed in the phase-locked loop. In addition to adaptively compensating for the frequency overlap nonlinearity and frequency modulation slope nonlinearity of the voltage-controlled oscillator to reduce the changes in the tuning curve caused by temperature, voltage and other factors, the required digital predistortion algorithm also needs to accelerate the fitting convergence of the phase-locked loop through background calibration so that the frequency modulation signal output by the phase-locked loop converges to the desired linear frequency modulation curve as quickly as possible.

[0101] Based on the above, the phase-locked loop and related contents proposed in this application will be described in detail below with reference to Figures 4 to 15.

[0102] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions between different embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0103] In the description of this application, "coupling" can be understood as an electrical connection. Coupling between two electrical components can be a direct or indirect connection between the two components. For example, coupling between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components, such as a direct connection between A and B, a direct connection between A and C, a direct connection between C and B, or even a wireless connection between A and B. In short, coupling between A and B enables the transmission of electrical signals between them.

[0104] In this application, the terminology used for the terminals of electronic components is merely an exemplary representation and can be understood as a coupling terminal, connection terminal, or connection point, used for connecting to other circuit components. In other examples, terminals, connection terminals, or connection points may also have other names; for instance, in some scenarios, a terminal may also be referred to as a communication terminal, information transmission terminal, terminal, connection terminal, communication connection terminal, information connection terminal, connection point, communication connection point, information connection point, or electrode, etc.

[0105] Furthermore, in the textual description of this application, terms such as "control word," "frequency," and "position" do not refer to absolute values ​​and are allowed to have certain process or measurement deviations. For example, two frequency control words being equal does not mean they are absolutely equal; a certain deviation is allowed, as long as it is within the allowable deviation range of the process or the minimum measurable control word range.

[0106] Please refer to Figure 4, which shows a schematic diagram of a phase-locked loop (PLL) provided in this application. The PLL 400 includes a phase detector 410, an oscillator 420, a processing unit 430, and a logic unit 440. The phase detector 410 has a first input terminal a1, a second input terminal a2, and an output terminal a3. The processing unit 430 has a first input terminal b1, a second input terminal b2, a third input terminal b3, and an output terminal b4. The logic unit 440 has a first input terminal c1, a second input terminal c2, and an output terminal c3. The first input terminal a1 of the phase detector 410 is used to receive a reference signal Ref. The second input terminal a2 of the phase detector 410 is coupled to the output terminal of the oscillator 420. The output terminal a3 of the phase detector 410 is coupled to the first input terminal b1 of the processing unit 430 and the first input terminal c1 of the logic unit 440, respectively. The second input terminal c2 of logic unit 440 is coupled to the output terminal b4 of processing unit 430. The output terminal c3 of logic unit 440 is coupled to the second input terminal b2 of processing unit 430 and the input terminal of oscillator 420. The third input terminal b3 of processing unit 430 is used to receive the frequency control signal θ. in .

[0107] In the above content, the frequency control signal θ inThis can be understood as the signal output from the previous stage circuit element of the phase-locked loop 400 to the phase-locked loop 400. For example, it could be a voltage waveform signal output from a waveform generator, typically a triangular wave, but it could also be other waveforms; there are no limitations. The function of the phase-locked loop 400 is to generate a corresponding frequency waveform signal, i.e., a radio frequency (RF) signal, based on this voltage waveform signal. The RF signal is the frequency modulation signal θ output by the oscillator 420. out .

[0108] In the above, the reference signal can be understood as the local oscillator signal, such as the reference clock signal generated by a quartz oscillator. This reference clock signal is mainly used to provide the frequency modulation signal θ output by the oscillator 420. out and the frequency control signal θ output by the previous stage circuit element in A common reference frequency or reference clock is provided for signal synchronization. Optionally, the quartz oscillator can be located locally within the phase-locked loop 400 or externally to the phase-locked loop 400; Figure 4 shows the latter as an example.

[0109] As shown in Figure 4, when the phase-locked loop 400 is working, the logic unit 440 outputs a frequency adjustment signal TW, which enters the oscillator 420. The oscillator 420 outputs a frequency modulation signal θ according to the frequency adjustment signal TW. out FM signal θ out On one hand, it serves as the output of the phase-locked loop 400, and on the other hand, it is simultaneously fed back to the phase detector 410. The phase detector 410 receives the frequency-modulated signal θ output by the oscillator 420. out Then, calculate the frequency modulation signal θ. out The phase error ERR between the phase detector 410 and the reference signal Ref is calculated, and the phase error ERR is output to the processing unit 430 and the logic unit 440. The processing unit 430 calculates the phase error ERR output by the phase detector 410, the frequency adjustment signal TW output by the logic unit 440, and the frequency control signal θ. in Determine the frequency modulation signal θ out The boundary frequency and modulation slope of each FM band are calculated and output to logic unit 440. Logic unit 440 processes the phase error ERR output by phase detector 410 and the FM signal θ output by processing unit 430. out The boundary frequencies and modulation slopes of each FM band in the oscillator are used for logical operations to obtain the frequency adjustment signal TW, which is then output to the oscillator 420. The oscillator 420 regenerates the FM signal θ based on the frequency adjustment signal TW output by the logic unit 440. out The result is fed back to the phase detector 410 for further pre-distortion processing.

[0110] Referring to Figures 3a and 4 above, in the existing phase-locked loop architecture, the calculated frequency modulation signal TW is directly output to the oscillator 420, driving the oscillator 420 to output the frequency modulation signal θ. out This application, by setting up a processing unit and a logic unit in the phase-locked loop 400, is equivalent to setting up a negative feedback circuit. The calculated frequency adjustment signal TW is used on the one hand to drive the oscillator 420 to output a frequency modulation signal, and on the other hand, it is output to the processing unit and logic unit for negative feedback adjustment to calibrate the previous frequency adjustment signal TW. In one embodiment, even if the previous frequency adjustment signal TW is inaccurate, causing the frequency modulation signal θ output by the oscillator 420 to be... out The nonlinearity can also be used to improve the accuracy of the frequency modulation signal TW based on this calibration, and a more accurate frequency modulation signal can also drive the oscillator 420 to output a frequency modulation signal θ with better linearity. out Therefore, compared to existing phase-locked loop (PLL) architectures, the PLL structure provided in this application can improve the output frequency modulation signal θ. out The linearity.

[0111] Optionally, in addition to the components shown in Figure 4, the phase-locked loop 400 may also include other components. For example, please refer to Figure 5, which shows a schematic diagram of another phase-locked loop provided in this application. In this example, the phase-locked loop 400 may also include a filter 450. The filter 450 is coupled between the output terminal a3 of the phase detector 410 and the first input terminal c1 of the logic unit 440, and is used to perform low-pass filtering on the phase error ERR output by the phase detector 410 before outputting it to the logic unit 440. Here, low-pass filtering can be understood as filtering out the high-frequency components in the phase error ERR, allowing only low-frequency components to pass. Since noise signals and interference signals are basically high-frequency, noise signals and interference signals in the phase error ERR are also filtered out, making the output signal purer and the signal quality better.

[0112] Optionally, as shown in Figure 5, the phase-locked loop 400 may further include a frequency divider 460. The frequency divider 460 has a first input terminal d1, a second input terminal d2, and an output terminal d3. The first input terminal d1 is used to receive the frequency control signal θ. in The second input terminal d2 is coupled to the output terminal of oscillator 420, and the output terminal d3 is coupled to the second input terminal a2 of phase detector 410. Frequency divider 460 is mainly used to modulate the frequency signal θ output by oscillator 420. out Frequency division can be performed, for example, based on the frequency control signal θ input from the previous stage circuit element. in The frequency modulation signal θ output by oscillator 420 out The frequency is divided to the reference frequency, and the frequency-modulated signal θ after division is... outIt is sent to phase detector 410. The reference frequency is the frequency of the reference signal Ref.

[0113] In frequency sweep scenarios, a frequency modulation signal θ is required. out The frequency of θ changes continuously, therefore, the frequency control signal θ in This requires indicating the frequency variation pattern, that is, the required frequency at each time point; this information is called the frequency control word (FCW). When the oscillator 420 outputs the frequency modulation signal θ... out and frequency control signal θ in After all the signals are sent to the frequency divider 460, the frequency divider 460 controls the frequency according to the frequency control signal θ. in Different frequency control words (FCW) in the frequency modulation signal θ out The frequency is decomposed to near the reference signal Ref frequency (e.g., 20MHz) of phase detector 410 and output to phase detector 410 for phase comparison. For example, frequency divider 460 can determine the division ratio of each time node according to the frequency control word of each time node, and use the division ratio of each time node to modulate the frequency signal θ output by oscillator 420. out Frequency division is performed. In this way, the frequency control signal θ can be used as the basis for the calculation. in Continuously adjust the frequency modulation signal θ out The frequency is sufficient to meet the requirements of continuous frequency sweep.

[0114] Optionally, to achieve linear frequency modulation, the frequency control signal θ in The various time points and their corresponding frequency values ​​exhibit a linear relationship. This linear relationship can include both direct and inverse proportional relationships; that is, the frequency control signal θ... in The frequency control signal θ includes both the rising and falling frequency segments, as shown in Figure 6a. Alternatively, it may only include a direct proportional relationship, that is, the frequency control signal θ... in It only includes the frequency rising segment, as shown in Figure 6b. Of course, there may be other forms, such as one part having only the frequency rising segment and another part having both the frequency rising and falling segments, as shown in Figure 6c, or it may only have the frequency falling segment, or one part having only the frequency falling segment and another part having both the frequency rising and falling segments, etc., which will not be listed here.

[0115] The above content describes the basic components and some signals in the phase-locked loop 400. To further illustrate the solution, the following section uses the structure shown in Figure 5 as an example to describe each component involved, providing an exemplary implementation scheme.

[0116] I. Oscillator.

[0117] Alternatively, the oscillator can be a voltage-controlled oscillator, such as a digital voltage-controlled oscillator, or simply a numerically controlled oscillator.

[0118] To balance tuning range and tuning accuracy, numerically controlled oscillators (CNCs) can employ a combination of coarse and fine tuning capacitor arrays. That is, the CNC oscillator includes a 6-dimensional coarse tuning capacitor array and a 6-dimensional fine tuning capacitor array, as shown in Figure 3a above. Correspondingly, the frequency adjustment signal TW includes coarse tuning control signals and fine tuning control signals. The coarse tuning control signal controls the coarse tuning capacitor array to achieve a wider tuning range. The fine tuning control signal controls the fine tuning capacitor array to achieve higher tuning accuracy.

[0119] Optionally, the coarse tuning control signal includes a fine tuning word (TW_F), which indicates the start and end positions of each FM band and the corresponding frequency value. The fine tuning control signal, on the other hand, includes fine tuning words (TW_C) for each position between the start and end positions of each FM band. Here, position refers to the time node.

[0120] For example, suppose the frequency control signal θ in Presented as shown in Figure 6a, the coarse adjustment control signal and the fine adjustment control signal can be seen in Figure 7. Let's first introduce the coarse adjustment control signal. The coarse adjustment control signal is mainly used to divide each frequency rising segment and each frequency falling segment into multiple FM bands, and assign a coarse adjustment control word to each FM band. For ease of distinction, the coarse adjustment control word for the frequency rising segment is called the first coarse adjustment control word, and the coarse adjustment control signal for the frequency falling segment is called the second coarse adjustment control word.

[0121] As shown in Figure 7, taking the first two frequency rising segments and the frequency falling segment as examples, assuming the frequency control signal θ in In the first frequency rise segment, the frequency changes from 0 to 6 MHz; in the first frequency fall segment, the frequency changes from 6 MHz to 0; in the second frequency rise segment, the frequency changes from 0 to 12 MHz; and in the second frequency fall segment, the frequency changes from 12 MHz to 0. Therefore:

[0122] In the first frequency rise segment, it is divided into three frequency bands, corresponding to three first coarse adjustment control words. The first coarse adjustment control word of the first frequency band is 1, which means that the frequency rises from the starting position of 0 to 2MHz. The first coarse adjustment control word of the second frequency band is 2, which means that the frequency rises from the ending frequency of the first frequency band of 2MHz to 4MHz. The first coarse adjustment control word of the third frequency band is 3, which means that the frequency rises from the ending frequency of the second frequency band of 4MHz to 6MHz.

[0123] In the first frequency drop segment, it is divided into three FM bands, corresponding to three second coarse adjustment control words. The second coarse adjustment control word for the first FM band is 3 (because it is the same as the first coarse adjustment control word for the third FM band in the first frequency rise segment, so it is drawn in the same cell), which means that the frequency drops from the termination frequency of the third FM band in the first frequency rise segment of 6MHz to 4MHz. The second coarse adjustment control word for the second FM band is 2, which means that the frequency drops from the termination frequency of the first FM band of 4MHz to 2MHz. The second coarse adjustment control word for the third FM band is 1, which means that the frequency drops from the termination frequency of the second FM band of 2MHz to 0.

[0124] In the second frequency rise segment, it is divided into six FM bands, corresponding to six first coarse adjustment control words. The first coarse adjustment control word of the first FM band is 1, which means that the frequency rises from the starting position of 0 to 2MHz. The first coarse adjustment control word of the second FM band is 2, which means that the frequency rises from the ending frequency of the first FM band of 2MHz to 4MHz. The first coarse adjustment control word of the third FM band is 3, which means that the frequency rises from the ending frequency of the second FM band of 4MHz to 6MHz. The first coarse adjustment control word of the fourth FM band is 4, which means that the frequency rises from the ending frequency of the third FM band of 6MHz to 8MHz. The first coarse adjustment control word of the fifth FM band is 5, which means that the frequency rises from the ending frequency of the fourth FM band of 8MHz to 10MHz. The first coarse adjustment control word of the sixth FM band is 6, which means that the frequency rises from the ending frequency of the fifth FM band of 10MHz to 12MHz.

[0125] In the second frequency drop segment, it is divided into six FM bands, corresponding to six second coarse adjustment control words. The second coarse adjustment control word for the first FM band is 6, representing that the frequency drops from the termination frequency of the sixth FM band in the second frequency rise segment (12MHz) to 10MHz. The second coarse adjustment control word for the second FM band is 5, representing that the frequency drops from the termination frequency of the first FM band (10MHz) to 8MHz. The second coarse adjustment control word for the third FM band is 4, representing that the frequency drops from the termination frequency of the second FM band (8MHz) to 6MHz. The second coarse adjustment control word for the fourth FM band is 3, representing that the frequency drops from the termination frequency of the third FM band (6MHz) to 4MHz. The second coarse adjustment control word for the fifth FM band is 2, representing that the frequency drops from the termination frequency of the fourth FM band (4MHz) to 2MHz. The second coarse adjustment control word for the sixth FM band is 1, representing that the frequency drops from the termination frequency of the fifth FM band (2MHz) to 0.

[0126] The content of other frequency rising and falling segments is similar and will not be described in detail here.

[0127] Next, we will explain the fine-tuning control signals.

[0128] For each FM band divided by the coarse adjustment control signal, the fine adjustment control signal contains fine adjustment control words for each position between the start and end positions of that FM band. Essentially, multiple position points are inserted within each FM band, and fine adjustment control words are used to indicate the frequency values ​​at these positions. Optionally, the size of the fine adjustment control word is positively correlated with the frequency; a larger fine adjustment control word corresponds to a higher frequency, and a smaller fine adjustment control word corresponds to a lower frequency. Therefore, if an FM band belongs to the rising frequency range, the later the inserted position point, the larger the corresponding fine adjustment control word, and the fine adjustment control word for the last position point is the largest fine adjustment control word within that FM band. Conversely, if it belongs to the falling frequency range, the later the inserted position point, the smaller the fine adjustment control word, and the fine adjustment control word for the last position point is the smallest fine adjustment control word within that FM band.

[0129] For ease of distinction, the fine-tuning control word in the rising frequency band is referred to as the first fine-tuning control word, and the fine-tuning control word in the falling frequency band is referred to as the second fine-tuning control word. Based on this, referring to Figure 7, let's still take the first two rising and falling frequency bands as examples. In the first rising frequency band, there are three FM bands, all of which belong to the rising frequency band. Therefore, the first fine-tuning control word in each FM band increases from small to large. In the first falling frequency band, there are three FM bands, all of which belong to the falling frequency band. Therefore, the second fine-tuning control word in each FM band decreases from large to small. Similarly, in the second rising frequency band, there are six FM bands, all of which belong to the rising frequency band. Therefore, the first fine-tuning control word in each FM band increases from small to large. In the second falling frequency band, there are six FM bands, all of which belong to the falling frequency band. Therefore, the second fine-tuning control word in each FM band decreases from large to small.

[0130] In summary, the coarse adjustment control word is mainly used to divide the FM bands, while the fine adjustment control word is used to indicate the frequency values ​​at various positions within each FM band. Therefore, by combining the coarse and fine adjustment control words, the oscillator 420 can be driven to output a well-defined waveform. The better the accuracy of the fine and coarse adjustment control words, the better the linearity of the output waveform.

[0131] II. Processing Unit.

[0132] As described above, the processing unit 430 can control the input frequency signal θ. in The phase error signal ERR and the frequency adjustment signal TW are used to determine the frequency modulation signal θ. outThe boundary frequencies and modulation slopes of each frequency modulation band in the PLL are defined. The boundary frequencies are used to compensate for frequency overlap nonlinearity in the existing PLL, while the modulation slopes are used to compensate for tuning gain nonlinearity in the existing PLL. These two parts will be explained in detail below.

[0133] Compensation for frequency overlap nonlinearity

[0134] Optionally, the boundary frequencies of each FM band are determined based on the frequency control signal θ. in The frequency control signal θ, obtained from the fine-tuning control signal in the frequency adjustment signal TW, is used to compensate for the frequency overlap nonlinearity in the existing phase-locked loop. For ease of understanding, the frequency control signal θ shown in Figure 7 will still be used below. in Taking the fine-tuning control signal as an example, we will introduce the specific compensation method.

[0135] In one possible implementation, combining Figures 5 and 7 above, the frequency control signal θ in During the rising frequency segment, processing unit 430 can detect whether the first fine-tuning control word at each position reaches the first threshold. When the first fine-tuning control word at a certain position reaches the first threshold, the position is recorded as a first position, and the corresponding first fine-tuning control word is also recorded. The recorded first position and first fine-tuning control word are then output to logic unit 440. The first fine-tuning control word recorded here is the overlap compensation value of the rising frequency segment. The solid arrow at the bottom of Figure 7 indicates the timing of recording the first fine-tuning control word, which is the first position.

[0136] Optionally, the first threshold can be set to a relative value, such as the maximum value among all first fine-tuning control words within a frequency modulation band. That is, within each frequency modulation band in the frequency rise phase, if the first fine-tuning control word reaches the maximum value within the current frequency modulation band, the current position is recorded as the first position, and the first position and the corresponding first fine-tuning control word are output to the logic unit 440.

[0137] Based on this, and referring to Figure 7, in the frequency control signal θ inIn the first frequency rise segment, there are three FM bands. The first fine-tuning control word within each of these three bands increases in size. Therefore, the largest first fine-tuning control word in each band is the fine-tuning control word at the last position in that band. Processing unit 430 records the three last positions of the three FM bands as three first positions and sends these three first positions and their corresponding three first fine-tuning control words to logic unit 440. Similarly, in the second frequency rise segment, there are six FM bands. The first fine-tuning control word within each of these six bands also increases in size. The largest first fine-tuning control word in each band is the fine-tuning control word at the last position in that band. Therefore, processing unit 430 can record the six last positions of the six FM bands as six first positions and send these six first positions and their corresponding six first fine-tuning control words to logic unit 440. This will not be listed exhaustively.

[0138] Alternatively, in another example, the first threshold can be set to the maximum value or a value near the maximum value that the first fine-tuning control word can take, such as 80%, 70%, 60%, 65%, 90%, etc. The first fine-tuning control word can be understood as the value generated after data is stored in a fixed storage space, which is typically a few bits (binary digits), usually 2 or 3 bits, and generally no more than 8 bits. Although the maximum value that the first fine-tuning control word can take is when all bits of the storage space are filled, some bits are usually reserved to carry other data or perform other functions. Therefore, in some scenarios, when the amount of data stored in the storage space reaches a certain percentage of the maximum storage capacity, it can be considered that the storage space is full, or in other words, the first fine-tuning control word has reached the first threshold. This percentage can be set by those skilled in the art according to needs or actual scenarios, for example, it could be 80%, 70%, 60%, 65%, 90%, etc. For example, taking an 80% ratio as an example, if it's a 6-bit storage space, then when 5 bits of it are filled with data, the first fine-tuning control word can be considered to have reached the first threshold. As another example, taking a 60% ratio as an example, if it's a 6-bit storage space, then when 4 bits of it are filled with data, the first fine-tuning control word can be considered to have reached the first threshold. And so on.

[0139] Optionally, only one first position is recorded within a single FM band. For example, within an FM band, when the first fine-tuning control word first reaches a first threshold or the maximum value within that FM band, a first position is recorded, and no further recording is made regardless of whether the first threshold or the maximum value is reached again. This ensures that only one maximum or relatively large first fine-tuning control word is recorded within a single FM band, avoiding frequency overlap within the same FM band.

[0140] Optionally, in the frequency rise segment, since the first fine-tuning control word within each FM band increases in size, the first fine-tuning control word that reaches the first threshold or the maximum value is generally located at or near the last position within that FM band. This position belongs to the boundary region between the current FM band and the next FM band, also known as the overlap region. In other words, the first position is located in the overlap region of adjacent FM bands, and the overlap region can be seen in the elliptical filled region shown in Figure 7.

[0141] Optionally, in the overlapping area of ​​two adjacent FM bands, only one first position is recorded. For example, in an overlapping area, when the first fine-tuning control word first reaches the first threshold or maximum value, a first position is recorded. Afterward, as long as it does not move out of the overlapping area, even if it reaches the first threshold or maximum value again, the first position is not recorded. In this way, it can be ensured that only one recorded first fine-tuning control word exists in the overlapping area of ​​two adjacent FM bands.

[0142] Understandably, existing phase-locked loops (PLLs) record two fine-tuning control words at the boundary between two adjacent frequency modulation (FM) bands. One is the fine-tuning control word at the last position of the previous FM band, as shown by the small square in the fine-tuning control word block diagram in Figure 8, and the other is the fine-tuning control word at the beginning position of the next FM band, as shown by the small triangle in the fine-tuning control word block diagram in Figure 8. Following this recording method, assuming the difference between the fine-tuning control word at the beginning position and the last fine-tuning control word of each FM band is called the fine-tuning control difference, then when the fine-tuning control differences of two adjacent FM bands are different, frequency overlap will occur in the overlapping area of ​​these two FM bands. For example, referring to Figure 8, in the second frequency rise segment, for the beginning positions of the three FM bands enclosed by the large ellipse, there is a sudden drop region. Correspondingly, the output signal will have a region where the frequency suddenly drops, then rises, and then linearly increases. After linear fitting, this region becomes the FM curve shown in Figure 9(A). On this frequency modulation curve, there will be a frequency overlap in the boundary region of two adjacent frequency modulation bands. This is the reason why existing phase-locked loops have frequency overlap nonlinearity.

[0143] In contrast, in the phase-locked loop provided in this application, only one first fine-tuning control word is recorded in the overlapping region of two adjacent frequency modulation bands. When generating the output signal, only the recorded first fine-tuning control word is used in the overlapping region, while the original first fine-tuning control word is still used in the non-overlapping region. Thus, since only one first fine-tuning control word is recorded in the overlapping region, the boundaries of two adjacent frequency modulation bands correspond to the same first fine-tuning control word. The frequency modulation curve after linear fitting based on this first fine-tuning control word is shown in Figure 9(B). Clearly, according to the recording method of this application, the boundaries of two adjacent frequency modulation bands can be aligned, and frequency overlap will not occur in the overlapping region of two adjacent frequency modulation bands, which can compensate for the frequency overlap nonlinearity existing in existing phase-locked loops. Furthermore, since the original fine-tuning control word is still used in the non-overlapping region, it can avoid increasing the workload, improve the compensation speed of overlap nonlinearity, and reduce the frequency modulation delay introduced by adding a negative feedback circuit in the phase-locked loop.

[0144] Alternatively, similar to the frequency rise segment, if the frequency control signal θ in If the frequency band has a frequency drop segment, then in the frequency drop segment, the processing unit 430 can record the position of the second fine-tuning control word in each frequency band that reaches the second threshold or the minimum as a second position, and send the recorded second position and the corresponding second fine-tuning control word to the logic unit 440. The second threshold is a relatively small percentage of the maximum value that the second fine-tuning control word can take, such as 10%, 5%, 15%, 3%, etc. Furthermore, in the overlapping area of ​​two adjacent frequency bands, the second position can be recorded only once. When outputting a signal in the frequency drop segment, the recorded second position and second fine-tuning control word are used in the frequency overlapping area, while other positions still use the original fine-tuning control word. Based on this, the frequency overlap problem existing in the frequency drop segment of the current phase-locked loop can be compensated, such as the frequency overlap problem corresponding to the large elliptical region in the second frequency drop segment in Figure 8.

[0145] Alternatively, in another example, considering that frequency modulation curves are typically symmetrically set with a frequency rise segment and an adjacent frequency fall segment, therefore, if the frequency control signal θ in The frequency range has both rising and falling segments. To reduce the complexity of compensating for frequency overlap in the falling segment, it is also possible to record only the first fine-tuning control word of the rising segment and mirror it to the falling segment.

[0146] For example, referring to Figures 5 and 7 above, in the previous processing flow for the rising frequency segment, processing unit 430 can not only record the first position and the first fine-tuning control word, but also synchronously record the first frequency control word at the first position (i.e., the small rectangle in the frequency control word block diagram shown in Figure 7). Based on the recorded first frequency control word, during the falling frequency segment, the size of the current second frequency control word and the first frequency control word recorded in the rising segment are compared in real time. When the two are equal, the current position is recorded as a second position, and the second position and the corresponding second fine-tuning control word (i.e., the small circle in the fine-tuning control word block diagram shown in Figure 7) are sent to logic unit 440. The second fine-tuning control word recorded here is the overlap compensation value for the falling frequency segment. The dashed arrow at the bottom of Figure 7 indicates the recording time of the second fine-tuning control word, which is the second position.

[0147] Based on the above implementation method, it is equivalent to directly mirroring the first fine-tuning control word recorded for the overlapping region of the frequency rising segment to the overlapping region corresponding to the frequency falling segment. In this way, it can ensure that the overlapping region of the frequency falling segment has only one recorded second fine-tuning control word, and also ensure that the frequency rising segment and frequency falling segment in a sweep waveform are symmetrical. Based on the symmetrical sweep waveform, a regular sweep curve can be fitted more quickly.

[0148] For example, existing phase-locked loops (PLLs) that perform frequency modulation only in the rising and falling segments require frequency difference accumulation and fitting within a narrow time window to obtain a regular sweep curve. The convergence time of these algorithms is typically over 100 sweep cycles, meaning at least 100 sweep cycles are needed for the sweep waveform to stabilize. However, the PLL provided in this application does not require frequency difference accumulation and fitting within a narrow time window. Instead, it directly mirrors the fine-tuning control word of the rising segment to the falling segment, ensuring that each sweep waveform is symmetrical in both the rising and falling segments. Based on these symmetrical sweep waveforms, a regular sweep waveform can be quickly fitted. For instance, verification shows that a stable sweep waveform can be fitted in approximately 2-3 sweep cycles, significantly reducing the PLL's convergence time compared to previous methods.

[0149] Understandably, since the second position and the second fine-tuning control word are obtained by mirroring the first fine-tuning control word of the first position, the relevant content of the first position and the first fine-tuning control word also applies to the second position and the second fine-tuning control word. For example, the second position is also located in the overlapping area of ​​adjacent FM bands. For another example, in the frequency drop segment, the second position is recorded only once in the overlapping area of ​​each adjacent FM band. For yet another example, in the frequency drop segment, the second fine-tuning control word of the recorded second position is used in the overlapping area of ​​adjacent FM bands, while other positions still use the original second fine-tuning control word, and so on. These will not be repeated here.

[0150] Based on the above, in summary, for frequency overlap nonlinearity, the processing unit 430 performs frequency jump recording in the frequency rising segment, that is, records the fine-tuning control word boundary value in each FM band. In the frequency falling segment, it directly mirrors the fine-tuning control word of the frequency rising segment by performing an overlap snapshot. The first position and the second position recorded in the frequency rising and frequency falling segments, as well as the corresponding second fine-tuning control word, are used as the overlap compensation value for frequency overlap nonlinearity. The first and second row arrows at the bottom of Figure 7 indicate the recording timing of the fine-tuning control word.

[0151] Understandably, there are many possible structures for the processing unit 430 to achieve the above functions. For example, in one possible structure, the processing unit 430 includes a central processing unit (CPU) with logic analysis capabilities, storage capabilities, and data transmission and reception capabilities, performing all the aforementioned operations. Another possible structure includes a storage unit that stores the first position, first fine-tuning control word, second position, and second fine-tuning control word, and also has a communication interface to support subsequent logic units 440 accessing the internally stored data. Yet another possible structure includes a logic operation unit, or a chip or circuit, and so on.

[0152] In a specific example, please refer to Figure 10, which shows a schematic diagram of the structure of a processing unit provided in this application. This example uses a frequency control word θ. in Taking an example that includes both rising and falling frequency bands, as shown in Figure 10, the processing unit 430 may include a first recorder 4311 and a second recorder 4312. The first recorder 4311 is also called a rising frequency recorder, and the second recorder 4312 is also called a falling frequency recorder. The output terminal of the first recorder 4311 is coupled to the input terminal of the second recorder 4312, and the output terminal of the second recorder 4312 is coupled to the second input terminal c2 of the logic unit 440. The frequency adjustment signal TW output by the logic unit 440 includes a fine-tuning control signal, which includes a fine-tuning control word TW_C at each position in each frequency band. These fine-tuning control words TW_C are input to the first recorder 4311 and the second recorder 4312. Furthermore, the frequency control signal θ... in It will also be input to the first recorder 4311 and the second recorder 4312.

[0153] Based on this, the first recorder 4311 receives the frequency control signal θ in After the fine-tuning control word TW_C at each position, the frequency control signal θ inIn the rising frequency range, if the first fine-tuning control word at the first position is detected to reach the first threshold, the first position, the first fine-tuning control word, and the first frequency control word are recorded, and the recorded first position, the first fine-tuning control word, and the first frequency control word are output to the second recorder 4312. The second recorder 4312 receives the frequency control signal θ. in After the fine-tuning control words TW_C at each position, the first position, the first fine-tuning control word, and the first frequency control word, the frequency control signal θ... in In the frequency drop segment, if the second frequency control word at the second position is detected to be the same as the first frequency control word, the second position and the second fine-tuning control word are recorded. Then, the first position, the second position, the first fine-tuning control word, and the second fine-tuning control word are output together to the logic unit 440. In this way, through the cooperation of the first recorder 4311 and the second recorder 4312, compensation for the overlapping frequency of the frequency rise segment and the frequency drop segment can be achieved.

[0154] Understandably, Figure 10 only uses the frequency control word θ. in Taking an example that includes both a frequency rise segment and a frequency fall segment, we will introduce the possible structures of the processing unit 430. In another example, if the frequency control word θ... in If the frequency control includes a rising segment but not a falling segment, then the processing unit 430 may only include a first recorder 4311, excluding the second recorder 4312. The output of the first recorder 4311 is coupled to the second input c2 of the logic unit 440. The first recorder 4311 sends the recorded first position and the first fine-tuning control word to the logic unit 440. Alternatively, if the frequency control word θ in If the frequency includes a falling segment but not a rising segment, then similar to the recording method described above, the processing unit 430 may only include a third recorder. The output of the third recorder is coupled to the second input c2 of the logic unit 440. The third recorder receives the frequency control signal θ. in And the fine-tuning control word TW_C at each position, in the frequency control signal θ in In the frequency drop-off segment, if the second fine-tuning control word at the second position is detected to be as small as the second threshold, the second position and the second fine-tuning control word are recorded and output to the logic unit. Here, the second threshold can be configured by those skilled in the art based on experience or actual needs. For example, it can be the minimum value within each FM band, or 10%, 20%, or 5% of the maximum value that the second fine-tuning control word can take, etc., without limitation. Of course, other situations may exist, but they can all be deduced from the above description and will not be elaborated here.

[0155] Compensation for tuning gain nonlinearity

[0156] Optionally, the modulation slope of each frequency band is obtained based on the phase error ERR and the coarse adjustment control signal in the frequency adjustment signal TW, and is used to compensate for the nonlinearity of the tuning gain in the existing phase-locked loop.

[0157] For example, taking the coarse adjustment control signal shown in Figure 7 as an example, and combining Figures 5 and 7 above, after receiving the phase error output by the phase detector 410 and the coarse adjustment control signal fed back by the logic unit 440, the processing unit 430 obtains the frequency modulation slope of the frequency modulation band indicated by each coarse adjustment control word in the coarse adjustment control signal based on the phase error fitting. Then, it accumulates the frequency modulation slopes of multiple frequency modulation bands to obtain the target frequency modulation slope, and outputs the target frequency modulation slope to the logic unit 440.

[0158] Understandably, frequency overlap compensation only aligns the boundaries of each FM band. However, the fine-tuning control words at each position within each FM band remain discrete. In other words, the FM curve after frequency overlap compensation may be curved. Therefore, it is necessary to first fit a straight line within each FM band based on the phase error. Then, the slopes of the straight lines within each FM band are accumulated over time to make the slopes of each FM band more consistent, thus obtaining the same FM slope and therefore the same FM gain.

[0159] For example, referring to Figures 7 and 9 above, in the second frequency rise segment shown in Figure 7, the processing unit 430 fits the FM slopes of the three FM bands indicated by the coarse adjustment control words "3", "4", and "5" respectively, so that the FM curves of these three FM bands each exhibit a linear relationship, as shown in (B) of Figure 9. Then, the FM slopes of these three FM bands are accumulated over time, so that the three FM bands have the same FM slope, as shown in (C) of Figure 9.

[0160] Since the segmentation proposed in this invention is based on the current coarse adjustment control word rather than the frequency control word, the boundaries of each segment in the FM gain compensation stage can be naturally aligned with the boundaries of the FM bands used in the frequency overlap compensation stage. The frequency overlap nonlinear compensation keeps the boundaries of adjacent FM bands aligned, while the FM gain nonlinear compensation keeps the slopes of each FM band consistent. In this way, the FM curve after the combination of frequency overlap compensation and FM gain nonlinear compensation can have a better linear relationship, such as appearing as a regular straight line.

[0161] Understandably, there are many structures for the processing unit 430 that can achieve the above functions. For example, it can be implemented through a central processing unit, a memory unit, a logic unit, a chip, or a circuit, etc., without limitation.

[0162] In a specific example, referring to Figure 10, the processing unit 430 may include a slope calibrator 4321 and an accumulator 4322. The slope calibrator 4321 is also called a piecewise slope fitter. The input of the slope calibrator 4321 is coupled to the output of the phase detector 410, and the output of the slope calibrator 4321 is coupled to the input of the accumulator 4322. The output of the accumulator 4322 is coupled to the second input c2 of the logic unit 440. The frequency adjustment signal TW output by the logic unit 440 includes a coarse adjustment control signal, which includes a coarse adjustment control word TW_F for each frequency band. These coarse adjustment control words TW_F are input to the slope calibrator 4321. After receiving these coarse adjustment control words and the phase error ERR output by the phase detector 410, the slope calibrator 4321 fits the FM slope of the FM band indicated by each coarse adjustment control word according to the phase error ERR, and outputs it to the accumulator 4322. The accumulator 4322 accumulates the FM slopes of multiple FM bands to obtain the target FM slope, and outputs it to the logic unit 440.

[0163] Optionally, after the phase error ERR output by the phase detector 410 and the coarse adjustment control word TW_F output by the logic unit 440 are both sent to the slope calibrator 4321, the slope calibrator 4321 can use each FM band indicated by the coarse adjustment control word as a reference and assign a fitting slope to each FM band based on the principle of minimizing frequency difference, called the sweep slope. For example, the sweep slope of each FM band can be fitted using the least squares method to obtain the optimal fitting slope value that minimizes the frequency difference. Here, the frequency difference can be understood as the frequency error between the actual output FM signal and the desired FM signal. The frequency and time in the desired FM signal have a linear relationship, satisfying the form y = kx + b. By testing the sweep curve in the 1G to 5.3G broadband range in advance, and then connecting the start and end frequency points of each FM band to form a straight line, this straight line can be used as the desired FM signal. Based on the desired frequency modulation signal, after fitting a frequency modulation slope, the frequency difference between the output frequency modulation signal and the desired frequency modulation signal can be calculated. Then, it is determined whether the frequency difference is 0. If it is not 0, the fitting continues until a frequency modulation signal with a frequency difference of 0 is fitted. The current frequency modulation slope is then used as the frequency modulation slope within the current frequency modulation band.

[0164] Furthermore, after fitting the modulation slope of each FM band, the modulation slopes are accumulated over time (e.g., summed and averaged). Since the modulation slope of each FM band maintains the minimum frequency difference, the accumulated modulation slope also satisfies the criterion of minimum frequency difference, and also ensures that the modulation slopes of each FM band remain consistent. The frequency difference of existing FM signals is mostly around 0.6%, while simulation tests show that using the FM gain nonlinear compensation method provided in this application, the frequency difference of the final output FM signal compared to the desired FM signal can be reduced to less than one-thousandth, or even to a few ten-thousandths.

[0165] For example, please refer to Figure 11a, which shows a schematic diagram of the maximum frequency modulation bandwidth and frequency difference curves of the phase-locked loop (PLL) provided in this application at a sweep rate of 26 MHz / μs. Figure 11a(A) shows the frequency modulation bandwidth curve of the PLL in each sweep cycle, and Figure 11a(B) shows the frequency difference curve of the PLL in each sweep cycle. Combining Figure 11a(A) and Figure 11a(B), at a sweep rate of 26 MHz per microsecond, the maximum bandwidth that the PLL can achieve is approximately 5.3 GHz, while the sweep frequency error FM calculated based on the root mean square (RMS) formula is... ERR It is approximately 0.0041%, or 0.41‰.

[0166] For example, please refer to Figure 11b, which shows a schematic diagram of the maximum modulation bandwidth and frequency difference curves of the phase-locked loop (PLL) provided in this application at a sweep rate of 106 MHz / μs. Figure 11b(A) shows the modulation bandwidth curve of the PLL in each sweep cycle, and Figure 11b(B) shows the frequency difference curve of the PLL in each sweep cycle. Combining Figure 11b(A) and Figure 11b(B), at a sweep rate of 106 MHz per microsecond, the maximum bandwidth that the PLL can achieve is approximately 5.35 GHz. The sweep frequency error FM calculated based on the root mean square formula is... ERR It would be approximately 0.0095%, or 0.95‰, which is below one ten-thousandth.

[0167] It is understandable that, in addition to the first recorder 4311, the second recorder 4312, the slope calibrator 4321 and the accumulator 4322 shown above, the processing unit 430 may also include other components.

[0168] For example, in one example, considering that the coarse adjustment control word TW_F is only used to determine the frequency modulation slope during the compensation stage and does not need to be corrected, while the fine adjustment control word TW_C needs to be corrected, the fine adjustment control word TW_C needs to be sent to the oscillator 420 for drive control and also needs to be fed back to the processing unit 430. In order to avoid the feedback fine adjustment control word TW_C affecting the process of the processing unit 430 calibrating the fine adjustment control word TW_C, it is also necessary to distinguish the feedback fine adjustment control word TW_C from the fine adjustment control word TW_C currently calibrated by the processing unit 430. Based on this, in one example, as shown in Figure 12, the phase-locked loop 400 may also include a delay circuit 470. The delay circuit 470 is coupled between the output terminal c3 of the logic unit 440 and the input terminal of the processing unit 430, more specifically, it is coupled between the fine adjustment control signal output terminal of the logic unit 440 and the fine adjustment control signal receiving terminal of the processing unit 430. The fine-tuning control signal output by logic unit 440 first enters delay circuit 470 for delay processing, and then is output to processing unit 430 for fine-tuning control word correction in overlapping areas. For example, it is output to the first recorder 4311 in processing unit 430 to record the first fine-tuning control word when each frequency modulation band first reaches the first threshold in the frequency rising segment.

[0169] By setting a delay circuit 470 in the phase-locked loop 400, the fine-tuning control signal input to the processing unit 430 can be delayed by one beat compared to the fine-tuning control signal output by the logic unit 440. Therefore, the processing unit 430 can accurately distinguish between the feedback fine-tuning control signal and the fine-tuning control signal it is correcting. The time delay between the two feedback processing of the fine-tuning control signal by the processing unit 430 can ensure that the processing unit 430 accurately executes the calibration operation of the fine-tuning control word each time.

[0170] III. Logic Units.

[0171] Optionally, the logic unit 440 can be an adder, which can sum the input signals to obtain the output signal.

[0172] For example, referring to Figure 10, the logic unit can add the overlap compensation value (including the first position and the first fine-tuning control word, or the second position and the second fine-tuning control word) output by the processing unit 430, the fitting slope output by the processing unit 430, and the filtered phase error output by the filter 450 to obtain the frequency adjustment signal TW. This frequency adjustment signal TW serves as the final oscillator control word. On the one hand, it is output to the oscillator 420 to drive the oscillator 420 to output a linear frequency modulation signal, thereby achieving linear fitting of multiple frequency bands and realizing a smaller frequency error. On the other hand, it is fed back to the processing unit 430 to realize adaptive digital predistortion processing of the frequency adjustment signal TW.

[0173] IV. Phase detector.

[0174] Optionally, the phase detector 410 can be any type of device or combination of devices capable of identifying the phase difference between two signals, such as including but not limited to: frequency phase detector, diode balanced phase detector, sampling phase detector, multiplication phase detector, logic gate phase detector, etc., without limitation.

[0175] In some scenarios, when the phase-locked loop 400 is a digital phase-locked loop, the phase detector 410 may specifically include a time-to-digital converter (TDC). The TDC can calculate the time difference between two input signals and decode the time difference into a digital signal.

[0176] V. Filters.

[0177] The Filter 450, also known as a loop filter, is a linear low-pass filter. Its basic principle is to use a feedback loop to add part of the output signal to the input signal in order to filter and enhance the signal, such as filtering out high-frequency components and noise in the input signal.

[0178] Optionally, filter 450 can be any type of low-pass filter, such as, but not limited to: active low-pass filter, passive low-pass filter, digital low-pass filter, switched capacitor low-pass filter, resistor-capacitance (RC) low-pass filter, resistor-resistor (LR) low-pass filter, etc.

[0179] VI. Frequency Divider

[0180] Optionally, the frequency divider 460 can be any type of device or combination of devices capable of performing frequency division. For example, it can be a multi-modulus divider (MMD), or include MMD and other devices such as dividers of two, dividers of four, triggers, etc., without limitation.

[0181] The above content describes the structure and function of the basic components included in the phase-locked loop 400. To facilitate understanding by those skilled in the art, a specific digital circuit architecture of the phase-locked loop 400 provided in this application is given below, using a digital phase-locked loop as an example.

[0182] Please refer to Figure 13, which shows a detailed circuit structure diagram of a phase-locked loop (PLL). As shown in Figure 13, it is assumed that the oscillator in the PLL is a digitally controlled oscillator (DCO), including a 6D-fine bank and a 6D-coarse bank. The phase detector is a time-to-digital converter (TDC), the frequency divider is a multi-mode divider (MMD), and the processing unit is an overlap-snapshot posterior-segment digital pre-distortion processor (OSPS-PDP), or simply a digital pre-distortion processor. The filter is a loop filter, specifically including Kp (the gain coefficient of the filter) in the figure, adder 11, adder 12, and delay circuit 21 (Z in the figure). -1 21 represents a one-beat delay of the signal. The logic unit is adder 13.

[0183] As shown in Figure 13, in addition to the components mentioned above, the phase-locked loop can also include other components, such as a four-divider (DIV4), a ramp tracker, a decision unit 31, an adder 14, a Q-flip-flop, and a delay circuit 22. Among these, the adder 14, the Q-flip-flop, and the delay circuit 22 are mainly used to form the feedback loop for the fine-tuning control word TW_C. The coupling relationships of each component can be directly referred to in Figure 13 and will not be explained in detail here. The following mainly describes the functional implementation of the circuit.

[0184] The numerically controlled oscillator (DOC) is mainly used to output a frequency modulation (FM) signal. This FM signal serves as the output of the phase-locked loop (PLL) and is also input to the frequency divider (DIV4). In DIV4, the frequency is divided by four, reducing the sweep frequency by a factor of four before entering the MMD (Multi-channel oscillator). The MMD receives the divided FM signal and awaits an external FM control signal. When the FM control signal arrives, the MMD adjusts the division ratio based on the constantly changing FCW (Frequency Control Word) within the FM control signal. It then uses this adjusted division ratio to further divide the FM signal, bringing its frequency to the reference signal REF while simultaneously satisfying the continuous sweep requirement. The MMD inputs the divided FM signal to the TDC (Transmitter Controlled oscillator). The TDC calculates and decodes the time difference between the divided FM signal and the reference signal REF to obtain the phase error ERR_F. This phase error ERR_F is then output to the loop filter and the ramp tracker. In the loop filter, the phase error ERR_F is multiplied by the filter's gain coefficient Kp before entering the adder 11.

[0185] In addition to receiving the phase error, the ramp tracker also receives the frequency modulation polarity (FM Polarity) signal. The ramp tracker performs ramp tracking based on the FM Polarity signal and the phase error ERR_F, obtains the tracking result, and outputs the tracking result to the judgment unit 31, as well as to the digital predistortion processor. The FM Polarity signal is also output to the digital predistortion processor. The digital predistortion processor also receives the frequency control word FCW, the coarse adjustment control word TW_F, and the fine adjustment control word TW_C. When it is determined that the phase-locked loop is not unstable based on the FM Polarity signal and the tracking result input from the ramp tracker, it performs overlapping frequency nonlinearity compensation based on the frequency control word FCW and the fine adjustment control word TW_C to obtain the overlapping compensation value Ci (including each first position and the first fine adjustment control word, or also including each second position and the second fine adjustment control word), and outputs the overlapping compensation value Ci to the adder 13. Furthermore, frequency modulation gain nonlinearity compensation is performed based on the modulation control word TW_F to obtain the slope compensation value Si, and the slope compensation value Si is output to the judgment unit 31.

[0186] The judgment unit 31 determines whether the phase-locked loop (PLL) is currently in a stable state based on the tracking result input from the ramp tracker. If not, it indicates that the PLL is unstable, and to protect the PLL, initialization can be performed. Conversely, if the PLL is currently in a stable state, the slope compensation value S input from the digital predistortion processor is applied. i The output is sent to adder 11. This slope compensation value S i The phase error ERR_F, multiplied by the filter gain coefficient Kp, is added to adder 11. The sum is then input to adder 12, where it is added to the delay signal fed back from delay circuit 21. The sum is output to adder 14 and simultaneously enters delay circuit 21 for delay. The delayed signal, in addition to being fed back to adder 12, also enters adder 13, where it is added to the overlap compensation value Ci input from the digital predistortion processor to obtain the frequency adjustment signal.

[0187] The frequency adjustment signal includes a coarse adjustment control word TW_F and a fine adjustment control word TW_C. The coarse adjustment control word TW_F is output to the 6D coarse adjustment capacitor array of the DCO for coarse adjustment of the capacitor array, and is also directly fed back to the digital predistortion processor to determine the new slope compensation value Si, thus achieving adaptive predistortion processing of the slope compensation value Si. The fine adjustment control word TW_C is output to the 6D fine adjustment capacitor array of the DCO for fine adjustment of the capacitor array, and is also fed back to the digital predistortion processor. Specifically, the feedback link first adds the signal output from adder 12 to adder 14, then samples the signal through a Q-flip-flop. The sampled signal is then delayed by one clock cycle through delay circuit 22 and sent to the digital predistortion processor to determine the new overlap compensation value Ci, thus achieving adaptive predistortion processing of the overlap compensation value Ci.

[0188] The phase-locked loop (PLL) structure shown in Figure 13 is equivalent to introducing a negative feedback circuit into the existing PLL structure. This negative feedback circuit employs digital predistortion technology, which can quickly fit and compensate for the frequency band overlap nonlinearity and tuning gain nonlinearity of multi-band CNC oscillators during continuous wave frequency modulation (CWFM), supporting various sweep bandwidths and sweep cycles. This digital predistortion technology has adaptive capabilities, solving the frequency jump problem of multi-band CNC oscillators during continuous frequency sweeps, reducing the impact of environmental factors such as temperature and voltage on circuit characteristics, such as changes in the frequency modulation curve, and ensuring that the final sweep waveform has good linearity. It is applicable to triangular wave frequency modulation or other CNC oscillators with various waveforms, frequency bands, and tuning characteristics. Simultaneously, this PLL structure employs overlap fitting and tuning gain nonlinearity fitting methods, enabling rapid convergence of the fitting algorithm. Compared to the convergence time of over 100 sweep cycles for existing algorithms, the convergence time of this invention is significantly shortened.

[0189] It should be noted that the phase-locked loop architecture shown in Figure 13 is only an example. In other examples, the phase-locked loop may include more, fewer, or different structures, and each structure may include more, fewer, or different components. This application does not make any specific limitations in this regard.

[0190] The phase-locked loops described above can be applied to chips or circuits, such as radio frequency chips or radio frequency circuits.

[0191] Taking a radio frequency (RF) circuit as an example, please refer to Figure 14, which shows a possible structural schematic diagram of an RF circuit provided in this application. The RF circuit 1400 includes a phase-locked loop (PLL) 400, which can be the PLL described in any of the above embodiments, such as the PLL 400 in any of the figures 4, 5, 10, 12, and 13.

[0192] Optionally, as shown in Figure 14, the RF circuit 1400 may further include a waveform generator 1410. The output of the waveform generator 1410 is coupled to the input of the phase-locked loop 400, and the first output of the phase-locked loop 400 (the output on the left side of the figure) is coupled to the transmitter T of the RF circuit 1400. When the RF circuit 1400 is operating, the waveform generator 1410 can generate a frequency control signal θ. in and the frequency control signal θ in The output is sent to the phase-locked loop 400, which controls the frequency based on the reference signal Ref and the frequency control signal θ. in Generate frequency modulation signal θ out and the frequency modulation signal θ out The output to the transmitter T of the RF circuit 1400 causes the frequency modulation signal θ to... out It is emitted to the outside of the radio frequency circuit 1400 through the transmitter T.

[0193] It should be noted that the circuit for generating the reference signal Ref can be located outside the phase-locked loop 400 or locally within the phase-locked loop 400. Figure 14 shows the former as an example. In this case, the phase-locked loop 400 can also have another input terminal, which is coupled to the circuit for generating the reference signal Ref, and is used to receive the reference signal Ref generated by this circuit.

[0194] Optionally, to increase the power of the signal emitted from the transmitter T, as shown in Figure 14, the RF circuit 1400 may further include a power amplifier (PA) 1420. PA1420 is coupled between the first output terminal of the phase-locked loop 400 and the transmitter T, and is used to modulate the frequency-modulated signal θ output by the phase-locked loop 400. out The signal is amplified before output. By amplifying the signal power before output, the signal can be transmitted to a farther location, meeting the needs of long-distance transmission. For example, in the field of detection, it can detect targets at greater distances, improving ranging capabilities.

[0195] The above content introduced the relevant components of the transmitting path of the RF circuit 1400. In some scenarios, the RF circuit 1400 may also include a receiving path, through which the RF circuit 1400 processes the returned signal (called the echo signal). The possible components of the receiving path will be described below.

[0196] In one example, as shown in Figure 14, the RF circuit 1400 may further include a mixer 1430, which is coupled between the receiver R of the RF circuit 1400 and the second output terminal (the output terminal shown below) of the phase-locked loop 400. The phase-locked loop 400 receives the frequency control signal θ output from the waveform generator 1410. in In the future, we can first control the frequency signal θin The reference signal Ref is used to generate the output signal, and then a portion of the output signal is used as the frequency modulation signal θ. out One portion is output to the transmitter T, while the other portion is output as the local oscillator signal to mixer 1430. Frequency modulation signal θ out The signal emitted from the transmitter T to the radio frequency circuit 1400 corresponds to the echo signal (or, in the detection range, the frequency modulation signal θ). out The signal reflected back from the target after being illuminated (and may also include interference signals) is received by the receiver R and enters the mixer 1430. The mixer 1430 mixes the echo signal from the receiver with the local oscillator signal to obtain the intermediate frequency (IF) signal.

[0197] Optionally, due to the local oscillator signal and the frequency modulation signal θ out Both are derived from the same output signal; therefore, the local oscillator signal and the frequency modulation signal θ out Same frequency. Based on this, when the mixer 1430 performs mixing operation, it can only perform mixing operation on the part of the echo signal with the same frequency as the local oscillator signal, while the part with different frequencies is directly ignored, so as to reduce noise interference and improve the accuracy of the intermediate frequency signal.

[0198] Optionally, to avoid the separation of the local oscillator signal having a significant impact on the radio frequency transmission process, a small portion of the output signal with high power can be used as the local oscillator signal and output to mixer 1430, while the majority of the signal with high power can be used as the frequency modulation signal θ. out The output is sent to the transmitter T. This ensures that the frequency modulation signal θ is... out It transmits to the farthest possible location while ensuring that there is a local oscillator signal on the receiving path for reference mixing.

[0199] Optionally, to improve the accuracy of the mixing operation, as shown in Figure 14, the RF circuit 1400 may further include a low-noise amplifier (LNA) 1440. The LNA 1440 is coupled between the receiver R and the mixer 1430 of the RF circuit 1400, and is used to amplify the echo signal from the receiver R with low noise before outputting it. The LNA is typically used in conjunction with the receiver to amplify the effective components of the signal received by the receiver, while reducing the introduction of its own and external noise, thereby improving the signal-to-noise ratio and reception quality of the received signal. By outputting the echo signal processed by the LNA to the mixer 1430, the mixing quality of the mixer 1430 can be improved, that is, the accuracy of the intermediate frequency signal can be improved.

[0200] Optionally, as shown in Figure 14, the RF circuit 1400 may further include a high-pass filter (HPF) 1450. The HPF 1450 is coupled between the output terminal of the mixer 1430 and the output terminal M of the RF circuit 1400, and is used to perform high-pass filtering on the intermediate frequency (IF) signal output from the mixer 1430 before output. High-pass filtering removes low-frequency components from the IF signal, allowing only IF or high-frequency components to pass through, ensuring that the IF signal output to subsequent components is free of low-frequency noise.

[0201] Optionally, as shown in Figure 14, the RF circuit 1400 may also include an intermediate frequency amplifier (IF-AMP) 1460. The IF-AMP 1460 is coupled between the output terminal of the high-pass filter 1450 and the output terminal M of the RF circuit 1400, and is used to amplify the power of the filtered intermediate frequency signal output by the high-pass filter 1450, so that subsequent components can more easily detect the intermediate frequency signal and improve the detection sensitivity.

[0202] Optionally, as shown in Figure 14, the RF circuit 1400 may also include an analog-to-digital converter (ADC) 1470. The ADC 1470 is coupled between the output terminal of the IF-AMP 1460 and the output terminal M of the RF circuit 1400, and is used to receive the intermediate frequency signal output by the IF-AMP 1460, and convert the intermediate frequency signal from a continuous analog signal into a discrete digital signal, so as to facilitate the sampling and analysis of subsequent components.

[0203] Optionally, as shown in Figure 14, the RF circuit 1400 may further include a fast fourier transform (FFT) 1480. The FFT 1480 is coupled between the output of the ADC 1470 and the output M of the RF circuit 1400, and is used to perform a Fourier transform on the digital signal output from the ADC 1470, converting the digital signal from the time domain to the frequency domain, and outputting it to the output M of the RF circuit 1400. The frequency domain signal is then output through the output M to the next stage component of the RF circuit 1400 to determine some characteristics in the frequency domain.

[0204] It should be noted that the RF circuit architecture shown in Figure 14 is only an example. In other examples, the RF circuit may include more, fewer, or different structures, and each structure may include more, fewer, or different components. This application does not make any specific limitations in this regard.

[0205] Based on the structure and functional principles of the phase-locked loop or radio frequency circuit described above, this application can also provide a terminal device.

[0206] Please refer to Figure 15. The terminal device 1500 may include the phase-locked loop (PLL) described above, such as the PLL 400 in Figures 4, 5, 10, 12, and 13. Alternatively, it may include the radio frequency (RF) circuit described above, such as the RF circuit 1400 shown in Figure 14. Figure 15 uses the latter as an example.

[0207] Optionally, as shown in Figure 15, the terminal device 1500 may further include a processor 1510 and a memory 1520. The memory 1520 is used to store programs or instructions. The processor 1510 is used to call the programs or instructions in the memory 1520 to control the operation of the aforementioned radio frequency circuit 1400. Optionally, the processor 1510 may also receive information from the radio frequency circuit 1400, such as information in the frequency domain, and control other components in the terminal device to perform corresponding operations based on this information.

[0208] For example, in one example, terminal device 1500 could be a detection device or a vehicle equipped with a detection device. The detection device could be, for example, a lidar or millimeter-wave radar, installed outside the vehicle to detect information about targets outside the vehicle, such as speed and / or distance. In specific implementations, radio frequency circuit 1400 can transmit frequency-modulated signals into the detection space outside the vehicle and receive echo signals reflected back from targets in the detection space. It then processes the echo signals to obtain relevant target information, such as the target's distance and / or speed. Radio frequency circuit 1400 can also output the target information to processor 1510. Processor 1510 uses this information to perform vehicle path planning, braking, or starting. For example, latitude and longitude can be used to determine the vehicle's position, or speed and orientation can be used to determine the vehicle's future direction and destination, or the distance to surrounding objects can be used to determine the number and density of obstacles around the vehicle.

[0209] Alternatively, in some scenarios, the detection device can also be installed inside the vehicle for purposes such as liveness detection or recognition of driver and passenger seat operations. Taking liveness detection as an example, when the vehicle is powered off, doors are closed, windows are closed, and doors are locked, the radio frequency circuit 1400 can transmit frequency-modulated signals into the cabin space, especially the rear seat space, and receive echo signals reflected back from objects on the rear seats. Based on the echo signals, it identifies breathing frequencies. If it determines that an object on the seat has a specific breathing frequency, it identifies the object as a live person, and the radio frequency circuit 1400 notifies the processor 1510 of the presence of a live person in the vehicle. The processor 1510 then controls relevant vehicle components based on this information, such as controlling the headlights to flash and the horn to sound an alarm, or it can call the communication module to send text messages or make phone calls to the vehicle owner.

[0210] For example, in another example, terminal device 1500 can be a sensor, or a device integrating sensors, such as a smart home device. The sensor can be a millimeter-wave sensor, radar sensor, perception sensor, or AI super-sensing sensor, etc. Sensors can be integrated into smart home devices to assist in achieving whole-house intelligence. For example, a sensor can be mounted on the ceiling to detect user activity in the room in real time and notify the main control unit of the smart home device, such as processor 1510. Based on the user activity, processor 1510 controls the devices in the room to perform corresponding operations, such as turning on the lights in a room when a user enters, recording the user's sleep patterns while the user is sleeping, or calling a medical emergency number when a user falls or faints, and so on.

[0211] It is understandable that the terminal device 1500 can also have other application scenarios, which will not be listed here.

[0212] The processor 1510 may include one or more processing units. For example, the processor 1510 may include an application processor (AP), an image signal processor (ISP), a controller, a digital signal processor (DSP), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Different processing units may be independent devices or integrated into one or more processors.

[0213] The memory 1520 described above includes, but is not limited to, random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. Exemplarily, the storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside within an ASIC.

[0214] Understandably, in addition to the radio frequency circuit 1400, processor 1510 and memory 1520, the terminal device 1500 may also include other components, such as wireless communication devices.

[0215] Furthermore, the aforementioned terminal equipment, RF circuits, or phase-locked loops can be extended to any device or system requiring linear frequency modulation. For example, they can be applied to other in-vehicle equipment, such as camera devices, seat adjustment devices, or other types of sensors, or to other means of transportation besides vehicles, including but not limited to ships, airplanes, high-speed trains, trains, helicopters, lawnmowers, and mobile robots. Alternatively, they can be applied to smart terminals, such as mobile phones, computers, tablets, PDAs, desktop computers, headphones, speakers, wearable devices, in-vehicle equipment, virtual reality devices, and augmented reality devices. They can also be applied to robots, surveying equipment, drones, projectors, surveillance cameras, printers, smart home devices, smart industrial equipment, smart manufacturing equipment, or smart transportation equipment, and so on.

[0216] Furthermore, as system architecture evolves and new scenarios emerge, the solutions provided in this application are also applicable to similar technical problems, and this application does not impose any specific limitations on them.

[0217] In the above description, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, E and / or F can represent: E alone, E and F simultaneously, or F alone, where E and F can be singular or plural. In the textual description of this application, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0218] Additionally, in this application, the terms "optionally" or "exemplary" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design described as "optional" or "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or design options. Alternatively, it can be understood that the use of the terms "exemplary" or "optional" is intended to present concepts in a specific manner and does not constitute a limitation of this application.

[0219] It is understood that the various numerical designations used in this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic. The terms "first," "second," "third," and similar expressions are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

Claims

A phase-locked loop, characterized in that include: Phase detector, oscillator, processing unit, and logic unit; The first input terminal of the phase detector is used to receive a reference signal. The second input terminal of the phase detector is coupled to the output terminal of the oscillator. The output terminal of the phase detector is coupled to the first input terminal of the logic unit and the first input terminal of the processing unit. The second input terminal of the logic unit is coupled to the output terminal of the processing unit. The output terminal of the logic unit is coupled to the second input terminal of the processing unit and the input terminal of the oscillator. The third input terminal of the processing unit is used to receive a frequency control signal. The oscillator is used to output a frequency modulation signal according to the frequency adjustment signal output by the logic unit; The phase detector is used to determine the phase error between the frequency modulation signal and the reference signal, and outputs the phase error to the processing unit and the logic unit. The processing unit is configured to determine the boundary frequency and modulation slope of each frequency modulation band in the frequency modulation signal based on the phase error, the frequency control signal, and the frequency adjustment signal. The logic unit is used to perform logical operations on the phase error and the boundary frequencies and modulation slopes of each frequency modulation band in the frequency modulation signal to obtain and output the frequency adjustment signal. The phase-locked loop of claim 1, wherein The frequency adjustment signal includes a fine-tuning control signal, which contains fine-tuning control words at various positions between the start and end positions of each frequency modulation band. The processing unit is specifically configured to: when the frequency rise segment of the frequency control signal detects that the first fine-tuning control word at the first position reaches the first threshold, record the first position and the first fine-tuning control word, and output the first position and the first fine-tuning control word to the logic unit. The phase-locked loop of claim 2, wherein The frequency control signal includes frequency control words at various positions; The processing unit is further configured to: record the first frequency control word corresponding to the first position; when the frequency drop segment of the frequency control signal detects that the second frequency control word of the second position is the same as the first frequency control word, record the second position and the corresponding second fine-tuning control word, and output the second position and the second fine-tuning control word to the logic unit. The phase-locked loop as claimed in claim 2 or 3, characterized in that The first position is located in the overlapping area of ​​adjacent frequency modulation bands. The phase-locked loop as claimed in any one of claims 2 to 4, characterized in that The overlapping area of ​​adjacent FM bands is recorded only once for the first position or only once for the second position. The phase-locked loop as claimed in any one of claims 2 to 5, characterized in that The processing unit includes a first recorder, the input of which is used to receive the frequency control signal and the fine-tuning control signal, and the output of which is coupled to the second input of the logic unit. The first recorder is configured to record and output the first position and the first fine-tuning control word when the first position reaches a first threshold during the rising frequency segment of the frequency control signal. The phase-locked loop of claim 6, wherein The processing unit further includes a second recorder, which is coupled between the output of the first recorder and the second input of the logic unit. The second recorder is configured to, when detecting that the second fine-tuning control word at the second position is the same as the first fine-tuning control word during the frequency drop segment of the frequency control signal, record the second position and the second fine-tuning control word, and output the first position, the second position, the first fine-tuning control word, and the second fine-tuning control word to the logic unit. The phase-locked loop as claimed in any one of claims 2 to 7, characterized in that The phase-locked loop further includes a delay circuit, which is coupled between the output terminal of the logic unit and the second input terminal of the processing unit; The delay circuit is used to delay the fine-tuning control signal output by the logic unit before sending it to the processing unit. The phase-locked loop as claimed in any one of claims 1 to 8, characterized in that The frequency adjustment signal includes a coarse adjustment control signal, which includes a coarse adjustment control word corresponding to each frequency modulation band. The processing unit is specifically used to: within each frequency modulation band indicated by the coarse adjustment control word, to obtain the frequency modulation slope of each frequency modulation band based on the phase error fitting, to accumulate the frequency modulation slopes of multiple frequency modulation bands to obtain the target frequency modulation slope, and to output it to the logic unit. The phase-locked loop of claim 9, wherein The processing unit includes a slope calibrator and an accumulator. The input terminal of the slope calibrator is coupled to the output terminal of the phase detector, the output terminal of the slope calibrator is coupled to the input terminal of the accumulator, and the output terminal of the accumulator is coupled to the second input terminal of the logic unit. The slope calibrator is used to fit the frequency modulation slope of each frequency modulation band indicated by the coarse adjustment control word according to the phase error, and output it to the accumulator. The accumulator is used to accumulate the frequency modulation slopes of the multiple frequency modulation bands to obtain the target frequency modulation slope, and output it to the logic unit. The phase-locked loop as claimed in any one of claims 1 to 10, characterized in that The logic unit is an adder. The phase-locked loop as claimed in any one of claims 1 to 11, characterized in that The phase-locked loop further includes a frequency divider, the first input terminal of which is used to receive the frequency control signal, the second input terminal of which is coupled to the output terminal of the oscillator, and the output terminal of which is coupled to the second input terminal of the phase detector. The frequency divider is used to divide the frequency of the frequency-modulated signal output by the oscillator to a reference frequency according to the frequency control signal, and send the divided frequency-modulated signal to the phase detector, wherein the reference frequency is the frequency of the reference signal. The phase-locked loop as claimed in any one of claims 1 to 12, characterized in that The phase-locked loop also includes a filter, which is coupled between the output of the phase detector and the first input of the logic unit. The filter is used to perform low-pass filtering on the phase error output by the phase detector before outputting it to the logic unit. A radio frequency circuit, characterized by Includes the phase-locked loop as described in any one of claims 1 to 13. The radio frequency circuit of claim 14, wherein It also includes a waveform generator, the output of which is coupled to the input of the phase-locked loop, and the first output of the phase-locked loop is coupled to the transmitter of the radio frequency circuit. The waveform generator is used to generate the frequency control signal and output it to the phase-locked loop; The phase-locked loop is used to generate and output the frequency-modulated signal based on the frequency of the reference signal and the frequency control signal, and the frequency-modulated signal is emitted to the outside of the radio frequency circuit through the transmitting end. The radio frequency circuit as claimed in claim 14 or 15, characterized in that It also includes a power amplifier coupled between the first output terminal of the phase-locked loop and the transmitting terminal; The power amplifier is used to amplify the frequency modulation signal before outputting it. The radio frequency circuit of any one of claims 14 to 16, wherein It also includes a mixer coupled between the receiving end of the radio frequency circuit and the second output end of the phase-locked loop; The phase-locked loop is also used to output the local oscillator signal to the mixer; The mixer is used to mix the echo signal from the receiver with the local oscillator signal to obtain an intermediate frequency signal. A terminal device characterized by comprising: It includes a phase-locked loop as described in any one of claims 1 to 13, or a radio frequency circuit as described in any one of claims 14 to 17. The terminal device of claim 18, wherein The terminal device is a detection device used to measure the distance and / or speed of a target outside the terminal device. The terminal device of claim 18, wherein The terminal device is a sensor, which is used to detect the user status in the first space. The user status is used to assist smart home devices in realizing whole-house smart control of the first space.

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