Method, system and apparatus for remotely updating FPGA device, and storage medium

Abstract

The present application discloses a method, system and apparatus for remotely updating an FPGA device, and a storage medium, which are used for simplifying the update process of the FPGA device. The method of the present application comprises: an ARM processor parses an update file on the basis of an update instruction, and encapsulates a parsing result into packet information in a paginated manner; the ARM processor sends the packet information to an FPGA of a test instrument; and the FPGA parses the received packet information, generates a Flash standard instruction, and performs a read-write operation on a Flash memory so as to update a code of the FPGA.

Description

A method, system, apparatus, and storage medium for remote updating of FPGA devices. Technical Field

[0001] This application relates to the field of embedded technology, and in particular to a method, system, apparatus and storage medium for remotely updating FPGA devices. Background Technology

[0002] In electronic instruments and equipment, FPGA (Field Programmable Gate Array) devices are widely used in the display panel testing industry due to their high flexibility and customizability. The excellent scalability of FPGA devices can support a variety of video interface standards, such as VGA, DVI, HDMI, etc., and can be customized and expanded as needed, enabling designers to quickly respond to market demands and develop display solutions that meet specific application requirements.

[0003] Currently, electronic instruments using FPGAs on the market do not require frequent updates to their FPGA code due to their limited functionality. However, in the display panel testing industry, because the measuring instruments are non-standard customized products, and there are hundreds or even thousands of different display products under test, frequent updates to the FPGA code are necessary to adapt the testing instruments to different display products.

[0004] In existing technologies, FPGA code updates are typically performed using a programmer and specified programming software, or through designated hardware interfaces such as SPI and IIC. However, in real-world environments, test instruments are often integrated with automated equipment, requiring hardware disassembly and reconnection for each update. This process is inconvenient and time-consuming. This is especially true in aging or OTP (Optical Time To Phase) devices, where the number of test instruments in the cluster is large, significantly increasing the workload of FPGA code updates and resulting in low efficiency. Technical issues

[0005] This application provides a method, system, apparatus, and storage medium for remotely updating FPGA devices, which simplifies the update process of FPGA devices and reduces update and maintenance costs. Technical solutions

[0006] This application provides a method, system, apparatus, and storage medium for remotely updating FPGA devices, which simplifies the update process of FPGA devices and reduces update and maintenance costs.

[0007] The first aspect of this application provides a method for remotely updating an FPGA device, including:

[0008] The testing instrument receives update files and update commands from the host computer via the network port;

[0009] The ARM processor of the test instrument parses the update file according to the update instruction and a preset format, and encapsulates the parsing results into message information in pages;

[0010] The ARM processor sends the message information to the FPGA of the test instrument through a serial communication interface;

[0011] The FPGA parses the received message information and generates Flash standard instructions. It then uses these instructions to read and write to the Flash memory to update the FPGA's code.

[0012] Optionally, the ARM processor of the testing instrument parses the update file according to the update instruction and a preset format, and encapsulates the parsing results into paged message information, including:

[0013] The ARM processor of the testing instrument, according to the update instruction, disassembles the update file into several data blocks according to a preset page size;

[0014] The ARM processor encapsulates control instructions and the data block into message information. The control instructions include address configuration instructions, data write operation cache instructions, and trigger instructions.

[0015] Optionally, the FPGA parses the received message information to obtain Flash standard instructions, and performs read and write operations on the Flash memory using the Flash standard instructions, including:

[0016] The FPGA parses the received message information to obtain the write address of the Flash memory and the data block;

[0017] The FPGA generates Flash standard instructions based on the write address of the Flash memory and the data block, and triggers a write operation of the Flash memory through the trigger instructions. The write operation is used to write the data block to the target address.

[0018] Optionally, after the FPGA writes the data block to the target address, the method further includes:

[0019] The FPGA fills the address configuration instruction according to the target address, and triggers the read operation of the Flash memory through the trigger instruction;

[0020] The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent.

[0021] If so, proceed with the write operation for the next data block;

[0022] If not, the update is interrupted and an error message is returned to the host computer.

[0023] Optionally, the method further includes:

[0024] The testing instrument returns the update progress to the host computer in real time, so that the host computer can display the update progress through the progress bar on the UI interface.

[0025] Optionally, the update progress is the percentage of the currently updated data size relative to the total data size of the entire update file.

[0026] Optionally, the Flash memory uses a QSPI interface.

[0027] A second aspect of this application provides a system for remotely updating an FPGA device, comprising: a host computer, an instruction processing unit, and a Flash storage unit, wherein the instruction processing unit and the Flash storage unit are mounted on a test instrument, and the instruction processing unit includes an ARM processing module and an FPGA processing module.

[0028] The host computer is used to send update files and update commands to the instruction processing unit via the network port;

[0029] The ARM processing module is used to parse the update file according to the update instruction in a preset format and encapsulate the parsing result into paged message information according to the parsing result; and send the message information to the FPGA processing module through a serial communication interface.

[0030] The FPGA processing module is used to parse the received message information and generate Flash standard instructions, and to perform read and write operations on the Flash storage unit through the Flash standard instructions to update the FPGA code.

[0031] Optionally, the ARM processing module is further used for:

[0032] According to the update instruction, the update file is disassembled into several data blocks according to the preset page size;

[0033] The ARM processor encapsulates control instructions and the data block into message information. The control instructions include address configuration instructions, data write operation cache instructions, and trigger instructions.

[0034] Optionally, the FPGA processing module is further configured to:

[0035] The received message information is parsed to obtain the write address of the Flash storage unit and the data block;

[0036] Flash standard instructions are generated based on the write address of the Flash storage unit and the data block, and the write operation of the Flash storage unit is triggered by the trigger instruction. The write operation is used to write the data block to the target address.

[0037] Optionally, the FPGA processing module is further configured to:

[0038] The address configuration instruction is filled according to the target address, and the read operation of the Flash storage unit is triggered by the trigger instruction;

[0039] The read data returned by the read operation is compared with the write data to determine whether the read and write data are consistent.

[0040] If so, proceed with the write operation for the next data block;

[0041] If not, the update is interrupted and an error message is returned to the host computer.

[0042] Optionally, the instruction processing unit is used to return the update progress to the host computer in real time, so that the host computer can display the update progress through a progress bar on the UI interface.

[0043] Optionally, the update progress is the percentage of the currently updated data size relative to the total data size of the entire update file.

[0044] Optionally, the Flash storage unit uses a QSPI interface.

[0045] A third aspect of this application provides an apparatus for remotely updating an FPGA device, comprising: a system for remotely updating an FPGA device and a server mounted on the system, wherein the apparatus for remotely updating an FPGA device includes:

[0046] The system includes a host computer, an instruction processing unit, and a Flash storage unit. The instruction processing unit and the Flash storage unit are mounted on the test instrument. The instruction processing unit includes an ARM processing module and an FPGA processing module.

[0047] The host computer is used to send update files and update commands to the instruction processing unit via the network port;

[0048] The ARM processing module is used to parse the update file according to the update instruction in a preset format and encapsulate the parsing result into paged message information according to the parsing result; and send the message information to the FPGA processing module through a serial communication interface.

[0049] The FPGA processing module is used to parse the received message information and generate Flash standard instructions, and to perform read and write operations on the Flash storage unit through the Flash standard instructions to update the FPGA code. Beneficial effects

[0050] The test instrument remotely receives update files and update commands via its network port. The ARM processor of the test instrument automatically parses the update file and encapsulates it into a message. Upon receiving the message, the FPGA automatically executes the update. The entire update process requires no complex manual intervention, reducing operational complexity. Furthermore, it supports simultaneous remote updates of multiple test instrument FPGAs via a local area network, significantly reducing the manpower and time costs required for updates. Moreover, the update method of this application does not require dedicated programming equipment and software, nor does it rely on a specific FPGA device platform. It can update the FPGA using a general-purpose serial interface, reducing additional hardware and software costs and exhibiting good compatibility and scalability. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 is a flowchart illustrating an embodiment of the method for remotely updating an FPGA device provided in this application;

[0053] Figure 2 is a schematic diagram of the hardware connection in the method for remotely updating FPGA devices provided in this application;

[0054] Figure 3 is a flowchart illustrating another embodiment of the method for remotely updating FPGA devices provided in this application;

[0055] Figure 4 is a schematic diagram of an embodiment of the FPGA device remote update system provided in this application;

[0056] Figure 5 is a functional block diagram of the FPGA device remote update system provided in this application;

[0057] Figure 6 is a schematic diagram of an embodiment of the FPGA device remote update device provided in this application. Embodiments of the present invention

[0058] This application provides a method, system, apparatus, and storage medium for remotely updating FPGA devices, which simplifies the update process of FPGA devices and reduces update and maintenance costs.

[0059] Please refer to Figure 1, which illustrates an embodiment of the method for remotely updating an FPGA device provided in this application. The method includes:

[0060] 101. The testing instrument receives update files and update commands from the host computer via the network port;

[0061] In this embodiment, the host computer acts as the control and execution unit for the update process. It receives instructions from the UI software and communicates with the testing instrument (lower-level computer) to complete operations such as transmitting update files and issuing instructions. The UI software, or user interface software, is a part running on the host computer. The UI software provides a graphical user interface to help users intuitively operate and control the entire update process.

[0062] Specifically, the host computer can communicate with multiple test instruments simultaneously via the network port. The network port provides a high-speed, reliable data transmission channel, supporting the host computer to send update files to the test instruments in batches. The host computer first initiates a connection request and transfers the update files to the test instruments via the FTP protocol. After the file transfer is complete, the host computer also sends an update command, which notifies the test instruments to begin processing the update files. Upon receiving the FTP file transfer request from the host computer, the test instruments receive and store the update files in the designated storage area. Once the test instruments receive the update files and the update command, they will initiate the update process and begin executing subsequent update steps.

[0063] 102. The ARM processor of the test instrument parses the update file according to the update instruction and the parsing result is encapsulated into message information in pages according to the preset format.

[0064] Upon receiving an update command from the host computer, the ARM processor of the test instrument triggers an update process. The ARM processor parses the received update file according to a pre-defined format. The purpose of parsing is to extract the valid data from the update file—the data to be written to the FPGA—ensuring the file can be correctly segmented and encapsulated into a suitable transmission message. Update files are typically large, so the ARM processor paginates the file according to a preset page size, dividing the update file into multiple data blocks, each representing a part of the update file. The ARM processor then encapsulates each data block into a message according to the communication protocol requirements. The message contains the data block content, address information, and control instructions. Each message represents a part of the update file, and upon receiving these messages, the FPGA writes the data step-by-step into the Flash memory based on the content of the message.

[0065] 103. The ARM processor sends the message information to the FPGA of the test instrument through the serial communication interface;

[0066] In embedded systems, ARM processors typically work in conjunction with FPGAs to achieve efficient data processing and control. During the remote update process of the FPGA device in this embodiment, the ARM processor is primarily responsible for receiving update commands, parsing update files, and generating corresponding message information, while the FPGA is responsible for updating its own firmware or configuration based on this message information. Therefore, the ARM processor needs to send the encapsulated message to the FPGA via a serial communication interface.

[0067] It should be noted that the ARM processor can ensure the successful transmission of each message through an acknowledgment mechanism during the transmission process. If an error occurs, it will retransmit or terminate the update process.

[0068] 104. The FPGA parses the received message information and generates Flash standard instructions. It then uses these instructions to read and write to the Flash memory to update the FPGA's code.

[0069] FPGAs store firmware code via external Flash memory, allowing them to read and configure the code from Flash after power-on. When the FPGA receives a message from the ARM processor, it first parses the message and generates corresponding Flash standard instructions based on the parsing results. These Flash standard instructions conform to the standard Flash memory protocol, including write, erase, and read instructions. The FPGA then translates the custom instructions from the ARM processor into standard Flash operation instructions. The FPGA then communicates with the Flash memory to execute the specific read and write operations, writing the update file to the designated location in the Flash memory, thereby updating the FPGA code.

[0070] In some specific embodiments, the FPGA connects to the Flash memory via a QSPI interface. Compared to traditional SPI, QSPI uses four data lines for parallel transmission, significantly improving data write and read speeds. Refer to Figure 2, which illustrates the hardware connection between the host computer, ARM processor (embedded system), FPGA, and Flash memory. The host computer communicates with the ARM processor via a network, transmitting data between them via Ethernet or other network protocols. The ARM processor connects to the FPGA through a custom interface, designed to meet specific communication requirements. This custom interface allows the ARM processor to send instructions and data to the FPGA. The FPGA then connects to the Flash memory via the QSPI interface. QSPI is a high-speed serial communication interface that allows the FPGA to communicate with the Flash memory at high data transfer rates, enabling fast read and write operations and improving update efficiency.

[0071] In this embodiment, the test instrument remotely receives update files and update commands via a network port. The ARM processor of the test instrument automatically parses the update file and encapsulates it into a message. After receiving the message, the FPGA automatically executes the update. The entire update process requires no complex manual intervention, reducing operational difficulty. Furthermore, it supports simultaneous remote updates of multiple test instrument FPGAs via a local area network, significantly reducing the manpower and time costs required for updates. Moreover, the update method of this application does not require dedicated programming equipment and software, nor does it rely on a specific FPGA device platform. It can update the FPGA using a general serial interface, reducing additional hardware and software costs and exhibiting good compatibility and scalability.

[0072] The method for remotely updating an FPGA device provided in this application will be described in detail below. Please refer to Figure 3, which shows another embodiment of the method for remotely updating an FPGA device provided in this application. The method includes:

[0073] 301. The testing instrument receives update files and update commands from the host computer via the network port;

[0074] In this embodiment, step 301 is similar to step 101 in the previous embodiment, and will not be described again here.

[0075] 302. The ARM processor of the test instrument, according to the update instruction, disassembles the update file into several data blocks according to the preset page size;

[0076] To efficiently write the update file to the Flash memory, the data must be unpacked into appropriate sizes and transmitted in batches. In this embodiment, the ARM processor needs to unpack the update file received from the host computer into several data blocks according to a preset page size. Each unpacked data block is called a Page, and each Page contains a portion of the data that needs to be written to the Flash memory. The ARM processor sends the data blocks page by page to the FPGA for processing.

[0077] In some specific embodiments, for example, the size of the update file is fixed at 64MB and the preset page size is fixed at 256 bytes. Based on these parameters, the ARM processor splits the 64MB update file into several 256-byte data blocks, that is, it needs to be split into a total of 262,144 pages. The corresponding ARM processor needs to initiate 262,144 write operations, writing the data of one page to a specified address in the Flash memory each time.

[0078] 303. The ARM processor encapsulates control instructions and data blocks into message information. Control instructions include address configuration instructions, data write operation buffer instructions, and trigger instructions.

[0079] During Flash memory write operations, the ARM processor not only needs to split the data block but also configure the address and cache the data according to the Flash memory's operating protocol. To ensure data correctness and efficiency, the ARM processor uses a series of basic control instructions, such as address configuration instructions, trigger instructions, and data write operation caching instructions. These instructions ensure accurate address positioning and data caching for each write operation, thereby enabling the correct writing of the updated file into Flash. Specifically, the ARM processor encapsulates the control instructions and the actual data block into a message, which is transmitted to the FPGA via a serial interface. Each message contains complete address and data information, ensuring that the FPGA can correctly parse and execute the Flash write operation. Message encapsulation and transmission simplify the communication process between the ARM processor and the FPGA, improving overall update efficiency.

[0080] Specifically, these basic commands are shown in the table below:

[0081] In this embodiment, the ARM processor uses the address configuration instruction (0x20) to set the write address of the Flash memory. The address configuration instruction requires four parameters: Addr0, Addr1, Addr2, and Addr3, which represent specific address bits in the Flash memory. These address parameters allow the ARM processor to precisely locate the storage location of each data block in the Flash memory. Through this address configuration method, the ARM processor can ensure that each write operation begins at the correct address, avoiding data write misalignment.

[0082] To improve write efficiency, the ARM processor pre-caches the data block to be written before performing the actual write operation. That is, the data block is cached in the specified cache area through the data write operation cache instruction (0x58) and waits for the final write trigger.

[0083] Furthermore, after the data buffering is complete, the ARM processor uses a trigger instruction (0x63) to initiate a write operation to the Flash memory by the FPGA. The trigger instruction tells the FPGA to perform the actual write operation and returns status information upon completion. The trigger instruction takes a parameter of 1 or 0: passing 1 initiates the write operation; passing 0 completes the operation.

[0084] The ARM processor combines each data block with its associated control instructions and encapsulates them into a unified message. This message is transmitted to the FPGA via a serial interface, where the FPGA executes the write operation to Flash based on the message content. By encapsulating control instructions and data blocks, the ARM processor simplifies communication and control processes, ensuring that each operation is executed smoothly on the FPGA.

[0085] 304. The ARM processor sends the message information to the FPGA of the test instrument through the serial communication interface;

[0086] In this embodiment, step 304 is similar to step 103 in the previous embodiment, and will not be described again here.

[0087] 305. The FPGA parses the received message information to obtain the write address and data block of the Flash memory;

[0088] The FPGA parses the received message information, extracting control instructions and data blocks. These control instructions contain specific opcodes and parameters used to control the interaction between the FPGA and the Flash memory. The Flash memory typically supports a set of standard instructions used to perform basic operations such as reading, writing, and erasing data. These standard instructions are commands that the Flash memory can understand and execute.

[0089] In this embodiment, the FPGA parses the received message information, obtains the write address of the Flash memory through the address configuration instructions carried in the message information, and pre-caches the data block through the data write operation cache instructions carried in the message information.

[0090] 306. The FPGA generates Flash standard instructions based on the write address and data block of the Flash memory, and triggers the write operation of the Flash memory through the trigger instruction. The write operation is used to write the data block to the target address.

[0091] The FPGA parses the received message information, extracting the write address and data block. The write address specifies the location in the Flash memory where data should be written, while the data block contains the actual data to be written. Using this write address and data block, corresponding Flash standard instructions can be generated to control the Flash memory to write the data block to the target address. In practical applications, the FPGA can directly convert the parsed control instructions into Flash standard instructions according to predefined mapping rules.

[0092] The message also includes a trigger command, which the FPGA uses to initiate a write operation to the Flash memory. Under the trigger command, the Flash memory begins the write operation, and the FPGA writes the data from the data block to the target address.

[0093] 307. The FPGA fills the address configuration instruction according to the target address and triggers the read operation of the Flash memory through the trigger instruction;

[0094] After the write operation is complete, it is necessary to check and verify to ensure that the updated data has been correctly written to the Flash memory, thereby ensuring the accuracy and reliability of the FPGA remote update. Specifically, the FPGA fills the address configuration instruction (0x20) according to the target address, which is the location of the previously written data block, and then the FPGA initiates the Flash memory read operation through the trigger instruction (0x63).

[0095] 308. The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent.

[0096] The FPGA reads the data returned from the target address from the Flash memory and compares the read data with the originally written data block to determine if the read and write data are consistent. If the read and write data are consistent, step 309 is executed to continue the update. If the read and write data are inconsistent, the FPGA executes step 310 to interrupt the update process.

[0097] 309. Proceed to the write operation for the next data block;

[0098] If the read and write data are confirmed to be consistent, the FPGA will continue the update process, processing the write operation of the next data block according to the message information, in order to continue the subsequent update process.

[0099] 310. Interrupt the update and return an error message to the host computer;

[0100] If the read data is inconsistent with the written data, the FPGA will interrupt the update process to prevent erroneous data from being used in subsequent operations, ensuring the stability and reliability of the system. In addition, the FPGA needs to return error information to the host computer, triggering error handling procedures such as retrying the update, logging errors, or notifying maintenance personnel; specific actions are not limited here.

[0101] 311. The testing instrument returns the update progress to the host computer in real time, so that the host computer can display the update progress through the progress bar on the UI interface.

[0102] Throughout the remote update process, each testing instrument can report its update progress to the host computer in real time. The host computer's UI displays the update progress intuitively via a progress bar, enhancing the user experience and making the update process more transparent and controllable. Specifically, the update progress can be the percentage of the currently updated data size relative to the total update file size. That is, the testing instrument calculates the updated data size by tracking the amount of data already written to the Flash memory during the update process, and then calculates the progress percentage, thus achieving synchronization with the actual update progress.

[0103] In this embodiment, the ARM processor encapsulates control instructions and data blocks into message information. The FPGA parses the received message information, extracts the control instructions and data blocks, and then parses and converts the control instructions into standard instructions for the Flash memory. Operations are then performed using the standard instruction set, ultimately enabling the ARM processor to read and write to the Flash memory. By mapping control instructions to standard instructions for Flash memory, the FPGA improves compatibility between different devices and memories, reduces dependence on specific hardware, lowers development and maintenance costs, and allows this method to be more widely applied to various combinations of FPGAs and Flash memories.

[0104] The system for remotely updating FPGA devices provided in this application will be described in detail below. Please refer to Figure 4, which shows another embodiment of the system for remotely updating FPGA devices provided in this application. The system includes:

[0105] The host computer 401, instruction processing unit 402 and flash storage unit 403 are mounted on the test instrument. The instruction processing unit 402 includes an ARM processing module 4021 and an FPGA processing module 4022.

[0106] The host computer 401 is used to send update files and update commands to the instruction processing unit 402 via the network port;

[0107] The ARM processing module 4021 is used to parse the update file according to the update instruction and a preset format, and encapsulate the parsing result into paged message information; and send the message information to the FPGA processing module 4022 through the serial communication interface.

[0108] The FPGA processing module 4022 is used to parse the received message information and generate Flash standard instructions. The Flash standard instructions are used to read and write to the Flash storage unit 403 to update the FPGA code.

[0109] Optionally, the ARM processing module 4021 is also specifically used for:

[0110] According to the update instruction, the update file is unpacked into several data blocks according to the preset page size;

[0111] ARM processors encapsulate control instructions and data blocks into message information. Control instructions include address configuration instructions, data write operation buffer instructions, and trigger instructions.

[0112] Optionally, the FPGA processing module 4022 is also specifically used for:

[0113] The received message information is parsed to obtain the write address and data block of Flash storage unit 403;

[0114] Flash standard instructions are generated based on the write address and data block of Flash storage unit 403, and the write operation of Flash storage unit 403 is triggered by the trigger instruction. The write operation is used to write the data block to the target address.

[0115] Optionally, the FPGA processing module 4022 is also used for:

[0116] Fill the address configuration instruction according to the target address, and trigger the read operation of Flash storage unit 403 through the trigger instruction;

[0117] The read data returned by the read operation is compared with the write data to determine whether the read and write data are consistent.

[0118] If so, proceed with the write operation for the next data block;

[0119] If not, the update will be interrupted and an error message will be returned to the host computer 401.

[0120] Optionally, the instruction processing unit 402 is used to return the update progress to the host computer 401 in real time, so that the host computer 401 can display the update progress through the progress bar of the UI interface.

[0121] Optionally, the update progress is the percentage of the currently updated data size relative to the total data size of the update file.

[0122] Optionally, the Flash memory unit 403 uses a QSPI interface.

[0123] In this embodiment, the functions of each unit and module correspond to the steps in the method embodiments shown in Figure 1 or Figure 3 above, and will not be repeated here. Figure 5 is a functional block diagram of the host computer 401, instruction processing unit 402 and Flash storage unit 403 in the FPGA device remote update system provided in this application.

[0124] The entire update process is explained below using the host computer 401, instruction processing unit 402, and Flash storage unit 403 as examples:

[0125] The host computer 401 issues the update file and sends the update command. In addition, the host computer 401 can further check and judge whether the update file is reasonable. If it is not reasonable, the UI software will prompt an error and interrupt the update.

[0126] The instruction processing unit 402 splits the update file, fills a page of data into instruction 0x58, fills the write address into instruction 0x20, and fills trigger 1 to instruction 0x63.

[0127] Flash memory cell 403 parses write instructions and writes data to the corresponding address;

[0128] Instruction processing unit 402 fills the read address into instruction 0x20, which reads one page length at a time by default; filling triggers instructions 1 to 0x63.

[0129] Flash memory cell 403 parses the read instruction and returns the corresponding address data to the FPGA cache;

[0130] The instruction processing unit 402 compares whether the read and write data are consistent. If they are consistent, it fills the next page of data; if they are inconsistent, it interrupts the update and displays an error message.

[0131] This application also provides an apparatus for remotely updating an FPGA device. Please refer to Figure 6, which shows an embodiment of the apparatus for remotely updating an FPGA device provided in this application. The apparatus includes:

[0132] Processor 601, memory 602, input / output unit 603, bus 604;

[0133] The processor 601 is connected to the memory 602, the input / output unit 603, and the bus 604;

[0134] The memory 602 stores a program, which the processor 601 calls to execute the method of remotely updating any of the FPGA devices described above.

[0135] This application also relates to a computer-readable storage medium storing a program that, when run on a computer, causes the computer to perform a method for remotely updating any of the FPGA devices described above.

[0136] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0138] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0139] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for remotely updating an FPGA device, comprising: The testing instrument receives update files and update commands from the host computer via the network port; The ARM processor of the test instrument parses the update file according to the update instruction and a preset format, and encapsulates the parsing results into message information in pages; The ARM processor sends the message information to the FPGA of the test instrument through a serial communication interface; The FPGA parses the received message information and generates Flash standard instructions. It then uses these instructions to read and write to the Flash memory to update the FPGA's code.

2. The method according to claim 1, wherein, The steps of the ARM processor of the testing instrument parsing the update file according to the update instruction and encapsulating the parsing result into paged message information include: The ARM processor of the testing instrument, according to the update instruction, disassembles the update file into several data blocks according to a preset page size; The ARM processor encapsulates control instructions and the data block into message information. The control instructions include address configuration instructions, data write operation cache instructions, and trigger instructions.

3. The method according to claim 2, wherein, The steps of the FPGA parsing the received message information to obtain Flash standard instructions and performing read and write operations on the Flash memory using the Flash standard instructions include: The FPGA parses the received message information to obtain the write address of the Flash memory and the data block; The FPGA generates Flash standard instructions based on the write address of the Flash memory and the data block, and triggers a write operation of the Flash memory through the trigger instructions. The write operation is used to write the data block to the target address.

4. The method according to claim 3, wherein, After the step of the FPGA writing the data block to the target address, the method further includes: The FPGA fills the address configuration instruction according to the target address, and triggers the read operation of the Flash memory through the trigger instruction; The FPGA compares the read data returned by the read operation with the write data to determine whether the read and write data are consistent. If so, proceed with the write operation for the next data block; If not, the update is interrupted and an error message is returned to the host computer.

5. The method according to claim 1, wherein, The method further includes: The testing instrument returns the update progress to the host computer in real time, so that the host computer can display the update progress through the progress bar on the UI interface.

6. The method according to claim 5, wherein, The update progress is the percentage of the currently updated data size relative to the total data size of the updated file.

7. The method according to claim 1, wherein, The Flash memory uses a QSPI interface.

8. A system for remotely updating an FPGA device, comprising: The system includes a host computer, an instruction processing unit, and a Flash storage unit. The instruction processing unit and the Flash storage unit are mounted on the test instrument. The instruction processing unit includes an ARM processing module and an FPGA processing module. The host computer is used to send update files and update commands to the instruction processing unit via the network port; The ARM processing module is used to parse the update file according to the update instruction in a preset format and encapsulate the parsing result into paged message information according to the parsing result; and send the message information to the FPGA processing module through a serial communication interface. The FPGA processing module is used to parse the received message information and generate Flash standard instructions, and to perform read and write operations on the Flash storage unit through the Flash standard instructions to update the FPGA code.

9. The system according to claim 8, wherein, The ARM processing module is used for: According to the update instruction, the update file is disassembled into several data blocks according to the preset page size; The ARM processor encapsulates control instructions and the data block into message information. The control instructions include address configuration instructions, data write operation cache instructions, and trigger instructions.

10. The system according to claim 9, wherein, The FPGA processing module is used for: The received message information is parsed to obtain the write address of the Flash storage unit and the data block; Flash standard instructions are generated based on the write address of the Flash storage unit and the data block, and the write operation of the Flash storage unit is triggered by the trigger instruction. The write operation is used to write the data block to the target address.

11. The system according to claim 8, wherein, The FPGA processing module is used for: The address configuration instruction is filled according to the target address, and the read operation of the Flash storage unit is triggered by the trigger instruction; The read data returned by the read operation is compared with the write data to determine whether the read and write data are consistent. If so, proceed with the write operation for the next data block; If not, the update is interrupted and an error message is returned to the host computer.

12. The system according to claim 8, wherein, The instruction processing unit is used to return the update progress to the host computer in real time, so that the host computer can display the update progress through the progress bar of the UI interface.

13. The system according to claim 12, wherein, The update progress is the percentage of the currently updated data size relative to the total data size of the updated file.

14. The system according to claim 8, wherein, The Flash storage unit uses a QSPI interface.

15. An apparatus for remotely updating an FPGA device, comprising: A system for remotely updating FPGA devices and a server running the system, wherein the apparatus for remotely updating FPGA devices includes: The system includes a host computer, an instruction processing unit, and a Flash storage unit. The instruction processing unit and the Flash storage unit are mounted on the test instrument. The instruction processing unit includes an ARM processing module and an FPGA processing module. The host computer is used to send update files and update commands to the instruction processing unit via the network port; The ARM processing module is used to parse the update file according to the update instruction in a preset format and encapsulate the parsing result into paged message information according to the parsing result; and send the message information to the FPGA processing module through a serial communication interface. The FPGA processing module is used to parse the received message information and generate Flash standard instructions, and to perform read and write operations on the Flash storage unit through the Flash standard instructions to update the FPGA code.

16. The apparatus according to claim 15, wherein, The ARM processing module is used for: According to the update instruction, the update file is disassembled into several data blocks according to the preset page size; The ARM processor encapsulates control instructions and the data block into message information. The control instructions include address configuration instructions, data write operation cache instructions, and trigger instructions.

17. The apparatus according to claim 16, wherein, The FPGA processing module is used for: The received message information is parsed to obtain the write address of the Flash storage unit and the data block; Flash standard instructions are generated based on the write address of the Flash storage unit and the data block, and the write operation of the Flash storage unit is triggered by the trigger instruction. The write operation is used to write the data block to the target address.

18. The apparatus according to claim 15, wherein, The FPGA processing module is used for: The address configuration instruction is filled according to the target address, and the read operation of the Flash storage unit is triggered by the trigger instruction; The read data returned by the read operation is compared with the write data to determine whether the read and write data are consistent. If so, proceed with the write operation for the next data block; If not, the update is interrupted and an error message is returned to the host computer.

19. The apparatus according to claim 15, wherein, The instruction processing unit is used to return the update progress to the host computer in real time, so that the host computer can display the update progress through the progress bar of the UI interface.

20. The apparatus according to claim 19, wherein, The update progress is the percentage of the currently updated data size relative to the total data size of the updated file.

Images