Semiconductor structure and formation method therefor
By arranging doped pillars and body regions in different directions within the epitaxial layer, the problem of limited channel length in superjunction MOS devices was solved, resulting in performance improvement.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2025-09-18
- Publication Date
- 2026-07-30
AI Technical Summary
Existing superjunction MOSFET devices suffer from limited channel length during fabrication, leading to increased resistance and slower switching speed.
The first and second doped pillars are formed in the epitaxial layer and arranged in different directions. A body region is formed in the epitaxial layer and arranged in another direction to avoid the doped pillars limiting the spacing size, thereby increasing the channel length.
By increasing the channel length, the performance of the superjunction MOSFET device is improved, the resistance is reduced, and the switching speed is increased.
Smart Images
Figure CN2025122133_30072026_PF_FP_ABST
Abstract
Description
Semiconductor structure and its formation method
[0001] This application claims priority to Chinese Patent Application No. 202510097730.6, filed on January 21, 2025, entitled "Semiconductor Structure and Method for Forming the Same", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This invention relates to the field of semiconductors, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0003] Superjunction MOSFETs are a new type of high-voltage MOSFET. Their advantages include being able to withstand high voltage while providing an order of magnitude smaller on-resistance than traditional high-voltage MOSFETs. In addition to low on-resistance, they also have the advantages of low power consumption and low switching time.
[0004] However, existing superjunction MOSFET devices still have many problems in their fabrication process. Summary of the Invention
[0005] The technical problem solved by this invention is how to improve the performance of superjunction MOS transistor devices.
[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first surface; forming an epitaxial layer on the first surface using an epitaxial process, the epitaxial layer including a plurality of first regions and a second region located between adjacent first regions, the first regions and the second regions being arranged along a second direction; forming a first photoresist layer having a pattern of the first regions on the epitaxial layer, the first photoresist layer exposing the surface of the first regions; using the first photoresist layer as a mask, etching the epitaxial layer to form trenches located within the first regions; forming first doped pillars within the trenches, and forming a first doped pillar located within the first regions; ... The second doped pillars in the second region, the first doped pillars and the second doped pillars are arranged along a second direction; a second photoresist layer with a body region pattern is formed on the epitaxial layer, the second photoresist layer is arranged along a first direction, the first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction; using the second photoresist layer as a mask, ions are implanted into the epitaxial layer to form a body region, the body region is arranged along the first direction; a gate material layer is formed on the epitaxial layer; using a photolithography process, the gate material layer is etched to expose the body region to form a plurality of gates, each of the gates being discretely located on adjacent body regions.
[0007] Optionally, the step of forming the body region further includes: implanting a first ion into the body region; implanting a second ion into the epitaxial layer between adjacent body regions to form a JFET region.
[0008] Optionally, the type of the first doped column is opposite to that of the second doped column, the type of the first ion is opposite to that of the second ion, and the implantation concentration range of the first ion in the bulk region is 1E12 ions / cm². 2 Up to 1E16 ions / cm 2 The implantation concentration of the second ion within the JFET region ranges from 1E12 ions / cm². 2 Up to 1E16 ions / cm 2 .
[0009] Optionally, after forming several gates, the method further includes: using the gates as a mask, implanting second ions into the body regions on both sides of the gates to form source regions.
[0010] Optionally, the implantation concentration of the second ion in the source region ranges from 1E12 ions / cm³. 2 Up to 1E16 ions / cm 2 .
[0011] Optionally, the substrate further includes a second surface, and after the step of forming the plurality of gates, the substrate further includes: depositing a source metal layer on the plurality of gates; and depositing a drain metal layer on the second surface.
[0012] Accordingly, the present invention also provides a semiconductor structure, comprising: a substrate, the substrate including a first surface; an epitaxial layer located on the first surface, the epitaxial layer including a plurality of first regions and a second region located between adjacent first regions, the first regions and the second regions being arranged along a second direction; a first doped pillar located within the first region; a second doped pillar located within the second region, the first doped pillar and the second doped pillar being arranged along the second direction; a plurality of body regions discretely located within the epitaxial layer, the body regions being arranged along a first direction, the first direction and the second direction being parallel to the substrate surface, and the first direction being perpendicular to the second direction; and a plurality of gates, each of the gates being discretely located on adjacent body regions.
[0013] Optionally, the semiconductor structure further includes: a JFET region located within an epitaxial layer between adjacent body regions, wherein the JFET region has a second ion and the body region has a first ion.
[0014] Optionally, the type of the first doped column is opposite to the type of the second doped column, and the type of the first ion is opposite to the type of the second ion.
[0015] Optionally, the semiconductor structure further includes a source region located within the body regions on both sides of the gate, and the source region contains a second ion.
[0016] Optionally, the substrate further includes a second surface, and the semiconductor structure further includes: a source metal layer located on the plurality of gates; and a drain metal layer located on the second surface.
[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0018] In the semiconductor structure of the present invention, the epitaxial layer includes a first doped pillar and a second doped pillar, which are arranged along a second direction. The epitaxial layer also includes a body region arranged along a first direction. Compared with the prior art solution where the lower surface of the body region also contains a first doped pillar and a second doped pillar, the body region and the first and second doped pillars in the present invention are located in different directions of the epitaxial layer. This avoids the limitation of the spacing size of the superjunction MOS transistor device by the presence of the first and second doped pillars, so that the channel length of the superjunction MOS transistor device is not affected by the spacing size, thereby increasing the channel length and improving the performance of the superjunction MOS transistor device.
[0019] In the semiconductor structure formation method of the present invention, a first doped pillar and a second doped pillar are formed in the epitaxial layer, and the first doped pillar and the second doped pillar are arranged along a second direction to form a body region in the epitaxial layer. The body region is arranged along a first direction. Compared with the prior art solution, which further includes forming the first doped pillar and the second doped pillar on the lower surface of the body region before forming the body region, the body region and the first doped pillar and the second doped pillar in the present invention are located in different directions of the epitaxial layer. This avoids the existence of the first doped pillar and the second doped pillar limiting the spacing size of the superjunction MOS transistor device, so that the channel length of the superjunction MOS transistor device is not affected by the spacing size, thereby increasing the channel length and improving the performance of the superjunction MOS transistor device. Attached Figure Description
[0020] Figure 1 is a schematic diagram of a semiconductor structure;
[0021] Figure 2 is a schematic diagram of another semiconductor structure;
[0022] Figure 3 is a schematic diagram of the test results for a semiconductor structure;
[0023] Figures 4 to 14 are schematic diagrams of the formation process of a semiconductor structure in one embodiment of the present invention. Detailed Implementation
[0024] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0025] The current structure of the superjunction MOS transistor device is shown in Figure 1, including: a substrate, the substrate including a first surface a; an epitaxial layer 100 located on the first surface a; a first doped pillar 101 located on the epitaxial layer 100; a second doped pillar 102 adjacent to the first doped pillar 101; a body region 103 located on the first doped pillar 101; and a plurality of gates 104, each of the gates 104 being discretely located on an adjacent body region 103.
[0026] As can be seen, the gate 104 in the superjunction MOS device is located on the body region 103. Therefore, the superjunction MOS device is a planner gate structure. The channel is located in the body region 103 below the gate 104 and is a horizontal channel, i.e., the red circle 105 in Figure 1. However, the spacing dimension P1 of the superjunction MOS device in the above scheme is the sum of the widths of the first doped pillar 101 and the second doped pillar 102. Consequently, under the limitation of the spacing dimension, the channel length on both sides is also limited, resulting in a reduction in channel length, an increase in resistance, and consequently a slower switching speed of the device, thus reducing the performance of the superjunction MOS device.
[0027] Currently, in order to solve the above problems, the present invention provides another structure for a superjunction MOS transistor device. Please refer to Figure 2. The substrate includes a first surface a; an epitaxial layer 200 located on the first surface a; a first doped pillar 201 located on the epitaxial layer 200; a second doped pillar 202 adjacent to the first doped pillar 201; a body region 203 located on the first doped pillar 201; and a plurality of gates 204 located within the epitaxial layer 200 and adjacent to the body region 203.
[0028] In the above scheme, the gate 204 of the superjunction MOS transistor is located within the epitaxial layer 200, and the gate 204 is adjacent to the body region 203. Therefore, the superjunction MOS transistor has a trench gate structure, and the channel is located within the body region 203 connected to the sidewall of the gate 204. At this time, the channel is a vertical channel, i.e., the red circle part 205 in Figure 2. Furthermore, the spacing dimension P2 of the superjunction MOS transistor in the above scheme is the sum of the widths of the first doped pillar 201 and the second doped pillar 202. Thus, under the constraint of the spacing dimension, the length of the vertical channel is increased relative to the length of the horizontal channel in Figure 1.
[0029] In addition, please refer to Figure 3. Figure 3(a) shows the test results of the Planner gate structure, and Figure 3(b) shows the test results of the Trench gate structure. In Figure 3(a) and Figure 3(b), the horizontal axis represents the gate voltage, and the vertical axis represents the gate current. The gate voltage range of Figure 3(a) is -60V to 80V, and the gate voltage range of Figure 3(b) is -50V to 40V. Therefore, the leakage current of the Trench gate structure is greater than that of the Planner gate structure. That is, due to the inherent problems of the device structure, the Trench gate structure has a large leakage current problem, which will also affect the performance of the superjunction MOS device.
[0030] To address the aforementioned technical problems, the present invention provides a semiconductor structure and its formation method. The epitaxial layer includes a first doped pillar and a second doped pillar, which are arranged along a second direction. The epitaxial layer also includes a body region arranged along a first direction. Compared to the prior art where the lower surface of the body region contains a first doped pillar and a second doped pillar, the body region and the first and second doped pillars in the present invention are located in different directions of the epitaxial layer. This avoids the limitation imposed by the presence of the first and second doped pillars on the spacing dimension of the superjunction MOS transistor, allowing the channel length of the superjunction MOS transistor to be independent of the spacing dimension, thereby increasing the channel length and improving the performance of the superjunction MOS transistor.
[0031] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0032] Please refer to Figures 4 and 5. Figure 4 is a perspective view and Figure 5 is a cross-sectional view along the AA1 direction in Figure 4. A substrate 300 is provided, which includes a first surface a. An epitaxial layer 301 is formed on the first surface a using an epitaxial process.
[0033] In this embodiment, the substrate 300 is made of silicon.
[0034] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0035] In one embodiment, the epitaxial layer 301 is formed by a vapor phase epitaxy process, wherein the thickness of the epitaxial layer 301 ranges from 50 micrometers to 60 micrometers.
[0036] Please refer to Figure 6, which is a perspective view. The epitaxial layer 301 includes a plurality of first regions I and second regions II located between adjacent first regions I. The first regions I and the second regions II are arranged along the second direction Y. A first photoresist layer (not shown in the figure) with a pattern of the first regions I is formed on the epitaxial layer 301. The first photoresist layer exposes the surface of the first regions I. Using the first photoresist layer as a mask, the epitaxial layer 301 is etched to form trenches located in the first regions I. A first doped pillar 3011 and a second doped pillar 3012 located in the second regions II are formed in the trenches (not shown in the figure). The first doped pillar 3011 and the second doped pillar 3012 are arranged along the second direction Y.
[0037] In some embodiments of the present invention, the first doped pillar 3011 is a P pillar and the second doped pillar 3012 is an N pillar.
[0038] In other embodiments, the first doped pillar is an N-pillar and the second doped pillar is a P-pillar.
[0039] In some embodiments of the present invention, after the step of forming the first doped pillar 3011 in the trench, the method further includes: planarizing the top surface of the first doped pillar 3011 until the top surface of the first doped pillar 3011 is flush with the second doped pillar 3012.
[0040] In a specific embodiment, the planarization process includes a chemical mechanical polishing process.
[0041] Please refer to Figure 7, which is a cross-sectional view along the AA1 direction in Figure 6. A second photoresist layer 3021 with a bulk pattern is formed on the epitaxial layer 301. The second photoresist layer 3021 is arranged along the first direction X. The first direction X and the second direction Y are parallel to the surface of the substrate 300, and the first direction X is perpendicular to the second direction Y.
[0042] Please refer to Figure 8, which is in the same orientation as Figure 7. Using the second photoresist layer as a mask, ions are implanted into the epitaxial layer 301 to form a body region 302. The body region 302 is arranged along the first direction X.
[0043] In some embodiments of the present invention, the ions within the body region 302 are first ions, and the implantation concentration range of the first ions within the body region 302 is 1E12 ions / cm³. 2 Up to 1E16 ions / cm 2 .
[0044] In the above scheme, a first doped pillar 3011 and a second doped pillar 3012 are formed in the epitaxial layer 301, and the first doped pillar 3011 and the second doped pillar 3012 are arranged along the second direction Y. A body region 302 is formed in the epitaxial layer 301, and the body region 302 is arranged along the first direction X. Compared with the prior art scheme that includes forming the first doped pillar and the second doped pillar on the lower surface of the body region before forming the body region, the body region 302 and the first doped pillar 3011 and the second doped pillar 3012 in this invention are located in different directions of the epitaxial layer 301. This avoids the existence of the first doped pillar and the second doped pillar limiting the spacing size of the superjunction MOS device, so that the channel length of the superjunction MOS device is not affected by the spacing size, thereby increasing the channel length and improving the performance of the superjunction MOS device.
[0045] Please refer to Figure 9, which is in the same view direction as Figure 8. A second ion is implanted into the epitaxial layer 301 between adjacent body regions 302 to form a JFET region 303.
[0046] In some embodiments of the present invention, the type of the first ion is opposite to the type of the second ion, and the injection concentration range of the first ion in the body region 302 is 1E12 ions / cm³. 2 Up to 1E16 ions / cm 2 The implantation concentration of the second ion within the JFET region 303 is in the range of 1E12 ions / cm³. 2 Up to 1E16 ions / cm 2 .
[0047] In some embodiments of the present invention, the first ion is of type P and the second ion is of type N.
[0048] In other embodiments, the first ion is of type N and the second ion is of type P.
[0049] Please refer to Figure 10, which has the same view orientation as Figure 9. A gate material layer is formed on the epitaxial layer 301. The gate material layer is etched using a photolithography process to expose the body region 302, forming a plurality of gates 304. Each gate 304 is located separately on an adjacent body region 302.
[0050] In a specific embodiment, a gate oxide layer 3042 is formed on the epitaxial layer 301; a gate material layer is formed on the epitaxial layer 301; the gate material layer is etched using a photolithography process to expose the body region 302, forming a plurality of gate layers 3041, each gate 304 being discretely located on an adjacent body region 302.
[0051] In this embodiment, the process for forming the gate oxide layer 3042 is a growth process.
[0052] In this embodiment, the thickness of the gate oxide layer 3042 ranges from 800 angstroms to 1000 angstroms.
[0053] In this embodiment, the gate oxide layer 3042 is made of silicon nitride, silicon oxide, or borosilicate glass.
[0054] In this embodiment, the gate layer 3041 is made of monocrystalline silicon or polycrystalline silicon.
[0055] Please refer to Figure 11, which is in the same view direction as Figure 10. A third photoresist layer (not shown in the figure) is formed on the substrate, and the third photoresist layer exposes part of the gate oxide layer 3042 surface. Using the third photoresist layer as a mask, second ions are implanted into the body regions 302 on both sides of the gate layer 3041 to form source regions 305.
[0056] In some embodiments of the present invention, the implantation concentration of the second ion within the source region 305 is in the range of 1E12 ions / cm². 2 Up to 1E16 ions / cm 2 .
[0057] Please refer to Figure 12, which is in the same view direction as Figure 11. An interlayer dielectric layer 3043 is formed on the sidewall surface and the top surface of the gate layer 3041.
[0058] In some embodiments of the present invention, the process for forming the interlayer dielectric layer 3043 is a chemical vapor deposition process.
[0059] In this embodiment, the material of the interlayer dielectric layer 3043 is silicon nitride or borosilicate glass, and the thickness of the interlayer dielectric layer 3043 ranges from 0.5 micrometers to 1 micrometer.
[0060] Please refer to Figure 13. The view direction of Figure 13 is the same as that of Figure 12. The gate oxide layer 3042 is removed by dry etching process until the body region 302 is exposed.
[0061] In some embodiments of the present invention, the parameters of the dry etching process include: a chamber pressure of 5.5 mT to 50 mT, a source power of 180 watts to 1000 watts, an etching gas comprising one or more of CH2F2, Cl2, HBr, He and O2, a gas flow rate of 20 sccm to 200 sccm, and an etching time of 6 s to 40 s.
[0062] In other embodiments, after removing the gate oxide layer on the body region, the method further includes forming a conductive layer on a portion of the body region.
[0063] The conductive layer is made of titanium and titanium nitride.
[0064] Please refer to Figure 14, which is a perspective view. After the step of forming a plurality of gates 304, the method further includes: depositing a source metal layer 306 on the plurality of gates 304.
[0065] In some embodiments of the present invention, the method for forming the source metal layer 306 is a physical vapor deposition process, wherein the parameters of the physical vapor deposition process are a deposition rate of 350 angstroms per minute to 450 angstroms per minute and a deposition time of 12 seconds to 20 seconds, the material of the source metal layer 306 is AlCu, and the thickness of the source metal layer 306 ranges from 80 angstroms to 130 angstroms.
[0066] In some embodiments of the present invention, the substrate 300 further includes a second surface b, on which a drain metal layer 307 is deposited.
[0067] In some embodiments of the present invention, the method for forming the drain metal layer 307 is a physical vapor deposition process, wherein the parameters of the physical vapor deposition process are a deposition rate of 350 angstroms per minute to 450 angstroms per minute and a deposition time of 12 seconds to 20 seconds, the material of the drain metal layer 307 is AlCu, and the thickness of the drain metal layer 307 ranges from 80 angstroms to 130 angstroms.
[0068] Accordingly, referring to Figure 14, the present invention also provides a semiconductor structure, comprising: a substrate 300, the substrate 300 including a first surface a; an epitaxial layer 301 located on the first surface a, the epitaxial layer including a plurality of first regions and a second region located between adjacent first regions, the first regions and the second regions being arranged along a second direction; a first doped pillar located within the first region; a second doped pillar located within the second region, the first doped pillar and the second doped pillar being arranged along the second direction; a plurality of body regions 302 discretely located within the epitaxial layer 301, and the body regions being arranged along a first direction, the first direction and the second direction being parallel to the substrate surface, and the first direction being perpendicular to the second direction; and a plurality of gates 304, each of the gates 304 discretely located on adjacent body regions 302.
[0069] In a specific embodiment, the gate 304 includes a gate layer 3041, a gate oxide layer 3042 located on the bottom surface of the gate layer 3041, and an interlayer dielectric layer 3043 located on the sidewall surface and the top surface of the gate layer 3041.
[0070] In a specific embodiment, the thickness of the gate oxide layer 3042 ranges from 800 angstroms to 1000 angstroms, and the thickness of the interlayer dielectric layer 3043 ranges from 0.5 micrometers to 1 micrometer.
[0071] In this embodiment, the gate oxide layer 3042 is made of silicon nitride or silicon oxide.
[0072] In this embodiment, the gate layer 3041 is made of monocrystalline silicon or polycrystalline silicon.
[0073] In this embodiment, the material of the interlayer dielectric layer 3043 is silicon nitride or borosilicate glass.
[0074] In some embodiments of the present invention, the first doped pillar is a P-pillar and the second doped pillar is an N-pillar.
[0075] In other embodiments, the first doped pillar is an N-pillar and the second doped pillar is a P-pillar.
[0076] In some embodiments of the present invention, the semiconductor structure further includes: a JFET region 303 located within an epitaxial layer 301 adjacent to the body region 302, wherein the JFET region 303 has a second ion and the body region 302 has a first ion.
[0077] In one embodiment, the type of the first ion is opposite to the type of the second ion.
[0078] In a specific embodiment, the first ion is of type P and the second ion is of type N.
[0079] In some embodiments of the present invention, the type of the first ion is opposite to the type of the second ion.
[0080] In some embodiments of the present invention, the semiconductor structure further includes: a source region 305 located within a body region 302 on both sides of the gate 304, and the source region 305 contains a second ion.
[0081] In some embodiments of the present invention, the substrate 300 further includes a second surface b, and the semiconductor structure further includes: a source metal layer 306 located on the plurality of gates 304; and a drain metal layer 307 located on the second surface b.
[0082] In the above scheme, the epitaxial layer 301 includes a first doped pillar 3011 and a second doped pillar 3012, and the first doped pillar 3011 and the second doped pillar 3012 are arranged along the second direction Y. The epitaxial layer 301 also includes a body region 302, which is arranged along the first direction X. Compared with the scheme in the prior art where the lower surface of the body region also has a first doped pillar and a second doped pillar, the body region 302 and the first doped pillar 3011 and the second doped pillar 3012 in this invention are located in different directions of the epitaxial layer 301. This avoids the existence of the first doped pillar and the second doped pillar limiting the spacing size of the superjunction MOS transistor device, so that the channel length of the superjunction MOS transistor device is not affected by the spacing size, thereby increasing the channel length and improving the performance of the superjunction MOS transistor device.
[0083] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method of forming a semiconductor structure, characterized by, include: A substrate is provided, the substrate including a first surface; An epitaxial layer is formed on the first surface using an epitaxial process. The epitaxial layer includes a plurality of first regions and a second region located between adjacent first regions. The first regions and the second regions are arranged along a second direction. A first photoresist layer having a first region pattern is formed on the epitaxial layer, the first photoresist layer exposing the surface of the first region; Using the first photoresist layer as a mask, the epitaxial layer is etched to form a trench located in the first region; A first doped pillar is formed in the trench, and a second doped pillar is located in the second region, the first doped pillar and the second doped pillar are arranged along a second direction; A second photoresist layer with a bulk pattern is formed on the epitaxial layer. The second photoresist layer is arranged along a first direction, the first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction. Using the second photoresist layer as a mask, ions are implanted into the epitaxial layer to form a bulk region, which is arranged along a first direction. A gate material layer is formed on the epitaxial layer; The gate material layer is etched using a photolithography process to expose the body region, forming a plurality of gates, each of which is discretely located on an adjacent body region.
2. The method of forming a semiconductor structure of claim 1, wherein, The steps for forming the body region also include: Inject the first ion into the body region; A second ion is implanted into the epitaxial layer between adjacent body regions to form a JFET region.
3. The method of forming a semiconductor structure of claim 2, wherein, The type of the first doped column is opposite to that of the second doped column, the type of the first ion is opposite to that of the second ion, and the implantation concentration of the first ion in the bulk region is in the range of 1E12 ions / cm². 2 Up to 1E16 ions / cm 2 The implantation concentration of the second ion within the JFET region ranges from 1E12 ions / cm². 2 Up to 1E16 ions / cm 2 .
4. The method of forming a semiconductor structure of claim 1, wherein, After the step of forming several gates, the method further includes: Using the gate as a mask, second ions are injected into the body regions on both sides of the gate to form source regions.
5. The method of forming a semiconductor structure of claim 4, wherein, The implantation concentration of the second ions in the source region ranges from 1E12 ions / cm 2 to 1E16 ions / cm 2 .
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes a second surface, and after the step of forming the plurality of gates, it further includes: A source metal layer is deposited on the plurality of gate electrodes; A drain metal layer is deposited on the second surface.
7. A semiconductor structure, characterized by include: Substrate, the substrate including a first surface; An epitaxial layer is located on the first surface. The epitaxial layer includes a plurality of first regions and a second region located between adjacent first regions. The first regions and the second regions are arranged along a second direction. The first doped column is located within the first region; The second doped pillar is located in the second region, and the first doped pillar and the second doped pillar are arranged along the second direction; Several body regions are discretely located within the epitaxial layer, and the body regions are arranged along a first direction, the first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction; A plurality of gates, each of which is discretely located on an adjacent body region.
8. The semiconductor structure of claim 7, wherein, Also includes: The JFET region is located within the epitaxial layer between adjacent body regions, and the JFET region has a second ion, while the body region has a first ion.
9. The semiconductor structure as described in claim 8, characterized in that, The type of the first doped pillar is opposite to that of the second doped pillar, and the type of the first ion is opposite to that of the second ion.
10. The semiconductor structure as claimed in claim 7, characterized in that, Also includes: The source region is located within the body regions on both sides of the gate, and the source region contains a second ion.
11. The semiconductor structure of claim 7, wherein, The substrate further includes a second surface, and the semiconductor structure further includes: a source metal layer located on the plurality of gates; and a drain metal layer located on the second surface.