Display apparatus

Abstract

A display apparatus (100, 200, 1900), relating to the technical field of display. The display apparatus (100, 200, 1900) comprises a display module (20), a backlight module (10), a display drive circuit (40), and a backlight drive circuit (30). The display module (20) comprises N display sub-regions, and the backlight module (10) comprises N backlight sub-regions, wherein an nth backlight sub-region provides backlight for an nth display sub-region. The display drive circuit (40) is electrically connected to the display module (20) and is configured to output display drive signals to the N display sub-regions. The backlight drive circuit (30) is electrically connected to the backlight module (10) and is configured to output backlight drive signals to the N backlight sub-regions. The display period of one picture frame comprises M temporally consecutive sub-periods. The display sub-regions are configured to perform overdrive display during the sub-periods, and in each sub-period, the moment at which a display sub-region terminates the overdrive display is earlier than or overlaps with the moment at which a backlight sub-region starts backlight emission.

Description

Display device

[0001] This disclosure claims priority to a PCT international patent application (International Application No.: PCT / CN2025 / 075470, Invention Title: "Display Device") filed on January 27, 2025, with the State Intellectual Property Office of China (as the PCT receiving office). The entire description, claims, drawings, and abstract of that earlier PCT international application are incorporated herein by reference in their entirety as part of the technical solution disclosed herein. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display device. Background Technology

[0003] Color field-sequential display is one method for achieving color display in a display device. In field-sequential display technology, one field-sequential display cycle contains multiple subfields. Each subfield's sub-cycle requires the display device to sequentially perform TFT scanning, liquid crystal deflection, and backlight activation. The TFT scanning and liquid crystal deflection processes result in a shorter backlight activation time, which affects the overall display brightness and color gamut. Summary of the Invention

[0004] This disclosure provides a display device.

[0005] According to a first aspect, this disclosure provides a display device, comprising: a display module, a backlight module, a display driving circuit, and a backlight driving circuit; the display module includes N display zones, the backlight module includes N backlight zones, the nth backlight zone among the N backlight zones provides backlight to the nth display zone among the N display zones, 1≤n≤N, where n and N are positive integers; the output terminal of the display driving circuit is electrically connected to the N input terminals of the display module for outputting N display driving signals to the N display zones; the output terminal of the backlight driving circuit is electrically connected to the N input terminals of the backlight module for outputting N backlight driving signals to the N backlight zones; wherein, the display period for the display device to display one frame of an image includes M consecutive sub-cycles, where M is a positive integer; the display zones are used for overdrive display in the sub-cycles, and in the sub-cycle, the time when the display zone ends overdrive display is earlier than or equal to the time when the backlight zone starts backlighting. Attached Figure Description

[0006] Figure 1A shows a schematic diagram of the structure of an example display device;

[0007] Figure 1B shows a schematic diagram of an example array substrate structure;

[0008] Figure 1C shows a signal timing diagram of an example field sequence display;

[0009] Figure 1D shows a schematic diagram of an example field sequence display;

[0010] Figure 2 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure;

[0011] Figure 3A shows a schematic diagram of the field sequence display of a display module according to an embodiment of the present disclosure;

[0012] Figure 3B shows a schematic diagram of the field sequence display of a display module according to another embodiment of the present disclosure;

[0013] Figure 3C shows a timing diagram of the field sequence signals of a display module according to an embodiment of the present disclosure;

[0014] Figures 4A to 4D show schematic diagrams of backlight zoning according to embodiments of the present disclosure;

[0015] Figures 5A and 5B show schematic diagrams of the field sequence display of a display module according to another embodiment of the present disclosure;

[0016] Figure 5C shows a timing diagram of the field sequence signals of a display module according to an embodiment of the present disclosure;

[0017] Figure 5D shows a schematic diagram of the field sequence display of a display module according to another embodiment of the present disclosure;

[0018] Figure 6 shows a schematic diagram of the structure of the display module and the display driving circuit according to an embodiment of the present disclosure;

[0019] Figure 7A shows a timing diagram of the scan signal according to an embodiment of the present disclosure;

[0020] Figure 7B shows a timing diagram of a scan signal according to another embodiment of the present disclosure;

[0021] Figures 8A and 8B show schematic diagrams of the field sequence display of a display module according to another embodiment of the present disclosure;

[0022] Figure 8C shows a timing diagram of the field sequence signals of a display module according to an embodiment of the present disclosure;

[0023] Figure 9 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure;

[0024] Figure 10 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure;

[0025] Figure 11 shows a schematic diagram of the storage principle of RGB data according to an embodiment of the present disclosure;

[0026] Figure 12 shows a schematic diagram of the processor according to an embodiment of the present disclosure;

[0027] Figure 13A shows a schematic diagram of the backlight driving circuit according to an embodiment of the present disclosure;

[0028] Figure 13B shows a schematic diagram of the backlight driving circuit according to an embodiment of the present disclosure;

[0029] Figure 14 shows a schematic diagram of the structure of an LED chip according to an embodiment of the present disclosure;

[0030] Figure 15 shows a schematic diagram of a backlight driving circuit according to another embodiment of the present disclosure;

[0031] Figure 16 shows a schematic diagram of the structure of a drive unit according to an embodiment of the present disclosure;

[0032] Figure 17 shows a flowchart of a display method according to an embodiment of the present disclosure;

[0033] Figure 18A shows a schematic diagram of an example display without OD-driven grayscale;

[0034] Figure 18B shows a schematic diagram of an example of display based on an OD-driven grayscale;

[0035] Figure 18C shows a schematic diagram of an example of displaying grayscale based on another OD-driven method;

[0036] Figure 18D shows a schematic diagram of an example of displaying grayscale based on another OD-driven method;

[0037] Figure 19 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure;

[0038] Figure 20A shows a schematic diagram of display based on OD-driven grayscale according to an embodiment of the present disclosure;

[0039] Figure 20B shows a schematic diagram of display based on OD-driven grayscale according to another embodiment of the present disclosure;

[0040] Figure 20C shows a schematic diagram of display based on OD-driven grayscale according to another embodiment of the present disclosure;

[0041] Figure 21 shows a schematic diagram of the gamma curve of a display driving circuit according to an embodiment of the present disclosure;

[0042] Figure 22A shows a schematic diagram of the vertical partition scan timing according to an embodiment of the present disclosure;

[0043] Figure 22B shows a schematic diagram of the vertical partition scan timing according to another embodiment of the present disclosure; and

[0044] Figure 23 shows a timing diagram of the scan signal according to an embodiment of the present disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0046] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0047] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0048] Color field-sequence display is one method for achieving color display in display devices. Its principle is as follows: In field-sequence display, a frame of an image to be displayed is divided into multiple primary color images according to color. The display period of a frame is divided into multiple subfields corresponding one-to-one with the primary color images, forming a field sequence. The primary color images are displayed in their corresponding subfields. Within the display period of a frame, multiple primary colors switch rapidly, utilizing the persistence of vision in the human eye to achieve color superposition over time, thereby achieving color display.

[0049] The primary color image can be split according to the color system used by the field-sequence display device. For example, for a field-sequence display device using the three primary colors of red (R), green (G), and blue (B), during the field-sequence display stage, a frame of image to be displayed is split into a red image, a green image, and a blue image. The three primary color images are displayed in three subfields: the subfield used to display the red image is defined as the red subfield; the subfield used to display the green image is defined as the green subfield; and the subfield used to display the blue image is defined as the blue subfield.

[0050] It should also be noted that this article uses RGB three primary colors as an example to illustrate the scheme, but the scheme provided in this disclosure can be applied to any color system. This article describes the sequential display of the red, green, and blue subfields, but the red, green, and blue subfields only need to be displayed within the display cycle of one frame of image, and the display order can be arbitrary.

[0051] A liquid crystal display device that uses a field-sequential color liquid crystal display method to achieve color display is called a field-sequential color liquid crystal display (FSC-LCD), or simply a field-sequential display device. A field-sequential display device includes a display module and a backlight module.

[0052] Figure 1A shows a schematic diagram of the structure of an example display device.

[0053] As shown in Figure 1A, the field-sequence display device includes a backlight module 10 and a display module 20. The display module 20 includes a first polarizer 21, a first substrate 22, a liquid crystal layer 23, a second substrate 24, a black matrix 25, and a second polarizer 26, which are sequentially stacked on the surface of the backlight module 1.

[0054] The first substrate 22 includes a substrate substrate, a pixel circuit disposed on the substrate substrate, and a plurality of pixel electrodes connected to the pixel circuit. The second substrate 24 is provided with a common electrode corresponding to the pixel electrodes. An alignment layer is also disposed on the opposing surfaces of the first substrate 22 and the second substrate 24 to align the liquid crystal layer 3.

[0055] The display module 20 can be a liquid crystal display panel, such as a twisted nematic (TN) liquid crystal display panel, an in-planar switching (IPS) liquid crystal display panel, or a fringe field switching (FFS) liquid crystal display panel. Depending on the type of liquid crystal display panel, corresponding polarizers, alignment layers, and common electrodes are configured, which will not be elaborated here.

[0056] The backlight module 10 is located on the side of the display module 20 opposite to the display side, and the backlight module 10 provides backlight corresponding to the sub-sequence to the display module 20. The liquid crystal layer 23 controls the amount of light transmitted through the liquid crystal display panel by flipping.

[0057] The liquid crystal layer 23 includes multiple liquid crystal cells. When no driving voltage is applied between the pixel electrode and the common electrode, the liquid crystal cells located between the pixel electrode and the common electrode are in their initial state under the action of the alignment layer. When a driving voltage is applied between the pixel electrode and the common electrode, an electric field is generated between the pixel electrode and the common electrode. The liquid crystal cells flip under the action of the electric field. After the liquid crystal cells flip, the amount of backlight transmitted through the liquid crystal cells can be changed, so that the corresponding pixel cells produce corresponding brightness, i.e., pixel grayscale.

[0058] The pixel grayscale is related to the flip angle of the liquid crystal cell, which in turn is related to the electric field strength between the pixel electrode and the common electrode. Therefore, the size of the pixel grayscale can be adjusted by regulating the driving voltage between the pixel electrode and the common electrode.

[0059] In the subfield, a data signal corresponding to the primary color image is written to the display module 20. After the data signal is written, the liquid crystal cells in the display module 20 flip to the target position corresponding to the primary color image. Then, the backlight module 10 is controlled to turn on the backlight of the color corresponding to the subfield, so as to realize the display of the primary color image in the corresponding subfield. The above steps are repeated to complete the field sequence display of one frame of image to be displayed.

[0060] The backlight module 10 may include multiple LEDs capable of emitting red, green, and blue backlight. For example, during field sequence display, the backlight module 10 activates red backlight in the red subfield, green backlight in the green subfield, and blue backlight in the blue subfield.

[0061] Because field-sequential displays utilize temporal color mixing to achieve color display, they do not require color-corresponding sub-pixels (such as R, G, and B sub-pixels) within pixel units. Therefore, compared to display devices that use spatial color mixing, field-sequential displays can achieve a resolution several times higher. Furthermore, by using different backlight colors to colorize pixel units, a color filter layer (color resist structure) is unnecessary, avoiding the significant color resistance of the color filter layer on the backlight. Therefore, field-sequential displays offer significant advantages such as high resolution, high transmittance, lower cost, and a simpler, thinner structure.

[0062] Figure 1B shows a schematic diagram of an example array substrate.

[0063] As shown in Figure 1B, the first substrate 22 includes a plurality of pixel units 221, which are arranged in multiple rows and columns to form a pixel array. The pixel array includes a plurality of pixel rows extending along a first direction x, and the pixel rows are arranged side by side along a second direction y. Each pixel row includes a plurality of pixel units 221 arranged along the first direction x. The pixel units 221 between adjacent pixel rows are aligned to form a pixel column extending along the second direction y, and all pixel columns are arranged side by side along the first direction x.

[0064] The first substrate 22 also includes multiple scan lines Gate extending along the first direction x and multiple data lines Data extending along the second direction y. The scan lines Gate and data lines Data intersect to define pixel units 221. The pixel array formed by the pixel units 221 defines a display area, which is the area used by the display module 2 to display content.

[0065] Pixel unit 22 is connected to the scan line (Gate) and data line (Data) via a thin-film transistor (TFT) 222. The TFT 222 includes a gate, a source, and a drain. For example, the drain of the TFT 222 is connected to the pixel electrode of the corresponding pixel unit 221, the gate of the TFT 222 is connected to the scan line (Gate), and the source of the TFT 222 is connected to the data line (Data). The TFTs 222 are arranged correspondingly to the pixel units 221. The arrangement of the TFTs 222 can be referenced from the arrangement of the pixel units 221, and will not be described further here.

[0066] All scan lines (Gates) extend along the first direction (x), and multiple scan lines (Gates) are arranged side-by-side along the second direction (y). Each scan line (Gate) corresponds to a pixel row. The gate of the TFT 221 of the pixel unit 221 in the same pixel row is connected to the same scan line (Gate). All data lines (Data) extend along the second direction (y), and multiple data lines (Data) are arranged side-by-side along the first direction (x). Each data line (Data) corresponds to a pixel column. The source of the TFT 222 of the pixel unit 221 in the same pixel column is connected to the same data line (Data).

[0067] Multiple scan lines (Gates) sequentially provide scan signals to multiple pixel rows. The scan signals turn on the TFT 222 corresponding to the scan line (Gate), making the source and drain of the TFT 222 conduct. Multiple data lines (Data) write data signals, which are input to the corresponding pixel electrodes through the turned-on TFT 222, generating an electric field between the pixel electrode and the common electrode to control the liquid crystal.

[0068] The backlight module 10 is disposed on the side of the first substrate 22 away from the second substrate 24. The backlight generated by the backlight module 10 is emitted through the display module 2. The direction from the first substrate 22 to the second substrate 24 is the light emission direction of the display module 20. The side where the second substrate 24 is located is the display side of the display module 2, and the side where the first substrate 22 is located is the non-display side of the display module 20.

[0069] The backlight module 10 includes multiple backlight sources, each of which includes a light emitter corresponding to a subfield. For example, in this embodiment, the backlight source includes a red light emitter capable of emitting red backlight, a green light emitter capable of emitting green backlight, and a blue light emitter capable of emitting blue backlight. The light emitter can be a light-emitting diode (LED), a mini light-emitting diode (Mini LED), a micro light-emitting diode (Micro LED), or an organic light-emitting diode (OLED).

[0070] For example, the backlight module 20 can be a direct-lit backlight module or an edge-lit backlight module.

[0071] Figure 1C shows a signal timing diagram of an example field sequence display.

[0072] As shown in Figure 1C, taking the RGB three primary colors as an example, the display field sequence includes the red subfield Field_R (displaying the red image), the green subfield Field_G (displaying the green image), and the blue subfield Field_B (displaying the blue image). The display period of one frame of image can be divided into the first sub-period of the red subfield Field_R, the second sub-period of the green subfield Field_G, and the third sub-period of the blue subfield Field_B.

[0073] The display drive signal S-DIS can include scan signals and data signals to drive the display module. For example, in the red subfield Field_R, a high level of the display drive signal S-DIS scans the TFT to write a first data signal corresponding to the red pattern. After the first data signal is written, the liquid crystal flips. A high level of the backlight drive signal S-BLU controls the red light emitter of the backlight module to emit red backlight. The red backlight continues until the red subfield Field_R is completed and then turns off.

[0074] Similarly, in the green sub-field Field_G, the high level of the display drive signal S-DIS scans the TFT to write the second data signal corresponding to the green pattern. After the second data signal is written, the liquid crystal flips. The high level of the backlight drive signal S-BLU controls the green emitter of the backlight module to emit green backlight, which continues until the green sub-field Field_G is completed and then turns off. In the blue sub-field Field_B, the high level of the display drive signal S-DIS scans the TFT to write the third data signal corresponding to the blue pattern. After the third data signal is written, the liquid crystal flips. The high level of the backlight drive signal S-BLU controls the blue emitter of the backlight module to emit blue backlight, which continues until the blue sub-field Field_B is completed and then turns off.

[0075] The duration between the high level of the display drive signal S-DIS and the high level of the backlight drive signal S-BLU is the duration for the liquid crystal cell to complete its flip-flop.

[0076] Figure 1D shows a schematic diagram of an example field sequence display.

[0077] As shown in Figure 1D, a field sequence display period includes a red subfield Field_R, a green subfield Field_G, and a blue subfield Field_B. The sub-period of each subfield contains a scan time T. TFT Liquid crystal deflection time T LC Backlight illumination time T BL .

[0078] At scan time T TFT In this process, multiple scanning signals are used to scan all pixel rows in the display module. Data signals are written to the pixel circuit via the TFT, thereby driving the liquid crystal partition deflection. During the liquid crystal deflection time T... LC In the process, the liquid crystal cells in the liquid crystal layer complete their deflection. For example, for each pixel row, after the TFT scan is completed, the corresponding liquid crystal cell begins to deflect. After the last pixel row is scanned, the liquid crystal cell corresponding to the last pixel row begins to deflect. After all the liquid crystal cells have completed their deflection, the light-emitting element is lit up to emit the corresponding backlight. During the backlight illumination time T... BL In the backlight module, the light emitters emit backlight. At the start of the scan time for the next subfield, the light emitters for the previous subfield stop emitting backlight.

[0079] The backlight must be turned off during the data signal writing and liquid crystal response phases; otherwise, color mixing will occur in the display device because the corresponding liquid crystal cells have not fully flipped into position. Therefore, the backlight module is driven to emit backlight after all liquid crystal cells have completed their deflection. However, the scan time T in each sub-cycle... TFT and liquid crystal deflection time T LC Too long, and it will reduce the backlight illumination time.BL .

[0080] With the peak value of the driving current driving the backlight module to emit light remaining constant, the backlight illumination time T BL It is directly proportional to the backlight module. If the backlight illumination time T... BL The smaller sub-cycle time ratio of the subfield results in lower overall brightness of the display device, and the shorter backlight on time also limits the improvement of color gamut.

[0081] In one example, the field-sequence display device has a display frequency of 60Hz and a subfield frequency of 180Hz. Therefore, the time required to complete a single refresh of the three colors (red, green, and blue) is 1 / 60s, and the time required to complete a single refresh of a single color is 1 / 180s. A fast-response liquid crystal is used, and the liquid crystal deflection time T... LC Approximately 2ms. Scan time T TFT Approximately 3.12ms. In the field sequence display of three subfields, the sub-cycle time of one subfield is Ts = 5.56ms. In this case, the backlight illumination time T... BL = 0.44ms. The backlight duty cycle is: T B / Ts=8%, a low backlight duty cycle will result in insufficient overall brightness, and the short backlight on time also limits the improvement of color gamut.

[0082] In view of this, the present disclosure provides a field-sequential display device in which the backlight of the corresponding part is turned on sequentially as the liquid crystal flips line by line, and the backlight module is illuminated in sections to increase the backlight illumination time of each backlight section, thereby increasing the backlight illumination duty cycle and improving the brightness and color gamut of the entire field-sequential display device.

[0083] Figure 2 shows a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0084] As shown in Figure 2, the display device 100 includes a backlight module 10, a display module 20, a backlight driving circuit 30, and a display driving circuit 40.

[0085] In this embodiment, the display module 20 includes N display zones, namely, the first display zone, ..., the nth display zone, ..., the Nth display zone. The backlight module 10 includes N backlight zones, namely, the first backlight zone, ..., the nth backlight zone, ..., the Nth backlight zone. The nth backlight zone provides backlight for the nth display zone among the N display zones, where 1 ≤ n ≤ N, and n and N are positive integers.

[0086] The output of the display driving circuit 40 is electrically connected to the N inputs of the display module 20 to output N display driving signals to the N display zones. The output of the backlight driving circuit 30 is electrically connected to the N inputs of the backlight module 10 to output N backlight driving signals to the N backlight zones.

[0087] For example, the N display driving signals output by the display driving circuit 40 sequentially drive the N display zones to perform TFT scanning and liquid crystal cell deflection. The N backlight driving signals output by the backlight driving circuit 30 sequentially drive the N backlight zones to emit backlight. For example, when the nth display zone completes TFT scanning and liquid crystal deflection under the drive of the display driving signals, the backlight driving signals drive the nth backlight zone to emit backlight. The backlight emitted by the nth backlight zone is displayed through the nth display zone.

[0088] For example, the display driving circuit 40 includes a scan driving circuit, a data driving circuit, and a common voltage generating circuit. The scan driving circuit is connected to multiple scan lines (Gates) and sequentially provides scan signals to the multiple scan lines (Gates). The scan signals drive the connected TFTs to turn on. The data driving circuit is connected to multiple data lines (Data) and writes data signals to the multiple data lines (Data). The data signals are input to the corresponding pixel electrodes through the turned-on TFTs, generating an electric field between the pixel electrodes and the common electrode to control the liquid crystal. The common voltage generating circuit is electrically connected to the common electrode and provides a common voltage signal to the common electrode.

[0089] For example, each backlight zone of the backlight module 10 includes multiple backlight sources, and the backlight driving circuit 30 is connected to the multiple backlight sources to drive the light-emitting elements corresponding to the subfields in the backlight sources to work.

[0090] For example, the display driving signal includes a scan signal. When the scan signal received by the nth display partition is at a high level, the TFT of the nth display partition is turned on, and data signals are written to the nth display partition, causing the liquid crystal cell to deflect. When the scan signal received by the nth display partition is at a low level, the TFT of the nth display partition is turned off, data signals stop being written to the nth display partition, and the liquid crystal cell does not deflect.

[0091] For example, the backlight drive signal is the drive current applied to the backlight zone. When the drive current received by the nth backlight zone reaches the operating current value required for illumination, the nth backlight zone emits backlight. When the drive current received by the nth backlight zone is lower than the operating current value required for illumination, the nth backlight zone is turned off and stops emitting backlight.

[0092] In this embodiment of the disclosure, the display period for displaying one frame of an image by the display device includes M consecutive sub-cycles, where M is a positive integer. For example, if the color system of the display device uses red, green, and blue primary colors, then M = 3. The three sub-cycles are the sub-cycles of the red subfield, the green subfield, and the blue subfield, respectively. The time order of the three sub-cycles can be the sub-cycles of the red subfield, the green subfield, and the blue subfield.

[0093] Within each sub-cycle of a subfield, when the liquid crystal molecules in the nth display partition complete their deflection under the drive of the received display driving signal, the nth backlight partition is illuminated under the drive of the received backlight driving signal. When a display driving signal for the next subfield is received to begin scanning the TFTs of the nth display partition, the light emitter in the nth backlight partition that is emitting backlight for the previous subfield stops emitting backlight.

[0094] For example, in the sub-cycle of the red subfield, when the liquid crystal cell in the nth display zone completes its deflection, the red light emitter in the nth backlight zone emits red backlight and continues to emit red backlight. In the sub-cycle of the green subfield, when the nth display zone receives a high-level scan signal for the green subfield, the red light emitter in the nth backlight zone stops emitting red backlight.

[0095] In this embodiment of the disclosure, the moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle of M sub-cycles switches from the first state to the second state is the nth first moment, and the moment when the scan signal received by the nth display partition in the (m+1)th sub-cycle of M sub-cycles jumps from the first level to the second level is the nth second moment, 1≤m<M, m is a positive integer, and the nth first moment and the nth second moment are the same.

[0096] For example, M=3, the first sub-period is the sub-period of the red sub-field, the second sub-period is the sub-period of the green sub-field, and the third sub-period is the sub-period of the blue sub-field.

[0097] The first state of the backlight driving signal is when the driving current is sufficient to drive the backlight module to emit backlight. The second state of the backlight driving signal is when the driving current is sufficient to prevent the backlight module from emitting light. For example, the backlight driving signal can be converted into a driving current. For example, the voltage of the backlight driving signal can be supplied to the negative electrode of the light-emitting element in the backlight section. With the positive electrode voltage of the light-emitting element remaining constant, changing the voltage of the backlight driving signal changes the value of the driving current passing through the backlight section. For example, in the second state of the backlight driving signal, the driving current is less than 1A, and the backlight section with a driving current less than 1A does not emit light. In the first state of the backlight driving signal, the driving current is greater than or equal to 1A, and the backlight section emits light. When the driving current remains greater than or equal to 1A, changing the voltage value of the backlight driving signal changes the value of the driving current, thereby changing the intensity of the backlight emitted by the backlight section. For example, the brightness of the backlight emitted by the backlight section can increase as the driving current increases.

[0098] The nth first moment is the moment when the nth backlight partition receives the backlight drive signal with the second state in the mth sub-cycle, that is, the moment when the nth backlight partition stops emitting light in the mth sub-cycle.

[0099] The first level can be low, and the second level can be high. The nth second moment is the moment when the nth display partition receives a scan signal with the second level in the (m+1)th sub-cycle, that is, the moment when the TFT of the nth display partition is turned on in the (m+1)th sub-cycle.

[0100] In this embodiment of the disclosure, the moment when the TFT of the nth display partition is turned on in the (m+1)th sub-cycle coincides with the moment when the nth backlight partition stops emitting light in the m-th sub-cycle. That is, the moment when the nth backlight partition receives the backlight driving signal with the second state in the m-th sub-cycle coincides with the moment when the nth display partition receives the scan signal with the second level in the (m+1)th sub-cycle.

[0101] For example, the m-th sub-cycle is the sub-cycle for the red subfield, and the (m+1)-th sub-cycle is the sub-cycle for the green subfield. When the n-th display zone receives a high-level scan signal for the green subfield, the light emitter for the red subfield in the n-th backlight zone stops emitting red light.

[0102] In this embodiment of the disclosure, the scanning signals received by the N display zones in the m-th sub-cycle sequentially change from a first level to a second level, and the backlight driving signals received by the N backlight zones in the m-th sub-cycle sequentially switch from a first state to a second state.

[0103] For example, in the m-th sub-cycle, after the scan signal received by the nth display partition changes from low to high, the scan signal received by the (n+1)th display partition changes from low to high. That is, the nth display partition performs TFT scanning before the (n+1)th display partition.

[0104] For example, in the m-th sub-cycle, after the backlight drive signal received by the nth backlight partition switches from the first state to the second state, the backlight drive signal received by the (n+1)th backlight partition switches from the first state to the second state. That is, the nth backlight partition emits the corresponding backlight before the (n+1)th backlight partition.

[0105] For example, when the scan signal for the green subfield received by the nth display zone is high, the nth backlight zone stops emitting red light, but the (n+1)th backlight zone can still emit red light until the scan signal for the green subfield received by the (n+1)th display zone is high, at which point the (n+1)th backlight zone stops emitting red light.

[0106] In this embodiment, a backlight driving circuit drives N backlight zones to emit light independently. The start and end times of light emission for each backlight zone are only related to the corresponding display zone and are not affected by the scanning state of other display zones or the deflection state of the liquid crystal cells. For example, the end time of red light emission from the nth backlight zone is only related to the start time of TFT scanning of the nth display zone for the green subfield. Based on this, by delaying the stop time of light emission from each backlight zone, the duration of backlight emission from each backlight zone can be increased, thereby improving the brightness of the display device without changing the value of the driving current.

[0107] Figure 3A shows a schematic diagram of the field sequence display of a display module according to an embodiment of the present disclosure.

[0108] As shown in Figure 3A, N=12, the display module includes 12 display zones, and the backlight module includes 12 backlight zones. Figure 3A illustrates the operating status of the 12 display zones and 12 backlight zones in the sub-cycles of the red subfield (Field-R), green subfield (Field-G), and blue subfield (Field-B) within a single frame (1 frame) of an image. The legend for each row in Figure 3A illustrates the operating status of a single display zone within the sub-cycles of the red subfield (Field-R), green subfield (Field-G), and blue subfield (Field-B).

[0109] Display zones 1 through 12 undergo TFT scanning and liquid crystal deflection sequentially, while backlight zones 1 through 12 sequentially begin and cease illumination. The scanning time T for each display zone is... TFT Equal, the liquid crystal deflection time T for each display partitionLC Equal, the backlight illumination time T for each backlight zone is... BL equal.

[0110] In some embodiments, the duration of the display period is T, and the duration of the sub-period is T / M, where T is a positive number. For example, the display period is the time required to complete the refresh of all colors during the display of one frame of an image. The sub-period is the time required to complete the refresh of a single color during the display of one frame of an image. For example, for a field-sequence display of red, green, and blue, with a refresh rate of 60Hz, the display period is 1 / 60 = 16.68ms, and the sub-period is 1 / 180 = 5.56ms.

[0111] In this embodiment of the disclosure, the time interval between the moment when the scan signal for the red subfield received by the nth display partition changes from low to high and the moment when the scan signal for the green subfield received by the nth display partition changes from low to high can be the duration of one sub-cycle, and the interval duration is T / M.

[0112] In this embodiment, since the nth first moment and the nth second moment are the same, the time interval between the moment when the scan signal for the red subfield received by the nth display zone changes from low to high and the moment when the backlight drive signal for the red subfield received by the nth backlight zone changes from the first state to the second state can also be one sub-cycle. That is, the time interval between the start time of the TFT scan for the red subfield of the nth display zone and the stop time of the light emission of the red subfield of the nth backlight zone is one sub-cycle.

[0113] Since the scanning signals received by the N display zones in the m-th sub-cycle change from low level to high level in sequence, the backlight drive signals received by the N backlight zones in the m-th sub-cycle switch from the first state to the second state in sequence.

[0114] For the nth display zone and the nth backlight zone, the state change time of the backlight drive signal received by the nth backlight zone is related to the level change time of the scan signal received by the nth display zone.

[0115] For example, the state change time of the backlight drive signal received by the nth backlight zone is determined only by the change time of the scan signal received by the nth display zone. The state change time of the backlight drive signal received by the nth backlight zone is not affected by the level changes of the scan signals received by other display zones in the N display zones or the state changes of the backlight drive signals received by other backlight zones in the N backlight zones.

[0116] For example, if the second time of the nth display partition is advanced, the first time of the nth backlight partition is also advanced. If the second time of the nth display partition is delayed, the first time of the nth backlight partition is also delayed. If the second time of display partitions other than the nth display partition changes, the first time of the nth backlight partition may be unaffected. If the first time of backlight partitions other than the nth backlight partition changes, the first time of the nth backlight partition may be unaffected.

[0117] In this embodiment, since the interval between the start time of the TFT scan of the nth display zone for the red subfield and the stop time of the light emission of the nth backlight zone for the red subfield is the duration of one sub-cycle, the light emission duration of the nth backlight zone can be set within the duration of one sub-cycle. The maximum value of the light emission duration of the nth backlight zone can be the duration of one sub-cycle.

[0118] Figure 3B shows a schematic diagram of the field sequence display of a display module according to another embodiment of the present disclosure.

[0119] Figure 3B illustrates the operating status of a single display zone and a single backlight zone in their respective sub-cycles of the red subfield (Field-R), green subfield (Field-G), and blue subfield (Field-B). For example, the operating status of the first display zone and the first backlight zone is illustrated schematically. The first sub-cycle is the sub-cycle of the red subfield, the second sub-cycle is the sub-cycle of the green subfield, and the third sub-cycle is the sub-cycle of the blue subfield. For example, if M=3, when the first sub-cycle is the m-th cycle, the second sub-cycle is the (m+1)-th sub-cycle, and the third sub-cycle is the (m+2)-th sub-cycle. Similarly, when the second sub-cycle is the m-th sub-cycle, the third sub-cycle is the (m+1)-th sub-cycle. When the third sub-cycle is the m-th sub-cycle, the first sub-cycle of the next display cycle is the (m+1)-th sub-cycle.

[0120] As shown in Figure 3B, for each sub-cycle of a subfield, the moment when the backlight drive signal received by the first backlight zone in the first sub-cycle switches from the first state to the second state is the first time interval t1-1. The moment when the scan signal received by the first display zone in the second sub-cycle switches from the first level to the second level is the first time interval t2-1. The moment when the scan signal received by the first display zone in the first sub-cycle switches from the first level to the second level is the first time interval t3-1. The moment when the scan signal received by the first display zone in the first sub-cycle switches from the second level to the first level is the first time interval t4-1. The moment when the backlight zone received by the first backlight zone in the first sub-cycle switches from the second state to the first state is the first time interval t5-1.

[0121] In this embodiment of the disclosure, the display period is T, and the sub-period is T / 3. The first time interval t1-1 is the same as the first second time interval t2-1, and the interval between the first third time interval t3-1 and the first first time interval t1 is T / 3.

[0122] The interval between the first third time point t3-1 and the first fourth time point t4-1 is the scan time T. TFT The time interval between the first fourth time point t4-1 and the first fifth time point t5-1 is the liquid crystal deflection time T. LC The interval between the first fifth time point t5-1 and the first first time point t1-1 is the backlight illumination time T. BL .

[0123] For example, define scan time T TFT Let 'a' be the backlight illumination time T. BL For b.

[0124] Before the first backlight zone stops emitting red backlight, the Nth backlight zone begins emitting red backlight. This ensures that for a certain period of time, all N backlight zones emit red backlight. This also ensures that screen refresh can be achieved by controlling the N backlight zones to start and stop emitting light synchronously.

[0125] The moment when the backlight drive signal received by the Nth backlight partition in the first sub-cycle switches from the second state to the first state is defined as the Nth fifth moment, and the third interval between the Nth fifth moment and the first second moment is defined as c.

[0126] Since the first backlight zone begins emitting light after the first display zone has completed TFT scanning and liquid crystal deflection, without waiting for other display zones to complete TFT scanning and liquid crystal deflection, the illumination time of the first backlight zone can cover the TFT scanning time of the other display zones. Therefore, the backlight illumination time T of the first backlight zone... BL It can be expressed as b = a*(N-1) + c.

[0127] If N backlight zones are controlled to start emitting light synchronously and stop emitting light synchronously, the backlight illumination time T of the first backlight zone is... BL It can be c. Based on the display state provided in this disclosure, the backlight illumination time T BL It can be increased, at least by a*(N-1).

[0128] For example, defining the liquid crystal deflection time T LC For d. Scan time T TFT Liquid crystal deflection time T LC and backlight illumination time T BL The sum of these values ​​is equal to the duration of the sub-period, a + d + b = T / M. Where T is the liquid crystal deflection time.LC Let T / Mab, then a*N+d+c=T / M.

[0129] In this embodiment of the disclosure, the second interval duration is determined based on the first interval duration, the second interval duration is negatively correlated with the first interval duration, and the change in the second interval duration is positively correlated with the change in the first interval duration.

[0130] Backlight illumination time T BL It can be the scan time T TFT The backlight illumination time T is determined by [the specific factor]. BL With scan time T TFT The correlation is negative. Backlight illumination time T BL It can vary with the scan time T TFT The decrease increases by shortening the scan time T. TFT This can increase the backlight illumination time. BL .

[0131] The change can be an increase or decrease in time. Backlight illumination time T BL The increase can be determined by the scan time T. TFT The amount of reduction determines the backlight illumination time T. BL The increase in scan time T TFT The reduction in backlight duration T can be positively correlated. BL The increase can vary with scan time T TFT The increase is due to the decrease in quantity.

[0132] In this embodiment of the disclosure, by controlling the scan time T TFT The duration is used to control the backlight illumination time T. BL The increased duration of the display device improves its luminous efficiency and reduces its power consumption.

[0133] In this embodiment of the disclosure, when the nth backlight partition receives the backlight driving signal for the mth sub-cycle in a first state, at least one of the N backlight partitions receives the backlight signal for the (m+1)th sub-cycle in a first state.

[0134] When the nth backlight partition receives a backlight drive signal for the mth sub-cycle in a first state, the nth backlight partition emits corresponding backlight for the mth sub-cycle. When at least one of the N backlight partitions receives a backlight signal for the (m+1)th sub-cycle in a first state, that at least one backlight partition emits corresponding backlight for the (m+1)th sub-cycle.

[0135] The color of the backlight emitted for the m-th sub-cycle is different from the color of the backlight emitted for the (m+1)-th sub-cycle.

[0136] For example, the m-th sub-period is for the red subfield, and in the m-th sub-period, the backlight zone emits red backlight. The (m+1)-th sub-period is for the green subfield, and in the (m+1)-th sub-period, the backlight zone emits green backlight. If the n-th backlight zone emits red backlight, at least one of the N backlight zones emits green backlight. In this case, at least two of the N backlight zones simultaneously emit backlight of different colors.

[0137] For example, the moment when the backlight drive signal received by the Nth backlight partition in the first sub-cycle switches from the first state to the second state is the Nth first time t1-N. Since the Nth fifth time t5-N is later than the first fifth time t5-1, the Nth first time t1-N is later than the first first time t1-1. Since the first first time t1-1 coincides with the first second time t2-1, the Nth first time t1-N is later than the first second time t2-1. In this case, when the first display partition starts performing TFT scanning for the green sub-field, the Nth backlight partition is in a state of emitting red light.

[0138] The moment when the scan signal received by the Nth display zone in the first sub-cycle changes from the first level to the second level is the Nth third time t3-N. The moment when the backlight drive signal received by the first backlight zone for the next sub-field switches from the second state to the first state is the first sixth time t6-1.

[0139] If the first fifth time t5-1 is earlier than the Nth third time t3-N, and the first sixth time t6-1 is earlier than the Nth first time t1-N, then in this case, when the first backlight zone starts emitting green light, the Nth backlight zone is still emitting red light.

[0140] In this embodiment of the disclosure, when the nth backlight partition receives the backlight driving signal for the first sub-cycle and is in a first state, at least one of the N backlight partitions receives the backlight signal for the Mth sub-cycle and is in a first state.

[0141] The backlight zones can emit different colors of backlight for different sub-cycles. N backlight zones can enter a certain sub-cycle in sequence, and each N backlight zone emits backlight for that sub-cycle in sequence. Each backlight zone enters M sub-cycles in sequence, and each backlight zone emits a different color of backlight in sequence.

[0142] When the scan signal for the m-th sub-cycle is received in the n-th display partition and changes from the first level to the high level, both the n-th display partition and the n-th backlight partition enter the m-th sub-cycle.

[0143] For example, N backlight zones can sequentially enter the m-th sub-cycle and emit backlight for the m-th sub-cycle in sequence. After all N backlight zones have entered the m-th sub-cycle, the N backlight zones then sequentially enter the (m+1)-th sub-cycle and emit backlight for the (m+1)-th sub-cycle in sequence.

[0144] For example, with M=3, each backlight zone sequentially enters three sub-cycles, emitting three different colors of backlight in turn. For instance, in the first sub-cycle, the backlight zone emits red light. In the second sub-cycle, the backlight zone emits green light. In the third sub-cycle, the backlight zone emits blue light.

[0145] N backlight zones sequentially enter the first sub-cycle and emit red backlight sequentially. After all N backlight zones have entered the first sub-cycle, they then sequentially enter the second sub-cycle and emit green backlight sequentially. After all N backlight zones have entered the second sub-cycle, they then sequentially enter the third sub-cycle and emit blue backlight sequentially.

[0146] In this embodiment of the disclosure, when the nth backlight partition receives a backlight drive signal for the first sub-cycle in a first state, the nth backlight partition emits corresponding backlight for the first sub-cycle. When at least one of the N backlight partitions receives a backlight signal for the Mth sub-cycle in a first state, that at least one backlight partition emits corresponding backlight for the Mth sub-cycle.

[0147] Since the N backlight zones sequentially enter M sub-cycles, when the nth backlight zone enters the 1st sub-cycle and at least one backlight zone enters the Mth sub-cycle, at least M-2 backlight zones among the N backlight zones will be in M-2 sub-cycles respectively, and these M-2 backlight zones will emit their respective backlights for their respective sub-cycles. In this case, M backlight zones among the N backlight zones will emit backlights simultaneously.

[0148] For example, if the Nth backlight zone emits red backlight, at least one of the fourth backlight zones emits blue backlight. In this case, at least one of the first, second, and third backlight zones emits green backlight. Thus, the Nth, first, and fourth backlight zones can emit three colors of backlight.

[0149] In this embodiment of the disclosure, the nth display partition and the (n+1)th display partition can be two adjacent display partitions. The nth display partition and the (n+1)th display partition receive the scan signal and change from low level to high level in sequence. Therefore, the nth display partition and the (n+1)th display partition perform TFT scanning in sequence.

[0150] The (n+1)th fifth moment is the moment when the backlight drive signal received by the (n+1)th backlight zone in the m-th sub-cycle switches from the second state to the first state. The (n+1)th third moment is the moment when the scan signal received by the nth display zone in the m-th sub-cycle jumps from the first level to the second level. The (n+1)th first moment is the moment when the backlight drive signal received by the (n+1)th backlight zone in the m-th sub-cycle switches from the first state to the second state.

[0151] The interval between the fifth time of the nth moment and the fifth time of the (n+1)th moment is the same as the interval between the third time of the nth moment and the third time of the (n+1)th moment. The interval between the first time of the nth moment and the first time of the (n+1)th moment is the same as the interval between the third time of the nth moment and the third time of the (n+1)th moment. 1≤n<N.

[0152] For the same subfield, the interval between the start times of light emission of any two backlight zones is the same as the interval between the start times of TFT scanning of the two display zones corresponding to those two backlight zones. In this case, after the N display zones complete TFT scanning and liquid crystal deflection in sequence, the N backlight zones can start emitting light in sequence and stop emitting light in sequence.

[0153] By controlling the interval between the start times of TFT scanning in any two display zones, the interval between the start times of light emission in two backlight zones can be controlled. For example, by shortening the interval between the third time points of two display zones, the interval between the fifth time points of two backlight zones can be shortened. If the third time point of a certain display zone is advanced, the fifth time point of the corresponding backlight zone will also be advanced accordingly, thereby increasing the light emission duration of the backlight zone.

[0154] Since the interval between the start and end times of the two backlight zones is consistent with the interval between the start times of the TFT scan of the two display zones, the backlight illumination time T of the two backlight zones is... BL The duration is consistent. When the interval between the start and end times of any two backlight zones is short, it can be ensured that any two backlight zones can be in a state of simultaneous illumination for a longer period of time, thereby reducing the illumination difference between different backlight zones and optimizing the display effect.

[0155] It should be noted that the operating status of each of the N backlight zones and N display zones in their respective sub-cycles of the red subfield Field-R, green subfield Field-G, and blue subfield Field-B can be referenced from the operating status of the first backlight zone and the first display zone in the sub-cycle of the red subfield Field-R. For the sake of simplicity, similar parts will not be repeated.

[0156] Figure 3C shows a timing diagram of field sequence signals for a display module according to an embodiment of the present disclosure. Figure 3C shows a timing diagram of scan signals for the four display zones and backlight drive signals for the four backlight zones in the sub-cycles of the red subfield Field-R, green subfield Field-G, and blue subfield Field-B in a display cycle T of a frame (1 frame) image when N=4.

[0157] As shown in Figure 3C, in the red subfield Field-R, the scan signal S-DIS-R for the red subfield sequentially scans the four display zones. The scan signal S-DIS-R for the red subfield can be divided into display sub-signals S-DIS-R1, S-DIS-R2, S-DIS-R3, and S-DIS-R4. Display sub-signal S-DIS-R1 is used to scan the first display zone, display sub-signal S-DIS-R2 is used to scan the first display zone, display sub-signal S-DIS-R3 is used to scan the first display zone, and display sub-signal S-DIS-R4 is used to scan the first display zone.

[0158] For example, the first fourth time t4-1 is consistent with the second third time t3-2, the second fourth time t4-2 is consistent with the third third time t3-3, and the third fourth time t4-3 is consistent with the fourth third time t3-4.

[0159] Backlight sub-signal S-BLU-R1 is used to drive the first backlight zone to emit red backlight, backlight sub-signal S-BLU-R2 is used to emit red backlight to the first backlight zone, backlight sub-signal S-BLU-R3 is used to emit red backlight to the first backlight zone, and backlight sub-signal S-BLU-R4 is used to emit red backlight to the first backlight zone.

[0160] Taking the first display zone and the first backlight zone as examples, the timing of the scanning signal and the backlight drive signal is illustrated.

[0161] For example, when the level of the display sub-signal S-DIS-R1 changes from low to high, the display sub-signal S-DIS-R1 begins scanning the first display zone. When the level of the display sub-signal S-DIS-R1 changes from high to low, the display sub-signal S-DIS-R1 ends scanning the first display zone. When the level of the backlight sub-signal S-BLU-R1 changes from low to high, the backlight sub-signal S-BLU-R1 drives the red light emitter of the first backlight zone to start emitting light. When the level of the backlight sub-signal S-BLU-R1 changes from high to low, the backlight sub-signal S-BLU-R1 drives the red light emitter of the first backlight zone to stop emitting light.

[0162] Therefore, the interval between the first third time point t3-1 and the first fourth time point t4-1 is the scan time T of the first display partition for the red subfield Field-R. TFT The interval between the first fourth time point t4-1 and the first fifth time point t5-1 is the liquid crystal deflection time T of the first display partition for the red subfield Field-R. LC The interval between the first fifth time t5-1 and the first first time t1-1 is the backlight illumination time T of the red light emitter in the first backlight zone. BL .

[0163] When the display sub-signal S-DIS-R1 completes scanning of the first display zone, during the liquid crystal deflection time T LC The flipping of the liquid crystal in the first display zone is completed within the time interval. After the liquid crystal deflection time T... LC Then, the red light emitter in the first backlight zone is illuminated. The red light emitter in the first backlight zone is illuminated until the display sub-signal S-DIS-G1 transitions from low to high, at which point it is turned off. That is, the first second time t2-1 of the first display zone coincides with the first first time t1-1 of the first backlight zone. When the display sub-signal S-DIS-G1 begins scanning the first display zone, the red light emitter in the first backlight zone stops emitting light.

[0164] The timing variations of the scan signal S-DIS-G, backlight sub-signal S-BLU-G1, S-BLU-G2, S-BLU-G3, and S-BLU-G4 for the green sub-field Field-G can be referenced from the red sub-field Field-R. The driving methods of the scan signal S-DIS-G for the green sub-field Field-G on display zones 1 through 4, and the driving methods of the backlight sub-signals S-BLU-G1, S-BLU-G2, S-BLU-G3, and S-BLU-G4 for backlight zones 1 through 4, can be referenced from the red sub-field Field-R. The timing variations of the scan signal S-DIS-B, backlight sub-signals S-BLU-B1, S-BLU-B2, S-BLU-B3, and S-BLU-B4 for the blue sub-field Field-B can be referenced from the red sub-field Field-R. The driving methods of the scan signal S-DIS-B for the blue sub-field Field-B on display zones 1 through 4, and the driving methods of the backlight sub-signals S-BLU-B1, S-BLU-B2, S-BLU-B3, and S-BLU-B4 for backlight zones 1 through 4, can also be referenced from the red sub-field Field-R. For simplicity, similar parts will not be repeated.

[0165] For example, the interval between the second and third time points t3-2 and the second and fourth time points t4-2 is the scan time T of the second display partition for the red subfield Field-R. TFT The interval between the second fourth time point t4-2 and the second fifth time point t5-2 is the liquid crystal deflection time T of the second display partition for the red subfield Field-R. LC The interval between the second fifth time t5-2 and the second first time t1-2 is the backlight illumination time T of the red light emitter in the second backlight zone. BL .

[0166] For example, the interval between the third time step t3-3 and the fourth time step t4-3 is the scan time T of the third display partition for the red subfield Field-R. TFT The interval between the third and fourth time points t4-3 and the third and fifth time points t5-3 is the liquid crystal deflection time T of the third display partition for the red subfield Field-R. LC The interval between the third fifth time point t5-3 and the third first time point t1-3 is the backlight illumination time T of the red light emitter in the third backlight zone. BL .

[0167] For example, the interval between the third time step t3-4 and the fourth time step t4-4 is the scan time T of the fourth display partition for the red subfield Field-R. TFT The interval between the fourth time step t4-4 and the fifth time step t5-4 is the liquid crystal deflection time T of the fourth display partition for the red subfield Field-R. LC The interval between the fourth fifth time point t5-4 and the fourth first time point t1-4 is the backlight illumination time T of the red light emitter in the fourth backlight zone. BL .

[0168] In this embodiment of the disclosure, the second second time t2-2 of the second display partition coincides with the second first time t1-2 of the second backlight partition. The third second time t2-3 of the third display partition coincides with the third first time t1-3 of the third backlight partition. The fourth second time t2-4 of the fourth display partition coincides with the fourth first time t1-4 of the fourth backlight partition.

[0169] In this embodiment, since the fourth fifth time point t5-4 is later than the first fifth time point t5-1, the fourth first time point t1-4 is later than the first first time point t1-1. Since the first first time point t1-1 coincides with the first second time point t2-1, the fourth first time point t1-4 is later than the first second time point t2-1. In this case, when the first display zone begins TFT scanning for the green subfield, the fourth backlight zone is in a state of emitting red light.

[0170] At time t5-1 of the first fifth stage, the time t3-4 of the fourth third stage is earlier than at time t6-1 of the first sixth stage, the time t1-4 of the fourth first stage is earlier than at time t1-4 of the fourth stage. In this case, when the first backlight zone starts emitting green light, the fourth backlight zone is still emitting red light.

[0171] In this embodiment of the disclosure, the display period T of one frame includes three consecutive sub-periods. The interval between the first third time t3-1 and the first first time t1-1 is T / 3, the interval between the second third time t3-2 and the second first time t1-2 is T / 3, the interval between the third third time t3-3 and the third first time t1-3 is T / 3, and the interval between the third third time t3-3 and the third first time t1-3 is T / 3.

[0172] In this embodiment, the nth first moment is later than the (n+1)th fifth moment. The (n+1)th backlight partition begins emitting light in the mth sub-cycle before the nth backlight partition stops emitting light. For example, the first first moment t1-1 of the first backlight partition is earlier than the second fifth moment t5-2 of the second backlight partition. The red light emitter of the second backlight partition begins emitting light before the red light emitter of the first backlight partition stops emitting light. Therefore, there is a period when the first and second backlight partitions emit red light simultaneously.

[0173] In this embodiment of the disclosure, within a sub-cycle of the red subfield Field-R, the red emitter of the Nth backlight zone begins to emit light before the red emitter of the first backlight zone stops emitting light. For example, the first time interval t1-1 is later than the fourth time interval t5-4, and there is a period when the N backlight zones of the backlight module emit light simultaneously.

[0174] Because all backlight zones of the backlight module can emit the same color of backlight simultaneously within a certain period of time, the display effect of the display device is stable, and the display difference between different zones is small, which meets the user's visual needs.

[0175] Since the first moment of the nth time zone is later than the fifth moment of the (n+1)th time zone, the second moment of the nth time zone is later than the fifth moment of the (n+1)th time zone. Before the nth display zone begins TFT scanning in the (m+1)th sub-cycle, the (n+1)th backlight zone has already been lit. For example, the second fifth moment t5-2 of the second backlight zone is earlier than the first second moment t2-1 of the first display zone. Before the first display zone begins TFT scanning for the green sub-field Field-G, the red light emitter of the second backlight zone has already been lit. Therefore, there is a certain time interval between the lighting of the green light emitter in the first backlight zone and the lighting of the red light emitter in the second backlight zone. This prevents adjacent backlight zones from having different colored light emitters lit in close proximity, thus avoiding display anomalies.

[0176] In this embodiment, the (n+1)th fourth time point is earlier than the nth fifth time point. Before the nth backlight zone begins emitting light in the mth sub-cycle, the (n+1)th display zone has already completed the TFT scan in the mth sub-cycle. For example, the second fourth time point t4-2 of the second backlight zone is earlier than the first fifth time point t5-1 of the first display zone. Before the red light emitter of the first backlight zone begins emitting light, the second display zone has already completed the TFT scan for the red sub-field-R. Therefore, during the liquid crystal deflection period of the first display zone, the second display zone completes the TFT scan.

[0177] In this scenario, the short interval between the completion of TFT scanning by two adjacent display zones results in a short interval between the start of backlight illumination by two adjacent backlight zones. Consequently, the period during which adjacent backlight zones are simultaneously illuminated is relatively long. The scan time T for a single display zone... TFT When the time frame is sufficiently short, all backlight zones of the backlight module are illuminated by the same color light source for a shorter period of time, which can improve the display effect of the display device and reduce the display differences between different zones.

[0178] Comparing Figure 1C and Figure 3C, the backlight on-time in Figure 3C is significantly longer than the backlight illumination time in Figure 1C, which can significantly improve the display brightness. Moreover, the increase in backlight illumination time also helps to improve the color gamut.

[0179] Figures 4A to 4D show schematic diagrams of the backlight zones according to embodiments of the present disclosure. The N backlight zones can be arranged along the second direction y, and the positions of the N backlight zones correspond one-to-one with those of the N display zones.

[0180] Figure 4A shows the light emission state of the backlight zones between the Nth fifth moment for the red subfield and the first first moment for the red subfield. As shown in Figure 4A, the LEDs-R of the backlight zones 1 to N emit red backlight.

[0181] Figure 4B shows the light emission state of the backlight partitions between the first fifth moment for the green subfield and the Nth first moment for the red subfield. As shown in Figure 4B, the light emitter LED-G in the first backlight partition emits green backlight, and the light emitter LED-R in the Nth backlight partition emits red backlight.

[0182] Figure 4C shows the light emission state of the backlight partitions between the first fifth moment for the blue subfield and the Nth first moment for the green subfield. As shown in Figure 4C, the light emitter LED-B in the first backlight partition emits blue backlight, and the light emitter LED-G in the Nth backlight partition emits green backlight.

[0183] Figure 4D shows the light emission state of the backlight partitions between the first fifth moment for the red subfield and the Nth first moment for the blue subfield. As shown in Figure 4D, the light emitter LED-G in the first backlight partition emits red backlight, and the light emitter LED-B in the Nth backlight partition emits blue backlight.

[0184] The scanning time T of the embodiments of this disclosure is illustrated in conjunction with Figures 1D and 3A. TFT Liquid crystal deflection time T LC and backlight illumination time T BL Provide an illustrative explanation.

[0185] For example, the display device has a resolution of 2160*3840. The refresh rate of one frame of the field sequence is 60Hz, and the field sequence includes three sub-fields: R / G / B. Therefore, the refresh rate of a single sub-field is 180Hz. Thus, the total time for a single sub-field to complete its refresh is 5.56ms, of which the time for all display zones to complete TFT scanning is 3.12ms, and the liquid crystal response time is 2ms.

[0186] In the example shown in Figure 1D, the backlight illumination time T of the N backlight zones BL Both are 0.44ms.

[0187] In this embodiment of the disclosure, if N=12, the scan time T for each display partition is... TFT The liquid crystal deflection time T is 0.26ms. LC The backlight illumination time is 2ms, therefore the backlight illumination time T BL It takes 3.3ms.

[0188] If N=36, the scan time T for each display partition TFT The liquid crystal deflection time T is 0.087ms. LC The backlight illumination time is 2ms, therefore the backlight illumination time T BL It takes 3.473ms.

[0189] Backlight illumination time T BL The backlight operates for a long time with a large duty cycle. Since the average current driving the backlight module, I(average) = I(peak) * duty cycle, increasing the duty cycle can increase the average current while keeping the peak current constant. The average current can be kept constant by increasing the duty cycle and decreasing the peak current. Based on the volt-ampere characteristic curve of the backlight in the backlight module, reducing the peak current can reduce the operating voltage. According to P(power consumption) = I(average current) * U(operating voltage), reducing the operating voltage of the backlight reduces its power consumption.

[0190] Through the embodiments of this disclosure, by controlling the independent start and stop of light emission of N backlight zones, the backlight illumination duration of each backlight zone can be increased. Increasing the backlight illumination duration improves the luminous efficiency of the backlight module. This increases the brightness of the display device while maintaining a constant peak current, and reduces the power consumption of the display device while keeping the brightness constant. Furthermore, increasing the number of backlight zones divided into the backlight module increases the backlight illumination duration, thereby improving the luminous efficiency of the backlight module.

[0191] In some embodiments, the nth fifth time point and the nth third time point coincide. An exemplary illustration is provided in conjunction with Figures 5A and 5B.

[0192] Figures 5A and 5B show schematic diagrams of the field sequence display of a display module according to another embodiment of the present disclosure.

[0193] Figure 5A shows the scan time T for the 12 display partitions. TFT and liquid crystal deflection time T LC Please refer to the description in Figure 3A. Figure 5B shows the scan time T for a single display partition. TFT and liquid crystal deflection time T LC Please refer to the description in Figure 3B.

[0194] Since increasing the backlight illumination time of each backlight zone can improve the brightness and reduce the power consumption of the display device, the backlight illumination time can be increased by advancing the nth fifth moment. In extreme scenarios, the nth fifth moment is advanced to coincide with the nth third moment, that is, the moment when the scan signal received by the nth display zone changes from low to high level coincides with the moment when the backlight drive signal received by the nth backlight zone switches from the second state to the first state.

[0195] For example, the time interval between the first third time point t3-1 and the first fourth time point t4-1 is the scan time T. TFT The time interval between the first fourth time point t4-1 and the first fifth time point t-15 is the liquid crystal deflection time T. LC The interval between the first third time point t3-1 and the first first time point t1-1 is the backlight illumination time T. BL In this case, the backlight illumination time T BL The maximum value is T / M.

[0196] Figure 5C shows a timing diagram of the field sequence signals of a display module according to an embodiment of the present disclosure.

[0197] Figure 5C shows the timing diagram of the scan signals for the four display zones and the backlight drive signals for the four backlight zones in the sub-cycles of the red subfield Field-R, green subfield Field-G, and blue subfield Field-B in a display cycle T of a 1-frame image when N=4.

[0198] The functions of the scanning signals S-DIS-R, S-DIS-G, S-DIS-B, backlight sub-signals S-BLU-R1 to S-BLU-R4, S-BLU-G1 to S-BLU-G4, and S-BLU-B1 to S-BLU-B4 shown in Figure 5C can be found in the description of Figure 3C. For simplicity, similar parts will not be repeated.

[0199] The time intervals t1-1 to t1-4, t2-1 to t2-4, t3-1 to t3-4, t4-1 to t4-4, and t6-1 shown in Figure 5C can be referred to the description in Figure 3C. For the sake of brevity, similar parts will not be repeated.

[0200] In this embodiment of the disclosure, relative to the description in FIG3C, with the first third time t3-1, the second third time t3-2, the third third time t3-3, and the fourth third time t3-4 unchanged, the first fifth time t5-1 is consistent with the first third time t3-1, the second fifth time t5-2 is consistent with the second third time t3-2, the third fifth time t5-3 is consistent with the third third time t3-3, and the fourth fifth time t5-4 is consistent with the fourth third time t3-4.

[0201] In this embodiment of the disclosure, the display period T of one frame includes three consecutive sub-periods. The interval between the first fifth time t5-1 and the first first time t1-1 is T / 3, the interval between the second fifth time t5-2 and the second first time t1-2 is T / 3, the interval between the third fifth time t5-3 and the third first time t1-3 is T / 3, and the interval between the fourth fifth time t5-4 and the third first time t1-3 is T / 3.

[0202] Comparing Figures 1C, 3C, and 5C, the backlight on-time in Figure 5C is significantly longer than that in Figures 1C and 3C, which can further improve the display brightness. Moreover, the increase in backlight on-time also helps to improve the color gamut.

[0203] Figure 5D shows a schematic diagram of the field sequence display of a display module according to another embodiment of the present disclosure.

[0204] In this embodiment of the disclosure, the N backlight zones can emit light and stop emitting light synchronously. For example, at the first third moment, the N backlight zones emit backlight synchronously. At the first first moment, the N backlight zones stop emitting backlight synchronously.

[0205] In this embodiment of the disclosure, the backlight illumination time T BL The range is a*(N-1)+c≤T BL ≤T / M.

[0206] For example, the display device has a resolution of 2160*3840. The refresh rate of one frame is 60Hz, and the field sequence includes three sub-fields: R / G / B. Therefore, the refresh rate of a single sub-field is 180Hz. Thus, the total time for a single sub-field to complete its refresh is 5.56ms, of which the time for all display zones to complete TFT scanning is 3.12ms, the liquid crystal response time is 2ms, and the backlight illumination time T for each backlight zone is... BL The maximum value is 5.56ms.

[0207] Figure 6 shows a schematic diagram of the structure of the display module and the display driving circuit according to an embodiment of the present disclosure.

[0208] As shown in Figure 6, the display module includes a display panel, which may have multiple pixel electrodes arranged in an array, data lines and scan lines of different layers, and multiple thin-film transistors (TFTs) arranged in an array. The thin-film transistors include a source connected to the data lines, a gate connected to the scan lines, and a drain connected to the pixel electrodes.

[0209] For example, multiple pixel electrodes include H-row pixel electrodes and L-column pixel electrodes, and multiple thin-film transistors also include H-row thin-film transistors and L-column thin-film transistors.

[0210] The display driving circuit includes a scan driving circuit 41 and a data driving circuit 42. The scan driving circuit 41 is electrically connected to the gates of the H rows of thin-film transistors via H scan lines (Gate). The data driving circuit 42 is electrically connected to the sources of the L columns of thin-film transistors via 3L data lines (Data).

[0211] In this embodiment of the disclosure, the display driving signal includes a scan driving signal and a data signal. The scan driving circuit 41 is electrically connected to the gates of the respective H-row thin-film transistors via multiple scan lines, and is used to output the scan driving signal to the H-row thin-film transistors. The data driving circuit 42 is electrically connected to the sources of the respective L-row thin-film transistors via multiple data lines, and is used to output the data signal to the L-row thin-film transistors.

[0212] In this embodiment of the disclosure, the scan drive signal received by at least two rows of thin-film transistors (TFTs) transitions from a first level to a second level at the same time. For example, scan lines Gate1, Gate2, and Gate3 are electrically connected to the same output terminal of the scan drive circuit 41. The scan drive signal received by the first, second, and third row TFTs transitions from a low level to a high level at the same time. The first, second, and third row TFTs can perform TFT scanning simultaneously.

[0213] For example, a single scan line is electrically connected to the gates of at least two rows of thin-film transistors in a plurality of pixel rows. A single scan line can also be electrically connected to thin-film transistors in rows 1, 2, and 3, such that the scan drive signals received by the thin-film transistors in rows 1, 2, and 3 transition from low to high at the same time.

[0214] In this embodiment of the disclosure, the data signals received by at least two thin-film transistors in a single-row thin-film transistor switch from the third state to the fourth state at the same time, and the number of at least two thin-film transistors is the same as the number of rows of at least two thin-film transistors.

[0215] For example, data lines Data1, Data2, and Data3 are electrically connected to the three output terminals of the data driver circuit 42, respectively. The third state indicates that the data signal does not indicate RGB data, and the fourth state indicates that the data signal indicates RGB data. A data signal in the third state indicates no data, and a data signal in the fourth state indicates that data is present.

[0216] In this embodiment, the source of a single-column thin-film transistor is electrically connected to at least two of a plurality of data lines. For example, a single pixel column is electrically connected to three of a plurality of data lines. The data signals received by the first, second, and third thin-film transistors of the first column of thin-film transistors switch from a third state to a fourth state at the same time. The first, second, and third thin-film transistors of the first column of thin-film transistors can simultaneously receive data signals indicating RGB data.

[0217] Figure 7A shows a timing diagram of the scan signal according to an embodiment of the present disclosure.

[0218] As shown in Figure 7A, scan signals Gate1, Gate2, and Gate3 simultaneously transition from low to high levels. In this situation, the thin-film transistors in rows 1, 2, and 3 are simultaneously turned on, and data signals can be written to these thin-film transistors at the same time.

[0219] The first, second, and third thin-film transistors in the first column are located in the first, second, and third rows of thin-film transistors, respectively. Data signals for the first, second, and third thin-film transistors are provided by data lines Data1, Data2, and Data, respectively.

[0220] In this embodiment, the data lines can extend along the column direction of the thin-film transistor, and multiple data lines are arranged along the row direction. At least two data lines connected to a single column of thin-film transistors can be disposed between two columns of pixel electrodes. For example, three data lines are disposed between every two columns of pixel electrodes.

[0221] Data signals Data1, Data2, and Data3 simultaneously transition from low to high. The low level represents the third state, and the high level represents the fourth state. Since the first, second, and third thin-film transistors are turned on simultaneously, three data lines are needed to simultaneously write data signals to these transistors.

[0222] For example, the display device has a resolution of 2160*3840. The refresh rate of one frame of the field sequence is 80Hz, and the field sequence includes three sub-fields: R / G / B. Therefore, the refresh rate of a single sub-field is 240Hz. Thus, the total time for a single sub-field to complete its refresh is 5.56ms, of which the time for all display zones to complete the TFT scan is 4.2ms.

[0223] In this configuration, scanning one row of thin-film transistors takes 1.929 µs, and 2160 scans are required to complete scanning all rows of thin-film transistors. When the scan signal output from the scan drive circuit 41 can simultaneously scan three rows of thin-film transistors, 720 scans are needed to complete scanning all rows of thin-film transistors. Therefore, the time to complete scanning all rows of thin-film transistors is 1.4 ms. Due to the shortened scan time, the backlight illumination time for each sub-cycle can be increased by 2.8 ms.

[0224] Figure 7B shows a timing diagram of a scan signal according to another embodiment of the present disclosure.

[0225] As shown in Figure 7B, scan signals Gate1, Gate2, Gate3, GateH-2, GateH-1, and GateH simultaneously transition from low to high. In this state, the thin-film transistors in rows 1, 2, 3, H-2, H-1, and H are turned on, and data signals can be written to these transistors simultaneously.

[0226] For example, the scan signal output by the scan drive circuit 41 can scan simultaneously from the direction of the first row of thin-film transistors to the H row of thin-film transistors and from the H row of thin-film transistors to the first row of thin-film transistors, so as to shorten the time required to complete the scan of all rows of thin-film transistors.

[0227] For example, when the scan signal output by the scan drive circuit 41 can simultaneously scan six rows of thin-film transistors, all rows of thin-film transistors can be scanned after 360 scans. Therefore, the time to complete the scan of all rows of thin-film transistors is 0.7ms. Due to the shortened scan time, the backlight illumination time of each sub-cycle can be increased by 3.5ms.

[0228] Through the embodiments of this disclosure, by controlling the synchronous scanning of multiple rows of thin-film transistors in the display module, the TFT scanning time can be shortened. This allows the shortened scanning time to be converted into an increased backlight illumination time, thereby increasing the backlight illumination time and improving the luminous efficiency of the backlight module.

[0229] Figures 8A and 8B show schematic diagrams of the field sequence display of a display module according to another embodiment of the present disclosure.

[0230] Figure 8A shows the liquid crystal deflection time T for the 12 display zones. LC Please refer to the description in Figure 3A. Figure 8B shows the liquid crystal deflection time T for a single display zone. LC Please refer to the description in Figure 3B.

[0231] By controlling the synchronous scanning of multiple pixel rows in the display module, the TFT scanning time within a sub-cycle of a single subfield can be shortened. Within a sub-cycle of a single subfield, the liquid crystal deflection time T... LC The scan time T remains unchanged. TFT Shorten the backlight illumination time T BL This can be increased accordingly. Within a single sub-field's sub-cycle, the backlight illumination time T... BL Increased duration and scan time T TFT The shortened duration is consistent.

[0232] For example, when controlling the synchronous scanning of three pixel rows in the display module, the scanning time T shown in Figure 3B is... TFT Figure 8B shows the scan time T. TFT The scan time T shown in Figure 3B TFT 1 / 3, the scan time T shown in Figure 8B TFT The scan time T shown in Figure 3B was shortened. TFT 2 / 3. Therefore, relative to the backlight illumination time T shown in Figure 3B, BL Figure 8B shows the backlight illumination time T. BLThe scan time T shown in Figure 3B has been increased. TFT 2 / 3 of.

[0233] Figure 8C shows a timing diagram of the field sequence signals of a display module according to an embodiment of the present disclosure.

[0234] Figure 8C shows the timing diagram of the scan signals for the four display zones and the backlight drive signals for the four backlight zones in the sub-cycles of the red subfield Field-R, green subfield Field-G, and blue subfield Field-B in a display cycle T of a 1-frame image when N=4.

[0235] The functions of the scanning signals S-DIS-R, S-DIS-G, S-DIS-B, backlight sub-signals S-BLU-R1 to S-BLU-R4, S-BLU-G1 to S-BLU-G4, and S-BLU-B1 to S-BLU-B4 shown in Figure 8C can be found in the description of Figure 3C. For simplicity, similar parts will not be repeated.

[0236] The time intervals t1-1 to t1-4, t2-1 to t2-4, t3-1 to t3-4, and t6-1 shown in Figure 8C can be referenced in the description of Figure 3C. For the sake of brevity, similar parts will not be repeated.

[0237] In this embodiment of the disclosure, compared to the description in FIG3C, while the first third time interval t3-1, the second third time interval t3-2, the third third time interval t3-3, and the fourth third time interval t3-4 remain unchanged, the first fourth time interval t4-1, the second fourth time interval t4-2, the third fourth time interval t4-3, and the fourth fourth time interval t4-4 are all advanced. Therefore, the liquid crystal deflection time T LC With the time intervals remaining unchanged, the fifth time intervals t5-1 (1st), t5-2 (2nd), t5-3 (3rd), and t5-4 (4th) are all advanced. With the first time interval t1-1 (1st), t1-2 (2nd), t1-3 (3rd), and t1-4 (4th) remaining unchanged, the backlight illumination time T for the first to fourth backlight zones is determined. BL All increased.

[0238] In this embodiment, the Nth fourth time point is earlier than the first fifth time point. Before the first backlight zone begins to emit light in the mth sub-cycle, the Nth display zone has already completed the TFT scan in the mth sub-cycle. For example, the fourth fourth time point t4-2 of the fourth backlight zone is earlier than the first fifth time point t5-1 of the first display zone. Before the red light emitter of the first backlight zone begins to emit light, the fourth display zone has already completed the TFT scan for the red sub-field-R. Therefore, during the liquid crystal deflection period of the first display zone, the second, third, and fourth display zones have all completed their TFT scans.

[0239] In this scenario, the short interval between the completion of TFT scanning by the first and fourth display zones results in a short interval between the start of backlight illumination by the first and fourth backlight zones. Consequently, the period during which all backlight zones are simultaneously illuminated is longer. The scan time T for a single display zone... TFT When the time frame is sufficiently short, all backlight zones of the backlight module are illuminated by the same color light source for a shorter period of time, which can improve the display effect of the display device and reduce the display differences between different zones.

[0240] Comparing Figures 1C, 3C, and 8C, the backlight on-time in Figure 8C is significantly longer than that in Figures 1C and 3C, which can further improve the display brightness. Moreover, the increase in backlight on-time also helps to improve the color gamut.

[0241] In the example shown in Figure 1D, the backlight illumination time T of the N backlight zones BL Both are 0.44ms.

[0242] In this embodiment of the disclosure, when controlling the synchronous scanning of three pixel rows in the display module, if N=12, the scanning time T for each display partition is compared to Figure 3B. TFT The liquid crystal deflection time T was reduced from 0.26ms to 0.087ms. LC The backlight illumination time is 2ms, therefore the backlight illumination time T BL The time has increased from 3.3ms to 3.473ms.

[0243] When controlling the synchronous scanning of 3 pixel rows in the display module, if N=36, the scanning time T for each display partition is... TFT The liquid crystal deflection time T was reduced from 0.087ms to 0.029ms. LC The backlight illumination time is 2ms, therefore the backlight illumination time T BL It takes 3.531ms.

[0244] Figure 9 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0245] As shown in Figure 9, the display device 200 includes a backlight module 10, a display module 20, a backlight driving circuit 30, a display driving circuit, a processor 50, and a controller 60.

[0246] The first output terminal of the processor 50 is electrically connected to the input terminal of the controller 60 to output a display signal to the controller 60. The output terminal of the controller 60 is electrically connected to the input terminal of the display driver circuit 40 to output a scan signal to the display driver circuit 40. The second output terminal of the processor 50 is electrically connected to the input terminal of the backlight driver circuit 30 to output a backlight control signal to the backlight driver circuit 30.

[0247] In this embodiment of the disclosure, the processor 50 may be a Field Programmable Gate Array (FPGA) system board. The controller 60 may be a timing controller (TCON).

[0248] RGB source data is input to processor 50. Processor 50 divides the RGB source data into R data (R subfield), G data (G subfield), and B data (B subfield). Processor 50 outputs the R data, G data, and B data to controller 60 through a first output terminal. Controller 60 converts the R data, G data, and B data into corresponding clock signals, trigger signals, and display signals. It sends the clock signals and trigger signals to the scan drive circuit in display driver circuit 40 and the display signals to the data drive circuit in display driver circuit 40. The scan drive circuit outputs a scan signal to the display module based on the clock signal and trigger signal, and the data drive circuit outputs a data signal to the display module based on the display signal.

[0249] The processor 50 outputs a backlight control signal to the backlight driving circuit 30 through the second output terminal. The backlight control signal is used to indicate information such as the luminous brightness of the light-emitting element, the start time of luminous emission, and the stop time of luminous emission. Based on the backlight control signal, the backlight driving circuit 30 sends a backlight driving signal to the backlight module 10. The backlight driving signal can be a driving current that drives the backlight module to emit light.

[0250] For example, RGB source data can be transmitted in V-by-One (VBO) format, a digital interface standard specifically developed for image transmission. The RGB source data indicates a display resolution of 4K and a refresh rate of 60Hz. Processor 50 splits the RGB source data into R, G, and B data with a resolution of 4K and a refresh rate of 180Hz. The R, G, and B data with a resolution of 4K and a refresh rate of 180Hz are then output to controller 60.

[0251] Figure 10 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0252] As shown in Figure 10, the processor 50 is connected to the first backlight driving sub-circuit 31, and the first backlight driving sub-circuit 31 is connected to the second backlight driving sub-circuit 32.

[0253] When the backlight module is a large-size backlight module, a first backlight driving sub-circuit 31 and a second backlight driving sub-circuit 32 can be used to drive the backlight module. For example, the first backlight driving sub-circuit 31 can be a master backlight driving circuit, and the second backlight driving sub-circuit 32 can be a slave backlight driving circuit. For example, each backlight zone of the backlight module can be divided into two sub-zones, and the two sub-zones are arranged along a first direction x. The first backlight driving sub-circuit 31 and the second backlight driving sub-circuit 32 drive the two sub-zones respectively, controlling the two sub-zones to emit light synchronously and stop emitting light synchronously.

[0254] The processor 50 is electrically connected to the controller 60, which can be connected to the left X-printed circuit board assembly (XPCBA-L) and the right X-printed circuit board assembly (XPCBA-R) via two flexible circuit boards. The left X-printed circuit board assembly (XPCBA-L) and the right X-printed circuit board assembly (XPCBA-R) are then coupled to conductive connection terminals located in the bonding area on the array substrate of the display module via a chip-on-film (COF) film.

[0255] For example, the controller 60 will convert the display signal into the data signal format required by the data driving circuit, and then output the display signal to the data driving circuit via the flexible circuit board, the left X-printed circuit board assembly XPCBA-L, and the right X-printed circuit board assembly XPCBA-R. The controller 60 outputs a clock signal and a trigger signal to the scan driving circuit via the flexible circuit board, the left X-printed circuit board assembly XPCBA-L, and the right X-printed circuit board assembly XPCBA-R.

[0256] The RGB data indicated by the data signal is transmitted in units of pixels, with each pixel containing RGB data. For field-sequence display, the RGB data is stored separately for R, G, and B data.

[0257] Figure 11 shows a schematic diagram of the storage principle of RGB data according to an embodiment of the present disclosure.

[0258] As shown in Figure 11, 8 bits of RGB data can be transmitted using the VBO 3Byte data format, 10 bits of RGB data can be transmitted using the VBO 4Byte data format, and 12 bits of RGB data can be transmitted using the VBO 5Byte data format.

[0259] For example, in the VBO 3Byte data format, Byte0 stores 8 bits of R data, Byte1 stores 8 bits of G data, and Byte2 stores 8 bits of B data.

[0260] For example, in the VBO 4Byte data format, Byte0 stores 8 bits of R data, Byte1 stores 8 bits of G data, Byte2 stores 8 bits of B data, and Byte3 stores 2 bits of R data, 2 bits of G data, and 2 bits of B data.

[0261] For example, in the VBO 5-byte data format, Byte0 stores 8 bits of R data, Byte1 stores 8 bits of G data, Byte2 stores 8 bits of B data, Byte3 stores 2 bits of R data, 2 bits of G data, and 2 bits of B data, and Byte4 stores 2 bits of R data, 2 bits of G data, and 2 bits of B data.

[0262] Byte0, Byte1, and Byte2 are used to store the high-order bits of the RGB data, storing 8 bits of G data. Byte3 is used to store the middle bits of the RGB data. Byte4 is used to store the low-order bits of the RGB data.

[0263] Figure 12 shows a schematic diagram of the structure of a processor according to an embodiment of the present disclosure.

[0264] As shown in Figure 12, the processor 50 includes a microprocessor unit (MPU), synchronous dynamic random access memory (SDRAM), digital signal input interface, digital signal output interface, and peripheral device interface, etc.

[0265] Processor 50 receives RGB source data via digital signal input interface and stores it in frame buffer 0. Processor 50 outputs R data, G data, and B data to the data driving circuit via digital signal output interface.

[0266] For example, when the R data, G data and B data output by the processor 50 are applied to the data driving circuit 42 shown in Figure 6, the processor 50 needs to perform format conversion on the RGB source data so that the R data, G data and B data can be output to the three pixel rows simultaneously.

[0267] For example, RGB source data can be data with a resolution of 3840*2160, which includes 3840*2160*3 pixels. This 3840*2160*3 pixel data is stored in the frame buffer Frame buffer0.

[0268] The MPU stores the R data (pixels 1-3840) of the first row of frame buffer 0 in SDRAM, located in Byte0 of the first row of frame buffer 1. The R data of the second row of frame buffer 0 is stored in Byte1 of the first row of frame buffer 1. The R data of the third row of frame buffer 0 is stored in Byte2 of the first row of frame buffer 1. Frame buffer 1 is used to store R data, with Byte 0, Byte 1, and Byte 2 of each row storing the R data for three separate pixel rows.

[0269] The MPU stores the G data of pixels 1-3840 in the first row of frame buffer 0 in SDRAM at Byte0 of the first row of frame buffer 2. The G data of pixels 1-3840 in the second row of frame buffer 0 is stored at Byte1 of the first row of frame buffer 2. The G data of pixels 1-3840 in the third row of frame buffer 0 is stored at Byte2 of the first row of frame buffer 2. Bytes 0, 1, and 2 of each row of frame buffer 2 store the G data for three separate pixel rows.

[0270] The MPU stores the B data of pixels 1-3840 in the first row of frame buffer 0 in SDRAM at Byte0 of the first row of frame buffer 3. The B data of pixels 1-3840 in the second row of frame buffer 0 is stored at Byte1 of the first row of frame buffer 3. The B data of pixels 1-3840 in the third row of frame buffer 0 is stored at Byte2 of the first row of frame buffer 3. Bytes 0, 1, and 2 of each row of frame buffer 3 store the B data for three separate rows of pixels.

[0271] The MPU stores the R data of pixels 1-3840 in the fourth row of frame buffer 0 in SDRAM at Byte0 position of the second row of frame buffer 1, pixels 1-3840; the R data of pixels 1-3840 in the fifth row of frame buffer 0 is stored at Byte1 position of the second row of frame buffer 1, pixels 1-3840; and the R data of pixels 1-3840 in the sixth row of frame buffer 0 is stored at Byte2 position of the second row of frame buffer 1, pixels 1-3840.

[0272] A frame of 3840*3*2160 image data is stored as three monochrome data of 3840*3*720 RGB.

[0273] The digital signal output interface sends R, G, and B data of pixels in the three subfields of RBG respectively. When the digital signal output interface sends R data from frame buffer 1 to the controller, a red synchronization signal is output from the peripheral device interface to the backlight driver circuit to control the synchronization of the backlight module and the display module. When the digital signal output interface sends G data from frame buffer 2 to the controller, a green synchronization signal is output from the peripheral device interface to the backlight driver circuit. When the digital signal output interface sends B data from frame buffer 3 to the controller, a blue synchronization signal is output from the peripheral device interface to the backlight driver circuit.

[0274] After receiving R, G, and B data, the controller drives the display module. When the backlight drive circuit receives a synchronization signal, it illuminates the backlight of the corresponding color, achieving color synchronization between the display module and the backlight module.

[0275] The first row of Frame buffer1 contains Byte 0, Byte 1, and Byte 2, which contain the R data of the three pixel units located in the first pixel column of the three pixel rows. The controller outputs the R data of Byte 0, Byte 1, and Byte 2 of the first row to the first, second, and third pixels of the first pixel column via data lines Data1, Data2, and Data3 to realize the writing of R data.

[0276] The first row of Frame buffer 2 contains Byte0, Byte1, and Byte2, which contain the G data of the three pixel units located in the first pixel column of the three pixel rows. The controller outputs the first pixel, second pixel, and third pixel of the first pixel column from the first row of Byte0, Byte1, and Byte2 via data lines Data1, Data2, and Data3 to realize the writing of G data.

[0277] The first row of Frame buffer 3 contains Byte0, Byte1, and Byte2, which contain the B data of the three pixel units located in the first pixel column of the three pixel rows. The controller outputs the B data of Byte0, Byte1, and Byte2 of the first row to the first, second, and third pixels of the first pixel column via data lines Data1, Data2, and Data3 to realize the writing of B data.

[0278] In some embodiments, the backlight driving circuit includes: P driving sub-circuits, P power supply circuits, and a control circuit. The control circuit is connected in series with the P driving sub-circuits and outputs backlight control signals to the P driving sub-circuits. The output terminal of each of the P power supply circuits is electrically connected to Q backlight zones out of N backlight zones to provide operating voltage to the Q backlight zones, where P*Q = N, and P and Q are positive integers.

[0279] Taking P=3, Q=2, N=6, M=3 as an example, the structure of the backlight driving circuit is illustrated in Figure 13A.

[0280] Figure 13A shows a schematic diagram of the backlight driving circuit according to an embodiment of the present disclosure.

[0281] As shown in Figure 13A, the backlight driving circuit 30 includes three driving sub-circuits D1 to D3, three power supply circuits E1 to E3, a control circuit 311, a first power manager 312, and a second power manager 313.

[0282] In this embodiment, the control circuit 312 is connected to the drive sub-circuits D1 to D3 and is used to output backlight control signals to the drive sub-circuits D1 to D3. The output terminal of each of the power supply circuits E1 to E3 is electrically connected to two backlight partitions to provide operating voltage for the two backlight partitions.

[0283] The three driver sub-circuits provide backlight drive signals for a total of six backlight zones, and the three power supply circuits provide operating voltage for a total of six backlight zones.

[0284] In this embodiment of the disclosure, each driving sub-circuit includes three driving units. For example, driving sub-circuit D1 includes driving unit R1, driving unit G1, and driving circuit B1. Each driving unit includes two output terminals. Driving unit R1 includes two output terminals, which are electrically connected to the red light emitters of the two backlight zones respectively, to provide driving current to the red light emitters in the two backlight zones. Driving unit G1 includes two output terminals, which are electrically connected to the green light emitters of the two backlight zones respectively, to provide driving current to the green light emitters in the two backlight zones. Driving circuit B1 includes two output terminals, which are electrically connected to the blue light emitters of the two backlight zones respectively, to provide driving current to the blue light emitters in the two backlight zones.

[0285] Each power supply circuit includes three power supply units. For example, power supply circuit E1 includes power supply unit P1, power supply unit P2, and power supply unit P3. Power supply unit P1 provides operating voltage for the red light emitters in the two backlight zones, power supply unit P2 provides operating voltage for the green light emitters in the two backlight zones, and power supply unit P3 provides operating voltage for the blue light emitters in the two backlight zones.

[0286] In this embodiment, the first power manager 312 is electrically connected to the motherboard, and the motherboard supplies power to the first power manager 312. Power supply circuits E1 to E3 are also electrically connected to the motherboard, and the motherboard supplies power to the power supply circuits E1 to E3.

[0287] The first power manager 312 is electrically connected to the second power manager 313, and the first power manager 312 supplies power to the second power manager 313. The second power manager 313 is electrically connected to the control unit 311, and the second power manager 313 supplies power to the control unit 311.

[0288] Taking P=3, Q=12, N=36, M=3 as an example, the structure of the backlight driving circuit is illustrated in Figure 13B.

[0289] Figure 13B shows a schematic diagram of the backlight driving circuit according to another embodiment of the present disclosure.

[0290] The backlight driving circuit 30 includes a first backlight driving sub-circuit 31 and a second backlight driving sub-circuit 32. The backlight module includes 36 backlight zones, each backlight zone including a first sub-zone and a second sub-zone. The first backlight driving sub-circuit 31 is used to input backlight driving signals to the 36 first sub-zones, and the second backlight driving sub-circuit 32 is used to input backlight driving signals to the 36 second sub-zones.

[0291] The first backlight driving sub-circuit 31 includes three driving sub-circuits, three power supply circuits, a control circuit 311, a first power manager 312, and a second power manager 313.

[0292] Each driving sub-circuit may include three driving units, which provide backlight driving signals to the three color light emitters respectively. For example, the first driving sub-circuit may include driving unit R1, driving unit G1, and driving unit B1; the second driving sub-circuit may include driving unit R2, driving unit G2, and driving unit B2; and the third driving sub-circuit may include driving unit R3, driving unit G3, and driving unit B3.

[0293] Each power supply circuit may include three power supply units, which supply power to the three light-emitting elements of different colors respectively. For example, the first power supply circuit may include power supply units P1 to P3, the second driving sub-circuit may include power supply units P4 to P6, and the third driving sub-circuit may include power supply units P7 to P8.

[0294] For example, the control circuit 311 can be a microcontroller unit (MCU). The power supply units P1 to P9 can be boost circuits.

[0295] Each driver sub-circuit includes 12 output terminals, which are electrically connected to 12 backlight zones to provide backlight drive signals to Q backlight zones during a display cycle. For example, each output terminal of the driver sub-circuit includes a first drive output terminal of driver unit R1, a second drive output terminal of driver unit G1, and a third drive output terminal of driver unit B1.

[0296] The moment when the backlight driving signal sent by the driving sub-circuit to the nth backlight zone for the mth sub-cycle switches from the first state to the second state is the nth first moment. For example, in the mth sub-cycle, the moment when the backlight driving signal output by the driving unit R1 of the driving sub-circuit to the nth backlight zone through the first driving output terminal switches from the first state to the second state is the nth first moment.

[0297] For example, the output of each of the nine power supply units P1 to P9 is electrically connected to 12 of the 36 first sub-zones to provide operating voltage to the 12 backlight zones. Each first sub-zone includes a first input terminal, a second output terminal, and a third input terminal, which are the power supply input terminals for red, green, and blue LEDs, respectively. For example, power supply unit P1 is electrically connected to the first input terminal of the red LED in each of the 12 first sub-zones to provide operating voltage to the red LEDs in the 12 first sub-zones. Power supply unit P2 is electrically connected to the second input terminal of the green LED in each of the 12 first sub-zones to provide operating voltage to the green LEDs in the 12 first sub-zones. Power supply unit P3 is electrically connected to the third input terminal of the blue LED in each of the 12 first sub-zones to provide operating voltage to the blue LEDs in the 12 first sub-zones.

[0298] For example, control circuit 311 is serially connected to nine drive units to output backlight signals to the nine drive units. Each drive unit includes 12 output terminals, which are electrically connected to 12 first sub-sections to output backlight drive signals to the 12 first sub-sections. Each first sub-section includes a fourth input terminal, a fifth input terminal, and a sixth input terminal, which are the drive input terminals for red, green, and blue LEDs, respectively. For example, drive unit R1 is electrically connected to the fourth input terminal of the red LED in each of the 12 backlight sections to provide backlight drive signals to the red LEDs in the 12 first sub-sections. Drive unit G1 is electrically connected to the fifth input terminal of the green LED in each of the 12 first sub-sections to provide backlight drive signals to the green LEDs in the 12 first sub-sections. Drive unit B1 is electrically connected to the sixth input terminal of the blue LED in each of the 12 first sub-sections to provide backlight drive signals to the blue LEDs in the 12 first sub-sections.

[0299] In this embodiment, the output terminal of drive unit R1 is electrically connected to the first input terminal of drive unit G1, and the output terminal of drive unit G1 is electrically connected to the first input terminal of drive unit B1. The output terminal of drive unit B1 is electrically connected to the first input terminal of drive unit R2, and the output terminal of drive unit R2 is electrically connected to the first input terminal of drive unit G2. The output terminal of drive unit G2 is electrically connected to the first input terminal of drive unit B2, and the output terminal of drive unit B2 is electrically connected to the first input terminal of drive unit R3. The output terminal of drive unit R3 is electrically connected to the first input terminal of drive unit G3, and the output terminal of drive unit G3 is electrically connected to the first input terminal of drive unit B3. The first input terminal of drive unit G1 is electrically connected to the first output terminal of control circuit 311.

[0300] The first input terminal of the control circuit 311 is electrically connected to the input terminal IN1 of the first backlight driving sub-circuit 31, and the input terminal IN1 is connected to the processor 50. The input terminal IN1 is a Serial Peripheral Interface (SPI). The first backlight driving sub-circuit 31 receives the backlight control signal from the processor 50 through the input terminal IN1 and sends the backlight control signal to the control circuit 311.

[0301] Control circuit 311 packages the backlight signals used to control drive units R1 to B3 into a data packet and sends the data packet to drive unit R1. Drive unit R1 obtains the required backlight signal from the data packet and sends the data packet to drive unit G1. Drive unit G1 obtains the required backlight signal from the data packet and sends the data packet to drive unit B1. Similarly, drive unit B3 obtains the required backlight signal from the data packet and sends a feedback signal to control circuit 311, enabling control circuit 311 to determine that drive units R1 to B3 have all obtained the required backlight signal.

[0302] The input terminal of the first power controller 312 is electrically connected to an external motherboard, which provides operating voltage to the first power controller 312. The output terminal of the first power controller 312 is electrically connected to the input terminal of the second power controller 313 and the second input terminals of each of the nine drive units, providing operating voltage to the second power controller 313 and the nine drive units. The input terminal of the second power controller 313 is electrically connected to the first input terminal of the control circuit 311, providing operating voltage to the control circuit 311. The nine power supply units P1 to P9 are also electrically connected to the external motherboard, which provides operating voltage to the nine power supply units P1 to P9.

[0303] For example, the first power controller 312 and the second power controller 322 can be buck converters (Buck ICs) that reduce the received power supply voltage, periodically switch the input voltage to the output terminal using a switching transistor, and filter the voltage through an inductor and a diode to output a lower, stable voltage.

[0304] For example, the external motherboard provides a 24V operating voltage to the first power controller 312 and the nine power supply units P1 to P9. The first power controller 312 provides a 12V operating voltage to the second power controller 313 and the nine drive units. The second power controller 313 provides a 3.3V operating voltage to the control circuit 311.

[0305] In this embodiment of the present disclosure, the voltage output by the first power supply unit for the red light-emitting element is less than or equal to the voltage output by the third power supply unit for the blue light-emitting element, and the voltage output by the third power supply unit for the blue light-emitting element is less than or equal to the voltage output by the second power supply unit for the green light-emitting element.

[0306] For example, the operating voltage of red LEDs is 2.15V to 3.1V, that of green LEDs is 2.9V to 3.6V, and that of blue LEDs is 2.9V to 3.4V. If 15 LEDs form a string, the operating voltage output by power supply unit 1 must be at least 3.1 * 15 = 46.5V, the operating voltage output by power supply unit 2 must be at least 3.6 * 15 = 54V, and the operating voltage output by power supply unit 3 must be at least 3.4 * 15 = 51V.

[0307] To ensure the normal operation of the LED chips, the output voltages of power supply units P1, P2, and P3 must be slightly higher than the maximum voltage supported by the LED chips to ensure they emit light correctly and prevent burnout. Therefore, the operating voltage of power supply unit P1 can be 47–50V, power supply unit P2 can be 54–57V, and power supply unit P3 can be 51–54V. For example, power supply unit P1 could output 48.5V, power supply unit P2 could output 55.5V, and power supply unit P3 could output 52.5V.

[0308] The first backlight driving sub-circuit 31 also includes an input terminal IN3, which is used to receive the programming information of the control circuit 311.

[0309] The second backlight driving sub-circuit 32 includes 9 driving units, 9 power supply units P1 to P9, and a third power manager 321.

[0310] The input terminals of the third power manager 321 are electrically connected to an external motherboard, which provides operating voltage to the third power manager 321. The output terminals of the third power manager 321 are electrically connected to the second input terminals of each of the nine drive units, in order to provide operating voltage to the nine drive units.

[0311] The second input terminal of the control circuit 311 is electrically connected to the output terminal OUT1 of the first backlight driving sub-circuit 31, and the output terminal OUT1 is connected to the input terminal IN2 of the second backlight driving sub-circuit 32. The output terminal OUT1 and the input terminal IN2 are SPI interfaces. The first backlight driving sub-circuit 31 sends the backlight control signal to the second backlight driving sub-circuit 32 through the output terminal OUT1. The input terminal IN2 of the second backlight driving sub-circuit 32 is electrically connected to the first input terminal of the driving unit 1.

[0312] The nine driving units and nine power supply units included in the second backlight driving sub-circuit 32 can be referenced from the nine driving units and nine power supply units included in the first backlight driving sub-circuit 31. For the sake of simplicity, similar parts will not be described again.

[0313] The first backlight driving sub-circuit 31 and the second backlight driving sub-circuit 32 control the first and second sub-sections of the same backlight zone to emit light and stop emitting light synchronously.

[0314] Figure 14 shows a schematic diagram of the structure of an LED chip according to an embodiment of the present disclosure.

[0315] Figure 14 shows the structure of the LED chips included in the backlight module. Each LED chip includes a red LED-R, a green LED-G, and a blue LED-B. The red LED-R is used to emit red backlight, the green LED-G is used to emit green backlight, and the blue LED-B is used to emit blue backlight.

[0316] The LED chip includes input terminals 1 to 6. For example, input terminal 1 can be electrically connected to power supply unit 1 to receive the operating voltage provided by power supply unit 1. Input terminal 4 is electrically connected to drive unit 1 to receive the backlight drive signal provided by drive unit 1. Input terminal 1 can be the positive terminal of the red LED-R, and input terminal 4 can be the negative terminal of the red LED-R. When the backlight drive signal received by input terminal 1 switches from the second state to the first state, the red LED-R emits red backlight. When the backlight drive signal received by input terminal 1 switches from the first state to the second state, the red LED-R stops emitting red backlight.

[0317] For example, input terminal 2 can be electrically connected to power supply unit 2 to receive the operating voltage provided by power supply unit 2. Input terminal 5 is electrically connected to drive unit 2 to receive the backlight drive signal provided by drive unit 2. Input terminal 2 can be the positive terminal of the green LED-G, and input terminal 5 can be the negative terminal of the green LED-G. When the backlight drive signal received by input terminal 2 switches from the second state to the first state, the green LED-G emits green backlight. When the backlight drive signal received by input terminal 2 switches from the first state to the second state, the green LED-G stops emitting green backlight.

[0318] For example, input terminal 3 can be electrically connected to power supply unit 3 to receive the operating voltage provided by power supply unit 3. Input terminal 6 is electrically connected to drive unit 3 to receive the backlight drive signal provided by drive unit 3. Input terminal 3 can be the positive terminal of blue LED-B, and input terminal 6 can be the negative terminal of blue LED-B. When the backlight drive signal received by input terminal 3 switches from the second state to the first state, blue LED-B emits blue backlight. When the backlight drive signal received by input terminal 3 switches from the first state to the second state, blue LED-B stops emitting blue backlight.

[0319] Red LED-R, green LED-G, and blue LED-B are packaged into a single LED via a chip. The red LED-R, green LED-G, and blue LED-B are arranged along a second direction y. The pixel rows of the display section comprise multiple pixels arranged along a first direction x, which intersects the second direction y.

[0320] The red LED-R, green LED-G, and blue LED-B have the same light directionality in the first direction (x), but different light directions in the second direction (y). Arranging the red LED-R, green LED-G, and blue LED-B along the second direction (y) can prevent color difference in the backlight module along the first direction (x).

[0321] Figure 15 shows a schematic diagram of the structure of a first backlight driving sub-circuit according to an embodiment of the present disclosure.

[0322] As shown in Figure 15, the circuit board of the first backlight driving sub-circuit 31 is provided with connectors con1 to con9, driving units R1 to R3, driving units G1 to G3, driving units B1 to B3, power supply units P1 to P9, control circuit 311, first power manager 312 and second power manager 313.

[0323] In this embodiment of the present disclosure, drive unit R1, drive unit G1 and drive unit B1 are disposed on the first side of the circuit board along the second direction y, drive unit R2, drive unit G2 and drive unit B2 are disposed on the second side of the circuit board along the first direction x, drive unit R3, drive unit G3 and drive unit B3 are disposed on the third side of the circuit board along the second direction y, and the first power manager 312 and the second power manager 313 are disposed on the fourth side of the circuit board along the first direction x. The first side is opposite to the third side, and the second side is opposite to the fourth side.

[0324] In this embodiment of the disclosure, driving unit R1 is connected to the backlight module via con1, driving unit G1 is connected to the backlight module via con2, driving unit B1 is connected to the backlight module via con3, driving unit R2 is connected to the backlight module via con4, driving unit G2 is connected to the backlight module via con5, driving unit B2 is connected to the backlight module via con6, driving unit R3 is connected to the backlight module via con7, driving unit G3 is connected to the backlight module via con8, and driving unit B3 is connected to the backlight module via con9.

[0325] In this embodiment of the present disclosure, each driving unit includes a driving chip and 12 transistors, and the 12 transistors are connected to a connector to form the output terminal of the driving unit 12.

[0326] In this embodiment of the disclosure, the control circuit 311 may be disposed on one side of the drive unit R1.

[0327] In this embodiment of the present disclosure, power supply units P1 to P9 are arranged in a 3*3 array in the middle of the circuit board, and drive units R1 to R3, drive units G1 to G3, and drive units B1 to B3 are arranged around the power supply units P1 to P9.

[0328] Figure 16 shows a schematic diagram of the structure of a drive unit according to an embodiment of the present disclosure. The drive unit shown in Figure 16 is any one of drive units R1 to R3, drive units G1 to G3, and drive units B1 to B3 in Figures 14 and 15.

[0329] As shown in Figure 16, the driving unit includes a driver chip and 12 transistors MOS1 to MOS12.

[0330] For example, transistors MOS1 to MOS12 are N-type transistors. The drains of transistors MOS1 to MOS12 are electrically connected to the 12 output terminals LED-OUT1 to LED-OUT12, respectively. The sources of transistors MOS1 to MOS12 are electrically connected to pins S1 to S12 of the driver chip, respectively. The gates of transistors MOS1 to MOS12 are electrically connected to pins G1 to G12 of the driver chip, respectively.

[0331] The process of outputting the backlight drive signal using transistor MOS1 is illustrated schematically.

[0332] The gate of transistor MOS1 is electrically connected to the first terminal of resistor R1, and the second terminal of resistor R1 is electrically connected to pin G1. The drain of transistor MOS1 is electrically connected to the output terminal LED-OUT1. The gate of transistor MOS1 is also electrically connected to the first terminal of resistor R2, and the second terminal of resistor R2 is grounded. The source of transistor MOS1 is electrically connected to pin S1 and also electrically connected to the first terminal of resistor R3, and the second terminal of resistor R3 is grounded. Resistors R1, R2, and R3 divide the voltage flowing through them, thereby achieving the effect of protecting the circuit.

[0333] A high-level gate signal output from pin G1 can turn on transistor MOS1, at which point the source and drain of transistor MOS1 are turned on. The source signal output from pin S1 can be output to the output terminal LED-OUT1 via transistor MOS1, thus using the source signal as a backlight driving signal.

[0334] The connection relationships between transistors MOS2 to MOS12 and resistors R4 to R36 can be referenced to the connection relationships between transistor MOS1, resistors R1, R2, and R3. The operating processes of transistors MOS2 to MOS12 can be referenced to those of transistor MOS1. For simplicity, similar details will not be repeated.

[0335] In this embodiment, the VIN pin of the driver chip is used to receive the 12V operating voltage output by the first power manager 312. The FAULT pin is used to receive a fault signal, which can indicate the operating status of multiple driving units in the backlight driving circuit. The FB1 pin is used to receive a feedback signal, which is used to determine the power supply status of the power supply unit to the backlight module.

[0336] Pins CS, MOSI, MISO, and SCK are used to enable serial communication between multiple drive units.

[0337] Pin CS is used to electrically connect with control circuit 311 to realize communication with control circuit 311 and receive backlight signals from control circuit 311.

[0338] Pin MOSI is used to receive serially transmitted data packets. For example, pin MOSI is the first input terminal of drive unit G1, and pin MOSI of drive unit G1 is connected to the output terminal of drive unit R1.

[0339] The MISO pin is used to send data packets serially. For example, the MISO pin is the output terminal of the driver unit R1, and the MISO pin of the driver unit R1 is electrically connected to the MOSI pin of the driver unit G1, so that the driver unit R1 can send data packets to the driver unit G1.

[0340] The SCK pin is used to receive a clock signal, which is used to synchronize the timing of data transmission. The clock signal controls the data transmission rate and timing, ensuring that data is correctly transmitted between multiple drive units.

[0341] The VSYNC and CLKN pins are used to receive synchronization signals. For example, the VSYNC pin receives the vertical synchronization signal, and the CLKN pin receives the horizontal synchronization signal. These vertical and horizontal synchronization signals ensure that the backlight module and display module operate in sync.

[0342] Pins G13 to G16 function similarly to pins G1 to G12, and pins S13 to S16 function similarly to pins S1 to S12. Pins G13 to G16 and S13 to S16 can expand the number of output terminals to increase the number of backlight zones driven.

[0343] The Driver signal, based on the data packet received at pin MOSI, controls the signal outputs of pins G1-G12 and S1-S12, thereby controlling the output terminals LED-OUT1-LED-OUT12 to output backlight drive signals. By controlling the gate signals output from pins G1-G12, the source signal can be controlled to be output, thus controlling whether the connected backlight zones emit light or stop emitting light. By controlling the current value of the drive current represented by the source signals output from pins S1-S12, the brightness of the connected backlight zones can be controlled. The Driver signal can also control the magnitude of the drive current output to the backlight zones by controlling the drive current value represented by the source signals, thereby controlling whether the backlight emits light or stops emitting light.

[0344] Figure 17 shows a schematic flowchart of a display method according to an embodiment of the present disclosure.

[0345] As shown in Figure 17, the display method may include operation S110.

[0346] In the embodiments of this disclosure, the display method can be applied to any of the display devices described above.

[0347] In operation S110, when it is determined that the scanning signal received in the (m+1)th sub-cycle of the M sub-cycle of the nth display partition changes from the first level to the second level, the backlight drive signal received in the mth sub-cycle of the M sub-cycle of the nth backlight partition is controlled to switch from the first state to the second state, 1≤m<M, where m is a positive integer.

[0348] In this embodiment of the disclosure, the display device includes a display module, a backlight module, a display driving circuit, and a backlight driving circuit. The display module is divided into N display zones, and the backlight module is divided into N backlight zones. The nth backlight zone among the N backlight zones provides backlight to the nth display zone among the N display zones, where 1 ≤ n ≤ N, and n and N are positive integers. The output terminal of the display driving circuit is electrically connected to the N input terminals of the display module to output N scanning signals to the N display zones. The output terminal of the backlight driving circuit is electrically connected to the N input terminals of the backlight module to output N backlight driving signals to the N backlight zones. The display period for the display device to display one frame of an image includes M consecutive sub-cycles, where 1 ≤ m < M, and m and M are positive integers.

[0349] In this embodiment of the disclosure, operation S110 is similar to the operation performed by any of the display devices described above, and will not be repeated here.

[0350] In this embodiment, the duration of the display cycle is T, and the duration of the sub-cycle is T / M, where T is a positive number. The moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle of M sub-cycles switches from the first state to the second state is the nth first moment. The moment when the scan signal received by the nth display partition in the mth sub-cycle jumps from the first level to the second level is the nth third moment. The nth third moment is earlier than the nth first moment in the display cycle, and the interval between the nth third moment and the nth first moment is T / M.

[0351] In this embodiment of the disclosure, the scanning signals received by the N display zones in the m-th sub-cycle sequentially change from a first level to a second level, and the backlight driving signals received by the N backlight zones in the m-th sub-cycle sequentially switch from a first state to a second state; the moment when the scanning signal received by the n-th display zone in the m-th sub-cycle changes from a second level to a first level is the n-th fourth moment, and the moment when the backlight driving signal received by the n-th backlight zone in the m-th sub-cycle switches from a second state to a first state is the n-th fifth moment. The time sequence in the display cycle is the n-th third moment, the n-th fourth moment, the n-th fifth moment, and the n-th first moment; the first interval between the n-th third moment and the n-th fourth moment is a, the second interval between the n-th fifth moment and the n-th first moment is b, and the third interval between the n-th fifth moment and the n-th second moment is c, where b = a*(N-1) + c.

[0352] In this embodiment of the disclosure, the duration of the fourth interval between the nth fourth time point and the nth fifth time point is d, and a+d+c=T / M.

[0353] In this embodiment of the disclosure, the interval between the nth fifth time and the (n+1)th fifth time is the same as the interval between the nth third time and the (n+1)th third time, where 1 ≤ n < N. The interval between the nth first time and the (n+1)th first time is the same as the interval between the nth third time and the (n+1)th third time.

[0354] In this embodiment of the disclosure, the scanning signals received by the N display zones in the m-th sub-cycle sequentially change from a first level to a second level, and the backlight driving signals received by the N backlight zones in the m-th sub-cycle sequentially switch from a first state to a second state. The moment when the backlight driving signal received by the first backlight zone in the (m+1)-th sub-cycle switches from the second state to the first state is the first sixth moment. The Nth first moment is later than the first sixth moment.

[0355] In this embodiment of the disclosure, the display method further includes: when it is determined that the scanning signal received by the nth display partition in the mth sub-cycle changes from a first level to a second level, controlling the backlight driving signal received by the nth backlight partition in the mth sub-cycle to switch from a second state to a first state.

[0356] In this embodiment of the disclosure, the display module includes multiple pixel rows, the display driving circuit includes a scan driving circuit, and the display driving signal includes a scan driving signal; the output terminal of the scan driving circuit is electrically connected to the input terminal of the multiple pixel rows, and is used to output the scan driving signal to the multiple pixel rows. The display method further includes: controlling at least two of the multiple pixel rows to have the scan driving signal received change from a first level to a second level at the same time.

[0357] In this embodiment, the display module includes multiple pixel columns, the display driving circuit includes a data driving circuit, and the display driving signal includes a data signal; the output terminal of the data driving circuit is electrically connected to the input terminals of the multiple pixel columns, and is used to output data signals to the multiple pixel rows. The display method further includes: controlling the timing of the data signals received by at least two pixels in a single pixel column switching from a third state to a fourth state to be consistent, and the number of at least two pixels being consistent with the number of at least two pixel rows.

[0358] In the practical application of field-sequential display technology, TFT scanning occupies most of the time of a single field, and the slow response speed of liquid crystal results in a short LED illumination time, easily leading to color crosstalk between fields. For example, for a display screen with 4K resolution and a 180Hz refresh rate, the duration of a single field in field-sequential display is 1 / 180s = 5.56ms. The liquid crystal response time of this display screen when changing between different gray levels is shown in Table 1. As can be seen from Table 1, the average liquid crystal response time is approximately 4.76ms, and the liquid crystal response time from the minimum gray level L0 to the maximum gray level L255 is approximately 9.5ms. Therefore, in some gray level display scenarios, the liquid crystal of the first sub-field may not have finished responding before the next sub-field begins refreshing, resulting in color crosstalk between fields.

[0359] Table 1

[0360] In related technologies, one method to shorten the response time of liquid crystals is to add an overdrive function to the timing controller. Overdrive (OD) is a commonly used method to improve screen response speed. Its mechanism is to provide an overshoot voltage when the display data of two adjacent fields changes. The overshoot voltage undergoes a rise and a fall before finally falling back to the target voltage, thereby accelerating the response speed of pixel deflection and reducing screen ghosting.

[0361] For field-sequential display devices using the three primary colors of red (R), green (G), and blue (B), the system divides the image into three sub-fields: red, green, and blue. However, since the data for each of these three sub-fields is different, and the data between adjacent fields is constantly changing, field-sequential display technology requires the use of OD (Original Distributed Origin) technology for almost every field during operation. This high frequency of OD technology activation further exacerbates the instability of color display. For example, when displaying red, green, and blue separately at the same grayscale, the total brightness of the three monochromatic lights is not equal to the brightness of white displayed directly at the same grayscale. This results in a brightness imbalance where R+G+B ≠ W, leading to color deviation in field-sequential display.

[0362] In one example, the display device operates at a frequency of 240Hz, and the duration of each field is 1 / 240s = 4.17ms. Specifically, in the first subfield, the grayscale brightness of the image displayed by the display device is L63, and in the second to fourth subfields, the grayscale brightness of the image displayed by the display device is L127.

[0363] Figure 18A shows a schematic diagram of an example display without OD-driven grayscale.

[0364] As shown in Figure 18A, when grayscale is not driven by OD for display, the time taken for the liquid crystal to rotate to the target angle is 7.5ms, meaning the liquid crystal response time is 7.5ms. This response time is longer than the time of one field, resulting in color crosstalk between fields. Furthermore, in the second subfield, the liquid crystal does not rotate to the target angle, causing the light emitted by the liquid crystal in the second subfield to be insufficient.

[0365] The time of OD driving is measured in fields; the grayscale level will not change within a single field. When OD technology is activated to change the image from grayscale level L63 to L127, OD technology can be enabled in the second sub-field. When the grayscale levels set in OD are L159, L145, and L140, the grayscale response time of the display device is different, which in turn causes the rotation angle of the liquid crystal to be different.

[0366] Figure 18B shows a schematic diagram of an example of display based on an OD-driven grayscale.

[0367] As shown in Figure 18B, when the gray level of OD is set to L159, the gray level response time is 3ms, which is less than the time of one field. This means that the liquid crystal rotation angle reaches the target angle in the second subfield in 3ms. In the remaining 1.17ms of the current field, the liquid crystal continues to rotate beyond the target angle to reach the highest point, and then rotates to the target angle again in the third subfield.

[0368] Figure 18C shows a schematic diagram of an example of displaying grayscale based on another OD-driven method.

[0369] As shown in Figure 18C, when the gray level of OD is set to L145, the gray level response time is 4.17ms, which is equal to the time of one field, indicating that the liquid crystal rotation angle reaches the target angle when the second subfield ends.

[0370] Figure 18D shows a schematic diagram of an example of displaying grayscale based on another OD-driven method.

[0371] As shown in Figure 18D, when the grayscale setting of OD is L140, the grayscale response time is 5ms, which is greater than the time of one field. This indicates that the liquid crystal rotation angle did not reach the target value at the end of the second subfield. The liquid crystal needs to continue rotating for 1ms in the third subfield to reach the target value.

[0372] Therefore, regardless of how the OD grayscale is adjusted, the liquid crystal is always in a rotating state within the current field time, and the liquid crystal angle is not a constant value. This means that the liquid crystal in the current subfield is not stable at a particular grayscale, and the light emission of the liquid crystal in the current subfield is unstable. When displaying red, blue, green, or other color images in a field sequence, the liquid crystal is always in an OD overdrive state due to the OD effect, and the brightness of the image is affected by the OD setting; the brightness will vary depending on the grayscale setting. When displaying white images in a field sequence, since the grayscale of the same pixel in the subfield is the same, the OD has no effect, and the brightness of the white image is not affected by the OD setting. Thus, it is evident that the brightness and color of a color image are affected by the OD setting, resulting in a brightness imbalance.

[0373] In related technologies, brightness imbalance can be resolved by adjusting the OD (Obstruction Displacement) settings. For example, when the grayscale value is 127, precise adjustment of the OD parameters can ensure that the sum of the brightness of R127 (red in grayscale 127), G127 (green in grayscale 127), and B127 (blue in grayscale 127) equals the brightness of W127 (white in grayscale 127), i.e., satisfying R127 + G127 + B127 = W127. However, in real-world applications, the operating state of display devices is not fixed. If the illumination time of sub-pixels needs to be adjusted according to current display requirements, the brightness balance achieved through OD adjustment will be broken, and the brightness imbalance problem of R + G + B ≠ W will reappear.

[0374] Therefore, it is clear that simply adjusting the OD settings cannot fundamentally solve the color mixing problem and the inconsistency between the colors and the original image in field sequence display technology.

[0375] Therefore, the embodiments of this disclosure propose a new field-sequence display method. Based on the field-sequence display method of related technologies, each sub-cycle of the display period of a display device displaying a frame is divided into two sub-fields in M ​​sub-cycles. In the first sub-field, OD driving is used to accelerate the deflection speed of the liquid crystal. In the second sub-field, OD driving is not used, so that the deflection angle of the liquid crystal in the second sub-field is relatively stable, thereby eliminating the brightness deviation caused by the instability of liquid crystal deflection and at least partially improving the brightness imbalance problem.

[0376] Figure 19 shows a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0377] As shown in Figure 19, the display device 1900 includes a backlight module 10, a display module 20, a backlight driving circuit 30, and a display driving circuit 40.

[0378] In this embodiment, the display module 20 includes N display zones, namely, the first display zone, ..., the nth display zone, ..., the Nth display zone. The backlight module 10 includes N backlight zones, namely, the first backlight zone, ..., the nth backlight zone, ..., the Nth backlight zone. The nth backlight zone provides backlight for the nth display zone among the N display zones, where 1 ≤ n ≤ N, and n and N are positive integers.

[0379] The output of the display driving circuit 40 is electrically connected to the N inputs of the display module 20 to output N display driving signals to the N display zones. The output of the backlight driving circuit 30 is electrically connected to the N inputs of the backlight module 10 to output N backlight driving signals to the N backlight zones.

[0380] In this embodiment of the disclosure, the display driving signal may include a scan signal and a data signal. The scan signal can be used to control the TFT to turn on and off, and the data signal can be used to drive the liquid crystal cell to deflect.

[0381] The N display driving signals output by the display driving circuit 40 sequentially drive the N display zones to perform TFT scanning and liquid crystal cell deflection. The N backlight driving signals output by the backlight driving circuit 30 sequentially drive the N backlight zones to emit backlight. For example, when the nth display zone completes TFT scanning and liquid crystal deflection under the drive of the display driving signals, the backlight driving signals drive the nth backlight zone to emit backlight. The backlight emitted by the nth backlight zone is displayed through the nth display zone.

[0382] For example, the display driving circuit 40 includes a scan driving circuit, a data driving circuit, and a common voltage generating circuit. The scan driving circuit is connected to multiple scan lines (Gates) and sequentially provides scan signals to the multiple scan lines (Gates). The scan signals drive the connected TFTs to turn on. The data driving circuit is connected to multiple data lines (Data) and writes data signals to the multiple data lines (Data). The data signals are input to the corresponding pixel electrodes through the turned-on TFTs, generating an electric field between the pixel electrodes and the common electrode to control the liquid crystal. The common voltage generating circuit is electrically connected to the common electrode and provides a common voltage signal to the common electrode.

[0383] When the scan signal received by the nth display partition is at a high level, the TFT of the nth display partition is turned on, and the data signal is written to the nth display partition, causing the liquid crystal cell to deflect. When the scan signal received by the nth display partition is at a low level, the TFT of the nth display partition is turned off, the data signal stops being written to the nth display partition, and the liquid crystal cell does not deflect.

[0384] Each backlight zone of the backlight module 10 includes multiple backlight sources. The backlight driving circuit 30 is connected to the multiple backlight sources and drives the light-emitting elements corresponding to the subfields in the backlight sources to operate. For example, the backlight driving signal is a driving current applied to the backlight zone. When the current value of the driving current received by the nth backlight zone reaches the operating current value required for light emission, the nth backlight zone emits backlight. When the current value of the driving current received by the nth backlight zone is lower than the operating current value required for light emission, the nth backlight zone is turned off and stops emitting backlight.

[0385] In this embodiment of the disclosure, the display period for displaying one frame of an image by the display device includes M consecutive sub-cycles, where M is a positive integer. For example, if the color system of the display device is red, green, and blue, then M = 3. In each sub-cycle, the display partition can perform overdrive display, and the time when the display partition ends the overdrive display can be earlier than or equal to the time when the backlight partition starts backlighting.

[0386] Each sub-cycle can include two sub-fields, so the three sub-cycles are: the sub-cycle including the first red sub-field and the second red sub-field, the sub-cycle including the first green sub-field and the second green sub-field, and the sub-cycle including the first blue sub-field and the second blue sub-field. The time order of the three sub-cycles can be: the sub-cycle including the first red sub-field and the second red sub-field, the sub-cycle including the first green sub-field and the second green sub-field, and the sub-cycle including the first blue sub-field and the second blue sub-field.

[0387] In each subfield of each sub-cycle, the level of the data signal received by display module 20 can be a fixed value. In the two subfields of each sub-cycle, the levels of the data signals received by display module 20 can be different.

[0388] In the first subfield of each sub-cycle, driven by the received data signal, the liquid crystal molecules of the nth display partition can deflect, and before the end of the first subfield, the liquid crystal molecules deflect to a target angle, or at least close to the target angle. The target angle can be determined based on the desired target brightness value; that is, when the liquid crystal molecules are at the target angle, the brightness of the light emitted by the backlight after passing through the liquid crystal molecules can be the target brightness value. In the second subfield of each sub-cycle, driven by the received data signal, the liquid crystal molecules of the nth display partition can stabilize to the target angle and no longer deflect. In the second subfield, the nth backlight partition is illuminated under the drive of the received backlight driving signal. The target angle can be expressed as the liquid crystal rotation angle corresponding to the grayscale brightness of the target brightness value. For example, when the nth display partition emits light in the mth sub-cycle, the target angle can be expressed as the rotation angle corresponding to the display grayscale of the nth display partition in the mth sub-cycle.

[0389] In this embodiment, by dividing a sub-cycle into two sub-fields, the liquid crystal is accelerated by using a third level for OD driving in the first sub-field, and the OD driving is stopped in the second sub-field. The deflection angle of the liquid crystal is kept constant by using a fourth level, and the backlight emission time is set later than the start time of the second sub-field. Thus, the rotation angle of the liquid crystal is relatively stable during the backlight emission stage, and the luminous brightness of the corresponding sub-pixels is also relatively stable. This can effectively improve the field sequence color mixing abnormality problem and improve the display effect.

[0390] In this embodiment of the disclosure, the moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle switches from the second state to the first state is the nth fifth moment, and the moment when the data signal received by the nth display partition in the mth sub-cycle jumps from the third level to the fourth level is the nth seventh moment, 1≤m<M, where m is a positive integer.

[0391] The first state of the backlight driving signal is when the driving current is sufficient to drive the backlight module to emit backlight. The second state of the backlight driving signal is when the driving current is sufficient to prevent the backlight module from emitting light. For example, the backlight driving signal can be converted into a driving current. For example, the voltage of the backlight driving signal can be supplied to the negative electrode of the light-emitting element in the backlight section. With the positive electrode voltage of the light-emitting element remaining constant, changing the voltage of the backlight driving signal changes the value of the driving current passing through the backlight section. For example, in the second state of the backlight driving signal, the driving current is less than 1A, and the backlight section with a driving current less than 1A does not emit light. In the first state of the backlight driving signal, the driving current is greater than or equal to 1A, and the backlight section emits light. When the driving current remains greater than or equal to 1A, changing the voltage value of the backlight driving signal changes the value of the driving current, thereby changing the intensity of the backlight emitted by the backlight section. For example, the brightness of the backlight emitted by the backlight section can increase as the driving current increases.

[0392] The nth fifth moment is the moment when the nth backlight partition receives the backlight drive signal with the first state in the mth sub-cycle, that is, the moment when the nth backlight partition starts to emit light in the mth sub-cycle.

[0393] The third level can be the level when OD is started, and the fourth level can be the level when OD is turned off. The nth seventh moment is the moment when the nth display partition receives the data signal with the fourth level in the mth sub-cycle, that is, the moment when the nth display partition turns off OD in the mth sub-cycle. Optionally, for the mth sub-cycle, the nth seventh moment can also be the moment when the first subfield of the mth sub-cycle ends and the second subfield begins.

[0394] In this embodiment of the disclosure, the moment when the nth display partition turns off OD in the mth sub-cycle can be at least no later than the moment when the nth backlight partition starts emitting light in the mth sub-cycle, that is, the nth seventh moment is earlier than the nth fifth moment, or the nth seventh moment coincides with the nth fifth moment. In other words, the moment when the nth display partition receives a data signal with a fourth level in the mth sub-cycle can be earlier than the moment when the nth backlight partition receives a backlight driving signal with a first state in the mth sub-cycle, or the moment when the nth display partition receives a data signal with a fourth level in the mth sub-cycle can also coincide with the moment when the nth backlight partition receives a backlight driving signal with a first state in the mth sub-cycle.

[0395] In this embodiment, by dividing a sub-cycle into two sub-fields, the liquid crystal is accelerated by using a third level for OD driving in the first sub-field, and the OD driving is stopped in the second sub-field. The deflection angle of the liquid crystal is kept constant by using a fourth level, and the backlight emission time is set later than the start time of the second sub-field. Thus, the rotation angle of the liquid crystal is relatively stable during the backlight emission stage, and the luminous brightness of the corresponding sub-pixels is also relatively stable. This can effectively improve the field sequence color mixing abnormality problem and improve the display effect.

[0396] In embodiments of this disclosure, the display driving signal may further include a scan signal. The moment when the scan signal received by the nth display partition in the (m+1)th sub-cycle changes from a first level to a second level is the nth second moment, and the moment when the scan signal received by the nth display partition in the m sub-cycle changes from a first level to a second level is the nth third moment.

[0397] The nth second moment is the moment when the nth display partition receives a display drive signal with a second level in the (m+1)th sub-cycle, that is, the moment when the TFT of the nth display partition is turned on in the (m+1)th sub-cycle.

[0398] The nth third moment is the moment when the nth display partition receives a display drive signal with the second level in the mth sub-cycle, that is, the moment when the TFT of the nth display partition is turned on in the mth sub-cycle.

[0399] Between the nth third time and the nth seventh time, the data signal received by the nth display partition is at the third level; between the nth seventh time and the nth second time, the data signal received by the nth display partition is at the fourth level. That is, for each sub-cycle, the sub-cycle can include a first subfield and a second subfield that are continuous in time. The time period between the third time and the seventh time can be the time period range of the first subfield of the sub-cycle, and the time period between the seventh time and the second time can be the time period range of the second subfield of the sub-cycle.

[0400] In the embodiments of this disclosure, the duration of the display period is T, and the duration of the sub-period is T / M, where T is a positive number. Therefore, the interval between the nth third time point and the nth second time point is T / M, meaning the interval between the nth third time point and the nth second time point is the duration of one sub-period.

[0401] For example, the m-th sub-cycle includes the first red sub-field and the second red sub-field, and the (m+1)-th sub-cycle includes the first green sub-field and the second green sub-field. For the n-th display partition, at the third time of n, the sub-cycle including the first red sub-field and the second red sub-field begins TFT scanning, and at the second time of n, the sub-cycle including the first green sub-field and the second green sub-field begins TFT scanning.

[0402] In this embodiment of the disclosure, within the display cycle, the nth third moment is earlier than the nth seventh moment, and the nth second moment is later than the nth seventh moment. That is, within the sub-cycle of the nth display partition, the time sequence can be the nth third moment, the nth seventh moment, and the nth second moment. Optionally, the nth fifth moment can also be later than the nth seventh moment and earlier than the nth second moment. Therefore, within the sub-cycle of the nth display partition, the time sequence can also be represented as the nth third moment, the nth seventh moment, the nth fifth moment, and the nth second moment.

[0403] In the m-th sub-cycle of the n-th display partition, the time range of the first sub-field of the sub-cycle can be the time period between the n-th third time and the n-th seventh time, and the time range of the second sub-field can be the time period between the n-th seventh time and the n-th second time.

[0404] In some embodiments, the interval between the nth third time point and the nth seventh time point can be equal to the interval between the nth seventh time point and the nth second time point; that is, the duration of the first subfield of a sub-cycle can be equal to the duration of the second subfield. In each subfield, the display driving circuit provides only one level of data signal to the display zone.

[0405] Because a sub-cycle is split into two sub-fields, the refresh rate of the display device is correspondingly doubled. In the embodiments of this disclosure, the frequency of the data signal output by the display driving circuit is a first frequency, the frequency of the scan signal output by the display driving circuit is a second frequency, and the frequency of the backlight driving signal output by the backlight driving circuit is a third frequency; wherein, the second frequency and the third frequency are the same, and the first frequency is twice the second frequency or the third frequency.

[0406] In this embodiment, the third level represents the level in an overdrive state, and the fourth level represents the level in a non-overdrive state. That is, in each sub-cycle, overdrive (OD) can be performed only in the first subfield of the sub-cycle, and not in the second subfield of the sub-cycle. In this embodiment, the nth display partition includes the nth liquid crystal unit. The display driving circuit is used to provide the nth liquid crystal unit with a data signal at the third level between the nth third time and the nth seventh time, and to provide the nth liquid crystal unit with a data signal at the fourth level between the nth seventh time and the nth second time. That is, between the nth third time and the nth seventh time, the level driving the nth liquid crystal unit to rotate can be the third level, at which time the nth liquid crystal unit can accelerate its rotation towards the target angle; between the nth seventh time and the nth second time, the level driving the nth liquid crystal unit to rotate can be the fourth level, at which time the nth liquid crystal unit can maintain at the target angle, or continue to rotate to the target angle from other angles.

[0407] Depending on the setting of the third level, the moment when the nth liquid crystal cell rotates to the target angle can vary accordingly. In this embodiment, the moment when the nth liquid crystal cell rotates to the target angle in the mth sub-cycle is the nth eighth moment. The nth eighth moment can be set to be earlier than or equal to the nth fifth moment, so that the nth liquid crystal cell has rotated and maintained at the target angle before the backlight zone starts backlight emission, making the light emitted through the nth liquid crystal cell relatively stable.

[0408] Taking a display frequency of 240Hz as an example, the duration of each sub-cycle is 1 / 240s = 4.17ms. The duration of the first subfield of a sub-cycle can be equal to the duration of the second subfield, that is, the duration of each subfield of a sub-cycle can be 2.08ms. For the Xth frame of the nth display partition, when displaying the field sequence of the R127 screen, the Xth frame of the nth display partition can be divided into 6 subfields. When the screens of the 6 subfields are displayed, the backlight colors of the nth backlight partition are displayed in the following order: black, blue, black, red, black, green.

[0409] Optionally, the nth eighth moment is earlier than the nth seventh moment, and the rotation angle of the nth liquid crystal unit at the nth seventh moment is the first angle. The angle difference between the first angle and the target angle is within a preset range. The preset range can be represented as a small angle range, and its value can be determined based on the rotation speed of the liquid crystal without OD driving. That is, the third level can be set to control the liquid crystal unit to rotate to the target angle before the OD driving ends, and the rotation angle of the liquid crystal unit at the end of the OD driving is relatively close to the target angle. That is, at this time, the liquid crystal unit is sufficient to rotate to the target angle before the backlight is emitted under the driving of the fourth level.

[0410] Figure 20A shows a schematic diagram of display based on OD-driven grayscale according to an embodiment of the present disclosure.

[0411] As shown in Figure 20A, in grayscale display based on OD driving, the grayscale display order of the six sub-fields is L0, L0, L165, L127, L0, L0. That is, the third level is set to the level corresponding to L165, and the fourth level is set to the level corresponding to L127. At the beginning of the third sub-field, the display driving circuit can provide a data signal to the nth display zone based on the level corresponding to L165 to perform OD driving based on L165. The liquid crystal rotation angle rapidly deflects from the angle corresponding to L0 to the angle corresponding to L127, i.e., the target angle. 2ms after the start of the third sub-field, the nth liquid crystal cell rotates to the target angle and continues to rotate, reaching its maximum angle at the end of the third sub-field.

[0412] After the fourth subfield begins, the display driving circuit can provide a data signal to the nth display zone based on the level corresponding to L127 to stop OD driving. The data signal with the level corresponding to L127 can control the rotation angle of the liquid crystal to rotate in the opposite direction. At 0.3ms after the start of the fourth subfield, the nth liquid crystal cell rotates to the target angle and remains fixed at the target angle. At 1.08ms after the start of the fourth subfield, the nth backlight zone provides red backlight to the nth display zone. The brightness of the light transmitted through the liquid crystal by this red backlight can be consistent with the expected brightness of R127.

[0413] In this embodiment, the nth eighth moment can be the moment when the unit first rotates to the target angle, i.e., 2ms after the start of the third subfield, which is earlier than the end of the third subfield. The angle difference between the rotation angle of the nth liquid crystal unit at the end of the third subfield and the target angle is small, so the nth liquid crystal unit can rotate to the target angle again at 0.3ms after the start of the fourth subfield. The moment when the nth backlight unit emits light is 1.08ms after the start of the fourth subfield, meaning that the moment when the nth liquid crystal unit maintains the target angle can be earlier than the moment when the nth backlight unit emits light.

[0414] Optionally, the nth eighth time point can be equal to the nth seventh time point; that is, the third level can be set to control the liquid crystal cell to rotate to the target angle at the end of the OD drive. Figure 20B shows a schematic diagram of display based on OD drive grayscale according to another embodiment of the present disclosure.

[0415] As shown in Figure 20B, in grayscale display based on OD driving, the grayscale display order of the 6 sub-fields is L0, L0, L145, L127, L0, L0. That is, the third level is set to the level corresponding to L145, and the fourth level is set to the level corresponding to L127.

[0416] At the start of the third subfield, the display driving circuit can provide a data signal to the nth display zone based on the level corresponding to L145, so as to perform OD driving based on L145. The liquid crystal rotation angle rapidly deflects from the angle corresponding to L0 to the angle corresponding to L127, i.e., the target angle. At the end of the third subfield, the nth liquid crystal cell rotates to the target angle.

[0417] After the fourth subfield begins, the display driving circuit can provide a data signal to the nth display zone based on the level corresponding to L127 to stop OD driving. The data signal with the level corresponding to L127 can control the rotation angle of the liquid crystal to be fixed at the target angle. At 1.08ms after the start of the fourth subfield, the nth backlight zone provides red backlight to the nth display zone. The brightness of the light transmitted through the liquid crystal by this red backlight can be consistent with the expected brightness of R127.

[0418] In this embodiment, the nth eighth moment can be the end moment of the third subfield. The nth liquid crystal unit can maintain the target angle from the end moment of the third subfield, and the nth backlight unit emits light at 1.08ms after the start of the fourth subfield. That is, the moment when the nth liquid crystal unit maintains the target angle can be earlier than the moment when the nth backlight unit emits light.

[0419] Optionally, the nth eighth moment is later than the nth seventh moment, and the rotation angle of the nth liquid crystal unit at the nth seventh moment is the second angle. The angle difference between the second angle and the target angle is within a preset range. The preset range can be represented as a small angle range, and its value can be determined based on the rotation speed of the liquid crystal without OD driving. That is, the third level can be set to control the liquid crystal unit to not rotate to the target angle when the OD driving ends, but the rotation angle of the liquid crystal unit is relatively close to the target angle when the OD driving ends. That is, at this time, the liquid crystal unit is sufficient to rotate to the target angle before the backlight is emitted under the driving of the fourth level.

[0420] Figure 20C shows a schematic diagram of display based on OD-driven grayscale according to another embodiment of the present disclosure.

[0421] As shown in Figure 20C, in grayscale display based on OD driving, the grayscale display order of the 6 sub-fields is L0, L0, L140, L127, L0, L0. That is, the third level is set to the level corresponding to L140, and the fourth level is set to the level corresponding to L127.

[0422] At the start of the third subfield, the display driving circuit can provide a data signal to the nth display zone based on the level corresponding to L140, so as to perform OD driving based on L140. The liquid crystal rotation angle rapidly deflects from the angle corresponding to L0 to the angle corresponding to L127, i.e., the target angle. At the end of the third subfield, the nth liquid crystal cell has not rotated to the target angle.

[0423] After the fourth subfield begins, the display driving circuit can provide a data signal to the nth display zone based on the level corresponding to L127 to stop OD driving. The data signal with the level corresponding to L127 can control the liquid crystal to continue selecting the target angle. At 0.8ms after the start of the fourth subfield, the nth liquid crystal cell rotates to the target angle and remains fixed at the target angle. At 1.08ms after the start of the fourth subfield, the nth backlight zone provides red backlight to the nth display zone. The brightness of the light transmitted through the liquid crystal can be consistent with the expected brightness of R127.

[0424] In this embodiment, the nth eighth moment can be 0.8ms after the start of the fourth subfield, and the moment when the nth backlight unit emits light is 1.08ms after the start of the fourth subfield. That is, the moment when the nth liquid crystal unit maintains the target angle can be earlier than the moment when the nth backlight unit emits light.

[0425] In this embodiment of the disclosure, when the durations of the two subfields included in a sub-cycle are equal, the timing control logic of the display driving circuit can be developed and implemented based on the timing control logic of the original chip. For example, if the driving frequency output by the original chip is 120Hz, then the driving frequency output by the chip can be adjusted to 240Hz, and the output signal of each beat can be adjusted accordingly. This completes the development and implementation of the timing control logic, thus effectively saving development costs.

[0426] In this embodiment of the disclosure, the moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle of M sub-cycles switches from the first state to the second state is the nth first moment.

[0427] The nth first moment is the moment when the nth backlight partition receives the backlight drive signal with the second state in the mth sub-cycle, that is, the moment when the nth backlight partition ends emitting light in the mth sub-cycle.

[0428] In some embodiments, the interval between the nth third time point and the nth seventh time point may not be equal to the interval between the nth seventh time point and the nth second time point; that is, the duration of the first subfield in a sub-cycle may not be equal to the duration of the second subfield. In this case, the duration of the second subfield needs to be greater than or equal to the backlight emission duration, that is, the interval between the nth seventh time point and the nth second time point needs to be greater than or equal to the interval between the nth fifth time point and the nth first time point. For example, in one example, the duration of a sub-cycle is 4.17ms, the duration of the first subfield can be 2.67ms, then the duration of the second subfield is 1.5ms, and the backlight emission duration of the backlight partition in this sub-cycle can be less than or equal to 1.5ms.

[0429] In this embodiment, by dividing a sub-cycle into two sub-fields, the liquid crystal is accelerated by using a third level for OD driving in the first sub-field, and the OD driving is stopped in the second sub-field. The deflection angle of the liquid crystal is kept constant by using a fourth level, and the backlight emission time is set later than the start time of the second sub-field. Thus, the rotation angle of the liquid crystal is relatively stable during the backlight emission stage, and the luminous brightness of the corresponding sub-pixels is also relatively stable. This can effectively improve the field sequence color mixing abnormality problem and improve the display effect.

[0430] When displaying based on OD driving, the average grayscale response time can be shortened. However, since the voltage corresponding to L0 or L255 is the voltage boundary value of the data signal, OD technology cannot be used to improve the response speed when other grayscale changes to L0 or L255.

[0431] The display driver circuit can have multiple preset binding points. When the display driver circuit provides data signals to the display module, it can determine the voltage value of the data signal based on the grayscale to be displayed by linear fitting according to the multiple preset binding points. For example, the display driver circuit can preset 9 binding points Vr1 to Vr9, which correspond to L255 to L0 respectively, as shown in Figure 2.

[0432] Table 2

[0433] In this embodiment, the grayscale values ​​corresponding to each binding point can be reallocated. For example, for the nine binding points shown in Table 1, Vr1 can be adjusted to correspond to LH, Vr2 to correspond to L255, Vr8 to correspond to L0, and Vr9 to correspond to LL, as shown in Table 3. After the grayscale values ​​and binding points are reallocated, algorithms such as FRC (Frame Rate Control) and Dither can be used to adjust the voltage values ​​of Vr1, Vr2, Vr8, and Vr9 to match the OD parameters, which will not be elaborated here.

[0434] Table 3

[0435] Based on the adjusted binding points, when displaying other grayscale levels to L255, the voltage corresponding to LH can be used for OD driving. Similarly, when displaying other grayscale levels to LO, the voltage corresponding to LL can be used for OD driving, so as to realize the enhanced OD function of other grayscale changes to L0 or L255.

[0436] In this embodiment of the disclosure, the display grayscale of the nth display partition in the (m-1)th sub-cycle is the first grayscale, and the display grayscale of the nth display partition in the m-th sub-cycle is the second grayscale. Then, the fourth level can be represented as the level value corresponding to the second grayscale. Correspondingly, the third level can be represented as the level value when OD is driven.

[0437] For example, if the (m-1)th sub-cycle of the nth display partition is a sub-cycle for the red subfield and the mth sub-cycle is a sub-cycle for the green subfield, then the display grayscale of the light emitted by the nth display partition in the (m-1)th sub-cycle is the first grayscale, and the display grayscale of the light emitted by the nth display partition in the mth sub-cycle is the second grayscale.

[0438] In some embodiments, the first gray level can be consistent with the second gray level. When the first gray level and the second gray level are consistent, the liquid crystal at the nth display partition does not need to be deflected, and therefore, OD does not need to be activated for driving in the mth sub-cycle. Thus, the third level can be consistent with the fourth level.

[0439] In some embodiments, the first gray level may be smaller than the second gray level. When the first gray level is smaller than the second gray level, OD needs to be activated in the m-th sub-cycle, and a larger driving voltage needs to be applied to the liquid crystal to accelerate the deflection of the liquid crystal. Therefore, the third level may be greater than the fourth level.

[0440] Optionally, the first gray level can be any gray level less than L255, and the second gray level can be a white gray level (L255). Then, when OD is initiated in the m-th sub-cycle, the first binding point level can be used as the third voltage to drive the deflection of the liquid crystal. This first binding point level can be greater than the level value corresponding to the white gray level. For example, the voltage value of this first binding point level can be the voltage value of binding point Vr1 as shown in Table 2.

[0441] In some embodiments, the first gray level can be greater than the second gray level. When the first gray level is greater than the second gray level, OD needs to be activated in the m-th sub-cycle to apply a smaller driving voltage to the liquid crystal to accelerate the deflection of the liquid crystal. Therefore, the third level can be less than the fourth level.

[0442] Optionally, the first gray level can be any gray level greater than L0, and the second gray level can be the black gray level (L0). Then, when OD is initiated in the m-th sub-cycle, the second binding point level can be used as the third voltage to drive the deflection of the liquid crystal. This second binding point level can be less than the level value corresponding to the black gray level. For example, the voltage value of this second binding point level can be the voltage value of binding point Vr9 as shown in Table 2.

[0443] In this embodiment of the disclosure, the level of the first binding point can be greater than the level of the second binding point.

[0444] In some embodiments, since liquid crystals are prone to failure after being subjected to voltages of the same polarity for extended periods, the lifespan of the liquid crystal can be improved by periodically reversing the polarity of the data signal output by the display driving circuit to periodically apply voltages of opposite polarity. In this case, the binding points configured in the display driving circuit may include multiple binding points corresponding to the positive polarity and multiple binding points corresponding to the negative polarity.

[0445] For example, the display driver circuit can preset 18 binding points Vr1 to Vr18, corresponding to positive polarity L255 to L0 and negative polarity L0 to L255 respectively. The grayscale values ​​corresponding to each binding point can be redistributed as described above. Specifically, Vr1 can be adjusted to correspond to LH-H, Vr2 to correspond to positive polarity L255, Vr8 to correspond to positive polarity L0, Vr9 to correspond to LL-H, Vr10 to correspond to LL-L, Vr11 to correspond to negative polarity L0, Vr17 to correspond to negative polarity L255, and Vr18 to correspond to LH-L, as shown in Table 4. After the grayscale values ​​and binding points are redistributed, algorithms such as FRC (Frame Rate Control) and Dither can be used to adjust the voltage values ​​of Vr1, Vr2, Vr8, Vr9, Vr10, Vr11, Vr17, and Vr18 to match the OD parameters. This will not be elaborated on here.

[0446] Table 4

[0447] Figure 21 shows a schematic diagram of the gamma curve of a display driving circuit according to an embodiment of the present disclosure.

[0448] As shown in Figure 21, the gamma curve can be obtained based on the adjusted binding points. If the voltage corresponding to LH-H is the same as the voltage corresponding to LH-L, and the voltage corresponding to LL-L is the same as the voltage corresponding to LL-H, then based on the adjusted binding points, when displaying other positive grayscale levels to positive L255, the voltage corresponding to LH-H can be used for OD driving. Similarly, when displaying other positive grayscale levels to positive L0, the voltage corresponding to LL-H can be used for OD driving; when displaying other negative grayscale levels to negative L0, the voltage corresponding to LL-L can be used for OD driving; and when displaying other negative grayscale levels to negative L255, the voltage corresponding to LH-L can be used for OD driving, thus achieving enhanced OD function for other grayscale changes to L0 or L255.

[0449] In field-sequence display, the driving timing of the backlight zones and display zones in the vertical direction can be such that the backlight of the previous sub-cycle is turned off when the TFT of the next sub-cycle of the current zone begins scanning. However, the backlight has a certain mixing distance, meaning the backlight of one zone will illuminate adjacent zones, causing color crosstalk between adjacent zones. Let's take the example where the backlight of a zone only affects one adjacent zone.

[0450] Figure 22A shows a schematic diagram of the vertical partition scan timing according to an embodiment of the present disclosure.

[0451] As shown in Figure 22A, if the moment when the nth backlight partition stops emitting light in the mth sub-cycle coincides with the moment when the nth display partition starts scanning the TFT in the m+1th sub-cycle, then for the nth backlight partition, the backlight emission of the nth backlight partition in the mth sub-cycle will affect the TFT scanning of the (n-1)th display partition in the m+1th sub-cycle, but will have no effect on the (n+1)th display partition.

[0452] To reduce the overlap between the backlight time of the previous sub-cycle and the TFT scanning time of the next sub-cycle, the backlight partition can be controlled to turn off the backlight in advance. That is, there can be an extra time period between the end time of the backlight of the previous sub-cycle and the start time of the scanning of the next sub-cycle. During this extra time period, the backlight driving signal provided by the backlight driving circuit to the corresponding backlight partition can be switched to the second state, so that the corresponding backlight partition stops emitting light.

[0453] Specifically, in the embodiments of this disclosure, the moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle switches from the first state to the second state is the nth first moment, and the moment when the scan signal received by the nth display partition in the (m+1)th sub-cycle jumps from the first level to the second level is the nth second moment. The nth first moment can be earlier than the nth second moment. Furthermore, the interval between the nth third moment and the nth first moment can be less than T / M.

[0454] Figure 22B shows a schematic diagram of the vertical partition scan timing according to another embodiment of the present disclosure.

[0455] As shown in Figure 22B, the moment when the nth backlight partition stops emitting light in the mth sub-cycle is earlier than the moment when the nth display partition scans the TFT in the (m+1)th sub-cycle. The backlight of the current sub-cycle is turned off in advance before the TFT scan of the next sub-cycle. A backlight early shutdown period is inserted between the backlight emission period of the current sub-cycle and the TFT scan period of the next sub-cycle, separating the backlight emission period from the TFT scan period, thereby reducing the impact of backlight mixing on the next sub-cycle.

[0456] In the embodiments of this disclosure, the moment when the scan signal received by the nth display partition in the mth sub-cycle transitions from the second level to the first level is the nth fourth moment. The first interval between the nth third moment and the nth fourth moment is 'a', and the fifth interval between the nth first moment and the nth second moment is 'e'. That is, the backlight early shutdown period can be the period between the nth first moment and the nth second moment, i.e., the duration of the backlight early shutdown period can be 'e'. The TFT scanning period can be the period between the nth third moment and the nth fourth moment, i.e., the duration of the TFT scanning period is 'a'.

[0457] In some embodiments, the duration of the early backlight shutdown period can be set to an integer multiple of the TFT scanning period, depending on the number of adjacent display zones affected by the backlight partition. For example, if the backlight partition only affects the next display zone, the duration of the early backlight shutdown period can be set to be equal to the duration of the TFT scanning period, i.e., e = a. As another example, if the backlight partition affects two display zones above and below, the duration of the early backlight shutdown period can be set to twice the duration of the TFT scanning period, i.e., e = 2 * a.

[0458] In some embodiments, the duration of the backlight early shutdown period can be set according to the actual application scenario, including hardware status, LED light emission angle, etc. For example, the duration of the backlight early shutdown period can be set to 0.2 times, 0.5 times, 1.3 times, etc. of the duration of the TFT scanning period, without limitation.

[0459] In embodiments of this disclosure, the display device may further include a timing controller, which can provide a clock signal to the display driving circuit. This clock signal can be used to control the frequency of the display driving signal output by the display driving circuit. The total horizontal period of the display module is H, the total vertical period of the display module is V, the refresh rate of the display module is F, and the frequency of the clock signal is G, where H, V, F, and G are all positive integers.

[0460] In one example, the refresh rate F of the display module can be 180Hz, so the duration of each sub-cycle can be 5.56ms, the TFT scan duration is 5.33ms, and the vertical blanking duration is 0.22ms. The display module has 3840 horizontal pixels, a total horizontal cycle H of 4400 pixels, 2160 vertical pixels, and a total vertical cycle V of 2250 lines. Therefore, the rated clock signal frequency of this display module is 180*4400*2250 = 1.782GHz. The backlight module can be driven in a 36-segment configuration in the vertical direction, so the TFT scan duration of each segment is 5.33 / 36 = 0.15ms. That is, in field-sequence display, the TFT scan period in one sub-cycle almost occupies the entire sub-cycle time. The liquid crystal response time is generally longer than the duration of one sub-cycle. After increasing the OD, the liquid crystal response time approaches the time of one field. Therefore, when displaying the current sub-cycle of the image, the liquid crystal has not yet rotated to the target angle, and the display of the next sub-cycle of the image needs to begin. The LED backlight has almost no time to be on or a very short time to be on, which will cause the color displayed in the current sub-cycle of the image to be different from the target color. It will also cause color bleeding between the previous and next sub-cycles, or insufficient screen brightness.

[0461] In the embodiments of this disclosure, the frequency of the clock signal received by the display module can be increased by adjusting the control timing, while the total horizontal period H and refresh rate F remain unchanged. If the vertical resolution of the display module is K, the time taken for the display module to display K lines will be shortened, thereby providing more time for liquid crystal response and LED illumination.

[0462] Figure 23 shows a timing diagram of the scan signal according to an embodiment of the present disclosure.

[0463] As shown in Figure 23, the clock signal frequency can be increased from 1.782GHz to 2.376GHz while keeping the refresh rate and total horizontal cycle unchanged, i.e., G > H*V*F. Then, the time taken to scan 2160 lines of TFT is 4400*2160 / 2.376GHz = 4ms. The TFT scan duration of a single sub-cycle is shortened from 5.33ms to 4ms, the vertical blanking duration is increased from 0.22ms to 1.56ms, and the TFT scan duration of each horizontal partition is 4 / 36 = 0.11ms. That is, if the scan duration of each sub-cycle is i, then i = (H*K / G) / N, and i < K / (F*V*N).

[0464] In the embodiments of this disclosure, by increasing the clock signal frequency, the TFT scan duration of each sub-cycle can be shortened, thereby indirectly increasing the vertical blanking duration of each sub-cycle. A larger vertical blanking duration can reserve more time windows for the display and image processing system, which can ensure the complete switching of the frame buffer in high-resolution and high-refresh-rate scenarios, avoid screen tearing, and ensure the accurate transmission and processing of HDR (High Dynamic Range) dynamic metadata, image sensor data, etc. It can also optimize timing synchronization, reduce artifacts such as pixel residue and retrace lines, and provide time support for the background computing of the graphics processor and the interaction of embedded system peripherals, reduce the driving bandwidth and timing control difficulty of low-performance hardware, and ultimately improve screen continuity, system stability and scene adaptability.

[0465] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0466] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0467] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A display device, comprising: Display module, backlight module, display driver circuit and backlight driver circuit; The display module includes N display zones, and the backlight module includes N backlight zones. The nth backlight zone among the N backlight zones provides backlight for the nth display zone among the N display zones, where 1 ≤ n ≤ N, and n and N are positive integers. The output terminal of the display driving circuit is electrically connected to the N input terminals of the display module, and is used to output N display driving signals to the N display zones; The output terminal of the backlight driving circuit is electrically connected to the N input terminals of the backlight module to output N backlight driving signals to the N backlight zones. The display period for displaying one frame of an image by the display device includes M consecutive sub-cycles, where M is a positive integer; the display partition is used for overdrive display in the sub-cycle, and in the sub-cycle, the time when the display partition ends overdrive display is earlier than or equal to the time when the backlight partition starts backlight emission.

2. The display device according to claim 1, wherein, The display driving signal includes a data signal; The moment when the backlight drive signal received by the nth backlight partition in the mth sub-cycle switches from the second state to the first state is the nth fifth moment. The moment when the data signal received by the nth display partition in the mth sub-cycle jumps from the third level to the fourth level is the nth seventh moment. 1≤m<M, where m is a positive integer. The nth seventh moment is earlier than or equal to the nth fifth moment.

3. The display device according to claim 2, wherein, The display driving signal also includes a scanning signal; Wherein, the moment when the scan signal received by the nth display partition in the (m+1)th sub-cycle changes from the first level to the second level is the nth second moment, and the moment when the scan signal received by the nth display partition in the mth sub-cycle changes from the first level to the second level is the nth third moment; Specifically, between the nth third time and the nth seventh time, the data signal received by the nth display partition is at the third level; between the nth seventh time and the nth second time, the data signal received by the nth display partition is at the fourth level.

4. The display device according to claim 3, wherein, The third level represents the level in an overdriven state, and the fourth level represents the level in a non-overdriven state.

5. The display device according to claim 4, wherein, The fourth level includes a level corresponding to the white grayscale, and the third level includes a first binding point level, which is greater than the fourth level.

6. The display device according to claim 4, wherein, The fourth level includes the level corresponding to the black grayscale, and the third level includes the second binding point level, which is lower than the fourth level.

7. The display device according to claim 5 or 6, wherein, The voltage level at the first binding point is higher than that at the second binding point.

8. The display device according to any one of claims 2 to 7, wherein, The nth display partition includes an nth liquid crystal unit. The display driving circuit is used to provide a data signal at a third level to the nth liquid crystal unit between the nth third time and the nth seventh time, and to provide a data signal at a fourth level to the nth liquid crystal unit between the nth seventh time and the nth second time.

9. The display device according to claim 8, wherein, The nth liquid crystal cell rotates to the target angle at the moment when it reaches the target angle in the mth sub-cycle. The nth eighth moment is earlier than or equal to the nth fifth moment. The target angle represents the rotation angle corresponding to the display grayscale of the nth display partition in the mth sub-cycle.

10. The display device according to claim 9, wherein, The nth eighth moment is equal to the nth seventh moment.

11. The display device according to claim 9, wherein, The nth eighth moment is earlier than the nth seventh moment, and the rotation angle of the nth liquid crystal unit at the nth seventh moment is a first angle, and the angle difference between the first angle and the target angle is within a preset range.

12. The display device according to claim 9, wherein, The nth eighth moment is later than the nth seventh moment, and the rotation angle of the nth liquid crystal unit at the nth seventh moment is the second angle. The angle difference between the second angle and the target angle is within a preset range.

13. The display device according to claim 3, wherein, The moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle of the M sub-cycles switches from the first state to the second state is the nth first moment, and the nth first moment is earlier than the nth second moment.

14. The display device according to claim 13, wherein, The duration of the display cycle is T, and the duration of the sub-cycle is T / M, where T is a positive number; In the display cycle, the nth third moment is earlier than the nth first moment, and the interval between the nth third moment and the nth first moment is less than T / M.

15. The display device according to claim 13, wherein, The nth display partition is defined as the nth fourth moment when the scan signal received in the mth sub-cycle jumps from the second level to the first level. The first interval between the nth third moment and the nth fourth moment is a, and the fifth interval between the nth first moment and the nth second moment is e, where e = a, or e = 2*a.

16. The display device according to claim 13, wherein, The interval between the nth third time and the nth seventh time is equal to the interval between the nth seventh time and the nth second time.

17. The display device according to claim 16, wherein, The frequency of the data signal output by the display driving circuit is a first frequency, the frequency of the scanning signal output by the display driving circuit is a second frequency, and the frequency of the backlight driving signal output by the backlight driving circuit is a third frequency. Wherein, the second frequency is the same as the third frequency, and the first frequency is twice the second frequency or the third frequency.

18. The display device according to claim 1, further comprising: A timing controller is used to provide a clock signal to the display driving circuit; Wherein, the total horizontal period of the display module is H, the total vertical period of the display module is V, the refresh rate of the display module is F, and the frequency of the clock signal is G, where H, V, F, and G are all positive integers; Where G > H*V*F.

19. The display device according to claim 18, wherein, The scanning duration of each sub-cycle is i, and the vertical resolution of the display module is K. Then i = (H*K / G) / N, and i < K / (F*V*N).

20. The display device according to claim 1, wherein, The display driving signal also includes a scanning signal; the moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle of the M sub-cycles switches from the first state to the second state is the nth first moment, and the moment when the scanning signal received by the nth display partition in the (m+1)th sub-cycle jumps from the first level to the second level is the nth second moment, l≤m<M, m is a positive integer, and the nth first moment is the same as the nth second moment.

21. The display device according to claim 20, wherein, The duration of the display cycle is T, and the duration of the sub-cycle is T / M, where T is a positive number; the moment when the scan signal received by the nth display partition in the mth sub-cycle changes from the first level to the second level is the nth third moment; In the display cycle, the nth third moment is earlier than the nth first moment, and the interval between the nth third moment and the nth first moment is T / M.

22. The display device according to claim 14 or 21, wherein, The moment when the scan signal received by the nth display partition in the mth sub-cycle changes from the second level to the first level is the nth fourth moment. The moment when the backlight driving signal received by the nth backlight partition in the mth sub-cycle switches from the second state to the first state is the nth fifth moment. In the mth sub-cycle, the scanning signals received by the N display partitions sequentially change from the first level to the second level. In the mth sub-cycle, the backlight driving signals received by the N backlight partitions sequentially switch from the first state to the second state. The display cycle includes the nth third time, the nth fourth time, the nth fifth time, and the nth first time, which are sequentially discontinuous; the first interval between the nth third time and the nth fourth time is a, the second interval between the nth fifth time and the nth first time is b, and the third interval between the Nth fifth time and the 1st second time is c, where b = a*(N-1) + c.

23. The display device according to claim 22, wherein, The duration of the fourth interval between the nth fourth time point and the nth fifth time point is d; Where, a*N+d+c=T / M.

24. The display device according to claim 22, wherein, The second interval duration is determined based on the first interval duration. The second interval duration is negatively correlated with the first interval duration, and the change in the second interval duration is positively correlated with the change in the first interval duration.

25. The display device according to claim 22, wherein, The interval between the nth fifth time and the (n+1)th fifth time is the same as the interval between the nth third time and the (n+1)th third time, where 1 ≤ n < N; The interval between the nth first time point and the (n+1)th first time point is the same as the interval between the nth third time point and the (n+1)th third time point.

26. The display device according to claim 22, wherein, The first moment of the nth time interval is later than the fifth moment of the (n+1)th time interval.

27. The display device according to claim 22, wherein, The (n+1)th fourth moment is earlier than the nth fifth moment.

28. The display device according to claim 20, wherein, In the m-th sub-cycle, the scanning signals received by the N display zones sequentially change from the first level to the second level, and the backlight driving signals received by the N backlight zones sequentially switch from the first state to the second state in the m-th sub-cycle; the moment when the backlight driving signal received by the 1st backlight zone in the (m+1)-th sub-cycle switches from the second state to the first state is the 1st sixth moment; The Nth first moment is later than the 1st sixth moment.

29. The display device according to claim 20, wherein, When the nth backlight partition receives the backlight drive signal for the mth sub-cycle in the first state, at least one of the N backlight partitions receives the backlight signal for the (m+1)th sub-cycle in the first state.

30. The display device according to claim 20, wherein, When the nth backlight partition receives the backlight drive signal for the first sub-cycle and is in the first state, at least one of the N backlight partitions receives the backlight signal for the Mth sub-cycle and is in the first state.

31. The display device according to claim 21, wherein, The moment when the backlight drive signal received by the nth backlight partition in the mth sub-cycle switches from the second state to the first state is the nth fifth moment; The nth fifth moment is the same as the nth third moment.

32. The display device according to claim 20, wherein, The display module includes a display panel, which includes multiple pixel electrodes arranged in an array, data lines and scan lines of different layers, and multiple thin-film transistors arranged in an array. The thin-film transistors include a source connected to the data lines, a gate connected to the scan lines, and a drain connected to the pixel electrodes. The display driving circuit includes a scanning driving circuit, and the scanning signal includes a scanning driving signal; The output terminal of the scan drive circuit is electrically connected to the gate of the plurality of thin-film transistors via the plurality of scan lines, and is used to output the scan drive signal to the plurality of thin-film transistors; Wherein, at least two rows of thin-film transistors among the plurality of thin-film transistors receive the scan drive signal at the same time when it jumps from the first level to the second level.

33. The display device according to claim 32, wherein, Each scan line is electrically connected to the gate of at least two rows of thin-film transistors in the plurality of thin-film transistors.

34. The display device according to claim 32, wherein, The display driving circuit includes a data driving circuit, and the scanning signal includes a data signal; The data driving circuit is electrically connected to the source of the plurality of thin-film transistors via the plurality of data lines, and is used to output the data signal to the plurality of thin-film transistors; Wherein, the data signal received by at least two thin-film transistors in a single row switches from the third state to the fourth state at the same time, and the number of the at least two thin-film transistors is the same as the number of the at least two rows of thin-film transistors.

35. The display device according to claim 34, wherein, The source of a single-column thin-film transistor is electrically connected to at least two of the data lines, which are disposed in two columns of pixel electrodes.

36. The display device according to claim 20, wherein, The backlight driving circuit includes: P driving sub-circuits, P power supply circuits, and a control circuit; The control circuit is connected in series with the P driving sub-circuits to output backlight control signals to the P driving sub-circuits; The output of each of the P power supply circuits is electrically connected to Q of the N backlight zones to provide operating voltage to the Q backlight zones, where P*Q = N and P and Q are positive integers. Each of the P driving sub-circuits includes Q output terminals, which are electrically connected to the Q backlight zones to provide backlight driving signals to the Q backlight zones during the display cycle. The moment when the backlight driving signal for the m-th sub-cycle sent by the driving sub-circuit to the n-th backlight partition switches from the first state to the second state is the n-th first moment.

37. The display device according to claim 36, wherein, Each of the N backlight zones includes a first input terminal, a second input terminal, and a third input terminal; Each of the P power supply circuits includes a first power supply unit, a second power supply unit, and a third power supply unit. The first power supply unit includes a first power supply output terminal, the second power supply unit includes a second power supply output terminal, and the third power supply unit includes a third power supply output terminal. Wherein, the first power supply output terminal is connected to the Q first input terminals of the Q backlight zones among the N backlight zones, the second power supply output terminal is connected to the Q second input terminals of the Q backlight zones, and the third power supply output terminal is connected to the Q third input terminals of the Q backlight zones. The voltage output by the first power supply unit is less than or equal to the voltage output by the third power supply unit, and the voltage output by the third power supply unit is less than or equal to the voltage output by the second power supply unit.

38. The display device according to claim 36, wherein, The nth backlight zone includes a fourth input terminal, a fifth input terminal, and a sixth input terminal; Each of the P driving sub-circuits includes a first driving unit, a second driving unit, and a third driving unit. The first driving unit includes Q first driving output terminals, the second driving unit includes Q second driving output terminals, and the third driving unit includes Q third driving output terminals. Wherein, the Q first drive output terminals are respectively connected to the Q fourth input terminals of the Q backlight zones, the Q second drive output terminals are respectively electrically connected to the Q fifth input terminals of the Q backlight zones, and the Q third drive output terminals are respectively connected to the Q sixth input terminals of the Q backlight zones.

39. The display device according to claim 36, wherein, Each of the P driving sub-circuits includes a first driving unit, a second driving unit, and a third driving unit; Wherein, the output terminal of the first driving unit is electrically connected to the first input terminal of the second driving subunit of the second driving unit, and the output terminal of the second driving unit is electrically connected to the first input terminal of the third driving unit; The output terminal of the third driving unit of the p-th driving sub-circuit in the P driving sub-circuit is electrically connected to the first input terminal of the first driving unit of the (p+1)-th driving sub-circuit, where 1≤p<P and p is a positive integer. The first driving unit of the first driving sub-circuit is electrically connected to the first output terminal of the control circuit.

40. The display device according to claim 36, wherein, The backlight driving circuit further includes: a first power controller and a second power controller. Each of the P driving sub-circuits includes a first driving unit, a second driving unit, and a third driving unit; The output terminal of the first power controller is electrically connected to the input terminal of the second power controller, the P second input terminals of the P first drive units, the P second input terminals of the P second drive units, and the P second input terminals of the P third drive units, so as to provide operating voltage to the second power controller, the P first drive units, the P second drive units, and the P third drive units. The input terminal of the second power controller is electrically connected to the first input terminal of the control circuit to provide operating voltage to the control circuit.

41. The display device according to claim 36, wherein, The backlight driving circuit further includes: a first backlight driving sub-circuit and a second backlight driving sub-circuit. The display partition includes a first display sub-partition and a second display sub-partition, and the backlight partition includes a first backlight sub-partition and a second backlight sub-partition; the first backlight sub-partition provides backlight for the first display sub-partition. The first backlight driving sub-circuit is electrically connected to N first backlight sub-partitions to drive the N first backlight sub-partitions. The second backlight driving sub-circuit is electrically connected to N second backlight sub-partitions to drive the N second backlight sub-partitions; The first backlight driving sub-circuit includes the control circuit, and the second output terminal of the control circuit is electrically connected to the second backlight driving sub-circuit to output a backlight control signal.

42. The display device according to claim 20, wherein, The backlight module includes a plurality of backlight chips arranged in an array, each backlight chip including M light emitters arranged along a column direction, and the plurality of backlight chips being electrically connected to the backlight driving circuit. The backlight chip includes M light emitters arranged along a second direction, and each row of thin-film transistors in the display partition includes a plurality of thin-film transistors arranged along a first direction, which is perpendicular to the second direction.

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