Pixel driving circuit and display panel

Abstract

A pixel driving circuit (PX) and a display panel. The pixel driving circuit (PX) comprises: a pulse width modulation module (11), which comprises k1 first data input terminals, wherein each first data input terminal is configured to receive one bit of data of grayscale data, and the pulse width modulation module (11) is configured to output a pulse width modulation signal from a data output terminal (a1) of the pulse width modulation module (11) on the basis of the grayscale data; and at least k1 data read-write modules (14), wherein each first data input terminal of the pulse width modulation module (11) is electrically connected to one data read-write module (14), k1 is the number of bits of the grayscale data, each data read-write module (14) comprises a first data write unit (141), a first storage unit (142), a first data readout unit (143) and a second storage unit (144), the first data write unit (141) is configured to write the grayscale data into the first storage unit (142) in response to an external gating signal (Bsel), the first data readout unit (143) is configured to write, in response to a frame synchronization signal (FSYN) and into the first data input terminals, data which is stored in the first storage unit (142); and the second storage unit (144) is configured to maintain the potential of the first data input terminals.

Description

Pixel driving circuit and display panel

[0001] This application claims priority to Chinese Patent Application No. 202510127449.2, filed with the Chinese Patent Office on January 27, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a pixel driving circuit and a display panel. Background Technology

[0003] Micro LEDs (Micro Light Emitting Diodes) offer advantages such as high brightness, low power consumption, and long lifespan, making them a strong contender for next-generation display technology. Micro LEDs require pixel driving circuits, such as active pixel driving circuits.

[0004] However, as the size of Micro LED devices shrinks and pixel density increases, the number of pixel driving circuits required also increases exponentially. In other words, a large number of pixel driving circuits need to be integrated within the limited area of ​​the display panel, making the design of these circuits more complex or necessitating an increase in their area.

[0005] In related technologies, the pixel driving circuit occupies a large area of ​​the display panel, which limits the further improvement of pixel density. Summary of the Invention

[0006] This application provides a pixel driving circuit and a display panel to reduce the area of ​​the pixel driving circuit and increase the pixel density of the display panel.

[0007] According to one aspect of this application, a pixel driving circuit is provided, comprising:

[0008] At least one pulse width modulation module, the pulse width modulation module including k1 first data input terminals, each first data input terminal being configured to input one bit of grayscale data, the pulse width modulation module being configured to output a pulse width modulation signal from the data output terminal of the pulse width modulation module according to the grayscale data; the data output terminal of the pulse width modulation module being configured to be connected to at least one light-emitting unit.

[0009] At least k1 data read / write modules are provided, and each first data input terminal of the pulse width modulation module is electrically connected to one of the data read / write modules, where k1 is the number of bits of the grayscale data.

[0010] The data read / write module includes a first data write unit, a first storage unit, a first data write-out unit, and a second storage unit;

[0011] In the data read / write module corresponding to the first data input terminal, the first data writing unit is configured to write one bit of the grayscale data into the corresponding first storage unit in response to an external strobe signal; the first data writing unit is configured to write the data stored in the first storage unit into a first data input terminal of the pulse width modulation module in response to a frame refresh signal; the second storage unit is configured to maintain the potential of the first data input terminal of the pulse width modulation module.

[0012] Optionally, the pixel driving circuit includes:

[0013] There are n pulse width modulation modules, each pulse width modulation module further includes k2 second data input terminals, each second data input terminal is set to input one bit of address data within the block, and the pulse width modulation module is also set to output internal gating signals from m internal gating output terminals according to the address data within the block; n is greater than 1;

[0014] Each of the pulse width modulation modules corresponds to m pixel switches; among the m pixel switches corresponding to each pulse width modulation module, the first end of each pixel switch is electrically connected to the data output end of the corresponding pulse width modulation module, the control ends of the m pixel switches are electrically connected to the m internal gating output ends of the pulse width modulation module one by one, and the second end of each pixel switch is configured to connect to one of the light-emitting units; m > n;

[0015] Each data read / write module is connected to one of the data read / write modules, and k2 is the number of bits of the address data in the block.

[0016] In the data read / write module corresponding to the second data input terminal, the first data write unit is configured to write one bit of the block address data into the corresponding first storage unit in response to an external strobe signal; the first data write-out unit is configured to write the data of the first storage unit into a second data input terminal of the pulse width modulation module in response to a frame refresh signal; the second storage unit is configured to maintain the potential of the second data input terminal of the pulse width modulation module.

[0017] Optionally, the first end of the first data writing unit is connected to one bit of the grayscale data or the block address data, the second end of the first data writing unit is electrically connected to the first end of the first data writing unit, and the control end of the first data writing unit is connected to the external strobe signal.

[0018] The first end of the first storage unit is electrically connected to the second end of the first data writing unit, and the second end of the first storage unit is grounded;

[0019] The second end of the first data writing unit is electrically connected to the first data input end or the second data input end of the corresponding pulse width modulation module, and the control end of the first data writing unit is connected to the frame refresh signal; the first end of the second storage unit is electrically connected to the second end of the first data writing unit, and the second end of the second storage unit is grounded.

[0020] Optionally, the first data writing unit includes a first transistor, the first electrode of the first transistor serves as the first terminal of the first data writing unit, the second electrode of the first transistor serves as the second terminal of the first data writing unit, and the control electrode of the first transistor serves as the control terminal of the first data writing unit.

[0021] The first storage unit includes a first capacitor, wherein a first end of the first capacitor serves as a first end of the first storage unit, and a second end of the first capacitor serves as a second end of the first storage unit.

[0022] The first data writing unit includes a second transistor, the first electrode of the second transistor serves as the first terminal of the first data writing unit, the second electrode of the second transistor serves as the second terminal of the first data writing unit, and the control electrode of the second transistor serves as the control terminal of the first data writing unit.

[0023] The second storage unit includes a second capacitor, with a first terminal of the second capacitor serving as the first terminal of the second storage unit and a second terminal of the second capacitor serving as the second terminal of the second storage unit.

[0024] Optionally, the pixel driving circuit further includes:

[0025] A block address parsing module is provided, wherein the input terminal of the block address parsing module is connected to a block address signal, and the block address parsing module is configured to parse the block address signal; and generate the external strobe signal when the block address signal matches the address of the pixel driving circuit.

[0026] Optionally, the pixel driving circuit further includes:

[0027] An energy-saving control module is provided, wherein the energy-saving control module is connected to the external strobe signal and the frame refresh signal; the energy-saving control module is configured to enter a first state in response to the external strobe signal, and output a start signal when the frame refresh signal is received in the first state; the energy-saving control module is further configured to enter a second state when the external strobe signal corresponding to the next frame is not received in the current frame, and output a shutdown signal in response to the frame refresh signal of the next frame in the second state.

[0028] The start control terminal of the pulse width modulation module is connected to the start signal or the turn-off signal, and the pulse width modulation module is configured to start in response to the start signal and turn off in response to the turn-off signal.

[0029] Optionally, the energy-saving control module includes an enabling unit and a start-up control unit;

[0030] The enabling unit receives the external strobe signal and the frame refresh signal. The enabling unit is configured to set the enabling signal to a first level in response to the pulse end edge of the external strobe signal, and to set the enabling signal to a second level in response to the pulse end edge of the frame refresh signal.

[0031] The startup control unit receives the enable signal and the frame refresh signal. The startup control unit is configured to set the output signal to the first level at a preset time during the pulse time of the frame refresh signal when the enable signal is at the first level, in order to form the startup signal; and to set the output signal to the second level at a preset time during the pulse time of the frame refresh signal when the enable signal is at the second level, in order to form the shutdown signal.

[0032] Optionally, the pulse width modulation module includes: a counter, a comparator, an intra-block address decoding unit, a current generation unit, and a light-emitting control switch;

[0033] The counter is connected to the frame refresh signal and counts according to the frame refresh signal; the clock terminal of the counter is connected to a preset clock signal.

[0034] The comparator includes k1 first input terminals, the first input terminals of the comparator serving as the first data input terminals of the pulse width modulation module; the second input terminal of the comparator is electrically connected to the output terminal of the counter; the output terminal of the comparator is electrically connected to the control terminal of the light-emitting control switch.

[0035] The first terminal of the light-emitting control switch is electrically connected to the current generating unit, and the second terminal of the light-emitting control switch is electrically connected to the data output terminal of the pulse width modulation module.

[0036] The intra-block address decoding unit includes k2 input terminals, which serve as the second data input terminals of the pulse width modulation module. The m output terminals of the intra-block address decoding unit are electrically connected one-to-one with the m internal gating output terminals of the pulse width modulation module. The intra-block address decoding unit is configured to generate the internal gating signal based on the intra-block address data.

[0037] Optionally, the current generating unit includes a first current source, a second current source, and a current switching switch;

[0038] The output terminal of the first current source is electrically connected to the first terminal of the current switching switch, the second terminal of the current switching switch is electrically connected to the first terminal of the light-emitting control switch, and the control terminal of the current switching switch is electrically connected to the third data input terminal of the pulse width modulation module.

[0039] The second current source is electrically connected to the first terminal of the light-emitting control switch; the output current of the first current source is different from the output current of the second current source;

[0040] The pixel driving circuit includes Each of the aforementioned data read / write modules has a corresponding third data input terminal connected to one of the aforementioned data read / write modules; in the data read / write modules connected to the third data input terminal, the first data writing unit is configured to write current-selected data into the corresponding first storage unit in response to an external strobe signal; the first data writing unit is configured to write data from the first storage unit into the third data input terminal of the pulse width modulation module in response to a frame refresh signal; the second storage unit is configured to maintain the potential of the third data input terminal of the pulse width modulation module.

[0041] Optionally, the pixel driving circuit further includes a clock regeneration module;

[0042] The clock regeneration module is connected to q clock signals with a preset phase difference at its input terminal.

[0043] The clock regeneration module is configured to encode the states of the q clock signals and generate a quantity decoder representing the number of encoding types based on the number of encoding types.

[0044] The least significant bit of the quantity decoded is used as the preset clock signal.

[0045] According to another aspect of this application, a display panel is provided, the display panel including a plurality of pixel driving circuits arranged in an array as described above;

[0046] The display panel also includes multiple light-emitting units arranged in an array;

[0047] Each pixel driving circuit is connected to m light-emitting units. Attached Figure Description

[0048] Figure 1 is a schematic diagram of the circuit structure of a pixel driving circuit provided in an embodiment of this application;

[0049] Figure 2 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application;

[0050] Figure 3 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application;

[0051] Figure 4 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application;

[0052] Figure 5 is a timing diagram of a pixel driving circuit provided in an embodiment of this application;

[0053] Figure 6 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application;

[0054] Figure 7 is a phase relationship diagram of a clock signal provided in an embodiment of this application;

[0055] Figure 8 is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Detailed Implementation

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] Figure 1 is a schematic diagram of the circuit structure of a pixel driving circuit provided in an embodiment of this application. Referring to Figure 1, the pixel driving circuit includes:

[0058] At least one pulse width modulation module 11 is provided, the pulse width modulation module 11 includes k1 first data input terminals, each first data input terminal is configured to input one bit of grayscale data; the pulse width modulation module 11 is configured to output a pulse width modulation signal from its data output terminal a1 according to the grayscale data; the data output terminal a1 of the pulse width modulation module 11 is configured to be connected to at least one light-emitting unit 13.

[0059] At least k1 data read / write modules 14, each first data input terminal of the pulse width modulation module 11 is electrically connected to a data read / write module 14, and k1 is the number of bits of grayscale data;

[0060] The data read / write module 14 includes a first data writing unit 141, a first storage unit 142, a first data writing unit 143, and a second storage unit 144;

[0061] In the data read / write module 14 corresponding to the first data input terminal, the first data writing unit 141 is configured to write one bit of grayscale data into the corresponding first storage unit 142 in response to the external strobe signal Bsel; the first data writing unit 143 is configured to write the data stored in the first storage unit 142 into a first data input terminal of the pulse width modulation module 11 in response to the frame refresh signal FSYN; and the second storage unit 144 is configured to maintain the potential of the first data input terminal of the pulse width modulation module 11.

[0062] For example, the light-emitting unit 13 can be a Micro LED, or it can be a light-emitting unit with other structures. The light-emitting unit 13 is a current-driven device and requires a pixel driving circuit to emit light. In the display panel, all the light-emitting units 13 can be arranged in an array. The display panel may include multiple pixel driving circuits arranged in an array, and each pixel driving circuit drives at least one light-emitting unit 13.

[0063] Each pixel driving circuit includes at least one pulse width modulation module 11, and each pulse width modulation module 11 can drive one light-emitting unit 13. Each pulse width modulation module 11 includes k1 first data input terminals. Each first data input terminal is connected to a data read / write module. Here, k1 is the number of bits for grayscale data, which is the data corresponding to the light emitted by the light-emitting unit 13. Different grayscale data result in different grayscale levels emitted by the light-emitting unit 13. In this embodiment, the pixel driving circuit is a digital pixel driving circuit; different grayscale data result in different light-emitting times for the light-emitting unit 13 within a frame. It is understood that in some implementations, the driving current corresponding to different driven light-emitting units can be the same within the same frame. The number of bits for grayscale data can be determined by the number of grayscale levels corresponding to the light-emitting unit. The more grayscale levels there are, the more bits of grayscale data are corresponding to it, i.e., the larger k1 is. For example, k1 can be 12. The pulse width modulation module 11 can generate a corresponding pulse width modulation signal based on the grayscale data. The pulse width modulation signal is a signal with a certain current value and a certain pulse width. Different pulse width modulation signals have the same current value, but different pulse widths of the pulse width modulation signals corresponding to different grayscale data, thereby enabling the light-emitting unit 13 to display different grayscales.

[0064] Within one frame, the k1 first data input terminals of the pulse width modulation module 11 receive k1 bits of grayscale data in parallel. Specifically, the k1 bits of grayscale data are written in parallel to the k1 first data input terminals of the pulse width modulation module 11 by k1 data read / write modules. Since the grayscale data is input in parallel, each data read / write module 14 can only read or write one bit of data at a time. Therefore, each pulse width modulation module 11 requires at least k1 data read / write modules 14 to write data. Each data read / write module 14 needs to be connected to one data line, so each pixel driving circuit requires at least k1 data lines. As shown in Figure 1, the k1 data read / write modules 14 are connected to the block data input terminal BData, which contains at least k1 sub-terminals, each of which is connected to one data line.

[0065] In related technologies, reading and writing one bit of data in a pixel driving circuit requires two latches, while parallel reading and writing of k1 bits of data requires... Each latch is completed. However, each latch requires a relatively large number of transistors, such as at least six transistors per latch. This results in a large number of components required for the pixel driving circuit as a whole, and thus a larger area occupied by the pixel driving circuit.

[0066] In this embodiment, the data read / write module 14 can complete both reading and writing data using only two units. When the external strobe signal Bsel is enabled, the data read / write module 14 is in read mode. When the data read / write module 14 reads data, the first data writing unit 141 is turned on, and the corresponding data (i.e., grayscale data) is stored in the first storage unit 142. When the frame refresh signal FSYN arrives, the data read / write module 14 writes data to the pulse width modulation module 11. At this time, the first data writing unit 143 is turned on, and the data on the first storage unit 142 is written to the corresponding data input terminal (first data input terminal) of the pulse width modulation module 11. Furthermore, by setting the second storage unit 144, the potential of the first data input terminal of the corresponding pulse width modulation module 11 is maintained, enabling the pulse width modulation module 11 to stably output the pulse width modulation signal. In summary, the pixel driving circuit of this embodiment requires only a small number of components to complete the read and write operation of one bit of data. The small number of required components can greatly reduce the number of components needed for the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and increasing the pixel density of the display panel.

[0067] The technical solution of this embodiment employs a pixel driving circuit comprising: at least one pulse width modulation (PWM) module, the PWM module including k1 first data input terminals, each first data input terminal being configured to input one bit of grayscale data, and the PWM module being configured to output a pulse width modulation signal from its data output terminal based on the grayscale data; the data output terminal of the PWM module being configured to connect to at least one light-emitting unit; at least k1 data read / write modules, each first data input terminal of the PWM module being electrically connected to one data read / write module, where k1 is the number of bits of grayscale data; the data read / write module including a first data writing unit, a first storage unit, a first data writing unit, and a second storage unit; in the data read / write module corresponding to the first data input terminal, the first data writing unit is configured to write one bit of grayscale data into the corresponding first storage unit in response to an external strobe signal; the first data writing unit is configured to write the data stored in the first storage unit into one first data input terminal of the PWM module in response to a frame refresh signal; the second storage unit is configured to maintain the potential of the first data input terminal of the PWM module. Both reading and writing data in the data read / write module can be completed by two units. Pixel driving circuits require only a small number of components to complete the read and write operation of one bit of data. The small number of components required can greatly reduce the number of components needed for pixel driving circuits, thereby reducing the area of ​​pixel driving circuits and increasing the pixel density of display panels.

[0068] Optionally, Figure 2 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application. Referring to Figure 2, the pixel driving circuit includes:

[0069] There are n pulse width modulation modules 11, and each pulse width modulation module 11 also includes k2 second data input terminals. Each second data input terminal is set to input one bit of the address data within the block. The pulse width modulation module 11 is also set to output internal gating signals from its m internal gating output terminals a2 according to the address data within the block; n is greater than 1.

[0070] Each pulse width modulation module 11 corresponds to m pixel switches 12; among the m pixel switches 12 corresponding to each pulse width modulation module 11, the first end of each pixel switch 12 is electrically connected to the data output terminal a1 of the corresponding pulse width modulation module 11, the control terminals of the m pixel switches 12 are electrically connected to the m internal gating output terminals a2 of the pulse width modulation module 11 in a one-to-one correspondence, and the second end of the pixel switch 12 is configured to connect to a light-emitting unit 13; ;

[0071] Each data read / write module 14 has a corresponding second data input terminal connected to one data read / write module 14. Different second data input terminals are connected to different data read / write modules 14, and the first data input terminal and the second data input terminal are also connected to different data read / write modules 14. That is, in this embodiment, each pulse width modulation module 11 corresponds to (k1+k2) data read / write modules 14, where k1 is the number of bits of grayscale data and k2 is the number of bits of block address data.

[0072] In the data read / write module 14 corresponding to the second data input terminal, the first data writing unit 141 is configured to write one bit of the block address data into the corresponding first storage unit 142 in response to the external strobe signal Bsel; the first data writing unit 143 is configured to write the data of the first storage unit 142 into a second data input terminal of the pulse width modulation module 11 in response to the frame refresh signal FSYN; the second storage unit 144 is configured to maintain the potential of the second data input terminal of the pulse width modulation module 11.

[0073] For example, in this embodiment, the pixel driving circuit is configured to drive m light-emitting units 13. In the display panel, the m light-emitting units 13 can be arranged in an array. The display panel may include multiple pixel driving circuits arranged in an array, and from the perspective of the display panel as a whole, all the light-emitting units 13 can also be arranged in an array. For example, m can be 64, and the 64 light-emitting units corresponding to each pixel driving circuit can be arranged in an 8x8 array. In this embodiment, the second terminals of the m pixel switches 12 corresponding to each pulse width modulation module 11 are electrically connected to the m light-emitting units. That is, each light-emitting unit is connected to n pixel switches, and the n pixel switches 12 belong to different pulse width modulation modules 11.

[0074] For each pixel driving circuit, the pixel driving circuit includes n pulse width modulation modules 11. Each pulse width modulation module 11 can drive one light-emitting unit 13 to emit light according to the address data within the block. That is to say, within one frame, only a few of the m light-emitting units 13 corresponding to one pixel driving circuit can emit light, and the maximum number of light-emitting units emitting light simultaneously within one frame is n. Thus, one pixel driving circuit can sparsely drive m light-emitting units 13, thereby achieving sparse display of m light-emitting units 13. For example, the value of n is 8.

[0075] Each pulse width modulation module 11 includes k1 first data input terminals and k2 second data input terminals. Each first data input terminal is connected to a data read / write module, and each second data input terminal is connected to a data read / write module. Here, k1 represents the number of bits for the grayscale data, which is the data corresponding to the emission of the light-emitting unit 13. Different grayscale data result in different grayscale values ​​emitted by the light-emitting unit 13. In this embodiment, the pixel driving circuit is a digital pixel driving circuit; different grayscale data result in different emission times for the light-emitting unit 13 within a frame. It is understood that in some implementations, the driving current corresponding to different driven light-emitting units may be the same within the same frame. The number of bits for the grayscale data can be determined by the number of grayscale levels corresponding to the light-emitting unit; the more grayscale levels, the more bits of the corresponding grayscale data, i.e., the larger k1. For example, k1 can be 12.

[0076] k2 represents the number of bits in the intra-block address data, which indicates the position of the m light-emitting units 13 corresponding to the pixel driving circuit. Within one frame, each pulse width modulation module 11 drives one light-emitting unit 13 to emit light. The specific address of the driven light-emitting unit 13 is determined by the intra-block address data; each intra-block address data corresponds to one light-emitting unit 13, and different intra-block address data correspond to different light-emitting units 13. The number of bits in the intra-block address data is determined by the specific value of m; the larger the value of m, the larger the number of bits in the intra-block address data, i.e., the larger the value of k2. For example, when m is 64, the value of k2 can be 6.

[0077] Within one frame, the k1 first data input terminals of the pulse width modulation module 11 receive k1 bits of grayscale data in parallel. Specifically, the k1 bits of grayscale data are written in parallel to the k1 first data input terminals of the pulse width modulation module 11 by k1 data read / write modules. The k2 second data input terminals of the pulse width modulation module 11 receive k2 bits of block address data in parallel. Specifically, the k2 bits of block address data are written in parallel to the k2 second data input terminals of the pulse width modulation module 11 by k2 data read / write modules. Since both grayscale data and block address data are input in parallel, each data read / write module 14 can only read or write one bit of data at a time. Therefore, each pulse width modulation module 11 requires k1+k2 data read / write modules 14 to write data. Consequently, n pulse width modulation modules 11 require... Each data read / write module 14 writes data. When n=8, k1=12, and k2=6, n pulse width modulation modules 11 require a total of 144 data read / write modules 14. Each data read / write module 14 needs to be connected to one data line, therefore each pixel driving circuit requires a total of... There are 144 data lines. As shown in Figure 1, Each data read / write module 14 connects to the block data input terminal BData, which contains a total of [number missing] data read / write modules. Each terminal is connected to a data cable.

[0078] In related technologies, reading and writing one bit of data in a pixel driving circuit requires two latches, enabling parallel reading and writing. Bit data requires Each latch is completed. However, each latch requires a relatively large number of transistors, such as at least six transistors per latch. This results in a large number of components required for the pixel driving circuit as a whole, and thus a larger area occupied by the pixel driving circuit.

[0079] In this embodiment, both reading and writing data in the data read / write module 14 can be accomplished by two units. For example, when the external strobe signal Bsel is enabled, the data read / write module 14 is in read mode. When reading data, the first data writing unit 141 is turned on, and the corresponding data (i.e., one bit of grayscale data or one bit of block address data) is stored in the first storage unit 142. When the frame refresh signal FSYN arrives, the data read / write module 14 writes data to the pulse width modulation module 11. At this time, the first data writing unit 143 is turned on, and the data in the first storage unit 142 is written to the corresponding data input terminal (first data input terminal or second data input terminal) of the pulse width modulation module 11. Furthermore, by setting the second storage unit 144, the potential of the corresponding data input terminal of the pulse width modulation module 11 is maintained, enabling the pulse width modulation module 11 to stably output the internal strobe signal and the pulse width modulation signal. In summary, the pixel driving circuit of this embodiment requires only a small number of components to complete the read and write operation of one bit of data. The small number of required components can greatly reduce the number of components needed for the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and increasing the pixel density of the display panel.

[0080] The technical solution of this embodiment uses a pixel driving circuit including: n pulse width modulation modules, each pulse width modulation module further including k2 second data input terminals, each second data input terminal is set to input one bit of address data within the block, and the pulse width modulation module is also set to output internal gating signals from its m internal gating output terminals according to the address data within the block; n is greater than 1; Each pulse width modulation module 11 corresponds to m pixel switches 12; among the m pixel switches corresponding to each pulse width modulation module 11, the first end of each pixel switch is electrically connected to the data output end of the corresponding pulse width modulation module, the control end of the m pixel switches is electrically connected to the m internal gating output ends of the pulse width modulation module one by one, and the second end of the pixel switch is set to connect to a light-emitting unit. ; Each data read / write module has a corresponding second data input terminal connected to it, where k2 represents the number of bits of the address data within the block. Within the data read / write module corresponding to the second data input terminal, the first data writing unit is configured to write one bit of the address data within the block to the corresponding first storage unit in response to an external strobe signal; the first data writing unit is configured to write the data from the first storage unit to a second data input terminal of the pulse width modulation module in response to a frame refresh signal; the second storage unit is configured to maintain the potential of the second data input terminal of the pulse width modulation module. Both reading and writing data in the data read / write module can be completed by just two units. The pixel driving circuit requires only a small number of components to complete the read / write operation of one bit of data. This significantly reduces the number of components needed in the pixel driving circuit, thereby reducing the area of ​​the pixel driving circuit and increasing the pixel density of the display panel.

[0081] Optionally, referring to Figures 1 and 2, the first end of the first data writing unit 141 is connected to a bit of grayscale data or the address data within the block; the second end of the first data writing unit 141 is electrically connected to the first end of the first data writing unit 143; and the control end of the first data writing unit 141 is connected to an external strobe signal Bsel. The first end of the first storage unit 142 is electrically connected to the second end of the first data writing unit 141, and the second end of the first storage unit 142 is grounded. The second end of the first data writing unit 143 is electrically connected to the first data input or second data input of the corresponding pulse width modulation module 11, and the control end of the first data writing unit 143 is connected to a frame refresh signal FSYN. The first end of the second storage unit 144 is electrically connected to the second end of the first data writing unit 143, and the second end of the second storage unit 144 is grounded.

[0082] For example, in the data read / write module 14 corresponding to the input grayscale data, the first end of the first data writing unit 141 is connected to one bit of grayscale data, and different first data writing units 141 are connected to different bits of grayscale data. The second end of the corresponding first data writing unit 143 is electrically connected to one first data input terminal of the pulse width modulation module 11, and different first data writing units 143 are electrically connected to different first data input terminals.

[0083] In the data read / write module 14 corresponding to the address data within the input block, the first end of the first data writing unit 141 is connected to one bit of the address data within the block, and different first data writing units 141 are connected to different bits of the address data within the block. The second end of the corresponding first data writing unit 143 is electrically connected to a second data input terminal of the pulse width modulation module 11, and different first data writing units 143 are electrically connected to different first data input terminals.

[0084] For example, continuing to refer to FIG1, the first data writing unit 141 includes a first transistor T1, the first electrode of the first transistor T1 serves as the first terminal of the first data writing unit 141, the second electrode of the first transistor T1 serves as the second terminal of the first data writing unit 141, and the control electrode of the first transistor T1 serves as the control terminal of the first data writing unit 141.

[0085] The first storage unit 142 includes a first capacitor C1, with the first end of the first capacitor C1 serving as the first end of the first storage unit 142 and the second end of the first capacitor C1 serving as the second end of the first storage unit 142.

[0086] The first data writing unit 143 includes a second transistor T2. The first electrode of the second transistor T2 serves as the first terminal of the first data writing unit 143, the second electrode of the second transistor T2 serves as the second terminal of the first data writing unit 143, and the control electrode of the second transistor T2 serves as the control terminal of the first data writing unit 143.

[0087] The second storage unit 144 includes a second capacitor C2, with the first end of the second capacitor C2 serving as the first end of the second storage unit 144 and the second end of the second capacitor C2 serving as the second end of the second storage unit 144.

[0088] In this embodiment, the data read / write module 14 can complete the read and write operations of one bit of data using only two transistors and two capacitors, requiring fewer components and thus occupying less area for the pixel driving circuit. It is understood that in other embodiments, the first data write unit 141 and the first data write unit 143 may also employ other types of switching structures. The first storage unit 142 and the second storage unit 144 may also employ other types of charge storage elements.

[0089] Optionally, the capacitance value of the first capacitor C1 is greater than or equal to twice the capacitance value of the second capacitor C2. This ensures that the data in the first capacitor C1 is accurately written into the second capacitor C2.

[0090] Due to the characteristics of capacitance, the second capacitor C2 will gradually discharge over time, causing the voltage value on the second capacitor C2 to gradually decrease. Therefore, it is necessary to design the capacitance value of the second capacitor C2 so that it can maintain a certain amount of charge within the time range of one frame of image, thereby ensuring the accuracy of grayscale data.

[0091] The basic formula for capacitor discharge is:

[0092]

[0093] Among them, the discharge time constant It is a key factor determining the discharge rate of a capacitor, and its calculation formula is as follows: . It is the voltage across the capacitor at time t. R is the initial voltage across the capacitor, C is the resistance of the capacitor under load, t is time, and e is the base of the natural logarithm (approximately 2.718).

[0094] When the discharge time t is approximately equal to When the discharge time constant is constant, Value reaches the original of Assume that the circuit detects a voltage drop to the original voltage. If the discharge time is above a certain threshold, it can be assumed that the data stored in the capacitor can still be detected, and therefore the discharge time must meet the following condition. That is, the time constant of capacitor C2 must satisfy the following relationship:

[0095]

[0096] In the sparse high refresh rate display application proposed in this application, it is assumed that the system's frame refresh rate is 200kHz, i.e., the time period of each frame is T=5µs. The capacitance value of the second capacitor C2 needs to ensure that the voltage data it stores can still be accurately identified within 5µs, i.e., the discharge time t is at least equal to one T. Therefore, the discharge time constant of C2 can be deduced to satisfy:

[0097]

[0098] in This is the input impedance of the comparator.

[0099] The capacitance value of the second capacitor C2 must satisfy the following:

[0100]

[0101] In Complementary Metal Oxide Semiconductor (CMOS) technology, comparator impedance can typically reach the level of hundreds of GΩ. Assuming the comparator impedance is 10 GΩ, substituting it into the above formula, we can obtain the value of the second capacitor C2:

[0102]

[0103] According to the capacitance calculation formula for a parallel plate:

[0104]

[0105] in, Let be the dielectric constant of the dielectric material, A be the area of ​​the parallel plates, and d be the thickness of the dielectric material. Generally, in the CMOS process, SiO2 is used as the dielectric material, and its dielectric constant is... Assuming its thickness is 0.1µm, the area of ​​capacitor C2 can be derived as follows:

[0106]

[0107] Substitute d and From the constant value, the area of ​​C2 can be calculated to be 2.89 μm².

[0108] In the sparse driving method proposed in this patent, a single pixel driving circuit can... Within a pixel block unit, eight pixels are driven simultaneously. Assuming each pixel's driving data consists of 12 bits + 6 bits + 1 bit, a pixel block driving circuit needs to support... Data storage and refresh of bits. Then, the total area of ​​the first capacitor C1 used for data storage and the second capacitor C2 used for grayscale refresh in each block is at least (considering...). ):

[0109]

[0110] In CMOS processes, multilayer capacitor designs are often used. This is achieved by fabricating metal and dielectric material layers on different process layers. These layers are stacked together through specific design and process steps to form a capacitor structure. Multilayer capacitor designs can increase the capacitance value per unit area; in other words, capacitors of the same capacitance value can occupy a smaller planar area.

[0111] Assuming that the block pixel driving circuit proposed in this patent adopts a double-layer capacitor design, that is, one The total area of ​​the capacitor required by the pixel block occupies a plane area equal to the total area. ,Right now The size of this area will determine the maximum area of ​​a single pixel unit. This assumes that the capacitor layer wiring utilization can be achieved... That is, to achieve a The minimum planar area required for the block pixel driving circuit is:

[0112]

[0113] The minimum pixel pitch supported by this area is:

[0114]

[0115] Based on the above estimates, the block pixel driving circuit proposed in this patent can support the pitch of Micro-LED display devices to be reduced to approximately 3.5µm.

[0116] Furthermore, this scheme, which uses a capacitor structure for data storage and refresh, allows the data storage unit to be implemented through the upper metal layer during chip wiring design, without occupying the area of ​​the underlying metal oxide semiconductor (MOS) transistors. This provides the possibility of integrating more MOS transistors at the bottom layer and lays the foundation for display applications with higher parallel peripheral interfaces (PPI).

[0117] Optionally, Figure 3 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application. Referring to Figure 3, the pixel driving circuit further includes a block address parsing module 15. The input terminal of the block address parsing module 15 is connected to the block address signal ADData. The block address parsing module 15 is configured to parse the block address signal ADData and generate an external strobe signal Bsel when the block address signal ADData matches the address of the pixel driving circuit.

[0118] For example, the display panel contains multiple pixel driving circuits arranged in an array. Each pixel driving circuit corresponds to a block address, and different pixel driving circuits have different block addresses. Pixel driving circuits in the same column share the same data line. The display panel can select the corresponding pixel driving circuit to drive through the block address signal ADData. For example, if it is necessary to select the pixel driving circuit in the first row at a certain time, a block address signal ADData matching the address of the pixel driving circuit in the first row can be written to the data line. The pixel driving circuit in the first row receives the block address signal ADData and generates an external strobe signal Bsel. The block address signals ADData received by the pixel driving circuits in other rows do not match their own addresses, so the pixel driving circuits in other rows are not selected. That is to say, at this time, the grayscale data transmitted on the data line can only be received by the pixel driving circuit in the first row. Pixel driving circuits that do not need to be driven are not selected and do not work, which can reduce power consumption. In addition, the shared data line of a column of pixel driving circuits, due to the block address matching mode, can be understood as a bus mode matching block address mode, which can save data routing. For example, the block address resolution module 15 may include a decoder and a comparator. The decoder decodes the received block address signal ADData, and the comparator compares the decoding result with the address of the pixel driving circuit. If the decoding result matches the address of the pixel driving circuit, an external strobe signal is output.

[0119] Optionally, referring to Figure 3, the pixel driving circuit further includes an energy-saving control module 16. The energy-saving control module 16 is connected to an external strobe signal Bsel and a frame refresh signal FSYN. The energy-saving control module 16 is configured to enter a first state in response to the external strobe signal Bsel, and output a start signal when it receives the frame refresh signal FSYN in the first state. The energy-saving control module 16 is also configured to enter a second state when it does not receive the external strobe signal for the next frame in the current frame, and output a shutdown signal in response to the frame refresh signal of the next frame in the second state. The start control terminal of the pulse width modulation module 11 is connected to either the start signal or the shutdown signal. The pulse width modulation module is configured to start in response to the start signal and shut down in response to the shutdown signal.

[0120] In this embodiment, the pixel driving circuit in the display panel may not be driven in every frame, meaning there may be frames where the corresponding light-emitting unit 13 does not need to be displayed. When the pixel driving circuit does not need to be driven in a certain frame, the energy-saving control module 16 can control the pulse width modulation module 11 not to start in that frame. For example, it can control the comparator and / or counter units in the pulse width modulation module 11 not to start, thereby reducing power consumption.

[0121] A frame in the pixel driving circuit begins with the frame refresh signal FSYN of the current frame and ends with the frame refresh signal FSYN of the next frame. When the frame refresh signal FSYN arrives, the data in the data read / write module 14 is read into the pulse width modulation module 11. Before the frame refresh signal FSYN of the current frame arrives, the first storage unit 142 in the data read / write module 14 has already stored the data required for the current frame. That is, the external strobe signal of the current frame is received in the previous frame, and the external strobe signal received in the current frame indicates that data needs to be written in the next frame, that is, the pulse width modulation module 11 needs to be started. Therefore, when the energy-saving control module 16 receives the external strobe signal Bsel in the current frame, it indicates that the pulse width modulation module 11 needs to be started in the next frame. When the energy-saving control module 16 receives the external strobe signal Bsel, it first enters a first state. Upon receiving the frame refresh signal FSYN, indicating the arrival of the next frame, it starts the pulse width modulation module 11, avoiding increased power consumption by directly starting the pulse width modulation module when the external strobe signal is received in the current frame. Conversely, when the current frame does not receive the external strobe signal Bsel, indicating no data in the next frame, the pulse width modulation module 11 does not need to be started. In this case, the energy-saving control module 16 first enters a second state. Upon receiving the frame refresh signal FSYN, indicating the arrival of the next frame, it shuts down the pulse width modulation module 11, thereby saving power.

[0122] Optionally, Figure 4 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application, and Figure 5 is a timing diagram of a pixel driving circuit provided in an embodiment of this application. Referring to Figures 4 and 5, the energy-saving control module 16 includes an enable unit 161 and a start control unit 162. The enable unit 161 is connected to an external strobe signal Bsel and a frame refresh signal FSYN. The enable unit 161 is configured to set the enable signal ML to a first level in response to the end edge of the pulse of the external strobe signal Bsel, and to set the enable signal ML to a second level in response to the end edge of the pulse of the frame refresh signal. The start control unit 162 is connected to the enable signal ML and the frame refresh signal FSYN. The start control unit 162 is configured to set the output signal ACT to a first level at a preset time during the pulse time of the frame refresh signal FSYN when the enable signal ML is at the first level, in order to form a start signal; and to set the output signal ACT to a second level at a preset time during the pulse time of the frame refresh signal FSYN when the enable signal ML is at the second level, in order to form a turn-off signal.

[0123] For example, in this embodiment, the output signal ACT of the start control unit 162 controls the pulse width modulation module 11 to start or stop. The first level can be a high level, the second level can be a low level, or vice versa. As shown in Figure 5, three consecutive frames are schematically illustrated. In the first frame, there is an external strobe signal Bsel. Therefore, at the end edge of the pulse of the external strobe signal Bsel (i.e., the falling edge), the enable signal output by the enable unit 161 is set to the first level, and the energy-saving control module 16 enters the first state. After the frame refresh signal FSYN arrives in the second frame, the enable signal ML of the enable unit 161 is set to the second level at the falling edge, and the output signal ACT of the start control unit 162 is set to the first level at some moment in the middle of the frame refresh signal FSYN pulse (i.e., regardless of whether it is currently the first level or the second level is set to the first level). In this embodiment, the output signal ACT of the start control unit 162 changes at a certain moment between the start and end edges of the frame refresh signal FSYN pulse, enabling the pulse width modulation module 11 to start in advance. When the end edge of the frame refresh signal arrives, i.e., after data writing begins, the pulse width modulation module 11 can enter a stable operating state. As shown in Figure 5, in the second frame, there is no external strobe signal Bsel, so the enable signal ML remains at the second level. When the frame refresh signal FSYN arrives in the third frame, the output signal ACT is set to the second level.

[0124] In the above embodiment, the pulse width modulation module 11 needs to operate under the control of the input clock Dclk, and the duration of the external strobe signal Bsel includes at least one cycle of the input clock Dclk. The output signal ACT can transition at the midpoint of the frame refresh signal FSYN. In addition, the enable unit 161 and the start control unit 162 can be implemented based on a field programmable gate array (FPGA) or the like.

[0125] Optionally, Figure 6 is a schematic diagram of the circuit structure of another pixel driving circuit provided in an embodiment of this application. Referring to Figure 6, the pulse width modulation module 11 includes a counter 111, a comparator 112, an intra-block address decoding unit 113, a current generation unit 114, and a light emission control switch 115; the counter 111 is connected to the frame refresh signal FSYN; the clock terminal of the counter 111 is connected to a preset clock signal, i.e., the input clock Dclk. The comparator 112 includes k1 first input terminals, the first input terminals of the comparator 112 serve as the first data input terminals of the pulse width modulation module 11, and the second input terminals of the comparator 112 are electrically connected to the output terminal of the counter 111; the output terminal of the comparator 112 is electrically connected to the control terminal of the light emission control switch 115.

[0126] The first terminal of the light-emitting control switch 115 is electrically connected to the current generating unit 114, and the second terminal of the light-emitting control switch 115 is electrically connected to the data output terminal a1 of the pulse width modulation module 11. The block address decoding unit 113 includes k2 input terminals. The input terminals of the block address decoding unit 113 serve as the second data input terminals of the pulse width modulation module 11. The m output terminals of the block address decoding unit 113 are electrically connected to the m internal gating output terminals of the pulse width modulation module 11 in a one-to-one correspondence. The block address decoding unit 113 is configured to generate internal gating signals based on the block address data.

[0127] Referring to Figures 5 and 6, as an example, when the end edge of the frame refresh signal FSYN pulse arrives, counter 111 starts counting, and the count output value (Conter) of counter 111 gradually increases. The count output Conter is compared with the data (i.e., grayscale data) at the first input of comparator 112. If the grayscale data is greater than the count output Conter, comparator 112 controls the light-emitting control switch 115 to turn on; that is, the output control signal PWM of comparator 112 controls the light-emitting control switch 115 to turn on. The constant current generated by the current generating unit 114 is transmitted to the corresponding light-emitting unit 13, and the light-emitting unit 13 emits light. When the count output Conter is greater than the grayscale data, the output control signal PWM of comparator 112 controls the light-emitting control switch 115 to turn off, and the light-emitting unit 13 turns off. It can be understood that the intra-block address decoding unit 113 controls the corresponding pixel switch 12 to turn on according to the intra-block address data, so that the light-emitting unit 13 corresponding to the pixel switch 12 is connected to the light-emitting control switch 115, thereby achieving sparse display. When the energy-saving control module 16 outputs a shutdown signal, the comparator 112 does not perform comparisons, and the counter 111 does not count.

[0128] Optionally, referring to Figure 6, the current generating unit 114 includes a first current source I1, a second current source I2, and a current switching switch 1141; the output terminal of the first current source I1 is electrically connected to the first terminal of the current switching switch 1141, the second terminal of the current switching switch 1141 is electrically connected to the first terminal of the light-emitting control switch 115, and the control terminal of the current switching switch 1141 is electrically connected to the third data input terminal of the pulse width modulation module 11.

[0129] The second current source I2 is electrically connected to the first terminal of the light-emitting control switch 115. The output current of the first current source I1 is different from the output current of the second current source I2.

[0130] Pixel driving circuit includes Each data read / write module 14 has a corresponding third data input terminal connected to it. In the data read / write module 14 connected to the third data input terminal, the first data writing unit 141 is configured to write current selection data into the corresponding first storage unit 142 in response to the external strobe signal Bsel; the first data writing unit 143 is configured to write the data of the first storage unit 142 into the third data input terminal of the pulse width modulation module 11 in response to the frame refresh signal FSYN; and the second storage unit 144 is configured to maintain the potential of the third data input terminal of the pulse width modulation module 11.

[0131] For example, in this embodiment, the current generation module 114 can generate two different driving currents, and the current switching switch 1141 can be controlled to turn on or off according to the current selection data. That is, in this embodiment, different light-emitting units are driven by different pulse width modulation modules 11, and the current selection data corresponding to different pulse width modulation modules can be different. Therefore, the driving currents corresponding to different pulse width modulation modules can be different, and consequently, the driving currents corresponding to different light-emitting units can be different. The current selection data also needs to be read and written by a data read / write module 14. In this embodiment, each pixel driving circuit includes... There are 152 data read / write modules 14. When n is 8, k1 is 12, and k2 is 6, each pixel driving circuit includes a total of 152 data read / write modules 14, which means a total of 152 data lines are required. Both the first current source I1 and the second current source I2 can be current mirrors. The current generated by the first current source I1 can be... The current generated by the second current source I2 can be This allows for a wider dynamic brightness range.

[0132] For example, in a display panel, a wiring method that sends data to multiple pixel driving circuits via a 100Mbps bus can save on wiring density outside the pixel driving circuits. Assuming one bus supports one unit column (i.e., one column of pixel driving circuits), taking the parallel input data of the unit column proposed in the embodiment as an example, the number of buses required for one unit column is approximately... There are 165 buses, and according to the relevant 0.13µm process, the minimum wiring trace width is 0.42µm. The total width of these 165 buses is... Since each unit block consists of 8 columns of pixels, and considering that the bus uses 3 layers of metal for wiring, the minimum column width of the pixel block supported by this bus width is: That is, when a bus is routed to carry one unit column block, it can support a pixel size of up to 2.8um, and its row resolution is By using multiple sets of column-oriented bus routing methods, it is easy to achieve small-pitch, high-resolution display devices. In the formula, 4 represents the clock line, and the clock signal on the clock line is ultimately converted into the input clock Dclk; 9 represents the column addressing lines required for a column of pixel driving circuits. In this embodiment, each row of pixel driving circuits can correspond to 5 row addressing lines.

[0133] Optionally, referring to Figure 6, the pixel driving circuit further includes a clock regeneration module 17; the input of the clock regeneration module 17 is connected to q clock signals with a preset phase difference; the clock regeneration module 17 is configured to encode according to the state of the q clock signals, and generate a quantity decoder representing the number of encoding types according to the number of encoding types; the clock regeneration module 17 is also configured to use the least significant bit of the quantity decoder as the preset clock signal.

[0134] For example, q clock signals have the same period, and the phase difference between any two adjacent clock signals can be... Each clock signal has a distinct phase, meaning no two clock signals have the same phase. The clock regeneration module 17 acquires the state of each of the q clock signals at a given moment, encodes this state, and then decodes the total number of different codes to obtain the numerical decoder. The rate of change of the least significant bit in the numerical decoder is equal to the period of the clock signal. This signal is used as a preset clock signal, thus realizing the conversion from a low-speed clock signal to a high-speed clock signal. For example, as shown in Figure 7, which is a phase relationship diagram of a clock signal provided in an embodiment of this application, taking q as 4 as an example, it includes a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4, a total of four clock signals. Each pair of these four clock signals differs by 1 / 8 of a phase. In stage t1, the clock regeneration module 17 receives q clock signals encoded as 1111; in stage t2, 1110; in stage t3, 1100; in stage t4, 1000; in stage t5, 0000; in stage t6, 0001; in stage t7, 0011; and in stage t8, 0111. The corresponding number of encoding types is 8, meaning the quantity decoding requires a total of three bits. Assume the quantity decoding for stage t1 is 000, for stage t2 it's 001, for stage t3 it's 010, for stage t4 it's 011, for stage t5 it's 100, for stage t6 it's 101, for stage t7 it's 110, and for stage t8 it's 111. Therefore, the least significant bit of the quantity decoding changes periodically, with a cycle of 1 / 8 of the clock signal's duration.

[0135] Optionally, in counter 111, the quantity decoder can be used as the last three bits of the counter, and counter 111 may include a 9-bit register, thus counter 111 constitutes a 12-bit counter.

[0136] Optionally, continuing to refer to Figure 6, the pixel switch 12 includes a third transistor T3, the first electrode of the third transistor T3 serves as the first terminal of the pixel switch 12, the second electrode of the third transistor T3 serves as the second terminal of the pixel switch 12, and the control electrode of the third transistor T3 serves as the control terminal of the pixel switch 12.

[0137] The light-emitting control switch 115 includes a fourth transistor T4. The first electrode of the fourth transistor T4 serves as the first terminal of the light-emitting control switch 115, the second electrode of the fourth transistor T4 serves as the second terminal of the light-emitting control switch 115, and the control electrode of the fourth transistor T4 serves as the control terminal of the light-emitting control switch 115.

[0138] The current switching switch 1141 includes a fifth transistor T5. The first terminal of the fifth transistor T5 serves as the first terminal of the current switching switch 1141, the second terminal of the fifth transistor T5 serves as the second terminal of the current switching switch 1141, and the control terminal of the fifth transistor T5 serves as the control terminal of the current switching switch 1141.

[0139] The first transistor T1 to the fifth transistor T5 mentioned above can be either an N-type transistor or a P-type transistor.

[0140] This application also provides a display panel, as shown in FIG8, which is a schematic diagram of the structure of a display panel provided in an embodiment of this application. The display panel includes a plurality of pixel driving circuits PX arranged in an array as provided in any embodiment of this application. Each pixel driving circuit PX is connected to m light-emitting units. Since the display panel provided in the embodiment of this application includes the pixel driving circuit provided in the embodiment of this application, it also has the same effect, and will not be described again here.

[0141] This application also provides a display device, which includes the display panel provided in the embodiments of this application. The display device can be a mobile phone, tablet computer, Moving Picture Experts Group Audio Layer III (MP3), MP4 player, smartwatch, smart helmet, video phone, personal digital assistant, or other wearable device. Since the display device provided in the embodiments of this application includes the display panel provided in the embodiments of this application, it also has the same effect, and will not be described again here.

[0142] It should be understood that the various processes shown above can be used to rearrange, add, or delete steps. For example, the multiple steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

Claims

1. A pixel driving circuit, comprising: At least one pulse width modulation module (11) is provided, the pulse width modulation module (11) includes k1 first data input terminals, each of the first data input terminals is configured to input one bit of grayscale data, the pulse width modulation module (11) is configured to output a pulse width modulation signal from the data output terminal of the pulse width modulation module (11) according to the grayscale data; the data output terminal of the pulse width modulation module (11) is configured to be connected to at least one light-emitting unit (13). At least k1 data read / write modules (14), each of the first data input terminals of the pulse width modulation module (11) is electrically connected to one of the data read / write modules (14), and k1 is the number of bits of the grayscale data; The data read / write module (14) includes a first data write unit (141), a first storage unit (142), a first data write-out unit (143), and a second storage unit (144). In the data read / write module (14) corresponding to the first data input terminal, the first data writing unit is configured to write one bit of the grayscale data into the corresponding first storage unit (142) in response to an external strobe signal; the first data writing unit (143) is configured to write the data stored in the first storage unit (142) into a first data input terminal of the pulse width modulation module (11) in response to a frame refresh signal; the second storage unit (144) is configured to maintain the potential of the first data input terminal of the pulse width modulation module (11).

2. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit includes: There are n pulse width modulation modules (11), each pulse width modulation module (11) further includes k2 second data input terminals, each second data input terminal is set to input one bit of address data within the block, and the pulse width modulation module (11) is also set to output internal gating signals from m internal gating output terminals of the pulse width modulation module (11) according to the address data within the block; n is greater than 1; Each of the pulse width modulation modules (11) corresponds to m pixel switches (12); among the m pixel switches (12) corresponding to each pulse width modulation module (11), the first end of each pixel switch (12) is electrically connected to the data output end of the corresponding pulse width modulation module (11), the control end of the m pixel switches (12) is electrically connected to the m internal gating output ends of the pulse width modulation module (11) one by one, and the second end of the pixel switch (12) is configured to connect to one of the light-emitting units (13). ； Each data read / write module (14) is connected to one of the data read / write modules (14) corresponding to each of the second data input terminals, and k2 is the number of bits of the address data in the block; In the data read / write module (14) corresponding to the second data input terminal, the first data writing unit (141) is configured to write one bit of the address data in the block to the corresponding first storage unit (142) in response to an external strobe signal; the first data writing unit (143) is configured to write the data of the first storage unit (142) to a second data input terminal of the pulse width modulation module (11) in response to a frame refresh signal; the second storage unit (144) is configured to maintain the potential of the second data input terminal of the pulse width modulation module (11).

3. The pixel driving circuit according to claim 2, wherein, The first end of the first data writing unit (141) is connected to one bit of the grayscale data or the block address data, the second end of the first data writing unit (141) is electrically connected to the first end of the first data writing unit (143), and the control end of the first data writing unit (141) is connected to the external strobe signal. The first end of the first storage unit (142) is electrically connected to the second end of the first data writing unit (141), and the second end of the first storage unit (142) is grounded; The second end of the first data writing unit (143) is electrically connected to the first data input end or the second data input end of the corresponding pulse width modulation module (11), and the control end of the first data writing unit (143) is connected to the frame refresh signal; the first end of the second storage unit (144) is electrically connected to the second end of the first data writing unit (143), and the second end of the second storage unit (144) is grounded.

4. The pixel driving circuit according to claim 3, wherein, The first data writing unit (141) includes a first transistor (T1), the first electrode of the first transistor (T1) serves as the first terminal of the first data writing unit (141), the second electrode of the first transistor (T1) serves as the second terminal of the first data writing unit (141), and the control electrode of the first transistor (T1) serves as the control terminal of the first data writing unit (141). The first storage unit (142) includes a first capacitor (C1), the first end of the first capacitor (C1) serves as the first end of the first storage unit (142), and the second end of the first capacitor (C1) serves as the second end of the first storage unit (142). The first data writing unit (143) includes a second transistor (T2), the first electrode of the second transistor (T2) serves as the first terminal of the first data writing unit (143), the second electrode of the second transistor (T2) serves as the second terminal of the first data writing unit (143), and the control electrode of the second transistor (T2) serves as the control terminal of the first data writing unit (143). The second storage unit (144) includes a second capacitor (C2), the first end of the second capacitor (C2) serves as the first end of the second storage unit (144), and the second end of the second capacitor (C2) serves as the second end of the second storage unit (144).

5. The pixel driving circuit according to claim 1 or 2, further comprising: Block address parsing module (15), the input terminal of the block address parsing module (15) is connected to the block address signal, the block address parsing module (15) is configured to parse the block address signal; when the block address signal matches the address of the pixel driving circuit, the external strobe signal is generated.

6. The pixel driving circuit according to claim 5 further includes: Energy-saving control module (16), wherein the energy-saving control module (16) is connected to the external strobe signal and the frame refresh signal; The energy-saving control module (16) is configured to enter a first state in response to the external strobe signal, and output a start signal when the frame refresh signal is received in the first state; the energy-saving control module (16) is also configured to enter a second state when the external strobe signal corresponding to the next frame is not received in the current frame, and output a shutdown signal in response to the frame refresh signal of the next frame in the second state. The start control terminal of the pulse width modulation module (11) is connected to the start signal or the turn-off signal. The pulse width modulation module (11) is configured to start in response to the start signal and turn off in response to the turn-off signal.

7. The pixel driving circuit according to claim 6, wherein, The energy-saving control module (16) includes an enabling unit (161) and a start-up control unit (162). The enabling unit (161) is connected to the external strobe signal and the frame refresh signal. The enabling unit (161) is configured to set the enabling signal to a first level in response to the pulse end edge of the external strobe signal and to set the enabling signal to a second level in response to the pulse end edge of the frame refresh signal. The startup control unit (162) receives the enable signal and the frame refresh signal. The startup control unit (162) is configured to set the output signal to the first level at a preset time during the pulse time of the frame refresh signal when the enable signal is at the first level, in order to form the startup signal; and to set the output signal to the second level at a preset time during the pulse time of the frame refresh signal when the enable signal is at the second level, in order to form the shutdown signal.

8. The pixel driving circuit according to claim 2, wherein, The pulse width modulation module (11) includes: a counter (111), a comparator (112), an intra-block address decoding unit (113), a current generation unit (114), and a light-emitting control switch (115). The counter (111) is connected to the frame refresh signal and counts according to the frame refresh signal; the clock terminal of the counter (111) is connected to a preset clock signal; The comparator (112) includes k1 first input terminals, the first input terminals of the comparator (112) serve as the first data input terminals of the pulse width modulation module (11); the second input terminal of the comparator (112) is electrically connected to the output terminal of the counter (111); the output terminal of the comparator (112) is electrically connected to the control terminal of the light-emitting control switch (115). The first end of the light-emitting control switch (115) is electrically connected to the current generating unit (114), and the second end of the light-emitting control switch (115) is electrically connected to the data output end of the pulse width modulation module (11). The intra-block address decoding unit (113) includes k2 input terminals. The input terminals of the intra-block address decoding unit (113) serve as the second data input terminals of the pulse width modulation module (11). The m output terminals of the intra-block address decoding unit (113) are electrically connected to the m internal gating output terminals of the pulse width modulation module (11) in a one-to-one correspondence. The intra-block address decoding unit (113) is configured to generate the internal gating signal based on the intra-block address data.

9. The pixel driving circuit according to claim 8, wherein, The current generating unit (114) includes a first current source (I1), a second current source (I2), and a current switching switch (1141). The output terminal of the first current source (I1) is electrically connected to the first terminal of the current switching switch (1141), the second terminal of the current switching switch (1141) is electrically connected to the first terminal of the light-emitting control switch (115), and the control terminal of the current switching switch (1141) is electrically connected to the third data input terminal of the pulse width modulation module (11). The second current source (I2) is electrically connected to the first terminal of the light-emitting control switch (115); the output current of the first current source (I1) is different from the output current of the second current source (I2); The pixel driving circuit includes Each of the data read / write modules (14) is connected to a corresponding third data input terminal; in the data read / write modules (14) connected to the third data input terminal, the first data writing unit (141) is configured to write current selection data to the corresponding first storage unit (142) in response to an external strobe signal; the first data writing unit (143) is configured to write the data of the first storage unit (142) to the third data input terminal of the pulse width modulation module (11) in response to a frame refresh signal; the second storage unit (144) is configured to maintain the potential of the third data input terminal of the pulse width modulation module (11).

10. The pixel driving circuit according to claim 8 further includes a clock regeneration module (17). The clock regeneration module (17) is connected to q clock signals with a preset phase difference at its input terminal; The clock regeneration module (17) is configured to encode according to the state of the q clock signals, and generate a number decoder representing the number of types of the encoding according to the number of types of the encoding; The least significant bit of the quantity decoded is used as the preset clock signal.

11. A display panel comprising a plurality of pixel driving circuits arranged in an array as described in any one of claims 1-10; The display panel also includes multiple arrayed light-emitting units (13). Each pixel driving circuit is connected to m light-emitting units (13).

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