Flash memory management method and flash memory storage apparatus

Abstract

Provided in the present invention are a flash memory management method and a flash memory storage apparatus. The method is applied to a rewritable non-volatile flash memory module comprising a plurality of flash memory sub-modules. The method comprises: respectively acquiring a plurality of load values of a plurality of command queues corresponding to a plurality of flash memory sub-modules; on the basis of the plurality of load values, selecting a first command queue from among the plurality of command queues, wherein the first command queue corresponds to a first flash memory sub-module among the plurality of flash memory sub-modules; and pushing, into the first command queue, a first command to be processed among commands to be processed that corresponds to the first flash memory sub-module. In this way, command push probabilities of flash memory sub-modules are balanced on the basis of load values, thereby solving the problem of load imbalance caused by uneven distribution of reclaimed data or a read-write conflict in a host.

Description

Memory management methods and memory storage devices Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a memory management method and a memory storage device. Background Technology

[0002] Flash memory is a type of non-volatile memory widely used in electronic devices such as memory cards, solid-state drives, and portable multimedia players.

[0003] Currently, memory typically employs multi-channel, multi-die architecture and interleaved read / write modes to improve overall memory throughput. However, in certain scenarios, uneven load distribution among multiple dies may occur, thereby affecting the efficiency of flash interleave. Summary of the Invention

[0004] The present invention provides a single-buffered queue memory management method and memory storage device, which balances the command push probability of each memory sub-module by load value, thereby solving the problem of load imbalance caused by uneven distribution of garbage collection data or conflict with host read and write in garbage collection scenarios.

[0005] In an exemplary embodiment of the present invention, a memory management method is provided for a rewritable non-volatile memory module, the rewritable non-volatile memory module including multiple memory sub-modules, comprising: acquiring multiple load values ​​of multiple command queues corresponding to the multiple memory sub-modules respectively; selecting a first command queue from the multiple command queues according to the multiple load values, wherein the first command queue corresponds to a first memory sub-module; and pushing a first command to be processed corresponding to the first memory sub-module from the commands to be processed to the first command queue.

[0006] In an exemplary embodiment of the present invention, a memory storage device is provided, including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is electrically connected to a host system. The rewritable non-volatile memory module includes multiple memory sub-modules. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to acquire multiple load values ​​for multiple command queues corresponding to the multiple memory sub-modules. The memory control circuit unit is used to select a first command queue from the multiple command queues based on the multiple load values, wherein the first command queue corresponds to a first memory sub-module. The memory control circuit unit is used to push a first command to be processed corresponding to the first memory sub-module from the commands to be processed to the first command queue.

[0007] In an exemplary embodiment of the present invention, a memory control circuit unit is provided for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is electrically connected to a host system. The memory interface is electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple memory sub-modules. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used to acquire multiple load values ​​of multiple command queues corresponding to the multiple memory sub-modules. The memory management circuit is used to select a first command queue from the multiple command queues based on the multiple load values, wherein the first command queue corresponds to a first memory sub-module among the multiple memory sub-modules. The memory management circuit is used to push a first command to be processed corresponding to the first memory sub-module to the first command queue.

[0008] Based on the above, the present invention provides a memory management method and a memory storage device, which can determine the priority of pushing commands to the command queue by using the time required to execute all commands in each command queue as the initial load value of the corresponding command queue. The command queue with a smaller load will get more command push opportunities, thereby ensuring the load balance of all command queues. Thus, flash interleave is achieved under the condition of load balance in each command queue, effectively improving the throughput and efficiency of data processing.

[0009] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0011] Figure 1 is a schematic diagram of a host system, memory storage device and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0012] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to another exemplary embodiment of the present invention;

[0013] Figure 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

[0014] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0015] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0016] Figure 6 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0017] Figure 7 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention;

[0018] Figure 8 is a schematic diagram illustrating the selection of a command queue based on a load value to push commands according to an exemplary embodiment of the present invention. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0021] The ordinal numbers used in the specification and claims of this application, such as "first" and "second," are used to modify elements. These terms do not inherently imply or represent any prior ordinal number for that element, nor do they represent the order of one element with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one named element from another with the same name. The claims and specification may not use the same terminology; therefore, a first element in the specification may be a second element in the claims. It should be understood that the following embodiments can be implemented by substituting, recombining, or combining technical features from several different embodiments without departing from the spirit of this disclosure to complete other embodiments.

[0022] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). Typically, a memory storage device is used in conjunction with a host system to enable the host system to write data to or read data from the memory storage device.

[0023] Figure 1 is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, memory storage device, and I / O device according to another exemplary embodiment of the present invention.

[0024] Referring to Figures 1 and 2, the host system 11 generally includes a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 are all electrically connected to the system bus 110.

[0025] In this exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 is electrically connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0026] In this exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be electrically connected to the memory storage device 10 via wired or wireless means. The memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be electrically connected to various I / O devices such as the Global Positioning System (GPS) module 205, network adapter 206, wireless transmission device 207, keyboard 208, screen 209, and speaker 210 via the system bus 110. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 via the wireless transmission device 207.

[0027] In one exemplary embodiment, the host system mentioned is any system that can substantially cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, FIG3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Referring to FIG3, in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, camcorder, communication device, audio player, video player, or tablet computer, and the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded storage devices that directly electrically connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0028] Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0029] Referring to Figure 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

[0030] The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11. In this exemplary embodiment, the connection interface unit 402 conforms to the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the Non-Volatile Memory Express (NVM express) interface standard. Specifically, the NVM express standard is a protocol for communication between a host system and a memory device. It defines the cache interface, instruction set, and function set between the controller of the memory storage device and the operating system of the host system, and promotes the data access speed and data transfer rate of memory storage devices with PCIe interface as the primary interface by optimizing the interface standard of the memory storage device. However, in another exemplary embodiment, the connection interface unit 402 may also conform to other suitable standards. In addition, the connection interface unit 402 may be packaged in a chip with the memory control circuit unit 404, or the connection interface unit 402 may be disposed outside a chip containing the memory control circuit unit 404.

[0031] The memory control circuit unit 404 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11.

[0032] The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single-level cell (SLC) NAND memory module (i.e., a memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND memory module (i.e., a memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND memory module (i.e., a memory module that can store 3 bits in one memory cell), other memory modules, or other memory modules with the same characteristics.

[0033] Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving one or more bits stored in that memory cell.

[0034] In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 constitute multiple physical programming units, and these physical programming units constitute multiple physical erase units. Specifically, memory cells on the same character line form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same character line can be classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0035] In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units typically include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of storage units that are erased. For example, the physical erase unit is a physical block.

[0036] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0037] Please refer to Figure 5. The memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

[0038] The memory management circuit 502 controls the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

[0039] In this exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware form. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are written to the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0040] In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 406 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 502 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 406 into the random access memory of the memory management circuit 502. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0041] Furthermore, in another exemplary embodiment, the control instructions for the memory management circuit 502 can also be implemented in hardware. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are electrically connected to the microcontroller. The memory cell management circuit manages the memory cells or groups thereof of the rewritable non-volatile memory module 406. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasure circuit issues an erasure command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit processes data to be written to the rewritable non-volatile memory module 406 and data to be read from the rewritable non-volatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or scripts and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 502 may also issue other types of command sequences to the rewritable non-volatile memory module 406 to instruct it to perform corresponding operations.

[0042] The host interface 504 is electrically connected to the memory management circuit 502 and is used to receive and identify instructions and data transmitted by the host system 11. That is, instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto; the host interface 504 may also be compatible with PATA, IEEE 1394, SATA, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0043] Memory interface 506 is electrically connected to memory management circuitry 502 and is used to access rewritable non-volatile memory module 406. That is, data to be written to rewritable non-volatile memory module 406 is converted by memory interface 506 into a format acceptable to rewritable non-volatile memory module 406. Specifically, when memory management circuitry 502 needs to access rewritable non-volatile memory module 406, memory interface 506 transmits a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by memory management circuitry 502 and transmitted to rewritable non-volatile memory module 406 via memory interface 506. These instruction sequences may include one or more signals or data on a bus. These signals or data may include scripts or program code. For example, the read instruction sequence may include information such as the identification code to be read and the memory address.

[0044] In one exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

[0045] The error checking and correction circuit 508 is electrically connected to the memory management circuit 502 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 406. Subsequently, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and the error checking and correction circuit 508 performs error checking and correction operations on the read data based on this error correcting code and / or error detecting code.

[0046] Buffer memory 510 is electrically connected to memory management circuit 502 and is used to temporarily store data and instructions from host system 11 or data from rewritable non-volatile memory module 406. Power management circuit 512 is electrically connected to memory management circuit 502 and is used to control the power supply of memory storage device 10.

[0047] Figure 6 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0048] This application uses eight memory submodules as an example for illustration. Referring to Figure 6, the rewritable non-volatile memory module 406 includes a first memory submodule 310, a second memory submodule 320, a third memory submodule 330, a fourth memory submodule 340, a fifth memory submodule 350, a sixth memory submodule 360, a seventh memory submodule 370, and an eighth memory submodule 380. For example, the first, second, third, fourth, fifth, sixth, seventh, and eighth memory submodules 310, 320, 330, 340, 350, 360, 370, and 380 are memory dies. The first memory submodule 310 has physical erase units 410(0) to 410(N). The second memory submodule 320 has physical erase units 420(0) to 420(N). The third memory submodule 330 has physical erase units 430(0) to 430(N). The fourth memory submodule 340 has physical erase units 440(0) to 440(N). The fifth memory submodule 350 has physical erase units 450(0) to 450(N). The sixth memory submodule 360 ​​has physical erase units 460(0) to 460(N). The seventh memory submodule 370 has physical erase units 470(0) to 470(N). The eighth memory submodule 380 has physical erase units 480(0) to 480(N).

[0049] For example, the first, second, third, fourth, fifth, sixth, seventh, and eighth memory submodules 310, 320, 330, 340, 350, 360, 370, and 380 are electrically connected to the memory control circuit unit 404 via independent data buses 316, 326, 336, 346, 356, 366, 376, and 386, respectively. Based on this, the memory management circuit 502 can write data to the first, second, third, fourth, fifth, sixth, seventh, and eighth memory submodules 310, 320, 330, 340, 350, 360, 370, and 380 in a parallel manner via data buses 316, 326, 336, 346, 356, 366, 376, and 386.

[0050] However, it must be understood that in another exemplary embodiment of the present invention, the first, second, third, fourth, fifth, sixth, seventh, and eighth memory submodules 310, 320, 330, 340, 350, 360, 370, and 380 may also be electrically connected to the memory control circuit unit 404 via only one data bus. Here, the memory management circuit 502 can write data to the first, second, third, fourth, fifth, sixth, seventh, and eighth memory submodules 310, 320, 330, 340, 350, 360, 370, and 380 in an interleaved manner via a single data bus.

[0051] It is worth noting that although the exemplary embodiment of the present invention is described using a rewritable non-volatile memory module 406 comprising eight memory sub-modules as an example, the present invention is not limited thereto. In other embodiments, the rewritable non-volatile memory module 406 may also comprise two, four, six, or ten memory sub-modules.

[0052] In traditional architectures, each memory submodule corresponds to a command queue, and the scheduling algorithm between command queues is usually a round-robin algorithm. When the load on each command queue is relatively balanced, the round-robin algorithm can effectively achieve flash interleave. However, in single-buffered architectures, where commands are pushed to the command queue sequentially according to the order they are issued by the host, certain scenarios, such as conflicts between garbage collection (GC) operations and host system read / write operations, can lead to a situation where one memory submodule is blocked for an extended period. Commands for other memory submodules, issued later, cannot be pushed to an idle command queue and therefore cannot be executed. In this case, flash interleave efficiency will be significantly reduced.

[0053] For example, when performing a GC operation, it is necessary to read reclaimed data from 8 memory sub-modules. If the amount of reclaimed data distributed in each memory sub-module varies greatly, if the commands are pushed in the traditional order of command generation, it is possible that one memory sub-module is already full while other memory sub-modules are always idle. They can only receive and execute the corresponding command when the command push order reaches the corresponding command of that memory sub-module, thus causing memory resources to be wasted due to unnecessary waiting.

[0054] Alternatively, if GC operations require reading reclaimed data from 8 memory sub-modules, and host read / write operations require access to a specific memory sub-module, and if the traditional method of pushing commands to the command queue sequentially according to the order of host commands is followed, the read commands may be blocked by the host system's read / write operations during GC operations, thereby reducing the overall garbage collection efficiency.

[0055] If the commands mentioned above are pushed into the command queue in the order they are sent or in the order they are issued by the host, it is not conducive to the overall command execution efficiency, resulting in excessively long command waiting times. Therefore, this solution provides a memory management method to address the above problems.

[0056] The memory management method of the present invention will be described in detail below using a rewritable non-volatile memory module 406 comprising eight memory sub-modules as an example, and in conjunction with the embodiments shown in Figures 7 and 8. The various processes of this method can be adjusted according to the implementation situation, and are not limited thereto.

[0057] Figure 7 is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Figure 8 is a schematic diagram illustrating the selection of a command queue based on a load value to push commands according to an exemplary embodiment of the present invention.

[0058] As shown in Figures 7 and 8, in step S701, the memory management circuit 502 can put the command to be processed into the preprocessing command pool 800.

[0059] In one embodiment, the commands to be processed may include read commands and write instructions issued by the host system 11 for a certain memory submodule, as well as read commands issued by the memory management circuit 502 to read the reclaimed data of each memory submodule when performing GC operations, etc., and the present invention is not limited thereto. Moreover, the state of the preprocessing command pool 800 is updated in real time, that is, new commands to be processed are added or commands to be processed in the preprocessing command pool 800 are removed.

[0060] As shown in Figure 8, the pending commands may include pending commands corresponding to each memory submodule. For example, the first pending command 801 in the preprocessing command pool 800 corresponds to the first memory submodule 310, the second pending command 802 corresponds to the second memory submodule 320, the third pending command 803 corresponds to the third memory submodule 330, the fourth pending command 804 corresponds to the fourth memory submodule 340, the fifth pending command 805 corresponds to the fifth memory submodule 350, the sixth pending command 806 corresponds to the sixth memory submodule 360, the seventh pending command 807 corresponds to the seventh memory submodule 370, and the eighth pending command 808 corresponds to the eighth memory submodule 380.

[0061] In step S702, the memory management circuit 502 obtains the initial load value of each command queue corresponding to each memory submodule.

[0062] In one embodiment, commands to be processed can be classified into read commands, write commands, and erase commands based on their command type. Specifically, since the execution time of commands of different types is different, weights can be set according to the proportion of the execution time of each command type, or different priority weights can be set for different types of commands. In practical applications, the settings can be made according to specific needs, and no specific limitation is made here.

[0063] The memory management circuit 502 can obtain the execution completion time of each command based on the command type of each command included in each command queue, and sum the execution completion times of each command according to the weight of each command type to use as the load value or initial load value of each command queue.

[0064] The following explanation uses the calculation of the load value or initial load value of a command queue (first command queue and second command queue) as an example. A similar approach can be applied to other command queues.

[0065] The memory management circuit 502 can obtain the load value or initial load value of a command queue using the following formula 1: Ln-1=k1×Tread+k2×Tprog+k3×Terase

[0066] Where Ln-1 is the load value or initial load value of the nth command queue, k1 is the number of read commands in the nth command queue, k2 is the number of write commands in the nth command queue, k3 is the number of erase commands in the nth command queue, Tread is the execution completion time of a read command, Tprog is the execution completion time of a write command, and Terase is the execution completion time of an erase command. In this calculation, the priority of each command type is treated as the same. In practical applications, the corresponding priority weights can be set according to specific needs.

[0067] In one embodiment, if the first command queue includes two read commands, one write command, and one erase command, the execution completion time of each command is summed according to the above formula 1 to serve as the load value or initial load value of the first command queue: L0 = 2 × Tread + 1 × Tprog + 1 × Terase.

[0068] In another embodiment, if the second command queue includes one read command and one write command, the execution completion time of each command is summed according to Formula 1 above to serve as the load value or initial load value of the second command queue: L1 = 1 × Tread + 1 × Tprog.

[0069] Therefore, the memory management circuit 502 can obtain the initial load values ​​L0, L1, L2, L3, L4, L5, L6, and L7 corresponding to the first, second, third, fourth, fifth, sixth, seventh, and eighth command queues, respectively, as shown in Figure 8, through the above formula 1.

[0070] In step S703, the memory management circuit 502 can sort the initial load values ​​of each command queue according to the order of load values ​​from smallest to largest.

[0071] In one embodiment, the memory management circuit 502 can sort the initial load values ​​of each command queue in ascending order as L5, L1, L7, L0, L2, L4, L3, L6, with L5 having the smallest load value.

[0072] In step S704, the memory management circuit 502 selects the command queue with the smallest load value from each command queue as the target command queue for pushing the command to be processed.

[0073] In one embodiment, the memory management circuit 502 selects the target command queue with the smallest load value (L5) from each command queue, and this target command queue is the sixth command queue corresponding to the sixth memory submodule 360.

[0074] In step S705, the memory management circuit 502 can determine whether the target command queue (i.e., the sixth command queue) is not full and whether there is a command to be processed (i.e., the sixth processing command 806) corresponding to the target command queue in the preprocessing command pool 800.

[0075] Furthermore, if the target command queue is full, it indicates that the current memory submodule's load value has reached its maximum. Unless at least one command is dequeued from the target command queue, no pending commands can be pushed to the target command queue.

[0076] In one embodiment, the memory management circuit 502 can determine a threshold number of commands that the target command queue corresponding to the memory submodule can include based on the model number of the memory submodule. When the number of commands in the target command queue is greater than or equal to the threshold, the memory management circuit 502 can determine that the target command queue is full; when the number of commands in the target command queue is less than the threshold, the memory management circuit 502 can determine that the target command queue is not full. This invention is not limited thereto.

[0077] In one embodiment, the threshold is related to the model of this memory submodule.

[0078] When the target command queue is not full and there is a command to be processed corresponding to the target command queue in the preprocessing command pool 800, in step S706, the memory management circuit 502 can push the command to be processed corresponding to the target command queue to the target command queue and update the load value of the target command queue.

[0079] In this embodiment, the target command queue is the sixth command queue. If the sixth command queue is not full and there is a sixth command to be processed 806 corresponding to the sixth command queue in the preprocessing command pool 800, the memory management circuit 502 can push the sixth command to be processed 806 to the sixth command queue and update the load value of the sixth command queue. At this time, the updated load value L5′ corresponding to the sixth command queue is L5′=L5+1×T, where T is the execution completion time of the sixth command to be processed 806.

[0080] The above method determines the load value of each command queue corresponding to each memory submodule by the command execution time, selects the target command queue corresponding to the memory submodule for priority execution based on the load value, and pushes the command to the target command queue, thereby achieving a relatively balanced load for each command queue and improving the overall command processing efficiency.

[0081] In step S707, the memory management circuit 502 determines whether the preprocessing command pool 800 is empty.

[0082] The process ends when the preprocessing command pool 800 is empty, meaning there are no commands to be processed in the preprocessing command pool 800.

[0083] When the preprocessing command pool 800 is not empty, that is, there are still commands to be processed in the preprocessing command pool 800, the process returns to step S703. The memory management circuit 502 can sort the updated load values ​​of the target command queue and the initial load values ​​of each command queue other than the target command queue according to the order of load values ​​from small to large, and continue to execute the subsequent process of reselecting the target command queue to push the commands to be processed until each command queue is full or the preprocessing command pool 800 is empty.

[0084] In this embodiment, if the target command queue is full and there is no command to be processed corresponding to the target command queue, or if the memory submodule corresponding to the target command queue does not have a corresponding GC operation, in step S708, the memory management circuit 502 removes the target command queue from the command queue and removes the load value corresponding to the target command queue from the load value.

[0085] In one embodiment, if the target command queue is full and there is no command to be processed corresponding to the target command queue in the preprocessing command pool 800 (for example, there is no garbage collection operation in the target memory submodule corresponding to the target command queue), the above steps S704, S705 and S706 are performed on the remaining memory submodules other than the target memory submodule, so as to ensure that the load of the command queue corresponding to each memory submodule is in a relatively balanced state.

[0086] After removing the target command queue from the command queue and removing the load value corresponding to the target command queue from the load value, in step S709, the memory management circuit 502 determines whether there is a command queue to be selected.

[0087] If the memory management circuit 502 determines that there are still command queues to be selected, it returns to step S704 and continues to select the command queue with the smallest load value from each command queue.

[0088] The above-mentioned method of pushing pending commands to the target command queue that is not full and has the smallest load value helps to ensure that the load of each command queue corresponding to each memory submodule is relatively balanced. This not only improves the overall command processing performance, but also effectively avoids the situation where read commands are blocked by host read and write operations when performing GC operations on the same memory submodule at the same time, thereby reducing the overall garbage collection efficiency. This effectively solves the problem of load imbalance caused by uneven distribution of garbage collection data or conflict with host read and write operations.

[0089] If the memory management circuit 502 determines that there is no command queue to be selected, it means that each command queue is full, or the preprocessing command pool 800 is empty, and then the process ends.

[0090] Based on the above, the present invention provides a memory management method and a memory storage device, which can use the time required to execute all commands in each command queue as the load value of the corresponding command queue, thereby determining the priority of pushing commands to the command queue based on the load value of each command queue. The command queue with a smaller load will get more command push opportunities, thereby ensuring the load balance of all command queues. Thus, flash interleave is achieved under the condition of load balance of each command queue, effectively improving the throughput and efficiency of data processing.

[0091] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising multiple memory sub-modules, characterized in that, include: Obtain multiple load values ​​corresponding to multiple command queues of the multiple memory submodules respectively; A first command queue is selected from the plurality of command queues based on the plurality of load values, wherein the first command queue corresponds to a first memory submodule; as well as The first command to be processed, corresponding to the first memory submodule, is pushed to the first command queue.

2. The memory management method according to claim 1, characterized in that, The step of obtaining the multiple load values ​​corresponding to the multiple command queues of the multiple memory submodules further includes: The execution completion time of each command is obtained based on the command type of each command in each command queue; The execution completion times of each command are summed to form the load value for each command queue.

3. The memory management method according to claim 1, characterized in that, The step of selecting the first command queue from the plurality of command queues based on the plurality of load values, wherein the first command queue corresponds to the first memory submodule among the plurality of memory submodules, further includes: The load values ​​are sorted in ascending order to obtain a sorting result; and The first command queue is selected from the plurality of command queues according to the sorting result, wherein the first load value corresponding to the first command queue is the smallest.

4. The memory management method according to claim 3, characterized in that, After the step of selecting the first command queue from the plurality of command queues according to the sorting result, the method further includes: Determine whether the first command queue is not full and whether there is a first command to be processed in the pending commands that corresponds to the first command queue; When the first command queue is not full and there is a first command to be processed in the pending commands that corresponds to the first command queue, the first command to be processed is pushed into the first command queue.

5. The memory management method according to claim 3, characterized in that, After the step of selecting the first command queue from the plurality of command queues according to the sorting result, the method further includes: Determine whether the first command queue is not full and whether there is a first command to be processed in the pending commands that corresponds to the first command queue; When the first command queue is full, and / or there is no first command to be processed corresponding to the first command queue among the pending commands, the first command queue is removed from the plurality of command queues, and the first load value corresponding to the first command queue is removed from the plurality of load values.

6. The memory management method according to claim 4 or 5, characterized in that, The step of determining whether the first command queue is not full and whether there is a first command to be processed corresponding to the first command queue among the pending commands further includes: Whether the first command queue is not full is determined by whether the number of commands in the first command queue is less than a threshold.

7. The memory management method according to claim 1, characterized in that, The method further includes: After pushing the first command to be processed to the first command queue, update the first load value corresponding to the first command queue.

8. The memory management method according to claim 1, characterized in that, The commands to be processed include commands corresponding to the plurality of memory sub-modules respectively.

9. A memory storage device, characterized in that, include: A connection interface unit for electrically connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple memory sub-modules; as well as The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to acquire multiple load values ​​corresponding to multiple command queues of the multiple memory submodules. The memory control circuit unit is configured to select a first command queue from the plurality of command queues based on the plurality of load values, wherein the first command queue corresponds to a first memory submodule. The memory control circuit unit is used to push the first command to be processed, which corresponds to the first memory submodule, into the first command queue.

10. The memory storage device according to claim 9, characterized in that, In the operation of the memory control circuit unit acquiring the multiple load values ​​corresponding to the multiple command queues of the multiple memory sub-modules, the method further includes: The memory control circuit unit is further configured to obtain the execution completion time of each command based on the command type of each command in each command queue, and sum the execution completion times of each command to obtain the load value of each command queue.

11. The memory storage device according to claim 9, characterized in that, In the process of the memory control circuit unit selecting the first command queue from the plurality of command queues based on the plurality of load values, wherein the first command queue corresponds to the operation of the first memory sub-module among the plurality of memory sub-modules, the method further includes: The memory control circuit unit is further configured to sort the plurality of load values ​​in ascending order of load value, and obtain a sorting result. The memory control circuit unit is further configured to select the first command queue from the plurality of command queues according to the sorting result, wherein the first load value corresponding to the first command queue is the smallest.

12. The memory storage device according to claim 11, characterized in that, After the memory control circuit unit selects the first command queue from the plurality of command queues according to the sorting result, The memory control circuit unit is further configured to determine whether the first command queue is not full and whether there is a first command to be processed corresponding to the first command queue among the commands to be processed; When the first command queue is not full and there is a first command to be processed in the pending commands that corresponds to the first command queue, the memory control circuit unit is further used to push the first command to be processed into the first command queue.

13. The memory storage device according to claim 11, characterized in that, After the memory control circuit unit selects the first command queue from the plurality of command queues according to the sorting result, The memory control circuit unit is further configured to determine whether the first command queue is not full and whether there is a first command to be processed corresponding to the first command queue among the commands to be processed. When the first command queue is full, and / or there is no first command to be processed corresponding to the first command queue among the pending commands, the memory control circuit unit is further configured to remove the first command queue from the plurality of command queues, and remove the first load value corresponding to the first command queue from the plurality of load values.

14. The memory storage device according to claim 12 or 13, characterized in that, In the process of the memory control circuit unit determining whether the first command queue is not full and whether there is an operation of the first command to be processed corresponding to the first command queue, the method further includes: The memory control circuit unit is also used to determine whether the first command queue is not full based on whether the number of commands in the first command queue is less than a threshold.

15. The memory storage device according to claim 9, characterized in that, After the memory control circuit unit pushes the first command to be processed to the first command queue, the memory control circuit unit is also used to update the first load value corresponding to the first command queue.

16. The memory storage device according to claim 9, characterized in that, The commands to be processed include commands corresponding to the plurality of memory sub-modules respectively.

Images