Transaction processing method, storage medium, electronic device, and product

Abstract

Embodiments of the present disclosure provide a transaction processing method, a storage medium, an electronic device, and a product. The method comprises: parsing a received transaction request, determining the type and priority of the transaction request, and when there is an unused consistency queue resource, on the basis of the type and priority of the transaction request, scheduling a transaction to enter a corresponding processing flow; and performing protocol processing on a response and data returned after the transaction enters the corresponding processing flow, so that the response and the data conform to a consistency protocol.

Description

A transaction processing method, storage medium, electronic device, and product.

[0001] Relevant publicly available cross-references

[0002] This disclosure is based on Chinese Patent Publication 2025101236147, filed on January 24, 2025, entitled "A Transaction Processing Method, Storage Medium, Electronic Device and Product", and claims priority to that patent disclosure. All of its disclosed contents are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of communications, and more specifically, to a transaction processing method, storage medium, electronic device, and product. Background Technology

[0004] As semiconductor technology continues to advance, the number of processor cores integrated on chips is constantly increasing. Traditional bus or point-to-point communication structures are gradually showing shortcomings in bandwidth, power consumption, latency, and scalability, as well as difficulties in synchronizing global clocks, limited address space, and inability to support multi-core parallel communication. To solve these problems, a new method for communication between multi-core processors is needed. Network on Chip (NOC) has emerged as a solution. It is a new communication method for on-chip systems, and its core idea is to apply computer network technology to chip design to solve the interconnection and communication problems between multi-core processor systems. Furthermore, with the development of semiconductor manufacturing processes, the performance of processors and main memory is constantly improving. However, the improvement in main memory access speed lags behind the improvement in processor execution speed, resulting in an increasingly severe speed gap. Faced with this problem, cache memory has been given a crucial role and has undergone significant development. Maintaining cache consistency between different processors has become an essential issue, as cache consistency performance affects processor performance. Therefore, when designing a consistent interconnect bus, efficient scheduling and processing of all consistent transactions is also beneficial to improving cache consistency performance.

[0005] In related technologies, consistency queue management mechanisms often lack the ability to process transaction requests in a fine-grained manner. They cannot effectively distinguish between different types of transaction requests (such as read requests, write requests, data updates, etc.) and their priorities, resulting in uneven resource allocation. High-priority transactions may be blocked by low-priority transactions, further reducing the system's response speed and overall performance. Summary of the Invention

[0006] This disclosure provides a transaction processing method, a storage medium, an electronic device, and a product.

[0007] According to one embodiment of this disclosure, a transaction processing method is provided, comprising: parsing a received transaction request, determining the type and priority of the transaction request, and, if there are unused consistency queue resources, scheduling the transaction into the corresponding processing flow according to the type and priority of the transaction request; and performing protocol processing on the response and data returned after the transaction enters the corresponding processing flow, so that the response and data conform to the consistency protocol.

[0008] According to yet another embodiment of this disclosure, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0009] According to yet another embodiment of this disclosure, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0010] According to yet another embodiment of this disclosure, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps in any of the above method embodiments. Attached Figure Description

[0011] Figure 1 is a hardware structure block diagram of a computer terminal for a transaction processing method according to an embodiment of the present disclosure;

[0012] Figure 2 is a flowchart of a transaction processing method according to an embodiment of the present disclosure;

[0013] Figure 3 is a structural block diagram of a transaction processing apparatus according to an embodiment of the present disclosure;

[0014] Figure 4 is a structural block diagram of a transaction processing apparatus according to another embodiment of the present disclosure;

[0015] Figure 5 is a structural block diagram of a transaction processing apparatus according to yet another embodiment of the present disclosure;

[0016] Figure 6 is a structural block diagram of a transaction processing apparatus according to another embodiment of the present disclosure. Detailed Implementation

[0017] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings and examples.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0019] The method embodiments provided in this disclosure can be executed in a mobile terminal, computer terminal, or similar computing device. Taking running on a computer terminal as an example, FIG1 is a hardware structure block diagram of the computer terminal running in the method embodiments of this disclosure. As shown in FIG1, the computer terminal may include one or more (only one is shown in FIG1) processors 102 (processor 102 may include, but is not limited to, processing devices such as microprocessors MCUs or programmable logic devices FPGAs) and a memory 104 configured to store data. The computer terminal may also include a transmission device 106 configured for communication functions and an input / output device 108. Those skilled in the art will understand that the structure shown in FIG1 is only illustrative and does not limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG1, or have a different configuration than shown in FIG1.

[0020] The memory 104 may be configured to store computer programs, such as application software programs and modules, like the computer program corresponding to the transaction processing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, thereby implementing the aforementioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0021] The transmission device 106 is configured to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module configured to communicate with the Internet wirelessly.

[0022] This embodiment provides a transaction processing method running on the aforementioned computer terminal. Figure 2 is a flowchart of the transaction processing method according to an embodiment of this disclosure. As shown in Figure 2, the process includes the following steps:

[0023] Step S202: Parse the received transaction request, determine the type and priority of the transaction request, and if there are unused consistency queue resources, schedule the transaction into the corresponding processing flow according to the type and priority of the transaction request.

[0024] In an exemplary embodiment of this disclosure, scheduling a transaction into a corresponding processing flow according to the type and priority of the transaction request includes: determining a scheduling signal for the transaction request according to the type and priority of the transaction request, sending the scheduling signal to a consistency queue and a request pipeline, so that the consistency queue allocates corresponding resources to the transaction according to the scheduling signal, and the request pipeline controls the execution of the transaction according to the scheduling signal; wherein the scheduling signal allocates resources to the consistency queue and controls the instructions of the request pipeline.

[0025] It should be noted that the types of transaction requests include at least one of the following: read request, write request, data update request, status query request, replacement request, listen request, L3 fill request, and arbitration request.

[0026] Read requests are the most common type of transaction. A read request is sent when a processor needs to access data in a cache line; a write request is sent when a processor performs a write operation on a cache line; a listen response is a response to a listen request issued by another processor; and an L3 Fill request is sent when an L3 Cache needs to be filled from external memory.

[0027] In an exemplary embodiment of this disclosure, before parsing the received transaction request, the method further includes: checking the current queue resource status to determine if there are available resources for receiving new transactions.

[0028] By pre-checking the queue resource status, the system can avoid accepting new transaction requests when resources are insufficient, thereby preventing over-allocation of resources and unnecessary waiting, and improving the utilization of queue resources. Filtering out transaction requests that cannot be processed immediately during the resource check phase can effectively reduce latency caused by resource contention and avoid congestion problems caused by queue overflow, thus improving the system's response speed and throughput.

[0029] Step S204: Perform protocol processing on the response and data returned after the transaction enters the corresponding processing flow, so that the response and data conform to the consistency protocol.

[0030] In an exemplary embodiment of this disclosure, protocol processing is performed on the response and data returned after a transaction enters the corresponding processing flow, including: receiving the response and data from the processing flow, comparing the response and data with a consistency protocol to determine the legality of the response and data, and updating and processing the response and data according to the consistency protocol.

[0031] During the processing of transaction requests, a series of responses and data are generated. Upon receiving these responses and data, the system compares this information with the requirements of the consistency protocol to check whether they comply with the state transition and data propagation rules stipulated in the protocol. For example, the protocol might stipulate that after a write operation, all other cached data must be marked as invalid or in a shared state to reflect the latest data modification. If the responses and data fully comply with the consistency protocol requirements, they are considered valid and subsequent processing can continue, such as updating state information and releasing resources. If they are invalid, the system may need to take remedial measures, such as resending the request or performing data consistency repair operations.

[0032] In an exemplary embodiment of this disclosure, the consistency protocol includes at least one of the following: methods for receiving, scheduling, executing, and providing feedback on results for different types of transactions; and a preset resolution method for address conflicts or data access conflicts that occur during protocol processing.

[0033] In an exemplary embodiment of this disclosure, after processing the response and data returned after transaction processing to make the response and data conform to the consistent transaction protocol, the method further includes: generating a response message, arbitrating and scheduling the response message, and determining the sending order of the response message.

[0034] In an exemplary embodiment of this disclosure, after protocol processing is performed on the response and data returned after transaction processing to make the response and data conform to the consistent transaction protocol, the method further includes: releasing the resources of the consistency queue.

[0035] In exemplary embodiments of this disclosure, the types of transaction requests include read requests, write requests, and replacement requests.

[0036] Through the embodiments of this disclosure, by parsing the type and priority of transaction requests, transactions can be scheduled more quickly and accurately, ensuring that high-priority transactions are processed in a timely manner, thereby accelerating transaction response speed. Furthermore, even with limited Point of Conherency Queue (POCQ) resources, resources can be rationally allocated to transactions of different types and priorities, avoiding resource waste and ensuring efficient resource utilization. By processing the responses and data after receiving transactions using a consistency protocol, data access can be effectively guaranteed to comply with consistency principles, avoiding data conflicts and inconsistencies. Therefore, the problems of inefficiently managing and scheduling transaction requests and ensuring that transaction responses and data follow consistency protocols in related technologies can be solved.

[0037] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this disclosure.

[0038] This embodiment also provides a transaction processing apparatus configured to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0039] Figure 3 is a structural block diagram of a transaction processing apparatus according to an embodiment of the present disclosure. As shown in Figure 3, the apparatus includes a scheduling module 10 and a processing module 20.

[0040] The scheduling module 10 is configured to parse the received transaction requests, determine the type and priority of the transaction requests, and schedule the transactions into the corresponding processing flow according to the type and priority of the transaction requests if there are unused consistency queue resources.

[0041] The processing module 20 is configured to perform protocol processing on the responses and data returned after a transaction enters the corresponding processing flow, so that the responses and data conform to the consistency protocol.

[0042] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0043] To facilitate understanding of the technical solutions provided in the disclosed embodiments, the following description is based on specific scenario embodiments.

[0044] Figure 4 is a structural block diagram of a transaction processing apparatus according to another embodiment of the present disclosure, which includes the following modules as shown in Figure 4:

[0045] (1) ID Management Module (idmgt): It mainly implements the allocation and deletion of consistency queues, allocates queue resources for input requests and listeners, and queue IDs can be used to query entry information in the queue. When going to the pipeline, each request needs to be bound to a queue ID for marking.

[0046] (2) Arbitration module (arb): Controls all requests in the arbitration pipeline, including external requests, replacement requests, requests in the consistency queue, SF / SLC fill, etc.

[0047] (3) Arbitration and Packet Assembly Sending Module: Responsible for arbitrating all RDY control signals that need to use the sending channel, and reading the consistency queue and completing packet assembly based on the arbitration result.

[0048] (4) Consistency queue entry storage module (pocq_trker(tracker)): Stores entries generated after protocol processing by the request pipeline and response pipeline, and generates related control information, such as address data, cache status, conflict status, arbitration signals, etc.

[0049] (5) Response pipeline processing module (rsppipe): First, read out the latest state stored in the consistency queue, then process the response and data according to the state stored in the consistency queue, and finally write the modified state back to the consistency queue.

[0050] (6) Bypass control module: Implements control over all bypass paths, including bypass of response channels and bypass of request channels.

[0051] (7) Address conflict checking module: Implements full address conflict checking for all requests.

[0052] Figure 5 is a structural block diagram of a transaction processing apparatus according to another embodiment of the present disclosure. Based on the structural block diagram shown in Figure 5, a transaction flow based on the third-level cache (L3 Cache, L3) and snoop filter (SF) in the read request hit processor is proposed to introduce a consistent queue processing method. The specific flow includes the following steps:

[0053] Step S501: Receive a read request. When there is an available queue resource, the arbitrator of the request pipeline arbitrates the read request, and then the idmgt module (ID management module) allocates the corresponding queue resource, and then the request enters the request pipeline.

[0054] Step S502: Query L3Cache and SF in the request pipeline and find a hit.

[0055] Step S503: If L3 is hit, the L3Data Cache needs to be accessed to put the L3D data into the data cache.

[0056] Step S504: Query the request protocol table.

[0057] Step S505: Write the processing result of the query request protocol table into the fieldmgt module of pocq_trker.

[0058] Step S506: When the rdywait module of pocq_trker records a pending listener, the arbitration scheduler inside the Beforeearb module sends the listener.

[0059] In step S507, upon receiving a listening response, the system enters the response pipeline processing module (rsppipe). First, it reads the status information from the sfslc module of pocq_trker, queries the response protocol table, completes the protocol processing for the listening response, and finally writes the processed status into the entrymgt module of pocq_trker.

[0060] In step S508, the request data response message generated by the arbitration scheduling inside the Beforeearb module reads data from the data cache and enters the TXDAT Pktgen module to form a data response message.

[0061] In step S509, after the received listening response message is processed by the protocol, if it is necessary to modify the state of SF / L3, it is necessary to enter the request pipeline again and rewrite L3 / SF through the arbitration pipeline of the arb module.

[0062] Step S510: Write the latest status to L3 / SF.

[0063] Step S511: Upon receiving the final response, the resources in the queue are released.

[0064] Figure 6 is a structural block diagram of a transaction processing apparatus according to another embodiment of the present disclosure. Based on the structural block diagram shown in Figure 6, a transaction process based on L3 replacement is proposed to introduce a consistent queue processing method. The specific process includes the following steps:

[0065] Step S601: Receive a read request. When there is an available queue resource, the arbitrator of the request pipeline arbitrates the read request, and then the idmgt module (ID management module) allocates the corresponding queue resource, and then the request enters the request pipeline.

[0066] In step S602, the L3Cache and SF are queried in the request pipeline. L3 is not hit, and SF is also not hit.

[0067] Step S603: Query the request protocol table.

[0068] Step S604: Write the processing result of the query request protocol table into the fieldmgt module of pocq_trker.

[0069] Step S605: When a pending request is recorded in the rdywait module of pocq_trker, the request is sent by the arbitration scheduler inside the Beforeearb module.

[0070] In step S606, upon receiving a read data response, the system enters the response pipeline processing module (rsppipe). First, it reads the status information from the sfslc module of pocq_trker, queries the data response protocol table, completes the protocol processing for the data response, and finally writes the processed status into the entrymgt module of pocq_trker.

[0071] In step S607, the request data response message generated by the arbitrator inside the Beforeearb module reads data from the data cache and enters the TXDAT Pktgen module to form a data response message.

[0072] In step S608, upon receiving the completion response, the request is marked as complete in the rdywait module of pocq_trker, and data needs to be written to L3.

[0073] Step S609: The L3Fill operation is scheduled from the arb module in the queue and enters the pipeline.

[0074] Step S610: Query L3T to find the Way that needs to be replaced.

[0075] Step S611: Write the address of the replaced Cache line to the queue used by the current request, and write the replaced Cache line data to the data cache where the current request is located.

[0076] In step S6012, the address to be replaced is scheduled, an L3 replacement request is generated, and the status of the replaced address in SF is queried. The arbitration scheduler inside the Beforeearb module generates a write request message, and upon receiving the write response, it enters the response pipeline processing module (rsppipe), queries the response protocol table, and updates the queue status.

[0077] In step S6013, the write data response message generated by the arbitration scheduling inside the Beforeearb module reads data from the data cache and enters the TXDAT Pktgen module to form the write data and send it out.

[0078] Step S6014: Release the resources in the queue.

[0079] This disclosure implements a dynamic allocation and reclamation mechanism for queue resources, ensuring that each transaction request can obtain the required resources in a timely manner, avoiding resource waste and idle waiting. This disclosure introduces a queue resource status check, which can assess the queue capacity before receiving a new transaction request, avoiding over-allocation and potential queue overflow problems. This disclosure, through the cooperation of the arbitration module and the sending channel arbitration, achieves efficient scheduling and control of all request types (including external requests, replacement requests, consistency transaction requests, etc.), ensuring optimal resource allocation.

[0080] This disclosure also provides customized processing flows for different types of transaction requests. By parsing the transaction type and priority, the order and scheduling of transaction processing are optimized. The internally integrated response pipeline can perform fast protocol processing on transaction responses and data, ensuring that data access conforms to the cache consistency protocol and reducing data conflicts and inconsistencies.

[0081] The embodiments disclosed herein can effectively manage cache consistency transactions, reduce the latency of cache state updates and propagation, improve the overall performance and consistency of the cache, and provide a more stable and efficient data sharing environment for multi-core processors.

[0082] Embodiments of this disclosure also provide a computer-readable storage medium storing a computer program configured to perform the steps in any of the above method embodiments when executed.

[0083] In one exemplary embodiment, the computer-readable storage medium described above includes DDR.

[0084] Embodiments of this disclosure also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0085] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0086] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0087] It is obvious to those skilled in the art that the modules or steps of this disclosure described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this disclosure is not limited to any particular combination of hardware and software.

[0088] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A transaction processing method, comprising: The received transaction requests are parsed to determine their type and priority. If there are unused consistency queue resources, the transactions are scheduled to enter the corresponding processing flow according to their type and priority. The response and data returned after the transaction enters the corresponding processing flow are processed according to the protocol to ensure that the response and data conform to the consistency protocol.

2. The method according to claim 1, wherein, Based on the type and priority of the transaction request, the transaction is scheduled into the corresponding processing flow, including: The scheduling signal for the transaction request is determined based on the type and priority of the transaction request, and the scheduling signal is sent to the consistency queue and the request pipeline, so that the consistency queue allocates corresponding resources for the transaction according to the scheduling signal, and the request pipeline controls the execution of the transaction according to the scheduling signal. The scheduling signal is used for resource allocation to the consistency queue and instruction control to the request pipeline.

3. The method according to claim 1, wherein, The protocol processing includes handling the responses and data returned after the transaction enters the corresponding processing flow, including: The process receives the response and the data, compares the response and the data with the consistency protocol, and determines the legality of the response and the data. The response and the data are updated and processed according to the consensus protocol.

4. The method according to claim 1, wherein, After performing protocol processing on the response and data returned after the transaction processing to ensure that the response and data conform to the consistency transaction protocol, the process further includes: Generate a response message, perform arbitration scheduling on the response message, and determine the sending order of the response message.

5. The method according to claim 1, wherein, Before parsing the received transaction request, the process also includes checking the current queue resource status to determine if there are available resources to receive new transactions.

6. The method according to claim 1, wherein, After processing the response and data returned after the transaction to make the response and data conform to the consistency transaction protocol, the method further includes: releasing the resources of the consistency queue.

7. The method according to claim 3, wherein, The consensus protocol includes at least one of the following: Methods for receiving, scheduling, executing, and providing feedback on different types of transactions; The default resolution method for address conflicts or data access conflicts that occur during protocol processing.

8. The method according to claim 1, wherein, The types of transaction requests include read requests, write requests, and replacement requests.

9. A computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, wherein, When the computer program is executed by a processor, it implements the steps of the method described in any one of claims 1 to 8.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the method according to any one of claims 1 to 8.

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