Display apparatus and electronic device

Abstract

The present application provides a display apparatus and an electronic device. The display apparatus comprises a plurality of pixel circuits and a plurality of light emitting elements; the plurality of pixel circuits include a first pixel circuit corresponding to red sub-pixels, a second pixel circuit corresponding to blue sub-pixels and a third pixel circuit corresponding to green sub-pixels; the first pixel circuit comprises a first transistor; the first transistor comprises a first channel line disposed under a gate metal region; the second pixel circuit comprises a second transistor; the second transistor comprises a second channel line disposed under the gate metal region; the third pixel circuit comprises a third transistor; the third transistor comprises a third channel line disposed under a third metal region; the length of the first channel line is less than or equal to the length of the second channel line, and the length of the first channel line is less than the length of the third channel line. The display apparatus and the electronic device provided by the present disclosure can improve the peak brightness of red light emitting elements.

Description

Display devices and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510109281.2, filed on January 21, 2025, entitled "Display Device and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more specifically, to a display device and an electronic device. Background Technology

[0003] Wide color gamut displays have a broad color range, enabling them to display more vibrant colors. For example, the BT.2020 and BT.709 color space standards cover a wider color gamut than the BT.709 color space, and display devices that cover the BT.2020 color space can provide users with a better visual experience.

[0004] However, for wide color gamut red light-emitting devices, the current-to-brightness conversion efficiency drops significantly in high-brightness mode, making it difficult to achieve higher peak brightness in red light-emitting devices. Summary of the Invention

[0005] This application provides a display device and an electronic device that can achieve high peak brightness of red devices in high-brightness scenarios.

[0006] In a first aspect, a display device is provided, comprising a plurality of pixel circuits and a plurality of light-emitting elements. The plurality of pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The plurality of light-emitting elements include a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is a red light-emitting element, the second light-emitting element is a blue light-emitting element, and the third light-emitting element is a green light-emitting element. The first pixel circuit is coupled to the first light-emitting element, the second pixel circuit is coupled to the second light-emitting element, and the third pixel circuit is coupled to the third light-emitting element. The first pixel circuit includes a first transistor, which is a driving transistor in the first pixel circuit. The first transistor includes a first metal... The first channel line is located below the first metal region, which is the gate metal region of the first transistor. The second pixel circuit includes a second transistor, which is a driving transistor in the second pixel circuit. The second transistor includes a second channel line covering the second metal region, which is the gate metal region of the second transistor. The third pixel circuit includes a third transistor, which is a driving transistor in the third pixel circuit. The third transistor includes a third channel line covering the third metal region, which is the gate metal region of the third transistor. The length of the first channel line is less than or equal to the length of the second channel line, and the length of the first channel line is less than the length of the third channel line.

[0007] In the embodiments provided in this application, the line length of the first channel line in the red sub-pixel is greater than the line length of the second channel line in the blue sub-pixel and the line length of the third channel line in the green sub-pixel. This increases the driving current in the red sub-pixel under the same data voltage, thereby increasing the maximum current achievable by the red light-emitting element and improving the peak brightness of the red light-emitting element. Furthermore, the line length of the first channel line is equal to the line length of the second channel line, which simplifies the design of the display device.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the length of the second channel line is less than the length of the third channel line.

[0009] In the embodiments provided in this application, the length of the second channel line is less than that of the third channel line, which can improve the control accuracy of green sub-pixels at low gray levels and increase the control difficulty of green sub-pixels at low gray levels.

[0010] In conjunction with the first aspect, in some implementations of the first aspect, the difference in line length between the first channel line and the second channel line is less than or equal to 4 μm.

[0011] In the embodiments provided in this application, the difference in line length between the first channel line and the second channel line is less than or equal to 4μm, which can further improve the peak brightness of the red light-emitting element and improve the uniformity of the process.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the difference in line length between the second channel line and the third channel line is 4μm to 20μm.

[0013] In the embodiments provided in this application, the difference in line length between the second channel line and the third channel line is 4μm to 20μm, which can further increase the control difficulty of green sub-pixels at low gray levels.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, at least a portion of the first channel line extends in a first direction, at least a portion of the second channel line extends in a first direction, the first direction being the pixel row direction in the display device; at least a portion of the third channel line extends in the first direction and at least a portion of the third channel line extends in a second direction, the second direction being the pixel column direction in the display device.

[0015] In the embodiments provided in this application, at least a portion of the first channel line and the second channel line extend in a first direction, at least a portion of the third channel line extends in the first direction and at least a portion of the third channel line extends in a second direction, which is beneficial to improve the uniformity of the process, reduce the pixel size, and improve the resolution of the display device.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the emission spectrum of the first light-emitting element has an emission peak, the wavelength of which is 630 nm to 645 nm.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the display device displays white light at a first brightness, the light-emitting current of the first light-emitting element is greater than the light-emitting current of the second light-emitting element, and the light-emitting current of the second light-emitting element is greater than the light-emitting current of the third light-emitting element, and the first brightness is the maximum brightness of the display device.

[0018] In the embodiments provided in this application, the luminous current of the first light-emitting element is greater than that of the second light-emitting element, and the luminous current of the second light-emitting element is greater than that of the third light-emitting element, which is beneficial to improving the peak brightness of the display device.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the first pixel circuit further includes a first capacitor, one end of which is coupled to a power supply voltage, and the other end of which is coupled to the gate of the first transistor; the second pixel circuit further includes a second capacitor, one end of which is coupled to the power supply voltage, and the other end of which is coupled to the gate of the second transistor, wherein the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0020] In the embodiments provided in this application, the capacitance value of the first capacitor is greater than that of the second capacitor, which enables higher red light brightness to be achieved even when it is difficult to shorten the channel line length of the driving transistor, thereby improving the peak brightness performance of the display device.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the first capacitor includes a first plate and a second plate, the first plate being coupled to the power supply voltage and the second plate being coupled to the gate of the first transistor; the second capacitor includes a third plate and a fourth plate, the third plate being coupled to the power supply voltage and the fourth plate being coupled to the gate of the second transistor; the first plate and the second plate have a first overlapping area in a third direction, the third direction being perpendicular to the light-receiving surface of the display device; the third plate and the fourth plate have a second overlapping area in the third direction, the second overlapping area being smaller than the first overlapping area.

[0022] In the embodiments provided in this application, the first overlapping area of ​​the first electrode plate and the second electrode plate is greater than the second overlapping area of ​​the third electrode plate and the fourth electrode plate, which enables the first capacitor to have a larger capacitance value and improves the peak brightness of the red light-emitting element.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the second overlapping area is less than the first overlapping area and greater than or equal to 70% of the first overlapping area.

[0024] In the embodiments provided in this application, the second overlapping area is smaller than the first overlapping area and greater than or equal to 70% of the first overlapping area, which is beneficial to further improve the peak brightness of the red light-emitting element.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the metal area corresponding to the first electrode plate is larger than the metal area corresponding to the third electrode plate, and the first electrode plate includes a first opening, the third electrode plate includes a second opening, the size of the first opening in a first direction is smaller than the size of the second opening in the first direction, and / or, the size of the first opening in a second direction is smaller than the size of the second opening in the second direction, the first direction is the pixel row direction in the display device, and the second direction is the pixel column direction in the display device.

[0026] In the embodiments provided in this application, holes are made on the first electrode plate and the second electrode plate, which facilitates the connection of the gate regions of the first transistor and the second transistor with the drains of other transistors in the pixel circuit; the size of the first hole on the first electrode plate in the first direction is smaller than the size of the second hole on the third electrode plate in the first direction, and the size of the first hole in the second direction is smaller than the size of the second hole in the second direction, which is beneficial to make the first capacitor have a larger capacitance value and improve the peak brightness of the red light-emitting element.

[0027] In conjunction with the first aspect, in some implementations of the first aspect, the maximum inner diameter of the first opening is smaller than the maximum inner diameter of the second opening.

[0028] In the embodiments provided in this application, the maximum inner diameter of the first opening is smaller than the maximum inner diameter of the second opening, which is beneficial to enable the first capacitor to have a larger capacitance value and improve the peak brightness of the red light-emitting element.

[0029] In conjunction with the first aspect, in some implementations of the first aspect, the difference between the size of the first opening in the first direction and the size of the second opening in the first direction is 1 μm to 10 μm.

[0030] In conjunction with the first aspect, in some implementations of the first aspect, the difference between the size of the first opening in the second direction and the size of the second opening in the second direction is 1 μm to 10 μm.

[0031] In conjunction with the first aspect, in some implementations of the first aspect, the first metal region has a first edge, which does not overlap with the first channel line in the third direction; the first electrode is located in a fourth metal region, which has a second edge, which is located on the same side of the first edge as the first edge and has a first distance between it and the second edge, which is the shortest distance between the first edge and the second edge in the direction parallel to the light-receiving surface of the display device; the second metal region includes a third edge, which does not overlap with the second channel line in the third direction; the third electrode is located in a fifth metal region, which includes a fourth edge, which is located on the same side of the second channel line as the third edge and has a second distance between it and the third edge, which is the shortest distance between the third edge and the fourth edge in the direction parallel to the light-receiving surface of the display device; the first distance is less than the second distance.

[0032] In the embodiments provided in this application, the first distance between the first edge and the second edge of the first capacitor is smaller than the second distance between the third edge and the fourth edge of the second capacitor, which is beneficial to enable the first capacitor to have a larger capacitance value and improve the peak brightness of the red light-emitting element.

[0033] In conjunction with the first aspect, in some implementations of the first aspect, the difference between the first distance and the second distance is 1 μm to 9 μm.

[0034] In conjunction with the first aspect, in some implementations of the first aspect, the display device further includes a first gate reset signal line and a second gate reset signal line, the first gate reset signal line being connected to the first pixel circuit, the second gate reset signal line being connected to the second pixel circuit, and the voltage amplitude transmitted by the first gate reset signal line being greater than the voltage amplitude transmitted by the second gate reset signal line.

[0035] In the embodiments provided in this application, the voltage transmitted by the gate reset signal line is usually negative. The voltage amplitude transmitted by the first gate reset signal line is greater than the voltage amplitude transmitted by the second gate reset signal line. The first gate reset voltage is lower, and the data voltage required for gate voltage charging is higher, which is beneficial to improving the peak brightness of the red light-emitting element.

[0036] In a second aspect, a display device is provided, comprising a plurality of pixel circuits, including a first pixel circuit and a second pixel circuit. The first pixel circuit is a pixel circuit corresponding to a red sub-pixel, and the second pixel circuit is a pixel circuit corresponding to a blue sub-pixel. The first pixel circuit includes a first capacitor and a first transistor, the first transistor being a driving transistor. One end of the first capacitor is coupled to a power supply voltage, and the other end of the first capacitor is coupled to the gate of the first transistor. The second pixel circuit includes a second capacitor and a second transistor, the second transistor being a driving transistor. One end of the second capacitor is coupled to the power supply voltage, and the other end of the second capacitor is coupled to the gate of the second transistor. The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

[0037] In conjunction with the second aspect, in some implementations of the second aspect, the first capacitor includes a first plate and a second plate, the first plate being coupled to the power supply voltage and the second plate being coupled to the gate of the first transistor; the second capacitor includes a third plate and a fourth plate, the third plate being coupled to the power supply voltage and the fourth plate being coupled to the gate of the second transistor; the first plate and the second plate have a first overlapping area in a third direction, the third direction being perpendicular to the light-receiving surface of the display device; the third plate and the fourth plate have a second overlapping area in the third direction, the second overlapping area being smaller than the first overlapping area.

[0038] In conjunction with the second aspect, in some implementations of the second aspect, the second overlapping area is less than the first overlapping area and greater than or equal to 70% of the first overlapping area.

[0039] In conjunction with the second aspect, in some implementations of the second aspect, the metal area corresponding to the first electrode plate is larger than the metal area corresponding to the third electrode plate, and the first electrode plate includes a first opening, the third electrode plate includes a second opening, the size of the first opening in a first direction is smaller than the size of the second opening in the first direction, and / or, the size of the first opening in a second direction is smaller than the size of the second opening in the second direction, the first direction being the pixel row direction in the display device, and the second direction being the pixel column direction in the display device.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the maximum inner diameter of the first opening is smaller than the maximum inner diameter of the second opening.

[0041] In conjunction with the second aspect, in some implementations of the second aspect, the difference between the size of the first opening in the first direction and the size of the second opening in the first direction is 1 μm to 10 μm.

[0042] In conjunction with the second aspect, in some implementations of the second aspect, the difference between the size of the first opening in the second direction and the size of the second opening in the second direction is 1 μm to 10 μm.

[0043] In conjunction with the second aspect, in some implementations of the second aspect, the first metal region has a first edge, which does not overlap with the first channel line in the third direction; the first electrode is located in a fourth metal region, which has a second edge, which is located on the same side of the first edge as the first edge and has a first distance between it and the second edge, which is the shortest distance between the first edge and the second edge in the direction parallel to the light-receiving surface of the display device; the second metal region has a third edge, which does not overlap with the second channel line in the third direction; the third electrode is located in a fifth metal region, which has a fourth edge, which is located on the same side of the second channel line as the third edge and has a second distance between it and the third edge, which is the shortest distance between the third edge and the fourth edge in the direction parallel to the light-receiving surface of the display device, and the first distance is less than the second distance.

[0044] In conjunction with the second aspect, in some implementations of the second aspect, the difference between the first distance and the second distance is 1 μm to 9 μm.

[0045] Thirdly, an electronic device is provided, including a display device as described in the first aspect or any possible implementation thereof. Attached Figure Description

[0046] Figure 1 is a schematic diagram of the display device;

[0047] Figure 2 is a schematic diagram of the pixel circuit and a signal timing diagram in the display device;

[0048] Figure 3 is a luminance-current curve provided in an embodiment of this application;

[0049] Figure 4 is a partial cross-sectional structural schematic diagram of the display device provided in an embodiment of this application;

[0050] Figure 5 is a partial top view of the display device provided in an embodiment of this application;

[0051] Figure 6 is a schematic diagram of the line length and the corresponding drain current I provided in the embodiment of this application. D -Drain-source voltage V DS Line graph;

[0052] Figure 7 is a partial top view of the display device provided in an embodiment of this application;

[0053] Figure 8 is an electroluminescence spectrum of a display device provided in an embodiment of this application;

[0054] Figure 9 is a partial cross-sectional structural schematic diagram of the display device provided in an embodiment of this application;

[0055] Figures 10 to 12 are partial top views of the display device provided in the embodiments of this application;

[0056] Figure 13 is a schematic diagram of the gate reset module provided in an embodiment of this application;

[0057] Figure 14 is a gate signal timing diagram provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0059] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0060] In the various embodiments of this application, the terms "first," "second," etc., are merely to indicate that multiple objects are different. For example, "first transistor" and "second transistor" are only to indicate different transistors. They should not have any effect on the transistors themselves or their number, and the aforementioned "first," "second," etc., should not impose any limitations on the embodiments of this application.

[0061] The terms “including,” “comprising,” “having,” and variations thereof all mean “including but not limited to,” unless otherwise specifically emphasized.

[0062] Figure 1 is a schematic diagram of a display device provided in an embodiment of this application. As shown in Figure 1, it may include a display panel 110, a data driving circuit 120, and a peripheral driving circuit 130. The display panel 110 includes an active display area (AA) 112 and a non-active display area (NA) 111. The data driving circuit 120 can be used to provide data signals (DS) to the display panel 110 after receiving external image information and signals. The peripheral driving circuit 130 can be used to provide multiple sets of control signals (CS) and multiple pixel operating voltages (PV) required by the display panel 110. The following is a description of the various sub-parts of the organic light-emitting diode (OLED) display device:

[0063] Area AA 112: Contains multiple periodically arranged pixels 1121, multiple data lines, and multiple gate scan lines. A single data line connects to multiple pixels along the Y-axis, and a single gate scan line connects to multiple pixels along the X-axis. Each pixel within the panel is connected to the data lines, gate scan lines, power supply voltages ELVDD and ELVSS, and initialization voltage Vini. A pixel can be represented as a pixel circuit, which includes the OLED and circuit units used to control the OLED. The circuit units execute specific pixel circuit timing sequences, controlling the current flow from the positive power supply voltage VDD through the OLED to the negative power supply voltage VSS. The OLED emits light of a specific brightness at a specific current value. One pixel circuit represents one sub-pixel. Display devices typically have three primary color sub-pixels: red, blue, and green. In commonly used display devices, each white pixel consists of one red sub-pixel, one blue sub-pixel, and two green sub-pixels, with the pixel arrangement designed in a diamond or diamond-like form.

[0064] NA region 111: Located on both sides of AA region, it contains multiple scan line driving circuits 1111. Due to the use of gate driver on array (GOA) technology, this scan line driving circuit 1111 can also be called a GOA circuit or gate driving circuit. NA region 111 can include multiple GOA modules. Each GOA module has a shift register function. After receiving the control signal CS, the GOA circuit can generate shift pulse signals output line by line, providing multiple gate signals to multiple gate lines (GL). Each GL is connected to one or more rows of pixels. The GOA signals are output line by line through GL, controlling the thin-film transistors (TFTs) in the pixel circuit to turn on or off line by line. Different GOA circuits can use the same or different potential frequencies of the control signal CS, depending on the signal conditions.

[0065] Data drive circuit 120: Provides a data signal DS, which is input to the display panel through multiple data lines and connected to the pixel circuit elements to enable the pixels to function properly. This DS signal contains pixel data voltage information, used to control the brightness of the light-emitting elements.

[0066] The peripheral driving circuit 130 provides multiple sets of control signals CS, including a start voltage signal (STV), clock signals (CLK) CLK1 and CLK2, a gate high voltage VGH (Vgate high), and a gate low voltage VGL (Vgate low). The GOA receives the CS signals and generates corresponding high and low voltage gate signals. Additionally, the peripheral driving circuit 130 can also provide multiple sets of pixel operating voltages PV, including power supply voltages VDD and VSS, and an initialization voltage Vini. The PV voltages are input to the display panel via multiple signal lines and connected to the pixel circuit elements, enabling the pixels to function normally.

[0067] For example, FIG2 is a timing diagram example of a pixel circuit and gate signals provided in an embodiment of this application, wherein FIG2(a) is the pixel circuit and FIG2(b) is a timing diagram of a portion of the gate signals in the pixel circuit. The pixel circuit may be located in area AA of the display device described in FIG1 above, and the pixel circuit may constitute a sub-pixel in the display device.

[0068] As shown in Figure 2(a), the pixel circuit may include a light-emitting element D, which can be a light-emitting diode (LED) or an organic light-emitting diode (OLED), etc., and can emit light when driven by current. When the light-emitting element D is a red light-emitting element, the corresponding pixel circuit can form a red sub-pixel; when the light-emitting element D is a green light-emitting element, the corresponding pixel circuit can form a green sub-pixel; and when the light-emitting element D is a blue light-emitting element, the corresponding pixel circuit can form a blue sub-pixel. In this display device, the pixel circuit structures of the red, blue, and green sub-pixels can be similar.

[0069] When the pixel circuit is a pixel circuit for a red sub-pixel, the pixel circuit can be called the first pixel circuit, and the light-emitting element D can be called the first light-emitting element; when the pixel circuit is a pixel circuit for a blue sub-pixel, the pixel circuit can be called the second pixel circuit, and the light-emitting element D can be called the second light-emitting element; when the pixel circuit is a pixel circuit for a green sub-pixel, the pixel circuit can be called the third pixel circuit, and the light-emitting element D can be called the third light-emitting element.

[0070] The pixel circuit may further include a driving transistor Td, which can be connected in series with the light-emitting element D to control the driving current of the light-emitting element D. When the pixel circuit is for a red sub-pixel, the driving transistor Td can be called the first transistor; when the pixel circuit is for a blue sub-pixel, the driving transistor Td can be called the second transistor; and when the pixel circuit is for a green sub-pixel, the driving transistor Td can be called the third transistor.

[0071] The pixel circuit may also include a transistor T1. The first terminal of transistor T1 can be connected to a data line (DL) for inputting a data voltage (DATA) to transistor T1. The second terminal of transistor T1 can be connected to the first terminal of a driving transistor Td. The third terminal of transistor T1 can be connected to a gate signal S4, which controls the on / off state of transistor T1. The gate signal S4 can be generated by the GOA circuit in Figure 1 based on the control signal CS transmitted from the peripheral driving circuit, and output to the pixel line by line through the gate line GL. The S1, S2, S3, and EM signals mentioned later are similar.

[0072] The pixel circuit may further include transistors T5 and T6. The first terminal of transistor T5 can be connected to the positive power supply voltage ELVDD, and the second terminal of transistor T5 can be connected to the first terminal of the driving transistor Td. The first terminal of transistor T6 can be connected to the second terminal of the driving transistor Td, and the second terminal of transistor T6 can be connected to the light-emitting element D. The third terminal of transistors T5 and T6 can be connected to a light-emitting signal (EM), which can be used to simultaneously control the on / off state of transistors T5 and T6.

[0073] The pixel circuit may further include a transistor T7, the first terminal of which can be connected to an initialization voltage Vini3, which can be used to initialize the source and drain of the driving transistor. The second terminal of the transistor T7 can be connected to the first terminal of the driving transistor Td. The third terminal of the transistor T7 can be connected to an S4 signal, which can be used to control the on / off state of the transistor T7.

[0074] The pixel circuit may further include a transistor T4. The first terminal of transistor T4 can be connected to an initialization voltage Vini1, which can be used to initialize the gate of the driving transistor Td. This initialization voltage Vini1 can also be called the gate reset voltage. The second terminal of transistor T4 can be connected to the second terminal of the driving transistor Td, and the third terminal of transistor T4 can be connected to a gate signal S1, which can be used to control the on / off state of transistor T4.

[0075] The pixel circuit may further include transistor T2, whose first terminal can be connected to the second terminal of driving transistor Td, and whose second terminal is connected to the third terminal of driving transistor Td. The third terminal of transistor T2 can be connected to signal S2, which can be used to control the on / off state of transistor T2. Transistor T2 and transistor T4 together constitute the gate reset control module of the pixel circuit. When transistors T2 and T4 are simultaneously turned on, an initialization voltage Vini1 is written to the gate of driving transistor Td, resetting the gate of driving transistor Td.

[0076] The pixel circuit may further include a transistor T3. The first terminal of transistor T3 can be connected to an initialization voltage Vini2, also known as the anode reset voltage. The second terminal of transistor T3 can be connected to the anode of the light-emitting element D. The third terminal of transistor T3 can be connected to a gate signal S3. The S3 signal can be used to control the on / off state of transistor T3. When transistor T3 is on, the initialization voltage Vini2 is written to the anode of the light-emitting element D, initializing the anode of the light-emitting element D.

[0077] Transistors T1, T3, T4, T5, T6, and T7 can be silicon transistors, and can be P-type transistors. Transistor T2 can be an oxide transistor, that is, an N-type transistor.

[0078] The first terminal of a transistor can be the source, the second terminal can be the drain, and the third terminal can be the gate. As mentioned above, the source and drain of a transistor can also be interchanged, where the first terminal can be the drain and the second terminal can be the source.

[0079] The pixel circuit may also include a capacitor C, the first end of which is connected to the positive power supply voltage ELVDD, and the second end of which is connected to the third end of the driving transistor Td.

[0080] Figure 2(b) shows the timing diagram of signals S1, S2, and S4 in (a). Signals S1 and S4 include a negative waveform of a certain length during the non-light-emitting time. The duration of the negative waveform can be any time, such as 6H, 2H, 1H, or 0.7H, where H is the time allotted for a row of pixels to refresh on the display screen. Signal S2 includes a positive waveform of a certain length during the non-light-emitting time, with a duration of any time, such as 2H or 6H.

[0081] When signal S1 is negative and signal S2 is positive, transistors T2 and T4 are simultaneously turned on, and the initialization voltage Vini1 is written to the gate of the driving transistor Td. When signal S2 is positive and signal S4 is negative, transistors T2 and the driving transistor Td are simultaneously turned on, and the data voltage is written to the gate of the driving transistor Td. The gate-source voltage (Vgs) is changed, thereby changing the current flowing through the light-emitting device in the next emission time, resulting in different brightness levels on the screen.

[0082] It should be understood that Figure 2(a) is merely an example illustrating one pixel circuit that can be applied to the embodiments of this application. The embodiments of this application can also be applied to pixel circuits of types such as 6T1C, 8T1C, and 8T2C. Alternatively, the connection relationships between transistors in the applied pixel circuit can be adjusted. This application does not limit the types of pixel circuits that can be applied, the connection relationships between individual transistors, or the types of transistors. For example, the driving transistor Td in this pixel circuit can also be an oxide transistor.

[0083] As mentioned above, the current-to-brightness conversion efficiency of wide color gamut red light-emitting elements decreases significantly at high brightness levels, making it difficult to achieve higher peak brightness in wide color gamut display devices. Figure 3 is a schematic diagram of the relationship between brightness and current in a display device. As shown in Figure 3, for traditional red, blue, and green light-emitting elements, the luminous efficiency of the blue light-emitting element is lower than that of the red light-emitting element, and the luminous efficiency of the red light-emitting element is lower than that of the green light-emitting element. When the white light brightness reaches a specified level, the driving current of the blue light-emitting element is greater than that of the red light-emitting element, and the driving current of the red light-emitting element is greater than that of the green light-emitting element. However, for wide color gamut color spaces, the luminous efficiency of wide color gamut red light-emitting elements is lower than that of blue light-emitting elements. When the white light brightness needs to reach a specified level, the driving current required for the wide color gamut red light-emitting element exceeds that of the blue light-emitting element. Excessive driving current can easily become a current bottleneck, making it difficult to achieve the target brightness.

[0084] Therefore, this application provides a display device to enhance the peak brightness of a wide color gamut red light-emitting element.

[0085] Figure 4 is a partial cross-sectional view of the display device provided in an embodiment of this application, and Figure 4 can be a structural diagram of the region where the driving transistor Td is located in the above-mentioned display device. When the driving transistor Td is located in the first pixel circuit, the driving transistor Td can be the first transistor; when the driving transistor Td is located in the second pixel circuit, the driving transistor Td can be the second transistor; and when the driving transistor Td is located in the third pixel circuit, the driving transistor Td can be the third transistor.

[0086] As shown in Figure 4, the driving transistor Td is the silicon transistor 220 illustrated. The gate region of the driving transistor Td can be located in the first gate metal layer 222 (hereinafter referred to as the GM1 layer). The gate regions of the first transistor, the second transistor, and the third transistor can all be located in the GM1 layer 222. The portion of the GM1 layer 222 corresponding to the first transistor can be called the first metal region, the portion corresponding to the second transistor can be called the second metal region, and the portion corresponding to the third transistor can be called the third metal region. The GM1 layer 222 can be formed into the gate regions of multiple silicon transistors in the pixel circuit through exposure and patterning processes. The GM1 layer 222 can be a single layer or multiple layers, and the material of the GM1 layer 222 can be a metal or alloy material such as titanium, aluminum, nickel, copper, silver, or gold.

[0087] The source region, drain region, and channel region of the driving transistor Td can be located in the polysilicon layer 221 (hereinafter referred to as the P-Si layer), which can be disposed below the GM1 layer 222. The source region, drain region, and channel region of the first transistor, the second transistor, and the third transistor can all be disposed in the P-Si layer 221. The portion of the P-Si layer 221 corresponding to the first transistor can be called the first conductive region, the portion corresponding to the second transistor can be called the second conductive region, and the portion corresponding to the third transistor can be called the third conductive region. The P-Si layer 221 can be formed into the first conductive region, the second conductive region, and the third conductive region through exposure and patterning processes.

[0088] Several regions on the P-Si layer 221 can be doped (e.g., p-type doping and n-type doping) to form the source region 2211 and drain region 2212 in the pixel circuit silicon transistor 220. The source region 2211 and drain region 2212 can be portions not covered by the GM1 layer 222, while the portions covered by the GM1 layer 222 can form the channel region 2213 of the silicon transistor 220. The channel region 2213 can be located between the source region 2211 and drain region 2212 of the silicon transistor 220. For example, the regions of the first conductive region not covered by the first metal region can respectively form the source region and drain region of the first transistor, and the regions of the first conductive region covered by the first metal region can form the channel region of the first transistor. The channel region of the first transistor can be referred to as the first channel line. The regions of the second conductive region not covered by the second metal region can respectively form the source and drain regions of the second transistor, and the regions of the second conductive region covered by the second metal region can form the channel region of the second transistor, which can be called the second channel line. Similarly, the regions of the third conductive region not covered by the third metal region can respectively form the source and drain regions of the third transistor, and the regions of the third conductive region covered by the third metal region can form the channel region of the third transistor, which can be called the third channel line.

[0089] It should be understood that the source region 2211 shown in the figure is located to the left of the channel region 2213, and the drain region 2212 is located to the right of the channel region 2213. The positions of the source region 2211 and the drain region 2212 can also be interchanged. Since the channel region 2213, the source region 2211, and the drain region 2212 are formed by doping, and the doping type and doping concentration of the channel region 2213 are different from those of the source region 2211 and the drain region 2212, in actual products, there can be a transition region between the channel region 2213 and the source region 2211 and the drain region 2212, and there can also be a small area of ​​overlap between the source region 2211 and the drain region 2212 and the GM1 layer 222 in the Z-axis direction shown in the figure. The size of the channel region 2213 in the X-axis direction shown in the figure can be represented by the size of the gate region corresponding to the transistor in the X-axis direction.

[0090] To enhance the peak brightness of the red light-emitting element in high-brightness scenarios, the length of the first channel line is less than or equal to the length of the second channel line, and the length of the first channel line is less than the length of the third channel line.

[0091] Figure 5 is a top view of the region where the driving transistor Td is located in some embodiments. Figure 5(a) shows the top view of the first transistor, Figure 5(b) shows the top view of the second transistor, and Figure 5(c) shows the top view of the third transistor. As shown in Figure 5, the length of the first channel line refers to the length of its path, which is L1 as shown. The lengths of the second and third channel lines have similar meanings, being L2 and L3 respectively, where L1 ≤ L2 and L1 < L3. The fact that the lengths of the first, second, and third channel lines satisfy the above conditions is beneficial for increasing the driving current of the red light-emitting element at the same data voltage, thereby increasing the maximum current required by the red light-emitting element and improving its peak brightness.

[0092] Figure 6 shows a schematic diagram of the channel line length provided in this application, and the drain-source voltage V of the driving transistor Td corresponding to different channel line lengths. DS With drain current I D The relationship curve graph, with V on the horizontal axis. DS The vertical axis is I D The V DS To drive the voltage between the drain and source of transistor Td, I DThis refers to the current flowing through the drain of the driving transistor Td, that is, the current from the drain to the source of the driving transistor Td. In Figure 6(a), the channel line length of the driving transistor Td is shorter than that of the driving transistor Td corresponding to Figure 6(b). For example, Figure 6(a) shows a schematic diagram of the first channel line length and the V of the first transistor. DS -I D The curve, Figure 6(b) shows the line length of the second channel line and the V of the second transistor. DS -I D The curve, or Figure 6(b), can also be a schematic diagram of the length of the third channel line and the V of the third transistor. DS -I D curve.

[0093] Due to the different doping types and concentrations in the P-Si layer, the region where the channel line is located constitutes a semiconductor, while the source and drain regions constitute conductors. The shorter the length of the channel line, the smaller its resistance, and the greater the current that the channel line can conduct under the same potential.

[0094] As shown in Figure 6, in V DS At the same time, the shorter the channel line length, the better I D The larger the value, the higher the luminous brightness of the light-emitting element can be achieved. For example, V DS When I is V1, for the channel line length in Figure 6(a), I D The value is I1, and for the channel line length in Figure 6(a), I... D The value is I1', where I1 > I1'.

[0095] Furthermore, the drive current of the driving transistor Td typically satisfies the following equation:

[0096] Where L is the length of the active region of the driving transistor Td, W is the width of the active region, u is the carrier mobility, Cox is the gate oxide capacitance, Vgs is the gate-source voltage of the driving transistor Td, which is the difference between the gate voltage (Vg) and the source voltage (Vs), and Vth is the threshold voltage of the driving transistor Td. The active region can be the region corresponding to the aforementioned channel line. From the above equation, it can be seen that the driving current is inversely proportional to the length of the active region. Furthermore, it can be proven that the smaller the channel line length, the larger the achievable driving current.

[0097] Therefore, the length of the first channel line is less than or equal to the length of the second channel line, and the length of the first channel line is less than the length of the third channel line. The driving current achievable by the first transistor is greater than or equal to the driving current achievable by the second transistor, and the driving current achievable by the first transistor is greater than the driving current achievable by the third transistor. Under the same data voltage driving, the peak brightness of the red sub-pixel can be improved, thus enhancing the display effect. Furthermore, since the light-emitting characteristics of the blue and red sub-pixels are similar when the white light brightness is low, their current-brightness relationship curves are relatively similar. Having the same length for the first and second channel lines also simplifies the design of the pixel circuit.

[0098] It should be understood that in the line length diagram shown in Figure 6, the channel line is represented by a triangle. This diagram is used to show that when the driving transistor Td is turned on, due to the migration of charge carriers from the source region (S) to the drain region (D), the charge carrier concentration in different regions of the channel line is different, and the potential on the channel line gradually decreases from the source region to the drain region. The cross-sectional shape of the channel line should not be limited.

[0099] Since the luminous efficiency of blue subpixels is typically lower than that of green subpixels, in some embodiments, to further improve the display effect of the display device, the length of the second channel line can be shorter than the length of the third channel line. The principle by which the length settings of the second and third channel lines improve the display effect is similar to the principle of setting the lengths of the first, second, and third channel lines described above, and will not be repeated here.

[0100] Referring again to the brightness and current curves in Figure 3, to achieve the same peak brightness, the driving current required by the blue sub-pixel is greater than that required by the green sub-pixel. The shorter length of the second channel line compared to the third channel line increases the achievable driving current for the blue sub-pixel, thereby improving its peak brightness. Furthermore, since the green light-emitting element has higher luminous efficiency, its control at low grayscale levels is more difficult. Setting a longer channel line for the driving transistor in the green sub-pixel allows for better current control accuracy at low grayscale levels, reducing the control difficulty at these levels.

[0101] In the top view structure shown in Figure 5 above, the first channel line and the second channel line have the same shape, while the third channel line has a different shape than both the first and second channel lines. The first and second channel lines are straight lines, and at least a portion of them extend in a first direction, which can be a pixel row direction or, as shown, the X-axis direction. The third channel line is curved, and at least a portion of it extends in both the first and second directions. This second direction can be a pixel column direction in the display device or, as shown, the Y-axis direction.

[0102] As mentioned above, the length of the third channel line can be greater than the length of the second channel line, and the length of the second channel line can be greater than or equal to the length of the first channel line. The third channel line is routed in a curved structure on the XY plane, which can reduce the size occupied by the green sub-pixel in the X-axis direction. Under the same planar area, the display device can set more pixels and improve the resolution of the display device.

[0103] For example, the length difference between the first channel line and the second channel line is less than 4 μm, and the length difference between the second channel line and the third channel line is greater than 4 μm. When the length difference between the first channel line and the second channel line is less than 4 μm, the shapes of the first channel line and the second channel line can be the same. When the length difference between the second channel line and the third channel line is greater than 4 μm, the shape of the third channel line can be different from the shape of the second channel line, and the first channel line, the second channel line, and the third channel line can be routed in the shape shown in Figure 5.

[0104] For example, the length difference between the first channel line and the second channel line can be 1μm to 4μm, such as 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, etc.

[0105] For example, the length difference between the second channel line and the third channel line can be 4μm to 20μm, such as 5μm, 7μm, 10μm, 11μm, 13μm, 16μm, 18μm, 19μm, etc.

[0106] The third channel line shown in Figure 5 includes a first broken line segment SL1, a second broken line segment SL2, a third broken line segment SL3, a fourth broken line segment SL4, and a fifth broken line segment SL5 arranged sequentially and adjacently, and the adjacent broken line segments have an included angle, so that the third channel line forms an “Ω” shaped structure.

[0107] The third channel line can also be other curved shapes. For example, Figure 7 shows another channel line shape provided in the embodiment of this application. As shown in Figure 7, the third channel line can also include only the first broken line segment SL1, the second broken line segment SL2 and the third broken line segment SL3 arranged adjacently, with an included angle between the adjacent broken line segments, so that the third channel line forms a "Z" shaped structure.

[0108] It should be understood that the third channel line can also be other curved shapes, such that the third channel line has a length in both the X-axis and Y-axis directions as shown in the figure. For example, the included angle between the adjacent broken line segments may not be 90° as shown in the figure, or the broken line segments may not be straight lines, but rather curved shapes such as arcs. This application does not limit the specific shape of the third channel line.

[0109] In some embodiments, the length difference between the second channel line and the third channel line may also be less than 4 μm. When the length difference between the second channel line and the third channel line is less than 4 μm, the shape of the third channel line may be the same as the shape of the second channel line, and consequently, the shapes of the first channel line, the second channel line, and the third channel line may all be the same.

[0110] For example, the length difference between the second channel line and the third channel line can be 2μm to 4μm, such as 2.5μm, 3μm, 3.5μm, etc.

[0111] For example, the first channel line, the second channel line, and the third channel line can all be straight lines as shown in (a) or (b) of Figure 5.

[0112] It should be understood that the first channel line and the second channel line can also be curved. For example, the first channel line, the second channel line and the third channel line can all be curved as shown in Figure 5(c) or Figure 7.

[0113] In some embodiments, the line widths of the first, second, and third channel lines can be the same. Continuing to refer to Figure 5, the line width can be a dimension perpendicular to the routing path; the line width of the first channel line can be D1, the line width of the second channel line can be D2, and the line width of the third channel line can be D3.

[0114] For example, the linewidths of the first channel line, the second channel line, and the third channel line can be values ​​such as 2μm, 2.3μm, 3μm, 3.6μm, 4μm, and 5μm.

[0115] Figure 8 shows the electroluminescence (EL) spectrum of the display device. The horizontal axis represents wavelength, and the vertical axis represents luminous intensity. Curve A is the EL curve of the blue light-emitting element, curve B is the EL curve of the green light-emitting element, curve C is the EL curve of the traditional red light-emitting element, and curve D is the EL curve of the wide color gamut light-emitting element.

[0116] As shown in Figure 8, the emission peak wavelength of a blue light-emitting element is 455nm–465nm, that of a green light-emitting element is 520nm–540nm, and that of a traditional red light-emitting element is 610nm–630nm. However, the emission peak wavelength of a wide color gamut red light-emitting element is 630nm–645nm. The emission peak wavelength of the wide color gamut red light-emitting element is greater than that of the traditional red light-emitting element. The red light-emitting element used in this embodiment is this wide color gamut red light-emitting element, with a wavelength of 630nm–645nm.

[0117] When the display device reaches its maximum brightness, it displays white light. The luminous current of the red light-emitting element is greater than that of the blue light-emitting element, and the luminous current of the blue light-emitting element is greater than that of the green light-emitting element.

[0118] The length and shape of the channel lines in different color sub-pixels have been described above. To make the structure and location of the driving transistor Td clearer, the following section will continue to describe the other structural layers in the display device in conjunction with Figure 4.

[0119] As shown in Figure 4, the display device may further include a substrate (SUB) 201, on which other structural layers of the display device may be supported. The substrate 201 may be made of polyimide (PI) or glass.

[0120] A buffer layer (BUF) 202 may be disposed on the substrate 201. The buffer layer 202 may be one or more layers. The material of the buffer layer 202 may be one or more dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0121] The display device may further include a first interlayer dielectric layer (hereinafter referred to as ILD1 layer) 203, which is formed above the buffer layer 202. The ILD1 layer 203 may be formed of a suitable dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The aforementioned P-Si layer 221 may be formed on the ILD1 layer 203.

[0122] The display device may further include a first gate insulating layer (hereinafter referred to as GI1 layer) 204, which may be formed above the ILD1 layer 203 and the P-Si layer 221. The GI1 layer 204 may be formed of a suitable dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The aforementioned GM1 layer 222 is formed on the GI1 layer 204.

[0123] The display device may further include a second interlayer dielectric layer (hereinafter referred to as ILD2 layer) 205, which may be formed above the GI1 layer 204 and the GM1 layer 222. The ILD2 layer 205 may be one or more layers and may be formed of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0124] The display device may also include an insulating layer 206 (hereinafter referred to as the INS layer), which may be formed on top of the ILD2 layer 205. The INS layer 206 may be a single layer or a multilayer structure, and may be formed of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0125] The display device may further include a first source-drain metal layer (hereinafter referred to as SD1 layer) 225, which may be formed on the INS layer 206. The SD1 layer 225 may serve as an interconnect layer between the silicon transistor 220 and the signal lines. For example, the gate region of the silicon transistor 220 may be connected to the SD1 layer 225 via a via 224. The via 224 may pass sequentially through the ILD2 layer 205 and the INS layer 206, and be connected to the GM1 layer 222 and the SD1 layer 225, respectively.

[0126] The display device may further include a first planarization layer (hereinafter referred to as PLN1 layer) 207, which is formed above SD1 layer 225. The material of PLN1 layer 207 may be an organic polymer dielectric material. The arrangement of PLN1 layer 207 facilitates the formation of other structural layers located above PLN1 layer 207.

[0127] When the silicon transistor 220 is the driving transistor Td, the display device may further include a bottom shield metal (BSM) layer 223. The BSM layer 223 may be located at the bottom of the driving transistor Td, for example, below the P-Si layer 221. The BSM layer 223 may be formed on the buffer layer 202, and the ILD1 layer 203 may be formed on the BSM layer 223 and the buffer layer 202. The BSM layer 223 may be formed as the bottom gate of the driving transistor Td through exposure and patterning processes. This bottom gate can serve as the bottom structure of the driving transistor Td, used to adjust the threshold voltage of the driving transistor Td. The bottom gate can also be used to control the channel region and change the operating characteristics of the driving transistor Td.

[0128] In addition to controlling the channel line length to increase the peak brightness of the red sub-pixel, the peak brightness of the red sub-pixel can also be increased by designing the capacitor structure in the pixel circuit.

[0129] Referring again to the pixel circuit shown in Figure 2(a), in some embodiments, the first pixel circuit further includes a first capacitor, one end of which is coupled to a power supply voltage, and the other end of which is coupled to the gate of a first transistor; the second pixel circuit further includes a second capacitor, one end of which is coupled to a power supply voltage, and the other end of which is coupled to the gate of a second transistor, wherein the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor. The first and second capacitors can be coupled to a positive power supply voltage ELVDD.

[0130] After gate reset, the potential of the lower plate of the storage capacitor is Vini1 (e.g., -5V). When the storage capacitor is charged to its rated capacity and the same data voltage Vdata (e.g., 0.5V) is written, the gate potential can be charged from Vini1 to Vg (e.g., -4V). During this process, the voltage change of the gate varies due to different capacitance values, enabling different pixel circuits to achieve different drive currents.

[0131] When a given voltage Vdata (e.g., 0.5V) is applied to the storage capacitor, ΔQ remains the same. From ΔV = ΔQ / Cst, it can be seen that when the storage capacitor is larger, the voltage change ΔV of the capacitor will be relatively smaller. Therefore, the capacitor can maintain its original, more negative potential (e.g., -4.5V). However, the charging capability is limited by the development of the driver chip, making it difficult to increase ΔQ. Increasing the capacitor value can increase the peak value of the gate-source voltage Vgs, thereby achieving higher peak brightness. Given the limitation on shortening the length of the driver transistor channel line, by setting the capacitance value of the first capacitor to be greater than that of the second capacitor, higher red brightness can be achieved, improving the peak brightness performance of the display device.

[0132] It should be understood that the capacitance value of the first capacitor and the capacitance value of the second capacitor can also be equal. For example, if the peak brightness of the red light-emitting element can reach the target brightness through the design of the channel line length, the capacitance value of the first capacitor and the capacitance value of the second capacitor can be set to be equal.

[0133] In some embodiments, the first capacitor includes a first plate and a second plate. The first plate can be coupled to a power supply voltage, and the second plate can be coupled to the gate of a first transistor. The first plate and the second plate have a first overlapping area in a third direction, which is perpendicular to the light-receiving surface of the display device. The second capacitor includes a third plate and a fourth plate. The third plate is coupled to a power supply voltage, and the fourth plate is coupled to the gate of the second transistor. The third plate and the fourth plate have a second overlapping area in the first direction, and the first overlapping area is larger than the second overlapping area.

[0134] Figure 9 is a cross-sectional structure of another display device provided in an embodiment of this application. As shown in Figure 9, the display device may further include a second gate metal layer 311 (hereinafter referred to as GM2 layer). The GM2 layer 311 may be a single layer or multiple layers, and the material of the GM2 layer 311 may be a metal or alloy material such as titanium, aluminum, nickel, copper, silver, or gold. The GM2 layer 311 may be formed on the ILD2 layer 205, and the aforementioned INS layer 206 may be deposited on the GM2 layer 311 and the ILD2 layer 205.

[0135] The GM2 layer 311 can serve as the upper electrode of the capacitor 310. Correspondingly, the GM1 layer 222 can serve not only as the gate region of the silicon transistor 220 but also as the lower electrode of the capacitor 310. When the capacitor 310 is located in the first pixel circuit, it can be the first capacitor; when it is located in the second pixel circuit, it can be the second capacitor. Through patterning, the first electrode of the first capacitor and the third electrode of the second capacitor can be formed in different regions of the GM1 layer 222, and the second electrode of the first capacitor and the fourth electrode of the second capacitor can be formed in different regions of the GM2 layer 311. The first electrode and the second electrode have overlapping areas in a third direction, that is, the region of the GM1 layer 222 corresponding to the first capacitor and the region of the GM2 layer 311 corresponding to the first capacitor have overlapping areas in a third direction, which is the Z-axis direction shown in the figure.

[0136] The first overlapping area is larger than the second overlapping area, which enables the first capacitor to be larger than the second capacitor. This allows for higher red brightness even when the length of the driving transistor is limited, thereby improving the peak brightness performance of the display device.

[0137] It should be understood that the lower terminal of the capacitor and the gate terminal of the driving transistor may not share a metal layer; they can each be independent metal parts. For example, the lower terminal of the capacitor and the gate terminal of the driving transistor can be staggered.

[0138] In order to make the capacitance value of the first capacitor greater than the capacitance value of the second capacitor, the metal area corresponding to the first electrode plate can be greater than the metal area corresponding to the third electrode plate, or the metal area corresponding to the second electrode plate can be greater than the metal area corresponding to the fourth electrode plate, or the metal area corresponding to the first electrode plate can be greater than the metal area corresponding to the third electrode plate, and the metal area corresponding to the second electrode plate can be greater than the metal area corresponding to the fourth electrode plate.

[0139] In some embodiments, the second overlapping area may be greater than or equal to 70% of the first overlapping area.

[0140] For example, the second overlapping area can be 75%, 77%, 80%, 85%, 88%, 90%, or 95% of the first overlapping area.

[0141] The second overlapping area is greater than or equal to 70% of the first overlapping area, which enables the display device to have better peak brightness performance.

[0142] In some embodiments, the metal area corresponding to the first electrode plate may be larger than the metal area corresponding to the third electrode plate, and the first electrode plate includes a first opening, the third electrode plate includes a second opening, the size of the first opening in a first direction may be smaller than the size of the second opening in a first direction, and / or, the size of the first opening in a second direction may be smaller than the size of the second opening in a second direction.

[0143] The statement that the metal area of ​​the first electrode plate is greater than that of the third electrode plate can refer to the size relationship between the metal areas of the first and third electrode plates after the holes are made. Before the holes are made in the first and third electrode plates, the metal area of ​​the first electrode plate can be greater than, less than, or equal to the metal area of ​​the third electrode plate.

[0144] Referring again to the structure shown in Figure 9, the upper plate of capacitor 310 is provided with an opening 312. When the cross-sectional structure corresponds to the first pixel circuit, the opening 312 can be the first opening; when the cross-sectional structure corresponds to the second pixel circuit, the opening 312 can be the second opening. As mentioned above, the GM1 layer 222 can serve as both the gate region of the silicon transistor 220 and the lower plate of capacitor 310. The GM2 layer 311 is provided with an opening, which facilitates the connection of the driving transistor with other structural layers in the pixel circuit, such as the drain of other transistors.

[0145] For example, FIG10 is a top view of the display device, wherein FIG10(a) is a top view of the area where the first capacitor is located, and FIG10(b) is a top view of the area where the second capacitor is located. As shown in FIG10, the size of the first opening in the first direction can be W1 as shown in the figure, and the size in the second direction can be W2. The size of the second opening in the first direction can be W3, and the size in the second direction can be W4, where W1 < W3 and W2 < W4. The fact that the size of the first opening in the first direction is smaller than the size of the second opening in the first direction means that the maximum size of the first opening in the first direction is smaller than the maximum size of the second opening in the first direction. Similarly, the fact that the size of the first opening in the second direction is smaller than the size of the second opening in the second direction means that the maximum size of the first opening in the second direction is smaller than the maximum size of the second opening in the second direction.

[0146] The size of the first opening in the first direction is smaller than that in the first direction, and the size of the first opening in the second direction is smaller than that of the second opening in the second direction, which makes it easier to control the capacitance value of the first capacitor to be greater than that of the second capacitor.

[0147] In some embodiments, W1 and W2 can be 2μm to 20μm.

[0148] In some embodiments, the difference between the size of the first opening in the first direction and the size of the second opening in the first direction is 1 μm to 10 μm.

[0149] In some embodiments, the difference between the size of the first opening in the second direction and the size of the second opening in the second direction is 1 μm to 10 μm.

[0150] In some embodiments, the maximum inner diameter of the first opening is smaller than the maximum inner diameter of the second opening.

[0151] For example, Figure 11 is another top view of the display device. Figure 11(a) is a top view of the area where the first capacitor is located, and Figure 11(b) is a top view of the area where the second capacitor is located. The first and second openings can be irregular structures. The maximum inner diameter of the first opening can be the maximum dimension between two points on the inner wall of the first opening in a direction parallel to the light-receiving surface of the display device, and the maximum inner diameter of the second opening is similar. The maximum inner diameter of the first opening shown in Figure 11 can be H1, and the maximum inner diameter of the second opening can be H2, where H1 < H2.

[0152] The maximum inner diameter of the first opening is smaller than the maximum inner diameter of the second opening, which makes it easier to make the first overlapping area of ​​the first capacitor larger than the second overlapping area of ​​the second capacitor, thus making the capacitance value of the first capacitor larger.

[0153] It should be understood that for irregularly shaped openings, the dimensions of the first opening and the second opening in the first and second directions can also satisfy the above-mentioned size relationship. Furthermore, for the above-mentioned rounded rectangular opening, the maximum inner diameter of the first opening can also be smaller than the maximum inner diameter of the second opening. For the rounded rectangular opening, the maximum inner diameter of the opening can be the diagonal dimension of the rounded rectangle.

[0154] It should be understood that Figures 10 and 11 above are only examples illustrating the shape of the opening. The shapes of the first and second openings can also be other shapes, such as the circle shown in Figure 12. For a circular opening, the dimensions of the opening in the first direction, the second direction, and the maximum inner diameter of the opening can all be the diameter of the opening. The shape of the opening can also be rectangular, elliptical, trapezoidal, etc., and this application does not limit it in this regard.

[0155] Referring again to the structure shown in Figure 10, the second plate of the first capacitor has a first edge EL1, or in other words, the first metal region has a first edge EL1. In the third direction, the first edge EL1 does not overlap with the first channel line. The metal region corresponding to the first plate can be called the fourth metal region. The fourth metal region has a second edge EL2. The second edge EL2 and the first edge EL1 can be located on the same side of the first channel line. The shortest distance between the first edge EL1 and the second edge EL2 in the direction parallel to the XY plane is the first distance S1.

[0156] The fourth plate of the second capacitor includes a third edge EL3, or in other words, the second metal region includes a third edge EL3. The metal region corresponding to the third plate can be called the fifth metal region, which includes a fourth edge EL4. The third edge EL3 and the fourth edge EL4 can be located on the same side of the second channel line. Furthermore, in the third direction, the third edge EL3 and the fourth edge EL4 do not overlap with the P-Si layer region corresponding to the second transistor. The P-Si layer region corresponding to the second transistor can also be called the second conductive region. The shortest distance between the third edge EL3 and the fourth edge EL4 in the direction parallel to the XY plane is the second distance S2. The first distance S1 can be less than the second distance S2.

[0157] The first distance S1 can be smaller than the second distance S2, which makes it easier to make the first overlapping area larger than the second overlapping area, so that the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor, thereby improving the luminous brightness of the red light-emitting element.

[0158] In some embodiments, the difference between the first distance S1 and S2 is 1 μm to 9 μm.

[0159] When the first and fourth metal regions are polygonal structures, they may include multiple first edges EL1 and multiple second edges EL2. As shown in Figure 10, along the Y-axis direction, the edges of the first metal region located above and below the first channel line can both be called first edges. Correspondingly, the number of second edges can also be two. The third edges EL3 and fourth edges EL4 are similar. In this case, multiple sets of first edges EL1 and second edges EL2 can have multiple first distances S1, and multiple sets of third edges EL3 and fourth edges EL4 can have multiple second distances S2, with at least one set of corresponding first distances S1 being less than the second distance S2. For example, this corresponding position may mean that when the first edges EL1 and second edges EL2 are above the first channel line, the third edges EL3 and fourth edges EL4 are above the second channel line; and when the first edges EL1 and second edges EL2 are below the first channel line, the third edges EL3 and fourth edges EL4 are below the second channel line.

[0160] To further improve the peak brightness performance of the display device, higher blue light brightness can also be achieved by controlling the capacitance value. Therefore, the capacitance value of the second capacitor can be greater than that of the third capacitor.

[0161] Similarly, the third capacitor may include a fifth plate and a sixth plate, the fifth plate being coupled to a power supply voltage and the sixth plate being coupled to the gate of a third transistor, the fifth plate and the sixth plate having a third overlapping area that is smaller than the second overlapping area.

[0162] In some embodiments, the fifth electrode plate includes a third opening, the third opening having a size larger than the second opening in the first direction, and the third opening having a size larger than the second opening in the second direction.

[0163] In some embodiments, the sixth electrode plate is located in the third metal region, which has a fifth edge. In the third direction, the fifth edge does not overlap with the third channel line. The fifth electrode plate is located in the sixth metal region, which has a sixth edge. The sixth edge and the fifth edge can be located on the same side of the third channel line. The shortest distance between the fifth edge and the sixth edge is a third distance, and the second distance can be greater than the third distance.

[0164] It should be understood that the capacitor-related structural features described above can be arranged together with the channel line length structural features in the display device, or the display device can improve the peak brightness of the red light-emitting element solely through the above-mentioned capacitor structure arrangement.

[0165] The above embodiments improve the peak brightness of the red light-emitting element by designing the channel line length and capacitance value. The peak brightness of the red light-emitting element can also be improved by designing the voltage amplitude of the gate reset line.

[0166] In some embodiments, the display device further includes a first gate reset signal line and a second gate reset signal line. The first gate reset signal line is connected to the first pixel circuit, and the gate reset signal line is connected to the second pixel circuit. The voltage amplitude transmitted by the first gate reset signal line is greater than the voltage amplitude transmitted by the second gate reset signal line.

[0167] Referring again to the pixel circuit shown in Figure 2, the part marked by the dashed box in the figure can be called the gate reset module of this pixel circuit, and the signal line corresponding to the first initialization voltage Vini1 is also the gate reset signal line. When this pixel circuit is a first pixel circuit, this gate reset signal line can be called the first gate reset signal line; when this pixel circuit is a second pixel circuit, this gate reset signal line can also be called the second gate reset signal line.

[0168] For example, the voltage transmitted by the first gate reset signal line can be denoted as Vini1-1, where Vini1-1 can be -5V, and the voltage transmitted by the second gate reset signal line can be denoted as Vini1-2, where Vini1-2 can be -4V.

[0169] The lower the gate reset voltage, the higher the data voltage required for gate voltage charging, which is beneficial for improving the peak brightness of the red sub-pixel.

[0170] The gate reset module can be any combination of N-type and P-type transistors. By turning on 1 to 2 transistors, the gate of the driving transistor is connected to the gate reset voltage Vini1 for discharge.

[0171] For example, Figure 13 is a schematic diagram of the gate reset module. The connection relationship of the gate reset module shown in Figure 13(a) and (b) is similar to that shown in Figure 2(a). The first terminal of transistor T4 is connected to the initialization voltage Vini1, the second terminal of transistor T4 is connected to the second terminal of driving transistor Td, the first terminal of transistor T2 is connected to the second terminal of driving transistor Td, and the second terminal of transistor T2 is connected to the third terminal of driving transistor Td. When transistors T2 and T4 are turned on simultaneously, Vini1 is written to the gate of driving transistor Td, resetting the gate of driving transistor Td.

[0172] In Figure 13(a), transistor T4 is a silicon transistor. The third terminal of transistor T4 is connected to the S1P signal, and the third terminal of transistor T2 is connected to the S2N signal line. When the S1P signal is a negative voltage and the S2N signal is a positive voltage, transistors T2 and T4 are turned on, and Vini1 is written to the gate of the driving transistor Td to reset the gate of the driving transistor Td.

[0173] In Figure 11(b), transistor T4 is an oxide transistor. The third terminal of transistor T4 is connected to the S1N signal, and the third terminal of transistor T2 is connected to the S2N signal line. When both the S1N and S2N signals are positive, transistors T2 and T4 are turned on, and Vini1 is written to the gate of the driving transistor Td, resetting the gate of the driving transistor Td.

[0174] As mentioned above, the timing waveforms of the gate signals differ depending on the type of transistor T2. Therefore, the names of the gate signals connected to different types of transistor T2 are also different, and the same applies to transistor T4. Figure 14 shows the gate signal timing diagrams of transistors T2 and T4 corresponding to those in Figure 13. The timing diagram shown in Figure 14(a) corresponds to the structure shown in Figure 13(a), and the timing diagram shown in Figure 14(b) corresponds to the structure shown in Figure 13(b). As shown in Figure 14(a), when the S1P signal is negative and the S2N signal is positive, transistors T2 and T4 are turned on simultaneously. As shown in Figure 14(b), when the S1N signal is positive and the S2N signal is positive, transistors T2 and T4 are turned on simultaneously.

[0175] Unlike the gate drive modules shown in Figures 13(a) and (b), in Figures 13(c) and (d), the second terminal of transistor T4 is connected to the third terminal of drive transistor Td. When transistor T4 is turned on, the Vini1 voltage is written to the gate of drive transistor Td, resetting the gate of drive transistor Td. During this gate reset process, transistor T2 does not need to be turned on; transistor T2 can be turned on during the writing of the data voltage.

[0176] In Figure 13(c), transistor T4 is an oxide transistor, and its third terminal is connected to the S1N signal. Correspondingly, the timing sequence shown in Figure 14(c) corresponds to the structure shown in Figure 13(c). When the S1N signal is a positive voltage, Vini1 writes to the gate of the driving transistor Td, resetting the gate of Td. When the S1N signal is a positive voltage, the S2N signal can be a negative voltage.

[0177] In Figure 13(d), transistor T4 is a silicon transistor, and its third terminal is connected to the S1P signal. Correspondingly, the timing shown in Figure 14(d) corresponds to the structure shown in Figure 13(d). When the S1P signal is negative, Vini1 writes to the gate of the driving transistor Td, resetting the gate of Td. When the S1P signal is negative, the S2P signal can be positive.

[0178] It should be understood that the gate reset module may also have other connection methods, and this application does not limit them.

[0179] In some embodiments, the display device may further include a third gate reset signal line connected to a third pixel circuit, wherein the voltage amplitude transmitted by the third gate reset signal line is less than the voltage amplitude transmitted by the second gate reset signal line. The gate reset module of the third pixel circuit may be similar to that described in FIG13, and will not be described again here.

[0180] The above embodiments describe the relevant structures that can improve the peak brightness of the red light-emitting element. The display device also includes some other structures, such as the oxide transistor (transistor T2) in the pixel circuit shown in FIG2. The structure of the oxide transistor can be further referred to in the display device shown in FIG9.

[0181] As shown in Figure 9, the display device may further include an oxide layer 412 and a third gate metal layer (hereinafter referred to as the GM3 layer) 413. The oxide layer 412 can be exposed and patterned to form oxide traces with a specific linewidth. Several regions of the oxide layer 412 (e.g., regions not covered by the GM3 layer 413) can be doped (e.g., p-type doping and n-type doping) to form the source and drain regions of the oxide transistor 410. The GM3 layer 413 can be disposed above the oxide layer 412 to form the drain region of the oxide transistor 410.

[0182] In some embodiments, the INS layer 206 may include a first insulating layer 206-1, a second insulating layer 206-2, and a third insulating layer 206-3. The first insulating layer 206-1 may be formed on the GM2 layer 311 and the ILD2 layer 205, and the oxide layer 412 may be formed on the first insulating layer 206-1. The second insulating layer 206-2 may be formed on the oxide layer 412 and the first insulating layer 206-1. The GM3 layer 413 may be formed on the second insulating layer, and the third insulating layer 206-3 may be formed on the GM3 layer 413.

[0183] The first insulating layer 206-1 can also be referred to as the third interlayer dielectric layer (hereinafter referred to as ILD3), the second insulating layer 206-2 can also be referred to as the second gate insulating layer (hereinafter referred to as GI2), and the third insulating layer 206-3 can also be referred to as the oxide interlayer dielectric layer (hereinafter referred to as OILD layer).

[0184] When the oxide transistor 410 is connected to a silicon transistor, it can be connected to the interconnect line 415 via the via 414, and then connected to the corresponding silicon transistor via the interconnect line 415. When the interconnect line 415 is connected to the corresponding silicon transistor, it can also be connected to the source or gate region of the silicon transistor via a via. The interconnect line 415 can be located in the SD1 layer.

[0185] Similarly, the GM3 layer 413 can be connected to the interconnect 417 via the via 416, and connected to the gate signal line (the gate signal line of the oxide transistor 410 is not shown in the figure) via the interconnect 417. The interconnect 417 can also be located in the SD1 layer.

[0186] The oxide transistor 410 may also have a bottom gate, which may be located at the bottom of the oxide layer 412. The bottom gate may be located in the aforementioned GM2 layer 311.

[0187] The display device also includes a light-emitting element, which may be, for example, an organic light-emitting diode (OLED). Accordingly, the display device may also include an anode layer 611, which may be formed on the PLN2 layer 208 and constitute the anode terminal of the light-emitting element. The anode layer 611 can be coupled to an interconnect 419 through a via 511, allowing the TFT circuit signals within the pixel to be coupled to the light-emitting element. The interconnect 419 may be located in the SD2 layer, and the interconnect 419 can be coupled to the SD1 layer through a via 418, allowing the light-emitting element to be coupled to a transistor.

[0188] It should be understood that the anode conductor layer 611 may also include optical structure layers, such as pixel defining layers, organic light-emitting diode light-emitting materials, cathode layers, polarizers, glass cover plates, etc., which will not be listed here. The anode conductor layer 611 may also be formed on the third planarization layer (hereinafter referred to as the PLN3 layer). The PLN3 layer may be formed on the PLN2 layer and the third source / drain metal layer (SD3 layer) (not shown in the figure). The SD3 layer may serve as an interconnect layer for coupling between the transistor and the light-emitting element, or it may serve as an interconnect layer for the transistor and other signal lines. This application does not limit this.

[0189] It should be understood that in the display device shown in Figure 9, the various devices may be located in different positions within the display device. To illustrate the cross-sectional structure of each device in the same cross-sectional view, devices located in different positions are shown on the same cross-sectional view. The structures of other silicon transistors and oxide transistors involved in this display device are similar to the structures of silicon transistor 220 and oxide transistor 410 in Figure 9, respectively, and will not be described in detail here.

[0190] This application also provides an electronic device, which may include the display device described in the above embodiments. The electronic device may be a large-screen device such as a mobile phone, tablet computer, laptop computer, television, or e-reader; it may also be other products with display functions, and this application does not limit the scope of the application.

[0191] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display device, characterized in that, It includes multiple pixel circuits and multiple light-emitting elements. The multiple pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The multiple light-emitting elements include a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is a red light-emitting element, the second light-emitting element is a blue light-emitting element, and the third light-emitting element is a green light-emitting element. The first pixel circuit is coupled to the first light-emitting element, the second pixel circuit is coupled to the second light-emitting element, and the third pixel circuit is coupled to the third light-emitting element. The first pixel circuit includes a first transistor, which is a driving transistor in the first pixel circuit. The first transistor includes a first channel line covering a first metal region, which is the gate metal region of the first transistor. The second pixel circuit includes a second transistor, which is a driving transistor in the second pixel circuit. The second transistor includes a second channel line covering a second metal region, which is the gate metal region of the second transistor. The third pixel circuit includes a third transistor, which is a driving transistor in the third pixel circuit. The third transistor includes a third channel line covering a third metal region, which is the gate metal region of the third transistor. Wherein, the length of the first channel line is less than or equal to the length of the second channel line, and the length of the first channel line is less than the length of the third channel line.

2. The display device according to claim 1, characterized in that, The length of the second channel line is less than the length of the third channel line.

3. The display device according to claim 1 or 2, characterized in that, The difference in length between the first channel line and the second channel line is less than or equal to 4 μm.

4. The display device according to any one of claims 1 to 3, characterized in that, The difference in line length between the second channel line and the third channel line is 4μm to 20μm.

5. The display device according to any one of claims 1 to 4, characterized in that, At least a portion of the first channel line extends in a first direction, and at least a portion of the second channel line extends in the first direction, which is the pixel row direction in the display device; At least a portion of the third channel line extends in the first direction, and at least a portion of the third channel line extends in a second direction, which is the pixel column direction in the display device.

6. The display device according to any one of claims 1 to 5, characterized in that, The emission spectrum of the first light-emitting element has an emission peak, and the wavelength corresponding to the emission peak is 630nm to 645nm.

7. The display device according to any one of claims 1 to 6, characterized in that, The display device displays white light at a first brightness level, the luminous current of the first light-emitting element is greater than that of the second light-emitting element, and the luminous current of the second light-emitting element is greater than that of the third light-emitting element. The first brightness level is the maximum brightness of the display device.

8. The display device according to any one of claims 1 to 7, characterized in that, The first pixel circuit also includes a first capacitor, one end of which is coupled to the power supply voltage, and the other end of which is coupled to the gate of the first transistor. The second pixel circuit further includes a second capacitor, one end of which is coupled to the power supply voltage, and the other end of which is coupled to the gate of the second transistor. The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

9. The display device according to claim 8, characterized in that, The first capacitor includes a first plate and a second plate, the first plate being coupled to the power supply voltage and the second plate being coupled to the gate of the first transistor. The second capacitor includes a third plate and a fourth plate, the third plate being coupled to the power supply voltage and the fourth plate being coupled to the gate of the second transistor. The first electrode plate and the second electrode plate have a first overlapping area in a third direction, which is perpendicular to the light-incoming surface of the display device. The third electrode plate and the fourth electrode plate have a second overlapping area in the third direction, which is smaller than the first overlapping area.

10. The display device according to claim 9, characterized in that, The second overlapping area is less than the first overlapping area and greater than or equal to 70% of the first overlapping area.

11. The display device according to claim 9 or 10, characterized in that, The metal area corresponding to the first electrode plate is larger than the metal area corresponding to the third electrode plate, and the first electrode plate includes a first opening, the third electrode plate includes a second opening, the size of the first opening in a first direction is smaller than the size of the second opening in the first direction, and / or, The size of the first opening in the second direction is smaller than the size of the second opening in the second direction, where the first direction is the pixel row direction in the display device and the second direction is the pixel column direction in the display device.

12. The display device according to claim 11, characterized in that, The maximum inner diameter of the first opening is smaller than the maximum inner diameter of the second opening.

13. The display device according to claim 11 or 12, characterized in that, The difference between the size of the first opening in the first direction and the size of the second opening in the first direction is 1 μm to 10 μm.

14. The display device according to any one of claims 11 to 13, characterized in that, The difference between the size of the first opening in the second direction and the size of the second opening in the second direction is 1 μm to 10 μm.

15. The display device according to any one of claims 9 to 14, characterized in that, The first metal region has a first edge, which does not overlap with the first channel line in the third direction. The first electrode plate is located in the fourth metal region, which has a second edge. The second edge and the first edge are located on the same side of the first channel line. There is a first distance between the first edge and the second edge. The first distance is the shortest distance between the first edge and the second edge in the direction parallel to the light-inlet surface of the display device. The second metal region has a third edge, which does not overlap with the second channel line in the third direction. The third electrode is located in the fifth metal region, which has a fourth edge. The fourth edge and the third edge are located on the same side of the second channel line. There is a second distance between the third edge and the fourth edge. The second distance is the shortest distance between the third edge and the fourth edge in the direction parallel to the light-gathering surface of the display device. The first distance is less than the second distance.

16. The display device according to claim 15, characterized in that, The difference between the first distance and the second distance is 1 μm to 9 μm.

17. The display device according to any one of claims 1 to 16, characterized in that, The display device further includes a first gate reset signal line and a second gate reset signal line. The first gate reset signal line is connected to the first pixel circuit, and the second gate reset signal line is connected to the second pixel circuit. The voltage amplitude transmitted by the first gate reset signal line is greater than the voltage amplitude transmitted by the second gate reset signal line.

18. An electronic device, characterized in that, Includes the display device as described in any one of claims 1 to 17.

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