Power amplifier circuit, radio frequency front-end module and communication device

Abstract

The embodiments of the present application relate to the technical field of electronics. Provided are a power amplifier circuit, a radio frequency front-end module and a communication device, which are used for improving the saturation power and saturation efficiency of the power amplifier circuit. The power amplifier circuit uses, in at least one branch (which may be a main power amplifier branch or a peak power amplifier branch), an impedance matching network architecture in which a capacitor and an inductor are connected in series, in at least one branch (which may be a main power amplifier branch or a peak power amplifier branch). In such an architecture, both a fundamental-wave impedance and a harmonic impedance of the branch are adjusted by means of a series-connected capacitor-inductor network. However, since the capacitance value of the capacitor and / or the inductance value of the inductor can be changed while the fundamental-wave impedance remains fixed and a second harmonic impedance changes, when the second harmonic impedance is adjusted within a wideband range, the fundamental-wave impedance may not be affected. On this basis, by rationally selecting the capacitance value of a capacitor or the inductance value of an inductor, the fundamental-wave impedance and the second harmonic impedance in the branch can respectively meet corresponding requirements, such that the power amplifier circuit has relatively high saturation power and saturation efficiency.

Description

Power amplifier circuits, RF front-end modules and communication equipment

[0001] This application claims priority to Chinese Patent Application No. 202510115036.2, filed with the State Intellectual Property Office of China on January 23, 2025, entitled "Power Amplifier Circuit, RF Front-End Module and Communication Equipment", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of electronic technology, and in particular to a power amplifier circuit, a radio frequency front-end module, and a communication device. Background Technology

[0003] Power amplifier (PA) circuits are a crucial component of mobile communication systems. As the final amplification unit in the transmission channel, their function is to amplify low-power radio frequency signals before sending them to the antenna for transmission. With the development of mobile communication technology, communication equipment places increasingly higher demands on PA efficiency. Load-modulated power amplifiers (DPPAs) are gradually becoming an essential architecture for terminal devices. DPPAs must control not only the fundamental impedance but also the harmonic impedance. Only when the fundamental and harmonic impedances each meet the target requirements can the PA achieve optimal saturation power and saturation efficiency.

[0004] However, how to achieve independent adjustment of the fundamental impedance and harmonic impedance to meet the target requirements of each has become a technical problem to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a power amplifier circuit, an RF front-end module, and a communication device for improving the saturation power and saturation efficiency of the power amplifier circuit.

[0006] A first aspect of this application provides a power amplifier circuit, comprising: a radio frequency (RF) input terminal, an RF output terminal, a first power divider, a first branch, a second branch, and a first combining point. One of the first branch and the second branch is a main power amplifier branch, and the other is a peak power amplifier branch. The first branch and the second branch are combined at the first combining point, which is coupled to the RF output terminal. The first power divider includes a first power divider input terminal, a first power divider output terminal, and a second power divider output terminal; the first power divider input terminal is coupled to the RF input terminal. The first branch includes a first amplifier and a first impedance matching network. A first terminal of the first amplifier is coupled to the first power divider output terminal. The first impedance matching network includes a first capacitor and a first inductor series coupled between the second terminal of the first amplifier and the first combining point. The second branch includes a second amplifier and a second impedance matching network. A first terminal of the second amplifier is coupled to the second power divider output terminal. The second impedance matching network includes a second capacitor or a second inductor coupled between the second terminal of the second amplifier and the first combining point, or the second impedance matching network includes a second capacitor and a second inductor series coupled between the second terminal of the second amplifier and the first combining point. For example, the first branch is the main power amplifier branch, the second branch is the peak power amplifier branch, and the second impedance matching network includes a second capacitor or a second capacitor and a second inductor coupled in series. Alternatively, for example, the first branch is the peak power amplifier branch, the second branch is the main power amplifier branch, and the second impedance network includes a second inductor or a second capacitor and a second inductor coupled in series.

[0007] The power amplifier circuit provided in this application embodiment employs an impedance matching network architecture of capacitor and inductor series connection in at least the first branch (which can be the main power amplifier branch or the peak power amplifier branch). In this architecture, the fundamental and harmonic impedances of the first branch are determined by the series capacitor and inductor network. With appropriately selected values ​​for the first capacitor and inductor, the fundamental and second harmonic impedances in the first branch can respectively meet the requirements, thereby enabling the power amplifier circuit to have superior saturation power and saturation efficiency. When the second branch also includes a second capacitor and a second inductor series connection, the fundamental and second harmonic impedances in the second branch can also be made to meet the requirements, further optimizing the saturation power and saturation efficiency of the power amplifier circuit. Furthermore, the capacitor and inductor are broadband structures, suitable for broadband applications.

[0008] In one possible implementation, the capacitance values ​​of the first capacitor and the second capacitor are different. Based on these different capacitance values, the impedance matching network can be made capacitive or inductive to meet the branch impedance requirements.

[0009] In one possible implementation, the inductance values ​​of the first inductor and the second inductor are different. Based on these different inductance values, the impedance matching network can be made capacitive or inductive to meet the branch impedance requirements.

[0010] In one possible implementation, the fundamental impedance of one of the first and second impedance matching networks is inductive, while the fundamental impedance of the other is capacitive. This allows the power amplifier circuit to employ a Doherty architecture, improving the efficiency of the power amplifier circuit under back-off power.

[0011] In one possible implementation, the power amplifier circuit further includes a second power divider, a third power divider, a second combining point, a third combining point, a third branch, a fourth branch, and an impedance transformer. The second power divider includes a second power divider input, a third power divider output, and a fourth power divider output; the second power divider input is coupled to the RF input, and the third power divider output is coupled to the first power divider input. The third power divider includes a third power divider input, a fifth power divider output, and a sixth power divider output; the third power divider input is coupled to the fourth power divider output. The third branch includes a third amplifier and a third impedance matching network; the first terminal of the third amplifier is coupled to the sixth power divider output; the third impedance matching network includes a third capacitor or a third inductor coupled between the second terminal of the third amplifier and the second combining point, or the third impedance matching network includes a third capacitor and a third inductor coupled in series between the second terminal of the third amplifier and the second combining point. The fourth branch includes a fourth amplifier and a fourth impedance matching network. The first terminal of the fourth amplifier is coupled to the output terminal of the fifth power divider. The fourth impedance matching network includes a fourth capacitor or a fourth inductor coupled between the second terminal of the fourth amplifier and the second combining point, or the fourth impedance matching network includes a fourth capacitor and a fourth inductor coupled in series between the second terminal of the fourth amplifier and the second combining point. An impedance transformer is coupled between the first and third combining points. Based on the structure of the third and fourth branches described above, after the two branches are combined at the second combining point, they conform to the Doherty architecture, which can improve the efficiency of the power amplifier circuit under back-off power. Furthermore, the power amplifier circuit also includes an impedance transformer. When the impedance of the load coupled to the RF output terminal changes abruptly, the impedance on the path without an impedance transformer changes abruptly as well, resulting in a decrease in power. However, the impedance on the path with an impedance transformer changes abruptly in the opposite direction under the action of the impedance transformer, resulting in an increase in power. After the two paths are combined at the third combining point, power synthesis is performed. The synthesized power is more stable, thereby reducing the impact of impedance changes. The two paths can serve as impedance-complementary paths. Achieving broadband efficiency and load desensitization eliminates the need for complex, large-area, or high-insertion-loss circuit modules, simplifying the power amplifier circuit structure and reducing its footprint. Simultaneously, it avoids the insertion losses of complex modules, reduces circuit redundancy, improves the efficiency of the power amplifier circuit, and enhances the circuit's mismatch resilience at a relatively low cost.

[0012] In one possible implementation, the capacitance value of the fourth capacitor is different from that of the third capacitor. Based on the different capacitance values, the impedance matching network can be made capacitive or inductive to meet the branch impedance requirements.

[0013] In one possible implementation, the inductance value of the fourth inductor is different from that of the third inductor. Based on the different inductance values, the impedance matching network can be made capacitive or inductive to meet the branch impedance requirements.

[0014] In one possible implementation, one of the fourth and third impedance matching networks has an inductive fundamental impedance, while the other has a capacitive fundamental impedance. This allows the third and fourth branches to satisfy the Doherty architecture, improving the efficiency of the power amplifier circuit under back-off power.

[0015] In one possible implementation, the capacitance values ​​of the second and fourth capacitors are different. Based on these different capacitance values, the impedance matching network can be made capacitive or inductive to meet the branch impedance requirements.

[0016] In one possible implementation, the inductance values ​​of the second inductor and the fourth inductor are different. Based on these different inductance values, the impedance matching network can be made capacitive or inductive to meet the branch impedance requirements.

[0017] In one possible implementation, the impedance transformer includes a fifth inductor, a sixth inductor, and a fifth capacitor; the fifth and sixth inductors are connected in series between the third and first junction points; one end of the fifth capacitor is coupled to the reference ground voltage terminal, and the other end of the fifth capacitor is coupled between the fifth and sixth inductors. This is a simple 1 / 4 wavelength transformer.

[0018] In one possible implementation, the inductance value of the first inductor or the second inductor is greater than 0 and less than 3NH. By limiting the value of the first inductor or the second inductor to within 3NH, the first branch and the second branch can have better performance. Furthermore, the relatively small inductance value of the first inductor or the second inductor results in a smaller area occupied by the first inductor or the second inductor, making it suitable for application scenarios in terminal devices.

[0019] In one possible implementation, the capacitance value of the first capacitor or the second capacitor is greater than 0 and less than 10pF. By limiting the value of the first capacitor or the second capacitor to within 10pF, the first branch and the second branch can have better performance.

[0020] In one possible implementation, the inductance value of the third inductor or the fourth inductor is greater than 0 and less than 3NH. By limiting the value of the third or fourth inductor to within 3NH, the third and fourth branches can achieve better performance. Furthermore, the relatively small inductance value of the third or fourth inductor results in a smaller footprint, making it suitable for applications in terminal devices.

[0021] In one possible implementation, the capacitance of the third capacitor or the fourth capacitor is greater than 0 and less than 10pF. By limiting the value of the third or fourth capacitor to within 10pF, the third and fourth branches can achieve better performance.

[0022] In one possible implementation, the phase difference between the first and third combining points is 60° to 120° or -60° to -120°. This phase difference affects the impedance transformation capability of the impedance transformer, thus influencing the complementary effect between the branches containing the first and second combining points, and consequently affecting the output performance of the power amplifier circuit. Limiting the phase difference between the first and third combining points to 60° to 120° or -60° to -120° allows for a better complementary effect between the branches containing the first and second combining points, thereby ensuring the performance of the power amplifier circuit.

[0023] In one possible implementation, the second and third combining points are in phase. In another possible implementation, the second and third combining points are coupled via traces, or the second and third combining points coincide. This eliminates the need for an impedance transformer between the second and third combining points, simplifying the power amplifier circuit structure.

[0024] In one possible implementation, the power amplifier circuit further includes a fifth impedance matching network coupled between the first combining point and the RF output. The fifth impedance matching network is used to match the load impedance to the required impedance point, thereby improving the efficiency of the power amplifier circuit.

[0025] In one possible implementation, the power amplifier circuit including the first branch, second branch, third branch, and fourth branch may further include a first cascaded power amplifier coupled in series with the second power divider. The power amplifier circuit, including multiple cascaded power amplifiers, can increase the gain of the power amplifier circuit.

[0026] In one possible implementation, the first cascaded power amplifier includes a first sub-power amplifier and a second sub-power amplifier. The first sub-power amplifier is coupled between the output of the third power divider and the input of the first power divider, and the second sub-power amplifier is coupled between the output of the fourth power divider and the input of the third power divider. Since the first power divider itself has insertion loss, it requires relatively high power. Therefore, placing the first cascaded power amplifier at the output of the first power divider can reduce the power demand on the first cascaded power amplifier, thereby improving the efficiency of the power amplifier circuit.

[0027] In one possible implementation, the power amplifier circuit further includes a second cascaded power amplifier coupled between the RF input and the second power divider input. The power amplifier circuit, comprising multiple cascaded power amplifiers, can increase the gain of the power amplifier.

[0028] In one possible implementation, the power amplifier circuit including the first and second branches may further include a third cascaded power amplifier, which is coupled in series with the first power divider. The power amplifier circuit may include multiple cascaded power amplifiers to increase the gain of the power amplifier circuit.

[0029] In one possible implementation, the RF input is used to transmit a broadband signal, which is an RF signal with a relative bandwidth greater than 20%. In broadband scenarios, the power amplifier circuit provided in this application embodiment still exhibits superior saturation power and saturation efficiency.

[0030] In one possible implementation, the first and second power divider outputs have a phase difference. Alternatively, the third and fourth power divider outputs have a phase difference. Alternatively, the fifth and sixth power divider outputs have a phase difference. Alternatively, the first power divider further includes a seventh power divider output coupled to a reference ground voltage terminal. Alternatively, the second power divider further includes an eighth power divider output coupled to a reference ground voltage terminal. Alternatively, the third power divider further includes a ninth power divider output coupled to a reference ground voltage terminal. Alternatively, the power amplifier circuit further includes a first resistor coupled between the seventh power divider output and the reference ground voltage terminal. Alternatively, the power amplifier circuit further includes a second resistor coupled between the eighth power divider output and the reference ground voltage terminal. Alternatively, the power amplifier circuit further includes a third resistor coupled between the ninth power divider output and the reference ground voltage terminal. This is a structurally simple implementation.

[0031] A second aspect of this application provides a radio frequency (RF) front-end module, including: a substrate and a power amplifier circuit; the power amplifier circuit includes the power amplifier circuit of any one of the first aspects; the power amplifier circuit is disposed on the substrate. The RF front-end module provided in the second aspect of this application includes the power amplifier circuit of the first aspect, and its beneficial effects are the same as those of the power amplifier circuit, which will not be repeated here.

[0032] In one possible implementation, the RF front-end module further includes a low-noise amplifier circuit disposed on the substrate. The power amplifier circuit and the low-noise amplifier circuit can be integrated on the same substrate.

[0033] In one possible implementation, the RF front-end module also includes a filter; the RF output of the power amplifier circuit is coupled to the input of the filter. The power amplifier circuit and the filter can be integrated on the same substrate.

[0034] A third aspect of this application provides a communication device including a radio frequency (RF) front-end module and an antenna, as described in any of the second aspects, wherein the antenna is coupled to the RF front-end module. The communication device provided in the third aspect of this application includes the RF front-end module of the second aspect, and its beneficial effects are the same as those of the RF front-end module, which will not be repeated here. Attached Figure Description

[0035] Figure 1 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0036] Figure 2 is a structural schematic diagram of an RF front-end module provided in an embodiment of this application;

[0037] Figures 3A-3C are schematic diagrams of the topology of a power amplifier circuit;

[0038] Figures 4A-4C are schematic diagrams of a power amplifier circuit provided in an embodiment of this application;

[0039] Figure 5A is a graph showing the effect of second harmonic impedance on the saturation power of a power amplifier circuit according to an embodiment of this application.

[0040] Figure 5B is a graph showing the effect of second harmonic impedance on the saturation efficiency of a power amplifier circuit according to an embodiment of this application.

[0041] Figure 6 is a schematic diagram of another power amplifier circuit provided in an embodiment of this application;

[0042] Figures 7A and 7B are schematic diagrams of another power amplifier circuit provided in the embodiments of this application;

[0043] Figures 8A-8F are schematic diagrams of another power amplifier circuit provided in the embodiments of this application;

[0044] Figures 9A and 9B are schematic diagrams of another power amplifier circuit provided in the embodiments of this application;

[0045] Figure 10 is a schematic diagram of another power amplifier circuit provided in an embodiment of this application;

[0046] Figures 11A-11C are schematic diagrams of another power amplifier circuit provided in the embodiments of this application;

[0047] Figure 12 is a schematic diagram of the layout of a power amplifier circuit provided in an embodiment of this application. Detailed Implementation

[0048] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0049] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0050] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0051] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupling" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0052] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0053] The technical solution of this application can be applied to various communication devices that include power amplifiers. These communication devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted. They can also be deployed on water (such as ships) or in the air (e.g., on airplanes, balloons, and satellites). For example, the channel device can be a terminal or a base station. For example, the terminal includes, but is not limited to: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, etc.), in-vehicle devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flying equipment (such as smart robots, hot air balloons, drones, airplanes), radio frequency front-end modules, etc.

[0054] Figure 1 is a schematic diagram of the structure of a communication device provided in an embodiment of this application.

[0055] In this embodiment of the application, the communication device is described using a mobile phone as an example. The communication device includes: a radio frequency (RF) front-end module 101, a memory 102, a processor 103, a sensor component 104, a multimedia component 105, a power supply component 106, and an input / output interface 107.

[0056] The following is a detailed introduction to the various components of this mobile phone, with reference to Figure 1:

[0057] The RF front-end module 101 can be used to receive and send signals during information transmission or calls. In particular, it receives downlink information from the communication device, processes it with the processor 103, and sends uplink data to the communication device.

[0058] The memory 102 can be used to store data, software programs, and modules. The mobile phone may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0059] The processor 103 is the control center of the mobile phone. It connects to various parts of the device through various interfaces and lines. By running or executing software programs and / or modules stored in the memory 102, and by calling data stored in the memory 102, it performs various functions and processes data of the mobile phone, thereby controlling the mobile phone as a whole. The processor 103 may include, for example, an application processor and a baseband processor.

[0060] Sensor assembly 104 includes one or more sensors for providing various aspects of the mobile phone's status assessment. Sensor assembly 104 may include light sensors, accelerometers, gyroscopes, magnetometers, pressure sensors, or temperature sensors, etc., and can detect the phone's acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes, etc. Furthermore, sensor assembly 104 may also include light sensors, such as CMOS or CCD image sensors, for use in imaging applications.

[0061] The multimedia component 105 provides a screen that serves as an output interface between the mobile phone and the user. This screen can be a touch panel, and when it is a touch panel, it can be implemented as a touchscreen to receive input signals from the user. Furthermore, the multimedia component 105 also includes at least one camera; for example, it includes a front-facing camera and / or a rear-facing camera.

[0062] The power supply component 106 is used to provide power to the various components of the mobile phone. The power supply component 106 may include a power management system, one or more power supplies, and other components associated with the generation, management and distribution of power by the mobile phone.

[0063] Input / output interface 107 provides an interface between processor 103 and peripheral interface modules, such as keyboards and mice.

[0064] Although not shown, the mobile phone may also include audio components and communication modules, such as audio components including a microphone and a speaker, and communication modules including one or more of the following: wireless fidelity (WiFi) module, Bluetooth module, near field communication (NFC) module, global navigation satellite system (GNSS) module, or frequency modulation (FM) module. Further details are omitted here. Those skilled in the art will understand that the mobile phone structure shown in Figure 1 does not constitute a limitation on the mobile phone and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0065] Figure 2 is a structural schematic diagram of an RF front-end module provided in an embodiment of this application.

[0066] Typically, the RF front-end module 101 includes, but is not limited to, radio frequency switches, duplexers, filters, power amplifier circuits (PA), and low noise amplifier circuits (LNA). For example, as shown in Figure 2, the RF front-end module 101 may include: a radio frequency switch, a duplexer, a filter, a power amplifier circuit (PA), and a low noise amplifier (LNA). For instance, the RF front-end module 101 includes a substrate, and one or more of the power amplifier circuit (PA), the low noise amplifier (LNA), the radio frequency switch, the duplexer, and the filter are disposed on the substrate.

[0067] The RF front-end module 101 may include a transmit channel and a receive channel. The transmit channel includes a power amplifier circuit PA and a transmit channel filter. The RF output terminal of the power amplifier circuit PA is coupled to the input terminal of the transmit channel filter. The power amplifier circuit PA is used to amplify the RF signal of the transmit channel, and the transmit channel filter is used to filter the signal of the transmit channel. For example, the RF output terminal of the power amplifier circuit PA is coupled to the input terminal of the transmit channel filter.

[0068] The receiving channel includes a low-noise amplifier (LNA) and a receiving channel filter. The output of the receiving channel filter is coupled to the RF input of the LNA. The LNA amplifies the RF signal from the receiving channel, and the receiving channel filter filters the signal. For example, the RF input of the LNA is coupled to the output of the receiving channel filter.

[0069] A duplexer is used for duplex switching in a frequency division duplex system and for filtering the radio frequency signals of the receive / transmit channel. An RF switch is used for switching between the receive and transmit channels.

[0070] The baseband signal is transmitted to the transmit channel via the transceiver. The transmit channel amplifies the received RF signal and outputs it to the antenna, which then transmits it. The power amplifier circuit PA is responsible for amplifying the RF signal from the transmit channel, and the transmit channel filter is responsible for filtering the RF signal from the transmit channel.

[0071] It should be clarified that when an electronic device includes multiple antennas, one antenna may correspond to one power amplifier circuit PA, one antenna may correspond to multiple power amplifier circuits PA, or multiple antennas may share one power amplifier circuit PA. The application scenarios in the related technologies are all applicable to the embodiments of this application.

[0072] The receiving channel receives radio frequency (RF) signals from the antenna. These RF signals are amplified by the receiving channel and then output, before being transmitted to the baseband via a transceiver. A low-noise amplifier (LNA) amplifies the RF signals from the receiving channel, and a receiving channel filter filters the RF signals from the receiving channel. Furthermore, the antenna frequencies applicable to this embodiment may include frequency bands with relatively high bandwidth requirements, such as the n77 band. Of course, other frequency bands, such as Wi-Fi bands (e.g., 2.4GHz, 5GHz), can also be applied.

[0073] With the development of mobile communication technology, communication equipment has increasingly higher requirements for the efficiency of power amplifier circuits (PA). Load modulation power amplifiers have gradually become an essential architecture for terminal equipment. Load modulation power amplifiers must not only control the position of the fundamental impedance, but also the position of the harmonic impedance in order to achieve high efficiency performance of the power amplifier.

[0074] Figures 3A-3C are schematic diagrams of the topology of a power amplifier circuit.

[0075] The Doherty architecture is a circuit architecture that improves the efficiency of power amplifier circuits (PAs) under back-off power. In some structures, in the traditional Doherty architecture power amplifier circuit (PA, which can also be called Doherty power amplifier circuit in the industry), only the fundamental impedance is considered, and the harmonic impedance is not considered.

[0076] In some embodiments, as shown in FIG3A, the power amplifier circuit PA includes an RF input terminal RFI, an RF output terminal RFO, a power splitter (PS), a main power amplifier M, a peak power amplifier P, an inductor L, a capacitor C, and an impedance tuning module. An inductor L is set in the main power amplifier branch of the power amplifier circuit PA to adjust the fundamental impedance, and a capacitor C is set in the peak power amplifier branch to adjust the fundamental impedance.

[0077] In the architecture shown in Figure 3A, the power amplifier circuit A only considers the fundamental impedance and does not consider the harmonic impedance, which affects the saturation power and saturation efficiency of the power amplifier circuit PA.

[0078] In some embodiments, as shown in FIG3B, the power amplifier circuit PA includes an RF input terminal RFI, an RF output terminal RFO, a power divider PS, a main power amplifier M, a peak power amplifier P, a 90° phase delay line, a capacitor C, and an impedance tuning module. A capacitor C connected in parallel to ground is placed in the main power amplifier branch of the power amplifier circuit PA. The capacitor C is coupled between the main power amplifier M and the 90° phase delay line. The capacitor C and the 90° phase delay line are used together to adjust the fundamental impedance and harmonic impedance of the power amplifier circuit PA.

[0079] For example, based on the topology shown in Figure 3B, when the power amplifier circuit PA does not include capacitor C, the fundamental impedance of the power amplifier circuit PA is Z. l After adding a parallel capacitor C, the fundamental impedance of the power amplifier circuit PA becomes... Among them, Z C The impedance Z of the parallel capacitor C =jw*c. w is the frequency, and c is the capacitance of capacitor C. Connecting capacitor C in parallel allows for adjustment of the harmonic impedance, but it will cause a change in the fundamental impedance.

[0080] That is, in the topology shown in Figure 3B, capacitor C, while controlling the harmonic impedance, also influences and changes the fundamental impedance. If capacitor C is set to satisfy the target value for the harmonic impedance, the fundamental impedance will deviate significantly from the target value, resulting in performance degradation. Conversely, if the fundamental impedance is set to satisfy the target value, the harmonic impedance will deviate significantly from the target value, also resulting in performance degradation. The fundamental and harmonic impedances of the power amplifier circuit PA influence each other, and only one of them can satisfy the target value, preventing further optimization of the saturation power and saturation efficiency of the power amplifier circuit PA.

[0081] In some embodiments, as shown in FIG3C, the power amplifier circuit PA includes an RF input terminal RFI, an RF output terminal RFO, a power divider PS, a main power amplifier M, a peak power amplifier P, a 90° phase delay line, a stub, and an impedance tuning module. A parallel stub is provided in the main power amplifier branch of the power amplifier circuit PA. The stub is coupled between the main power amplifier M and the 90° phase delay line. The stub and the 90° phase delay line are used together to adjust the fundamental impedance and harmonic impedance of the power amplifier circuit PA.

[0082] Short stubs can adjust harmonic impedance to ensure the power amplifier (PA) circuit's harmonic impedance meets target values. However, short stubs also affect the PA's fundamental impedance, causing the harmonic impedance to meet the target value while the fundamental impedance does not. Adjusting the fundamental impedance, in turn, causes the set short stub to fail to meet the harmonic impedance target value. That is, in the topology shown in Figure 3C, the PA's fundamental and harmonic impedances influence each other, with only one meeting the target value, preventing further optimization of the PA's saturation power and efficiency. Furthermore, in sub-7GHz frequency bands, the stub length is approximately 1 / 8 of the fundamental frequency wavelength. For example, in the 3.75GHz band, the stub length is around 6mm. The relatively long stub length is unsuitable for end-product applications. Additionally, short stubs are narrowband structures, unsuitable for broadband applications (such as the n77 band).

[0083] This application provides a power amplifier circuit PA that adjusts the fundamental impedance and harmonic impedance through an impedance network, while also enabling independent adjustment of the fundamental and harmonic impedances. This allows the adjustment of harmonic impedances over a wide bandwidth to not affect the fundamental impedance, ensuring that both the fundamental and harmonic impedances reach their target values, thereby optimizing the saturation power and saturation efficiency of the power amplifier circuit PA.

[0084] Figures 4A-4C are schematic diagrams of a power amplifier circuit provided in an embodiment of this application.

[0085] This application provides a power amplifier circuit PA, as shown in Figure 4A. The power amplifier circuit PA includes an RF input terminal RFI, an RF output terminal RFO, a first power splitter PS1, a first branch A1, a second branch A2, and a first combining point Q1. The first combining point Q1 is coupled to the RF output terminal RFO. The first combining point Q1 and the RF output terminal RFO can be the same endpoint, or they can be coupled through a trace. Other device structures can also be arranged between the first combining point Q1 and the RF output terminal RFO. Figure 4A is only one illustration.

[0086] Before introducing the power amplifier circuit provided in the embodiments of this application, let's briefly introduce the concepts of a few terms.

[0087] The power amplifier, or simply power amplifier, is the main amplifier of the RF front-end module 101. It converts low-power signals from communication and radar equipment into high-power transmission signals that are sent to the antenna. The goal of the power amplifier is to increase the signal gain to a high power level without degrading the signal quality.

[0088] A power divider, or simply power splitter, is a device that splits the energy of one input signal into two or more outputs of equal or unequal energy. Conversely, it can also combine the energy of multiple signals into one output, in which case it can also be called a combiner.

[0089] The power amplifier circuit PA provided in this application embodiment can be understood as a Doherty circuit, requiring two amplifiers for efficient operation and complete optimization of separation, matching combination, and phase to achieve the desired result and improve efficiency. The power amplifier circuit PA is, for example, a Doherty circuit using out-of-phase technology, where the signals output by the first amplifier P1 and the second amplifier P2 are out of phase.

[0090] Regarding the structure of the power amplifier circuit PA, the first power divider PS1 includes a first power divider input terminal i1, a first power divider output terminal o1, and a second power divider output terminal o2. The first power divider input terminal i1 is coupled to the radio frequency input terminal RFI. In some embodiments, the first power divider PS1 further includes a seventh power divider output terminal o7, for example, the seventh power divider output terminal o7 is coupled to the reference ground voltage terminal GND.

[0091] For example, as shown in Figure 4A, the first power divider input terminal i1 and the first power divider output terminal o1 are in phase, the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference, and the second power divider output terminal o2 and the seventh power divider output terminal o7 are in phase.

[0092] The same phase mentioned in the embodiments of this application is not limited to absolute sameness. Approximate sameness within the process error range (e.g., a phase difference of ±5°) also falls under the category of the same phase in the embodiments of this application.

[0093] Of course, the phases of the first power divider input terminal i1 and the first power divider output terminal o1 can also be different. Therefore, the phases of the corresponding second power divider output terminal o2 and the seventh power divider output terminal o7 will also be different. For example, if the phases of the first power divider input terminal i1 and the first power divider output terminal o1 differ by 10° or 20°, the phases of the corresponding second power divider output terminal o2 and the seventh power divider output terminal o7 will also differ by 10° or 20°. This embodiment is merely illustrative, using the example of the first power divider input terminal i1 and the first power divider output terminal o1 having the same phase, and the second power divider output terminal o2 and the seventh power divider output terminal o7 having the same phase; it does not impose any limitations.

[0094] Alternatively, as shown in Figure 4B, the first power divider input terminal i1 and the second power divider output terminal o2 are in phase, the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference, and the first power divider output terminal o1 and the seventh power divider output terminal o7 are in phase.

[0095] Optionally, the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference of 60° to 120° or -60° to -120°.

[0096] For example, the phase of the first power divider output terminal o1 leads the phase of the second power divider output terminal o2, and the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference of 60° to 120°.

[0097] The signal at the first power divider input terminal i1 is coupled to the first power divider output terminal o1, and the divided signal is transmitted to the second power divider output terminal o2 via a phase delay line.

[0098] For example, the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference of 70°, 80°, 90°, 100° and 110°.

[0099] Alternatively, for example, the phase of the first power divider output terminal o1 is delayed relative to the phase of the second power divider output terminal o2, and the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference of -60° to -120°.

[0100] The signal at the first power divider input terminal i1 is coupled to the second power divider output terminal o2, and the divided signal is transmitted to the first power divider output terminal o1 via a phase delay line.

[0101] For example, the first power divider output terminal o1 and the second power divider output terminal o2 have a phase difference of -70°, -80°, -90°, -100°, and -110°.

[0102] The first power divider PS1 is used to distribute the signal received by the radio frequency input terminal RFI to the first branch A1 and the second branch A2. The structure of the first power divider PS1 is not limited in this application embodiment, and the above is only an illustration.

[0103] The following illustration uses the example of a first power divider PS1 being a 90° power divider, also called a 90° coupler or a 90° bridge, with the phase of the second power divider output terminal o2 delayed by 90° (-90°) relative to the phase of the first power divider output terminal o1. For example, the phase of the first power divider output terminal o1 is 0°, and the phase of the second power divider output terminal o2 is -90°. Of course, the phase shown in this embodiment is merely illustrative and not intended to limit the scope. For example, a phase of 10° for the first power divider output terminal o1 and a phase of -80° for the second power divider output terminal o2 is also a possible implementation.

[0104] In some embodiments, as shown in FIG4A, the first branch A1 includes a first amplifier P1 and a first impedance matching network MAT1, the first impedance matching network MAT1 including a first capacitor C1 and a first inductor L1. The first terminal (e.g., the input terminal) of the first amplifier P1 is coupled to the first power divider output terminal o1, and the first capacitor C1 and the first inductor L1 are coupled in series between the second terminal (e.g., the output terminal) of the first amplifier P1 and the first combining point Q1. Either the first capacitor C1 or the first inductor L1 can be coupled to the second terminal of the first amplifier P1; FIG4A is merely an illustration and does not constitute any limitation. The first branch A1 can be understood, for example, as the main power amplifier branch of the power amplifier circuit PA, and the first amplifier P1 can be understood, for example, as the main amplifier (or main PA, carrier amplifier).

[0105] The second branch A2 includes a second amplifier P2 and a second impedance matching network MAT2, which includes a second capacitor C2. The first terminal (e.g., the input terminal) of the second amplifier P2 is coupled to the second power divider output terminal O2, and the second capacitor C2 is coupled between the second terminal (e.g., the output terminal) of the second amplifier P2 and the first combining point Q1. The second branch A2 can be understood, for example, as the peak power amplifier branch of the power amplifier circuit PA, and the second amplifier P2 can be understood, for example, as a peak amplifier (or PAK PA).

[0106] In some embodiments, as shown in FIG4B, the first branch A1 includes a first amplifier P1 and a first impedance matching network MAT1. The first impedance matching network MAT1 includes a first capacitor C1 and a first inductor L1 coupled in series. The first terminal (e.g., the input terminal) of the first amplifier P1 is coupled to the first power divider output terminal O1. The first capacitor C1 and the first inductor L1 are coupled in series between the second terminal (e.g., the output terminal) of the first amplifier P1 and the first combining point Q1. Either the first capacitor C1 or the first inductor L1 can be coupled to the second terminal of the first amplifier P1. FIG4B is only an illustration and is not intended to limit the specific implementation. The first branch A1 can be understood, for example, as the peak power amplifier branch of the power amplifier circuit PA, and the first amplifier P1 can be understood, for example, as a peak amplifier.

[0107] The second branch A2 includes a second amplifier P2 and a second impedance matching network MAT2, which includes a second inductor L2. The first terminal (e.g., the input terminal) of the second amplifier P2 is coupled to the second power divider output terminal O2, and the second inductor L2 is coupled between the second terminal (e.g., the output terminal) of the second amplifier P2 and the first combining point Q1. The second branch A2 can be understood, for example, as the main power amplifier branch of the power amplifier circuit PA, and the second amplifier P2 can be understood, for example, as the main amplifier.

[0108] In some embodiments, as shown in FIG4C, the first branch A1 includes a first amplifier P1 and a first impedance matching network MAT1, the first impedance matching network MAT1 including a first capacitor C1 and a first inductor L1. A first terminal (e.g., the input terminal) of the first amplifier P1 is coupled to a first power divider output terminal O1, and the first capacitor C1 and the first inductor L1 are coupled in series between a second terminal (e.g., the output terminal) of the first amplifier P1 and a first combining point Q1. Either the first capacitor C1 or the first inductor L1 can be coupled to the second terminal of the first amplifier P1; FIG4C is merely an illustration and does not constitute any limitation. The first branch A1 can be understood, for example, as the main power amplifier branch of the power amplifier circuit PA, and the first amplifier P1 can be understood, for example, as the main amplifier.

[0109] The second branch A2 includes a second amplifier P2 and a second impedance matching network MAT2, which includes a second capacitor C2 and a second inductor L2. The first terminal (e.g., the input terminal) of the second amplifier P2 is coupled to the second power divider output terminal O2. The second capacitor C2 and the second inductor L2 are coupled in series between the second terminal (e.g., the output terminal) of the second amplifier P2 and the first combining point Q1. Alternatively, the second capacitor C2 can be coupled to the second terminal of the second amplifier P2, or the second inductor L2 can be coupled to the second terminal of the second amplifier P2. Figure 4C is only one illustration and is not intended to limit the interpretation. The second branch A2 can be understood, for example, as the peak power amplifier branch of the power amplifier circuit PA, and the second amplifier P2 can be understood, for example, as the peak amplifier.

[0110] This application does not limit whether the first branch A1 is the main power amplifier branch or the peak power amplifier branch, nor does it limit the structure of the second impedance matching network MAT2 in the second branch A2. For example, the first branch A1 and the second branch A2 can satisfy the condition that the fundamental impedance of one of the first impedance matching network MAT1 and the second impedance matching network MAT2 is inductive and the fundamental impedance of the other is capacitive.

[0111] It should be understood that the main amplifier and the peak amplifier can have the same structure, distinguished by the different matching networks they are coupled to. Therefore, the signal received by the first branch A1 and the signal received by the second branch A2 have the aforementioned phase difference. In some embodiments, the phase difference between the second impedance matching network MAT2 and the first impedance matching network MAT1 is 60° to 120°.

[0112] For example, in some embodiments, the phase difference between the first power divider output terminal o1 and the second power divider output terminal o2 is the same as the phase difference between the second impedance matching network MAT2 and the first impedance matching network MAT1. Optionally, the phase difference between the second impedance matching network MAT2 and the first impedance matching network MAT1 is 90°.

[0113] Based on the impedance matching network composed of series capacitors and inductors, the fundamental impedance of the matching network is calculated by the following formula (1), and the second harmonic impedance of the matching network is calculated by the following formula (2).

[0114] Where Zm is the fundamental impedance, Zm2 is the second harmonic impedance, j represents the imaginary part, ω is the angular frequency, ω=2π*f, and f is the operating frequency. l is the inductance value, and c is the capacitance value.

[0115] Taking the first branch A1 as an example, by connecting the first capacitor C1 and the first inductor L1 in series, the fundamental impedance Zm can be fixed while the second harmonic impedance Zm2 can be adjusted. By reasonably selecting the capacitance value of the first capacitor C1 or the inductance value of the first inductor L1, both the fundamental impedance Zm and the second harmonic impedance Zm2 of the first branch A1 can meet the requirements.

[0116] For example, let the desired fundamental impedance in the first branch A1 be Zm = j*ω*l0. Substituting into the above formula (1), we can obtain formula (3). Wherein, l1 is the inductance of the first inductor L1, and c1 is the capacitance of the first capacitor C1. l0 can be determined according to the target value of the fundamental impedance Zm.

[0117] Formula (3) can be used to obtain Formula (4), which determines the capacitance value c1 of the first capacitor C1 in the first branch A1.

[0118] Substituting formula (4) into formula (2) above, we can obtain the second harmonic impedance Zm2 as shown in formula (5).

[0119] As shown in formula (5), the second harmonic impedance Zm2 changes with the inductance value l1 of the first inductor L1. Adjusting the inductance value l1 of the first inductor L1 using formula (5) allows the second harmonic impedance Zm2 to meet the requirements. Selecting the capacitance value c1 of the first capacitor C1 using formula (4) allows for changes in the inductance value l1 of the first inductor L1, but the fundamental impedance of the first branch A1 remains constant. Therefore, by reasonably setting the inductance value l1 of the first inductor L1 and the capacitance value c1 of the first capacitor C1, both the fundamental impedance Zm and the second harmonic impedance Zm2 in the first branch A1 can meet the requirements, thus enabling the first branch A1 to achieve optimal power amplifier saturation and efficiency.

[0120] Similarly, when the second branch A2 includes a second capacitor C2 and a second inductor L2 coupled in series, the fundamental impedance Zm can be fixed and the second harmonic impedance Zm2 can be adjusted by using the structure of the second capacitor C2 and the second inductor L2 in series. By adjusting the capacitance value of the second capacitor C2 and the inductance value of the second inductor L2, both the fundamental impedance Zm and the second harmonic impedance Zm2 of the second branch A2 can meet the requirements.

[0121] In some embodiments, the first impedance matching network MAT1 and the second impedance matching network MAT2 are networks with different matching characteristics. For example, one of the first impedance matching network MAT1 and the second impedance matching network MAT2 has an inductive fundamental impedance, while the other has a capacitive fundamental impedance.

[0122] For example, the capacitance of the first capacitor C1 is different from that of the second capacitor C2. Or, for example, the inductance of the first inductor L1 is different from that of the second inductor L2.

[0123] In this embodiment, the values ​​of the first capacitor C1 and the first inductor L1 in the first impedance matching network MAT1, and the values ​​of the second capacitor C2 and the second inductor L2 in the second impedance matching network MAT2 are not limited. As long as the phase of the signal output by the first impedance matching network MAT1 is the same as the phase of the signal output by the second impedance matching network MAT2, but the matching characteristics are different.

[0124] In some embodiments, the first impedance matching network MAT1 includes an inductive network, and the second impedance matching network MAT2 includes a capacitive network. For example, the fundamental impedance of the first capacitor C1 and the first inductor L1 in the first branch A1 is inductive, and the fundamental impedance of the second capacitor C2 and the second inductor L2 in the second branch A2 is capacitive. Alternatively, the fundamental impedance of the second capacitor C2 in the second branch A2 is capacitive.

[0125] For example, if the impedance of the first inductor L1 is positive, the impedance of the first capacitor C1 is negative, and the fundamental impedance Zm of the first branch A1 is positive, then the fundamental impedance of the first branch A1 is inductive. If the fundamental impedance Zm of the first branch A1 is negative, then the fundamental impedance of the first branch A1 is capacitive. Similarly, if the fundamental impedance Zm of the second branch A2 is positive, then the fundamental impedance of the second branch A2 is inductive. If the fundamental impedance Zm of the second branch A2 is negative, then the fundamental impedance of the second branch A2 is capacitive. By appropriately setting the capacitance values ​​of the first capacitor C1, the second capacitor C2, the inductance values ​​of the first inductor L1 and the second inductor L2, the fundamental impedance Zm of the first branch A1 and the second branch A2 can exhibit different characteristics.

[0126] In other embodiments, the first impedance matching network MAT1 includes a capacitive network, and the second impedance matching network MAT2 includes an inductive network. For example, the fundamental impedance of the first capacitor C1 and the first inductor L1 in the first branch A1 is capacitive, and the fundamental impedance of the second capacitor C2 and the second inductor L2 in the second branch A2 is inductive. Alternatively, the fundamental impedance of the second inductor L2 in the second branch A2 is inductive.

[0127] In some embodiments, the inductance value of the first inductor L1 or the inductance value of the second inductor L2 is greater than 0 and less than 3NH.

[0128] For example, the value of the first inductor L1 can be 0.01NH, 0.2NH, 0.3NH, 0.4NH, 0.5NH, 0.6NH, 0.7NH, 0.8NH, 0.9NH, 1.0NH, 1.1NH, 1.2NH, 1.3NH, 1.4NH, 1.5NH, 1.6NH, 1.7NH, 1.8NH, 1.9NH, 2.0NH, 2.1NH, 2.2NH, 2.3NH, 2.4NH, 2.5NH, 2.6NH, 2.7NH, 2.8NH, 2.9NH, or 3NH.

[0129] In some embodiments, the inductance of the second inductor L2 is greater than 0 and less than 3NH.

[0130] For example, the value of the first inductor L1 can be 0.01NH, 0.2NH, 0.3NH, 0.4NH, 0.5NH, 0.6NH, 0.7NH, 0.8NH, 0.9NH, 1.0NH, 1.1NH, 1.2NH, 1.3NH, 1.4NH, 1.5NH, 1.6NH, 1.7NH, 1.8NH, 1.9NH, 2.0NH, 2.1NH, 2.2NH, 2.3NH, 2.4NH, 2.5NH, 2.6NH, 2.7NH, 2.8NH, 2.9NH, or 3NH.

[0131] By limiting the value of the first inductor L1 or the second inductor L2 to within 3NH, the first branch A1 and the second branch A2 can have better performance. Furthermore, the inductance value of the first inductor L1 or the second inductor L2 is relatively small, and the area occupied by the first inductor L1 or the second inductor L2 is relatively small, making it suitable for application scenarios in terminal devices.

[0132] In some embodiments, the capacitance of the first capacitor C1 is greater than 0 and less than 10pF.

[0133] For example, the capacitance of the first capacitor C1 is 0.01pF, 0.1pF, 0.5pF, 1.0pF, 1.5pF, 2.0pF, 2.5pF, 3.0pF, 3.5pF, 4.0pF, 4.5pF, 5.0pF, 5.5pF, 6.0pF, 6.5pF, 7.0pF, 7.5pF, 8.0pF, 8.5pF, 9.0pF, 9.5pF, or 10pF.

[0134] In some embodiments, the capacitance of the second capacitor C2 is greater than 0 and less than 10pF.

[0135] For example, the capacitance of the second capacitor C2 is 0.01pF, 0.1pF, 0.5pF, 1.0pF, 1.5pF, 2.0pF, 2.5pF, 3.0pF, 3.5pF, 4.0pF, 4.5pF, 5.0pF, 5.5pF, 6.0pF, 6.5pF, 7.0pF, 7.5pF, 8.0pF, 8.5pF, 9.0pF, 9.5pF, or 10pF.

[0136] By limiting the value of the first capacitor C1 or the second capacitor C2 to within 10pF, the first branch A1 and the second branch A2 can have better performance.

[0137] For example, let the relationship between the first inductor L1 and the first capacitor C1 in series satisfy formula (4), and l0 = 0.2nH. The inductance value l1 of the first inductor L1 ranges from 0.3nH to 20nH. Simulation shows that as the inductance value l1 of the first inductor L1 changes, the fundamental impedance Zm remains constant. As the inductance value l1 of the first inductor L1 changes, the second harmonic impedance Zm2 changes along the upper half-circle of the Smith chart. That is, as the inductance value l1 of the first inductor L1 changes, the fundamental impedance Zm remains constant, while the second harmonic impedance Zm2 changes sequentially along the half-circle. Thus, the fundamental impedance Zm can remain constant, and the position of the second harmonic impedance Zm2 that meets the requirements can be selected by adjusting the values ​​of the first inductor L1 and the first capacitor C1. Applying the first inductor L1 with a determined inductance value and the first capacitor C1 with a determined capacitance value to the power amplifier circuit PA can give the power amplifier circuit PA better saturation power and saturation efficiency.

[0138] Figure 5A is a graph showing the effect of second harmonic impedance on the saturation power of a power amplifier circuit according to an embodiment of this application, and Figure 5B is a graph showing the effect of second harmonic impedance on the saturation efficiency of a power amplifier circuit according to an embodiment of this application.

[0139] In Figure 5A, the horizontal axis represents output power, and the vertical axis represents gain. The dashed line in Figure 5A represents the RF performance of the second branch A2 with only a 4.5pF capacitor in series. The solid line in Figure 5A represents the RF performance of the second branch A2 with a 3pF capacitor and a 0.2nH inductor in series. Substituting into the above formulas (1) and (2), it can be seen that the fundamental impedance Zm is equal in both cases, but the second harmonic impedance Zm2 is not equal. The dashed line indicates that the fundamental impedance Zm meets the requirements, but the second harmonic impedance Zm2 does not meet the requirements. The solid line indicates that both the fundamental impedance Zm and the second harmonic impedance Zm2 meet the requirements. As can be seen from Figure 5A, different second harmonic impedances Zm2 have a certain impact on the saturation power of the power amplifier circuit PA. When the second harmonic impedance Zm2 meets the requirements, the saturation power of the power amplifier circuit PA can be increased to a certain extent (e.g., 1.5dB).

[0140] In Figure 5B, the horizontal axis represents output power, and the vertical axis represents efficiency. The dashed line in Figure 5B indicates the RF performance when the second branch A2 is connected in series with only a 4.5pF capacitor. The solid line in Figure 5B indicates the RF performance when the second branch A2 is connected in series with a 3pF capacitor and a 0.2nH inductor. As can be seen from Figure 5B, different second harmonic impedances Zm2 have a certain impact on the peak efficiency of the power amplifier circuit PA. When the second harmonic impedance Zm2 meets the requirements, the saturation power of the power amplifier circuit PA can be increased to a certain extent (e.g., more than 5%).

[0141] The power amplifier circuit PA provided in this application embodiment adopts an impedance matching network architecture of capacitor and inductor series connection in at least the first branch A1 (which can be the main power amplifier branch or the peak power amplifier branch). In this architecture, the fundamental impedance and harmonic impedance of the first branch A1 are determined by the series capacitor and inductor network. With properly selected values ​​for the first capacitor C1 and the first inductor L1, the fundamental impedance Zm and the second harmonic impedance Zm2 in the first branch A1 can respectively meet the requirements, thereby giving the power amplifier circuit PA superior saturation power and saturation efficiency. When the second branch A2 also includes a second capacitor C2 and a second inductor L2 connected in series, the fundamental impedance Zm and the second harmonic impedance Zm2 in the second branch A2 can also respectively meet the requirements, further optimizing the saturation power and saturation efficiency of the power amplifier circuit PA. Furthermore, the capacitor and inductor are broadband structures, suitable for broadband (e.g., n77 band) applications.

[0142] Figure 6 is a schematic diagram of another power amplifier circuit provided in an embodiment of this application.

[0143] In some embodiments, as shown in FIG6, the power amplifier circuit PA further includes a first resistor R1, which is coupled between the seventh power divider output terminal o7 and the reference ground voltage terminal GND.

[0144] In some embodiments, the power amplifier circuit PA further includes a fifth impedance matching network MAT5, which is coupled between the first combining point Q1 and the RF output terminal RFO.

[0145] The fifth impedance matching network MAT5 is used to match the impedance of the load coupled to the RF output RFO to the required impedance point, thereby improving the efficiency of the power amplifier circuit PA. This application does not limit the structure of the fifth impedance matching network MAT5; impedance matching networks in related technologies are applicable to this application.

[0146] Figures 7A and 7B are schematic diagrams of another power amplifier circuit provided in the embodiments of this application.

[0147] In some embodiments, as shown in FIG7A, the power amplifier circuit PA further includes a second power divider PS2, a third power divider PS3, a second combiner Q2, a third combiner Q3, a third branch A3, and a fourth branch A4.

[0148] The second power divider PS2 includes a second power divider input terminal i2, a third power divider output terminal o3, and a fourth power divider output terminal o4. The second power divider input terminal i2 is coupled to the radio frequency input terminal RFI, and the third power divider output terminal o3 is coupled to the first power divider input terminal i1. Optionally, the second power divider PS2 also includes an eighth power divider output terminal o8, which is coupled to the reference ground voltage terminal GND. For example, the power amplifier circuit PA also includes a second resistor R2, which is coupled between the eighth power divider output terminal o8 and the reference ground voltage terminal GND.

[0149] For example, as shown in Figure 7A, the second power divider input terminal i2 and the third power divider output terminal o3 are in phase, the third power divider output terminal o3 and the fourth power divider output terminal o4 have a phase difference, and the fourth power divider output terminal o4 and the eighth power divider output terminal o8 are in phase.

[0150] Of course, the phases of the second power divider input terminal i2 and the third power divider output terminal o3 can also be different. Therefore, the phases of the corresponding fourth power divider output terminal o4 and eighth power divider output terminal o8 will also be different. For example, if the phases of the second power divider input terminal i2 and the third power divider output terminal o3 differ by 10° or 20°, the phases of the corresponding fourth power divider output terminal o4 and eighth power divider output terminal o8 will also differ by 10° or 20°. This embodiment is merely illustrative, using the example of the second power divider input terminal i2 and the third power divider output terminal o3 having the same phase, and the fourth power divider output terminal o4 and the eighth power divider output terminal o8 having the same phase; it does not impose any limitations.

[0151] Alternatively, as shown in Figure 7B, the second power divider input terminal i2 and the fourth power divider output terminal o4 are in phase, the third power divider output terminal o3 and the fourth power divider output terminal o4 have a phase difference, and the third power divider output terminal o3 and the eighth power divider output terminal o8 are in phase.

[0152] Optionally, the third power divider output terminal o3 and the fourth power divider output terminal o4 have a phase difference of 60° to 120° or -60° to -120°.

[0153] It should be noted that the phase of the third power divider output terminal o3 can be delayed by 60° to 120° relative to the phase of the fourth power divider output terminal o4, or the phase of the fourth power divider output terminal o4 can be delayed by 60° to 120° relative to the phase of the third power divider output terminal o3.

[0154] For example, taking Figure 7A as an example, the signal at the second power divider input terminal i2 is coupled to the third power divider output terminal o3, and the divided signal is transmitted to the fourth power divider output terminal o4 via a phase delay line.

[0155] For example, the third power divider output terminal o3 and the fourth power divider output terminal o4 have phase differences of 70°, 80°, 90°, 100° and 110°.

[0156] The third power divider PS3 includes a third power divider input terminal i3, a fifth power divider output terminal o5, and a sixth power divider output terminal o6; the third power divider input terminal i3 is coupled to the fourth power divider output terminal o4. As an example, the third power divider PS3 also includes a ninth power divider output terminal o9. Optionally, the ninth power divider output terminal o9 is coupled to the reference ground voltage terminal GND. For example, the power amplifier circuit PA also includes a third resistor R3, which is coupled between the ninth power divider output terminal o9 and the reference ground voltage terminal GND.

[0157] For example, as shown in Figure 7A, the third power divider input terminal i3 and the fifth power divider output terminal o5 are in phase, the fifth power divider output terminal o5 and the sixth power divider output terminal o6 have a phase difference, and the sixth power divider output terminal o6 and the ninth power divider output terminal o9 are in phase.

[0158] Of course, the phases of the third power divider input terminal i3 and the fifth power divider output terminal o5 can also be different. Therefore, the phases of the corresponding sixth power divider output terminal o6 and ninth power divider output terminal o9 will also be different. For example, if the phases of the third power divider input terminal i3 and the fifth power divider output terminal o5 differ by 10° or 20°, the phases of the corresponding sixth power divider output terminal o6 and ninth power divider output terminal o9 will also differ by 10° or 20°. This embodiment is merely illustrative, using the example of the third power divider input terminal i3 and the fifth power divider output terminal o5 having the same phase, and the sixth power divider output terminal o6 and the ninth power divider output terminal o9 having the same phase; it does not impose any limitations.

[0159] Alternatively, as shown in Figure 7B, the third power divider input terminal i3 and the sixth power divider output terminal o6 are in phase, the fifth power divider output terminal o5 and the sixth power divider output terminal o6 have a phase difference, and the fifth power divider output terminal o5 and the ninth power divider output terminal o9 are in phase.

[0160] Optionally, the fifth power divider output terminal o5 and the sixth power divider output terminal o6 have a phase difference of 60° to 120°.

[0161] It should be noted that the phase of the fifth power divider output terminal o5 can be delayed by 60° to 120° relative to the phase of the sixth power divider output terminal o6, or the phase of the sixth power divider output terminal o6 can be delayed by 60° to 120° relative to the phase of the fifth power divider output terminal o5.

[0162] For example, taking Figure 7A as an example, the signal at the third power divider input terminal i3 is coupled to the fifth power divider output terminal o5, and the divided signal is transmitted to the sixth power divider output terminal o6 via a phase delay line.

[0163] For example, the fifth power divider output terminal o5 and the sixth power divider output terminal o6 have phase differences of 70°, 80°, 90°, 100°, and 110°.

[0164] The following is an illustrative example, using the second power divider PS2 as a 90° power divider, the fourth power divider output terminal o4 having a phase delay of 90° (-90°) relative to the third power divider output terminal o3, the third power divider PS3 as a 90° power divider, and the sixth power divider output terminal o6 having a phase delay of 90° (-90°) relative to the fifth power divider output terminal o5.

[0165] The third branch A3 includes a third amplifier P3 and a third impedance matching network MAT3. The first terminal of the third amplifier P3 is coupled to the sixth power divider output terminal o6. The fourth branch A4 includes a fourth amplifier P4 and a fourth impedance matching network MAT4. The first terminal of the fourth amplifier P4 is coupled to the fifth power divider output terminal o5. An impedance transformer U is coupled between the first combining point Q1 and the third combining point Q3.

[0166] One of the third amplifier P3 and the fourth amplifier P4 is a main power amplifier, and the other is a peak power amplifier. This application does not limit the structure of the third amplifier P3 and the fourth amplifier P4; the structures of main power amplifiers and peak power amplifiers in related technologies are applicable to this application.

[0167] The third impedance matching network MAT3 and the fourth impedance matching network MAT4 can be any impedance matching network in the related art. The third impedance matching network MAT3 and the fourth impedance matching network MAT4 are combined at the second combining point Q2, so the output signals of the third impedance matching network MAT3 and the fourth impedance matching network MAT4 are in phase.

[0168] For example, the third power divider PS3 is a 90° power divider. The phase of the signal received at the third power divider input terminal i3 is -90°, the phase of the signal coupled to the fifth power divider output terminal o5 is -90°, and the phase of the signal received at the sixth power divider output terminal o6 is -180°. Of course, the phase shown in the embodiments of this application is only an illustration and is not intended to limit anything.

[0169] In some embodiments, the phase difference between the signals output by the third impedance matching network MAT3 and the fourth impedance matching network MAT4 is 60° to 120°.

[0170] For example, the fifth power divider output terminal o5 and the sixth power divider output terminal o6 have phase differences of 70°, 80°, 90°, 100°, and 110°.

[0171] In some embodiments, the phase difference between the fifth power divider output terminal o5 and the sixth power divider output terminal o6 is the same as the phase difference between the signals output by the third impedance matching network MAT3 and the fourth impedance matching network MAT4.

[0172] Optionally, the phase difference between the output signal of the fourth impedance matching network MAT4 and the output signal of the third impedance matching network MAT3 is 90°.

[0173] In some embodiments, the third impedance matching network MAT3 and the fourth impedance matching network MAT4 are networks with different matching characteristics. For example, one of the third impedance matching network MAT3 and the fourth impedance matching network MAT4 has an inductive fundamental impedance, while the other has a capacitive fundamental impedance.

[0174] For example, the fourth impedance matching network MAT4 includes an inductive network, and the third impedance matching network MAT3 includes a capacitive network. For instance, the fundamental impedance of the fourth impedance matching network MAT4 in the fourth branch A4 is inductive, and the fundamental impedance of the third impedance matching network MAT3 in the third branch A3 is capacitive.

[0175] In other embodiments, the fourth impedance matching network MAT4 includes a capacitive network, and the third impedance matching network MAT3 includes an inductive network. For example, the fundamental impedance of the fourth impedance matching network MAT4 in the fourth branch A4 is capacitive, and the fundamental impedance of the third impedance matching network MAT3 in the third branch A3 is inductive.

[0176] Figures 8A-8F are schematic diagrams of another power amplifier circuit provided in the embodiments of this application.

[0177] In some embodiments, as shown in FIG8A, the third impedance matching network MAT3 includes a third capacitor C3 coupled between the second terminal of the third amplifier P3 and the second combining point Q2. For example, the branch containing the third impedance matching network MAT3 is the peak power amplifier branch. For instance, the fundamental impedance of the fourth impedance matching network MAT4 is inductive, and the fundamental impedance of the third impedance matching network MAT3 is capacitive.

[0178] In other embodiments, as shown in FIG8B, the third impedance matching network MAT3 includes a third inductor L3 coupled between the second terminal of the third amplifier P3 and the second combining point Q2. For example, the branch containing the third impedance matching network MAT3 is the main power amplifier branch. For instance, the fundamental impedance of the fourth impedance matching network MAT4 is capacitive, and the fundamental impedance of the third impedance matching network MAT3 is inductive.

[0179] In some other embodiments, as shown in FIG8C, the third impedance matching network MAT3 includes a third capacitor C3 and a third inductor L3 series coupled between the second terminal of the third amplifier P3 and the second combining point Q2. For example, the branch containing the third impedance matching network MAT3 is the peak power amplifier branch. For instance, the fundamental impedance of the fourth impedance matching network MAT4 is inductive, and the fundamental impedance of the third impedance matching network MAT3 is capacitive.

[0180] In some embodiments, as shown in FIG8D, the fourth impedance matching network MAT4 includes a fourth capacitor C4 coupled between the second terminal of the fourth amplifier P4 and the second combining point Q2. For example, the branch containing the fourth impedance matching network MAT3 is the peak power amplifier branch. For instance, the fundamental impedance of the fourth impedance matching network MAT4 is capacitive, while the fundamental impedance of the third impedance matching network MAT3 is inductive.

[0181] In other embodiments, as shown in FIG8E, the fourth impedance matching network MAT4 includes four inductors L4 coupled between the second terminal of the fourth amplifier P4 and the second combiner point Q2. For example, the branch containing the fourth impedance matching network MAT3 is the main power amplifier branch. For instance, the fundamental impedance of the fourth impedance matching network MAT4 is inductive, and the fundamental impedance of the third impedance matching network MAT3 is capacitive.

[0182] In some other embodiments, as shown in FIG8C, the fourth impedance matching network MAT4 includes a fourth capacitor C4 and a fourth inductor L4 series coupled between the second terminal of the fourth amplifier P4 and the second combining point Q2. For example, the branch containing the fourth impedance matching network MAT3 is the main power amplifier branch. For instance, the fundamental impedance of the fourth impedance matching network MAT4 is inductive, while the fundamental impedance of the third impedance matching network MAT3 is capacitive.

[0183] Optionally, the capacitance value of the third capacitor C3 is different from that of the fourth capacitor C4. Alternatively, the inductance value of the third inductor L3 is different from that of the fourth inductor L4. This application embodiment does not limit the values ​​of the fourth capacitor C4 and the fourth inductor L4 in the fourth impedance matching network MAT4, nor the values ​​of the third capacitor C3 and the third inductor L3 in the third impedance matching network MAT3, as long as the phase of the signal output by the fourth impedance matching network MAT4 is the same as the phase of the signal output by the third impedance matching network MAT3, but their matching characteristics are different.

[0184] The first impedance matching network MAT1, the second impedance matching network MAT2, the third impedance matching network MAT3, and the fourth impedance matching network MAT4 in the power amplifier circuit PA can be any combination of the above structures, as shown in Figure 8F. It is possible that only the first impedance matching network MAT1 includes a series capacitor and inductor network.

[0185] In some embodiments, the inductance values ​​of the third inductor L3 and the fourth inductor L4 can be referred to the above description of the inductance values ​​of the first inductor L1 and the second inductor L2.

[0186] In some embodiments, the capacitance values ​​of the third capacitor C3 and the fourth capacitor C4 can be referenced to the above descriptions regarding the capacitance values ​​of the first capacitor C1 and the second capacitor C2.

[0187] In some embodiments, as shown in FIG7A, the power amplifier circuit PA further includes an impedance transformer U, which is coupled between the first combining point Q1 and the third combining point Q3, the second combining point Q2 and the third combining point Q3, and the third combining point Q3 is coupled to the RF output terminal RFO. For example, the first combining point Q1 is coupled to the third combining point Q3 after passing through the impedance transformer U, and the second combining point Q2 is coupled to the third combining point Q3 through a trace. Alternatively, the second combining point Q2 and the third combining point Q3 coincide, so that the signals of the branch where the first combining point Q1 is located and the signals of the branch where the second combining point Q2 is located are combined at the third combining point Q3, and the combined signal is transmitted to the RF output terminal RFO.

[0188] In some embodiments, the second merging point Q2 and the third merging point Q3 are in phase.

[0189] In some embodiments, the phase difference between the third merging point Q3 and the first merging point Q1 is 60° to 120° or -60° to -120°.

[0190] For example, the phase change of the impedance transformer U is matched with the phase difference between the third power divider output o3 and the fourth power divider output o4 of the second power divider PS2.

[0191] Optionally, the phase difference between the third merging point Q3 and the first merging point Q1 is 70°, 80°, 90°, 100°, or 110°.

[0192] For example, if the second power divider output terminal o2 is delayed by 90° (-90°) in phase relative to the first power divider output terminal o1, then the third combining point Q3 at both ends of the impedance transformer U is delayed by 90° (-90°) in phase relative to the first combining point Q1.

[0193] For example, the phase difference between the third combining point Q3 and the first combining point Q1 can be the phase difference between the third combining point Q3 and the first combining point Q1 at the center frequency of the operating bandwidth of the power amplifier circuit.

[0194] The phase difference between the third combining point Q3 and the first combining point Q1 affects the impedance transformation capability of the impedance transformer U, thus affecting the complementary effect of the branch containing the first combining point Q1 and the branch containing the second combining point Q2, thereby influencing the output performance of the power amplifier circuit PA. Limiting the phase difference between the third combining point Q3 and the first combining point Q1 to a range of 60°–120° or -60°–-120° allows for a better complementary effect between the branch containing the first combining point Q1 and the branch containing the second combining point Q2, ensuring the performance of the power amplifier circuit PA.

[0195] In some embodiments, the impedance transformer U is a 1 / 4 wavelength transformer, or a 90° delay line.

[0196] In some embodiments, the “1 / 4 wavelength” corresponding to the impedance transformer U is 1 / 4 of the wavelength corresponding to the center frequency of the operating bandwidth.

[0197] As shown in Figure 8C, for example, the impedance transformer U is a "T"-shaped network structure including a fifth inductor L5, a sixth inductor L6, and a fifth capacitor C5. The fifth inductor L5 and the sixth inductor L6 are connected in series between the first junction point Q1 and the third junction point Q3. One end of the fifth capacitor C5 is coupled to the reference ground voltage terminal GND, and the other end of the fifth capacitor C5 is coupled between the fifth inductor L5 and the sixth inductor L6.

[0198] Alternatively, for example, the impedance transformer U is a "π"-type network structure consisting of two capacitors and one inductor.

[0199] In some other embodiments, the power amplifier circuit PA further includes an impedance transformer U, which is disposed between the second combining point Q2 and the third combining point Q3, so as to combine the signals of the branch where the first combining point Q1 is located and the branch where the second combining point Q2 is located at the third combining point Q3, and the combined signal is transmitted to the radio frequency output terminal RFO.

[0200] In some other embodiments, the first combining point Q1 is coupled to the third combining point Q3 after passing through an impedance transformer U, and the second combining point Q2 is coupled to the third combining point Q3 after passing through another impedance transformer, so that the signals of the branch where the first combining point Q1 is located and the branch where the second combining point Q2 is located are combined at the third combining point Q3, and the combined signal is transmitted to the radio frequency output terminal RFO.

[0201] The power amplifier circuit PA includes an impedance transformer U. When the impedance of the load coupled to the RF output RFO changes abruptly, the impedance on the path without impedance transformer U changes abruptly as well, resulting in a decrease in power. However, the impedance on the path with impedance transformer U changes abruptly in the opposite direction under the action of impedance transformer U, resulting in an increase in power. The two paths are combined at the third combining point Q3 for power combining. The combined power is more stable, thus reducing the impact of impedance changes. The two paths can be used as impedance complementary paths. This achieves broadband efficiency and load desensitization without introducing complex, large-area, or high-insertion-loss circuit modules, simplifying the circuit structure of the power amplifier circuit PA and reducing its footprint. It also avoids the insertion loss of complex modules, reduces circuit redundancy, improves the efficiency of the power amplifier circuit PA, and improves the circuit's mismatch resistance at a relatively low cost.

[0202] Figures 9A and 9B are schematic diagrams of another power amplifier circuit provided in the embodiments of this application.

[0203] In some embodiments, as shown in FIG9A, the power amplifier circuit PA includes two cascaded power amplifiers, with FIG8C showing the cascaded power amplifier in the second stage. The power amplifier circuit PA also includes a first cascaded power amplifier PA1 in the first stage. The power amplifier circuit PA includes multiple cascaded power amplifiers, which can increase the gain of the power amplifier circuit PA.

[0204] As shown in Figure 9A, the first cascaded power amplifier PA1 is coupled in series with the second power divider PS2.

[0205] As an example, as shown in Figure 9A, the first cascaded power amplifier PA1 is coupled between the RF input RFI and the second power divider PS2. That is, the first cascaded power amplifier PA1 is located before the input of the second power divider PS2.

[0206] Alternatively, as shown in Figure 9B, the first cascaded power amplifier includes a first sub-power amplifier pa1 and a second sub-power amplifier pa2. The first sub-power amplifier pa1 is coupled between the third power divider output terminal o3 and the first power divider input terminal i1, and the second sub-power amplifier pa2 is coupled between the fourth power divider output terminal o4 and the third power divider input terminal i3. That is, the first cascaded power amplifier pa1 is located at the output terminal of the second power divider PS2.

[0207] Because the second power divider PS2 has insertion loss, it requires relatively high power. Therefore, placing the first cascaded power amplifier PA1 at the output of the second power divider PS2 can reduce the power requirement of the first cascaded power amplifier PA1 and improve the efficiency of the power amplifier circuit.

[0208] Figure 10 is a schematic diagram of another power amplifier circuit provided in an embodiment of this application.

[0209] In some embodiments, as shown in FIG10, the power amplifier circuit PA includes three cascaded power amplifiers, with FIG8C showing the cascaded power amplifier located in the third stage. The power amplifier circuit PA also includes a second cascaded power amplifier PA1 located in the first stage and a first cascaded power amplifier PA1 located in the second stage.

[0210] The second cascaded power amplifier PA2 is coupled between the radio frequency input terminal RFI and the second power divider input terminal i2. In some embodiments, when the power amplifier circuit PA also includes a first cascaded power amplifier PA1, the second cascaded power amplifier PA2 is coupled between the radio frequency input terminal RFI and the first cascaded power amplifier PA1.

[0211] It is understood that the first cascaded power amplifier PA1 can be the structure shown in Figure 9A or Figure 9B. Figure 10 is only an illustration and is not intended to limit the possibilities.

[0212] In some embodiments, the second cascaded power amplifier PA2 may further include a third sub-power amplifier and a fourth sub-power amplifier, wherein the third sub-power amplifier is located between the third power divider output terminal o3 and the first sub-power amplifier pa1, and the fourth sub-power amplifier is located between the fourth power divider output terminal o4 and the second sub-power amplifier pa2.

[0213] Figures 11A-11C are schematic diagrams of another power amplifier circuit provided in the embodiments of this application.

[0214] In some embodiments, as shown in FIG11A, the power amplifier circuit PA includes two cascaded power amplifiers, with FIG6 showing the cascaded power amplifier located in the second stage. The power amplifier circuit PA also includes a third cascaded power amplifier PA3 located in the first stage. The power amplifier circuit PA includes multiple cascaded power amplifiers, which can increase the gain of the power amplifier circuit PA.

[0215] As shown in Figure 11A, the third cascaded power amplifier PA3 is coupled in series with the first power divider PS2.

[0216] As an example, as shown in Figure 11A, the third cascaded power amplifier PA3 is coupled between the RF input RFI and the first power divider PS1. That is, the third cascaded power amplifier PA3 is located before the input of the first power divider PS1.

[0217] Alternatively, as shown in Figure 11B, the third cascaded power amplifier PA3 includes a fifth sub-power amplifier pa5 and a sixth sub-power amplifier pa6. The fifth sub-power amplifier pa5 is coupled between the first power divider output terminal o1 and the first amplifier PA1, and the sixth sub-power amplifier pa6 is coupled between the second power divider output terminal o2 and the second amplifier P2. That is, the third cascaded power amplifier PA3 is located at the output terminal of the first power divider PS1.

[0218] Because the first power divider PS1 has insertion loss, it requires relatively high power. Therefore, placing the third cascaded power amplifier PA3 at the output of the first power divider PS1 can reduce the power requirement of the third cascaded power amplifier PA3, thereby improving the efficiency of the power amplifier circuit.

[0219] In some embodiments, as shown in FIG11C, the power amplifier circuit PA includes three cascaded power amplifiers, with FIG6 showing the cascaded power amplifier located in the third stage. The power amplifier circuit PA also includes a fourth cascaded power amplifier PA4 located in the first stage and a third cascaded power amplifier PA3 located in the second stage.

[0220] The fourth cascaded power amplifier PA4 is coupled between the radio frequency input terminal RFI and the first power divider input terminal i1. In some embodiments, when the power amplifier circuit PA also includes a third cascaded power amplifier PA3, the fourth cascaded power amplifier PA4 is coupled between the radio frequency input terminal RFI and the third cascaded power amplifier PA3.

[0221] It is understood that the first cascaded power amplifier PA1 can be the structure shown in Figure 11A or Figure 11B. Figure 11C is only an illustration and is not intended to limit the possibilities.

[0222] In some embodiments, the fourth cascaded power amplifier PA4 may further include a fifth sub-power amplifier and a sixth sub-power amplifier, wherein the fifth sub-power amplifier is located between the first power divider output terminal o1 and the third sub-power amplifier pa3, and the sixth sub-power amplifier is located between the second power divider output terminal o2 and the fourth sub-power amplifier pa4.

[0223] In some embodiments, any of the power amplifier circuits PA provided in this application can be applied to narrowband or broadband scenarios. For example, the radio frequency input (RFI) of the power amplifier circuit PA is used to transmit broadband signals.

[0224] For example, a broadband signal is a radio frequency signal with a relative bandwidth greater than or equal to 20%, while a narrowband signal is a radio frequency signal with a relative bandwidth less than 20%. Relative bandwidth = (upper limit frequency - lower limit frequency) / center frequency.

[0225] For example, the RF input terminal RFI of the power amplifier circuit PA is used to transmit Sub6G signals, such as signals in the n77 band. Or, for example, the RF input terminal RFI of the power amplifier circuit PA is used to transmit signals in the n79 band.

[0226] In broadband scenarios, the power amplifier circuit PA provided in this application embodiment still has superior saturation power and saturation efficiency.

[0227] Figure 12 is a schematic diagram of the layout of a power amplifier circuit provided in an embodiment of this application.

[0228] As shown in Figure 12, the power amplifier circuit PA provided in this embodiment can be disposed on a substrate. Some structures in the power amplifier circuit PA can be disposed on the substrate in the form of power amplifier chips, and some structures in the power amplifier circuit PA can be bonded to the substrate.

[0229] For example, the power amplifier chip includes an RF input terminal RFI, a first output terminal O1, and a second output terminal O2. Alternatively, the power amplifier chip may also include a third output terminal O3 and a fourth output terminal O4, where the RF input terminal RFI is used to receive signals, and the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4 are used to output signals.

[0230] It should be noted that the RF input terminal RFI, the first output terminal O1, the second output terminal O2, the third output terminal O3, and the fourth output terminal O4 can be a port consisting of a single pad or a port consisting of multiple pads.

[0231] Based on this, as shown in Figure 12, the power amplifier chip also includes a first power divider PS1, a second power divider PS2, a third power divider PS3, a first amplifier P1, a second amplifier P2, a third amplifier P3, and a fourth amplifier P4 in the power amplifier circuit PA.

[0232] The output of the first amplifier P1 is coupled to the first output terminal O1, the output of the second amplifier P2 is coupled to the second output terminal O2, the output of the third amplifier P3 is coupled to the third output terminal O3, and the output of the fourth amplifier P4 is coupled to the fourth output terminal O4.

[0233] The first impedance matching network MAT1, the second impedance matching network MAT2, the third impedance matching network MAT3, the fourth impedance matching network MAT4, and the impedance transformer U in the power amplifier circuit PA are all disposed on the substrate or at least some of the devices are integrated in the substrate.

[0234] For example, the first capacitor C1, the first inductor L1, the second capacitor C2, the second inductor L2, the third capacitor C3, the third inductor L3, the fourth capacitor C4, the fourth inductor L4, the fifth inductor L5, the sixth inductor L6, and the fifth capacitor C5 are all disposed on the substrate or at least some of the devices are integrated in the substrate.

[0235] In some embodiments, the substrate includes a first region and a second region, the power amplifier chip is located in the first region, and at least one of the first capacitor C1, the first inductor L1, the second capacitor C2, the second inductor L2, the third capacitor C3, the third inductor L3, the fourth capacitor C4, the fourth inductor L4, and the impedance transformer U is located in the second region.

[0236] Alternatively, it can be understood that the first capacitor C1, the first inductor L1, the second capacitor C2, the second inductor L2, the third capacitor C3, the third inductor L3, the fourth capacitor C4, the fourth inductor L4, and the impedance transformer U are not integrated into the power amplifier chip.

[0237] In some embodiments, the first region and the second region of the substrate are different regions on the same side of the substrate. In some embodiments, the first region and the second region of the substrate are regions on different sides of the substrate (e.g., one side and the other side of the substrate).

[0238] For example, the first capacitor C1, the first inductor L1, the second capacitor C2, the second inductor L2, the third capacitor C3, the third inductor L3, the fourth capacitor C4, the fourth inductor L4, and the impedance transformer U are all discrete components (surface-mount components). The first output terminal O1 is coupled to the first inductor L1 (or the first capacitor C1) through a bonding wire. The second output terminal O2 is coupled to the second capacitor C2 (or the second inductor L2) through a bonding wire. The fourth output terminal O4 is coupled to the fourth inductor L4 (or the fourth capacitor C4) through a bonding wire. The third output terminal O3 is coupled to the third capacitor C3 (or the third inductor L3) through a bonding wire.

[0239] Alternatively, for example, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are discrete components, and the bonding wires are directly used as the first inductor L1, the second inductor L2, the third inductor L3, or the fourth inductor L4.

[0240] Alternatively, for example, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 are discrete devices, and the traces in the substrate, such as transmission lines or microstrip lines, serve as the first inductor L1, the second inductor L2, the third inductor L3, or the fourth inductor L4.

[0241] Of course, the embodiments in this application are not limited in this respect, and the above is only an illustrative description.

[0242] In the case where the power amplifier circuit PA also includes a first cascaded power amplifier PA1, a second cascaded power amplifier PA2, or a third cascaded power amplifier PA3, the first cascaded power amplifier PA1, the second cascaded power amplifier PA2, or the third cascaded power amplifier PA3 are also located in the power amplifier chip.

[0243] In the case where the power amplifier circuit PA also includes a fifth impedance matching network MAT5, the fifth impedance matching network MAT5 can also be disposed on the substrate.

[0244] It should be clarified that the above illustration uses the example where some components of the power amplifier circuit PA are located in the power amplifier chip and some are located on the substrate. Of course, all components in the power amplifier circuit PA provided in this application embodiment can also be disposed in the power amplifier chip. Alternatively, some components can be located in the power amplifier chip and some on the substrate, but the components located in the power amplifier chip will differ from those illustrated in the above embodiment. This application embodiment does not limit the component layout in the power amplifier circuit PA; the illustrations in the embodiments are merely illustrative.

[0245] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power amplifier circuit, characterized in that, include: The device includes a radio frequency input (RFI), a radio frequency output (RFO), a first power divider (PS1), a first branch (A1), a second branch (A2), and a first combiner point (Q1); the first combiner point (Q1) is coupled to the radio frequency output (RFO). The first power divider (PS1) includes a first power divider input terminal (i1), a first power divider output terminal (o1), and a second power divider output terminal (o2); the first power divider input terminal (i1) is coupled to the radio frequency input terminal (RFI); The first branch (A1) includes a first amplifier (P1) and a first impedance matching network (MAT1). The first terminal of the first amplifier (P1) is coupled to the first power divider output terminal (o1). The first impedance matching network (MAT1) includes a first capacitor (C1) and a first inductor (L1) coupled in series between the second terminal of the first amplifier (P1) and the first combining point (Q1). The second branch (A2) includes a second amplifier (P2) and a second impedance matching network (MAT2). The first terminal of the second amplifier (P2) is coupled to the second power divider output terminal (o2). The second impedance matching network (MAT2) includes a second capacitor (C2) or a second inductor (L2) coupled between the second terminal of the second amplifier (P2) and the first combining point (Q1). Alternatively, the second impedance matching network (MAT2) includes the second capacitor (C2) and the second inductor (L2) coupled in series between the second terminal of the second amplifier (P2) and the first combining point (Q1).

2. The power amplifier circuit according to claim 1, characterized in that, The capacitance value of the first capacitor (C1) is different from that of the second capacitor (C2); And / or, The inductance value of the first inductor (L1) is different from that of the second inductor (L2).

3. The power amplifier circuit according to claim 1 or 2, characterized in that, One of the first impedance matching network (MAT1) and the second impedance matching network (MAT2) has an inductive fundamental impedance, while the other has a capacitive fundamental impedance.

4. The power amplifier circuit according to any one of claims 1-3, characterized in that, The power amplifier circuit also includes: The second power divider (PS2) includes a second power divider input terminal (i2), a third power divider output terminal (o3), and a fourth power divider output terminal (o4); the second power divider input terminal (i2) is coupled to the radio frequency input terminal (RFI), and the third power divider output terminal (o3) is coupled to the first power divider input terminal (i1); The third power divider (PS3) includes a third power divider input terminal (i3), a fifth power divider output terminal (o5), and a sixth power divider output terminal (o6); the third power divider input terminal (i3) is coupled to the fourth power divider output terminal (o4); The second junction (Q2) and the third junction (Q3); The third branch (A3) includes a third amplifier (P3) and a third impedance matching network (MAT3). The first terminal of the third amplifier (P3) is coupled to the sixth power divider output terminal (o6). The third impedance matching network (MAT3) includes a third capacitor (C3) or a third inductor (L3) coupled between the second terminal of the third amplifier (P3) and the second combining point (Q2), or the third impedance matching network (MAT3) includes the third capacitor (C3) and the third inductor (L3) coupled in series between the second terminal of the third amplifier (P3) and the second combining point (Q2). The fourth branch (A4) includes a fourth amplifier (P4) and a fourth impedance matching network (MAT4), wherein the first terminal of the fourth amplifier (P4) is coupled to the fifth power divider output terminal (o5); the fourth impedance matching network (MAT4) includes a fourth capacitor (C4) or a fourth inductor (L4) coupled between the second terminal of the fourth amplifier (P4) and the second combining point (Q2), or the fourth impedance matching network (MAT4) includes the fourth capacitor (C4) and the fourth inductor (L4) coupled in series between the second terminal of the fourth amplifier (P4) and the second combining point (Q2); An impedance transformer (U) is coupled between the first combining point (Q1) and the third combining point (Q3).

5. The power amplifier circuit according to claim 4, characterized in that, The capacitance value of the third capacitor (C3) is different from that of the fourth capacitor (C4); And / or, The inductance value of the third inductor (L3) is different from that of the fourth inductor (L4).

6. The power amplifier circuit according to claim 4 or 5, characterized in that, One of the third impedance matching network (MAT3) and the fourth impedance matching network (MAT4) has an inductive fundamental impedance, while the other has a capacitive fundamental impedance.

7. The power amplifier circuit according to any one of claims 4-6, characterized in that, The impedance transformer (U) includes a fifth inductor (L5), a sixth inductor (L6), and a fifth capacitor (C5); The fifth inductor (L5) and the sixth inductor (L6) are connected in series between the first junction point (Q1) and the third junction point (Q3); one end of the fifth capacitor (C5) is coupled to the reference ground voltage terminal, and the other end of the fifth capacitor (C5) is coupled between the fifth inductor (L5) and the sixth inductor (L6).

8. The power amplifier circuit according to any one of claims 1-7, characterized in that, The inductance value of the first inductor (L1) or the inductance value of the second inductor (L2) is greater than 0 and less than 3NH; And / or, The capacitance value of the first capacitor (C1) or the capacitance value of the second capacitor (C2) is greater than 0 and less than 10pF.

9. The power amplifier circuit according to any one of claims 1-8, characterized in that, The phase difference between the first merging point (Q1) and the third merging point (Q3) is 60° to 120° or -60° to -120°.

10. The power amplifier circuit according to any one of claims 3-7, characterized in that, The power amplifier circuit also includes a first cascaded power amplifier (PA1), which is coupled in series with the second power divider (PS2).

11. The power amplifier circuit according to claim 10, characterized in that, The first cascaded power amplifier (PA1) includes a first sub-power amplifier (pa1) and a second sub-power amplifier (pa2). The first sub-power amplifier (pa1) is coupled between the third power divider output terminal (o3) and the first power divider input terminal (i1), and the second sub-power amplifier (pa2) is coupled between the fourth power divider output terminal (o4) and the third power divider input terminal (i3).

12. The power amplifier circuit according to claim 10 or 11, characterized in that, The power amplifier circuit further includes a second cascaded power amplifier (PA2), which is coupled between the radio frequency input terminal (RFI) and the second power divider input terminal (i2).

13. The power amplifier circuit according to claim 1 or 2, characterized in that, The power amplifier circuit also includes a third cascaded power amplifier (PA3), which is coupled in series with the first power divider (PS1).

14. The power amplifier circuit according to any one of claims 1-13, characterized in that, The radio frequency input (RFI) is used to transmit broadband signals, which are radio frequency signals with a relative bandwidth greater than 20%.

15. A radio frequency front-end module, characterized in that, include: The substrate and the power amplifier circuit as described in any one of claims 1-14; the power amplifier circuit is disposed on the substrate.

16. The radio frequency front-end module according to claim 15, characterized in that, The RF front-end module also includes a filter; the RF output terminal of the power amplifier circuit is coupled to the input terminal of the filter.

17. A communication device, characterized in that, It includes an antenna and a radio frequency front-end module as described in claim 15 or 16, wherein the antenna is coupled to the radio frequency front-end module.

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