Communication method and apparatus

Abstract

A communication method and an apparatus, applied to the technical field of communications. The method comprises: a first apparatus generating a first signal on the basis of a first sequence, the first sequence comprising H elements, wherein the value of a first element among the H elements is determined by a second sequence and P matrices, the P matrices comprise a first matrix, and the value of an element in an m-th row and a k-th column in the first matrix is used for indicating whether an m-th output node is related to a k-th input node; and sending the first signal. In embodiments of the present application, the value of the first element in the first sequence is determined by the second sequence and the P matrices, and the value of the first element is decoupled from the values of other elements in the first sequence, so that the values of a plurality of elements in the first sequence can be determined in parallel, thereby reducing the time overhead of sequence generation.

Description

A communication method and apparatus

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510099382.6, filed on January 21, 2025, entitled "A Communication Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a communication method and apparatus. Background Technology

[0004] In communication systems, some signals are generated from sequences. Terminals or base stations can select the appropriate sequence from a set of sequences, process that sequence to obtain the signal, and then transmit it. Currently, the generation of multiple elements in a sequence relies on iterative operations; that is, the value of the (x+1)th element is related to the values ​​of the x preceding elements, where x is a positive integer. The longer the sequence, the more iterations are required, resulting in higher time overhead and making it unsuitable for communication scenarios with low latency requirements. Summary of the Invention

[0005] This application provides a communication method and apparatus to reduce the time overhead of sequence generation, which is beneficial for adapting to communication scenarios with low latency requirements.

[0006] In a first aspect, this application provides a communication method that can be applied to a first device, such as a first equipment, a functional module included in the first equipment, or a larger device including the first equipment. The first device is, for example, a terminal-side device or a network-side device. The terminal-side device is also referred to as a terminal device or a terminal.

[0007] The terminal device may be, for example, a terminal equipment, or a component of a terminal equipment, such as a communication module, circuits or chips responsible for communication functions (e.g., modem chips, also known as baseband chips, or system-on-chip (SoC) chips containing modem cores, or system-in-package (SIP) chips, chip systems, or processors, etc.) or other functional modules that can be applied in the terminal equipment. This chip system or functional module can realize the functions of the terminal equipment. For example, if the chip system or functional module is located in the terminal equipment, it can also be a logic module or software that can realize all or part of the functions of the terminal equipment.

[0008] The network-side device is also referred to as a network device. This network device is, for example, a network equipment, or a component of a network equipment, such as a communication module, circuitry or chip responsible for communication functions (e.g., a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, a chip system, or a processor, etc.) or other functional module that can be applied within the network equipment. This chip system or functional module can implement the functions of the network equipment. This chip system or functional module, for example, is located within the network equipment and can also be a logic module or software that can implement all or part of the functions of the network equipment. Optionally, the network equipment can be an Open Radio Access Network (ORAN) architecture or an ORAN architecture; or, the network equipment can be a centralized unit (CU), a distributed unit (DU), or a radio unit (RU) under an ORAN architecture. The network equipment is, for example, located on the ground, or it can be, for example, a satellite or an aircraft, or a non-ground device. The network equipment includes, for example, access network equipment and / or core network equipment.

[0009] The method may include: a first device generating a first signal based on a first sequence, the first sequence comprising H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, wherein the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m, and k are all positive integers; and sending the first signal.

[0010] Alternatively, the method may include: a first device sending a first signal generated by a first sequence comprising H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, wherein the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m, and k are all positive integers.

[0011] In this embodiment, the value of the first element in the first sequence is determined by the second sequence and P matrices. The value of the first element is decoupled from the values ​​of other elements in the first sequence, allowing the values ​​of multiple elements in the first sequence to be determined in parallel. This reduces the time overhead of sequence generation and is beneficial for adapting to communication scenarios with low latency requirements. For example, the first device can determine H elements of the first sequence in parallel. Compared to determining the H elements one by one through iterative calculations, this embodiment can effectively reduce the time overhead of sequence generation.

[0012] In one possible implementation, the first signal may consist of H sub-signals; the first device generating the first signal based on the first sequence may include: the first device determining a second matrix based on the first sequence, wherein the second matrix consists of the first sequence and zero, the h-th element in the first sequence is the element in the h-th row and h-th column of the second matrix, and h belongs to {1, ..., H}; generating the first signal based on a third matrix, wherein the third matrix is ​​determined by the second matrix, and the sequence in the h-th row of the third matrix is ​​used to generate the h-th sub-signal among the H sub-signals.

[0013] In the above implementation, the first sequence is constructed as a diagonal matrix, which can realize signal scrambling, construct more types of sequences, and adapt to different communication scenarios.

[0014] Secondly, this application provides a communication method that can be applied to a second device, such as a second equipment, a functional module included in the second equipment, or a larger device including the second equipment. The second device is, for example, a terminal-side device or a network-side device. For a description of the terminal-side device or network-side device, please refer to the first aspect, and will not be repeated here. For example, the first device is a terminal-side device and the second device is a network-side device; or, the first device is a network-side device and the second device is a terminal-side device; or, both the first device and the second device are terminal-side devices; or, both the first device and the second device are network-side devices.

[0015] The method may include: a second device generating a first sequence, the first sequence comprising H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, wherein the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m, and k are all positive integers; and detecting a first signal based on the first sequence.

[0016] Alternatively, the method may include: a second device detecting a first signal according to a first sequence, the first sequence comprising H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, wherein the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m, and k are all positive integers.

[0017] Based on the first or second aspect mentioned above, in one possible implementation, the second sequence can be the original information bits.

[0018] Based on the first or second aspect above, in one possible implementation, the first matrix is ​​used to indicate that the m-th output node among M output nodes is related to q input nodes among K input nodes, where M and K are positive integers, q is a positive integer less than or equal to K, and m belongs to {1, ..., M}.

[0019] In the above implementation, the first matrix can be used to represent the relationship (such as connection relationship) between the M output nodes and the K input nodes, thereby obtaining the output of the output nodes. It should be understood that the connection relationship between the M output nodes and the K input nodes can be implemented by a matrix, or by a table, or by other means, and this application does not limit it.

[0020] Based on the first or second aspect above, in one possible implementation, q is 1, and the output of the m-th output node is the output of the q input nodes; or, q is greater than 1, and the output of the m-th output node is the value obtained by performing a modulo operation on a first value, where the first value is the product of the outputs of the q input nodes; or, q is 1, and the output of the m-th output node is the value obtained by performing a modulo operation on a second value, where the second value is the product of the outputs of the q input nodes and the weight corresponding to the m-th output node; or, q is greater than 1, and the output of the m-th output node is the value obtained by performing a modulo operation on a third value, where the third value is the product of the first value and the weight corresponding to the m-th output node, where the first value is the product of the outputs of the q input nodes.

[0021] In the above implementation, there are multiple ways to operate the output node, which can form different types of sequences, making it easier to adapt to different communication scenarios.

[0022] Based on the first or second aspect described above, in one possible implementation, M is greater than or equal to K. That is, the number of output nodes is greater than or equal to the number of input nodes.

[0023] Based on the first or second aspect described above, in one possible implementation, K and M can satisfy the following relationship: M = 2K - 1. Different values ​​of K and M have different effects on signal performance. In this implementation, M is (2K - 1), which is beneficial for reducing the peak-to-average power ratio (PAPR) of the signal. It should be understood that K and M can also satisfy other relationships, which are not limited in this application.

[0024] Based on the first or second aspect described above, in one possible implementation, the first matrix is ​​the first matrix among the P matrices, and the second sequence includes K elements, wherein: the output of the k-th input node is the value of the k-th element among the K elements; or, the output of the k-th input node is the value obtained by performing a modulo operation on a fourth value, where the fourth value is the product of the value of the k-th element among the K elements and the weight corresponding to the k-th input node; wherein k belongs to {1, ..., K}. For example, the P matrices can be used to indicate whether there is a relationship between nodes in each adjacent pair of layers in the first network, then the value of the first element can be determined by the second sequence and the first network, wherein the second sequence is the input of the first network.

[0025] Based on the first or second aspect described above, in another possible implementation, the first matrix is ​​the Pth matrix among the P matrices, and the value of the first element is the value obtained by performing a modulo operation on the fifth value, where the fifth value is the sum of the outputs of the M output nodes. For example, the P matrices can be used to indicate whether there is a relationship between nodes in each adjacent pair of layers in the first network. In this case, the value of the first element can be determined by the second sequence and the first network. Specifically, the value of the first element is related to the output of the first network.

[0026] Based on the first or second aspect above, in one possible implementation, the first element is the (n+1)th element among the H elements, and the value of the (i+1)th element in the second sequence can satisfy the following relationship:

[0027] The n belongs to {0, ..., H}; or,

[0028] The n belongs to {0, ..., 2} I -2};

[0029] Wherein, the x i Let I be the value of the (i+1)th element in the second sequence, where I is the number of elements in the second sequence. This is for floor function.

[0030] In the above implementation, the values ​​of the elements in the second sequence can be determined in two ways, which can be adapted to different communication scenarios. In one way, all elements in the second sequence can have a value of 0; in the other way, all elements in the second sequence have a value of non-zero. In this way, the first signal obtained from the second sequence can have lower time-domain cross-correlation characteristics.

[0031] Based on the first or second aspect described above, in one possible implementation, the H elements further include a second element. The value of the second element is determined by a third sequence and D matrices, where the D matrices include a fourth matrix. The value of the element in the e-th row and f-th column of the fourth matrix is ​​used to indicate whether the e-th output node is related to the f-th input node. D, e, and f are all positive integers. For example, the value of the second element can be determined by the third sequence and the second network, and the D matrices can be used to indicate whether there is a relationship between nodes in each adjacent layer of the second network.

[0032] In the above implementation, the value of the second element is determined by the third sequence and D matrices. The value of the second element is decoupled from the values ​​of other elements in the first sequence, such as the value of the first element. In this way, the first device can determine the values ​​of the first element and the second element in parallel, which can reduce iterative operations and thus reduce the time overhead of sequence generation, which is beneficial for adapting to communication scenarios with low latency requirements.

[0033] Based on the first or second aspect above, in one possible implementation, the value of the first element is determined by the second sequence and P matrices, including: the value of the first element is determined by the second sequence and the first network, the P matrices are used to indicate whether there is a relationship between nodes in each adjacent two layers of the first network, the input of the first network is the second sequence, and the output of the first network is the value of the first element.

[0034] Based on the first or second aspect described above, in one possible implementation, the second sequence is predefined, or the second sequence is preconfigured, or the second sequence is configured by the network device.

[0035] Based on the first or second aspect above, in one possible implementation, the P matrices are predefined, pre-configured, or configured by the network device.

[0036] Thirdly, this application provides a communication device that can be used to execute the methods described in the first aspect and any possible implementation thereof. The communication device can be a first device. The communication device may include modules, units, or means corresponding to the methods described in the first aspect and any possible implementation thereof. These modules, units, or means can be implemented in hardware, software, or by hardware executing corresponding software implementations. The hardware or software includes one or more modules or units corresponding to the above functions.

[0037] In one possible implementation, the communication device may include a baseband device and a radio frequency device.

[0038] In another possible implementation, the communication device may include a processing module (sometimes also called a processing unit) and a transceiver module (sometimes also called a transceiver unit). The transceiver module is capable of both sending and receiving functions. When the transceiver module performs the sending function, it may be called a sending module (sometimes also called a sending unit), and when it performs the receiving function, it may be called a receiving module (sometimes also called a receiving unit). The sending module and the receiving module may be the same functional module, referred to as the transceiver module, which performs both sending and receiving functions; or, the sending module and the receiving module may be different functional modules, with "transceiver module" being a collective term for these functional modules.

[0039] Fourthly, this application provides a communication device that can be used to execute the methods described in the second aspect and any possible implementation thereof. The communication device can be a second device. The communication device may include modules, units, or means corresponding to the methods described in the second aspect and any possible implementation thereof. These modules, units, or means may be implemented in hardware, software, or by hardware executing corresponding software implementations. The hardware or software includes one or more modules or units corresponding to the aforementioned functions.

[0040] In one possible implementation, the communication device may include a baseband device and a radio frequency device.

[0041] In another possible implementation, the communication device may include a processing module (sometimes also called a processing unit) and a transceiver module (sometimes also called a transceiver unit). The transceiver module is capable of both sending and receiving functions. When the transceiver module performs the sending function, it may be called a sending module (sometimes also called a sending unit), and when it performs the receiving function, it may be called a receiving module (sometimes also called a receiving unit). The sending module and the receiving module may be the same functional module, referred to as the transceiver module, which performs both sending and receiving functions; or, the sending module and the receiving module may be different functional modules, with "transceiver module" being a collective term for these functional modules.

[0042] Fifthly, this application provides a communication system that may include at least one of the following: the communication device provided in the third aspect above, or the communication device provided in the fourth aspect above.

[0043] Sixthly, this application also provides a communication device. The communication device may include one or more processors. Optionally, the communication device may further include a memory. The memory is used to store one or more computer programs or instructions. The one or more processors are used to execute the one or more computer programs or instructions stored in the memory, causing the communication device to perform the methods described in the first or second aspect and any possible implementation thereof.

[0044] In a seventh aspect, this application also provides a communication device, comprising: a processor and an interface circuit; the interface circuit is configured to receive signals from other communication devices outside the communication device and transmit them to the processor, or to send signals from the processor to other communication devices outside the communication device. The processor is configured to implement the methods described in the first or second aspect and any possible implementation thereof through logic circuits or by executing computer programs or instructions.

[0045] In some possible designs, when the device is a chip system, it can be composed of chips or contain chips and other discrete components.

[0046] Eighthly, this application also provides a chip system comprising at least one chip and a memory, wherein the at least one chip is configured to read and execute a program stored in the memory to implement the method described in the first or second aspect and any possible implementation thereof.

[0047] Ninthly, this application also provides a computer-readable storage medium for storing a computer program or instructions that, when executed, cause the methods described in the first or second aspect and any possible implementation thereof to be implemented.

[0048] In a tenth aspect, this application also provides a computer program product comprising a computer program or instructions that, when executed on a computer, cause the methods described in the first or second aspect and any possible implementation thereof to be implemented.

[0049] The technical effects achievable by the second to tenth aspects and any of their possible implementations are described in the same manner as the technical effects achievable by the first aspect and any of its possible implementations, and will not be repeated here. Attached Figure Description

[0050] Figures 1A and 1B are schematic diagrams of two structures of the access network device in the embodiments of this application;

[0051] Figure 2 is a schematic diagram of a communication system provided in an embodiment of this application;

[0052] Figure 3 is a schematic diagram of a parallel generation of H elements provided in an embodiment of this application;

[0053] Figure 4 is a schematic diagram of two structures of the first network provided in the embodiments of this application;

[0054] Figure 5 is a flowchart illustrating a communication method provided in an embodiment of this application;

[0055] Figure 6 is a schematic diagram of determining the third matrix provided in an embodiment of this application;

[0056] Figure 7 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0057] Figure 8 is a schematic diagram of another communication device provided in an embodiment of this application;

[0058] Figure 9 is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0059] The relevant terms used in the embodiments of this application will be explained below. It should be noted that these explanations are for the purpose of making the embodiments of this application easier to understand, and should not be regarded as a limitation on the scope of protection claimed by this application.

[0060] 1) A terminal device is a device with wireless transceiver capabilities. It can be a fixed device, a mobile device, a handheld device (e.g., a mobile phone), a wearable device, an in-vehicle device, or a wireless device (e.g., a communication module, modem, or chip system) built into the above devices. The terminal device is used to connect people, objects, and machines, and can be widely used in various scenarios, including but not limited to the following: sensing scenarios, cellular communication, device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine / machine-type (M2M / MTC) communication, Internet of Things (IoT), virtual reality (VR), augmented reality (AR), industrial control, self-driving, remote medical care, smart grid, smart furniture, smart office, smart wearables, smart transportation, smart city, drones, robots, and terminal devices in indoor commercial scenarios (e.g., mobile phone screen mirroring, file sharing, and video transmission from mobile phones to VR glasses). When the terminal equipment is applied to V2X, it can also be called a V2X device, such as a smart car, digital car, unmanned car, driverless car, pilotless car, or automobile, self-driving car, or autonomous car, pure electric vehicle (EV), hybrid electric vehicle (HEV), range-extended electric vehicle (REEV), plug-in hybrid electric vehicle (PHEV), new energy vehicle, or roadside unit (RSU). The terminal equipment can also be a device used in D2D communication, such as an electricity meter or water meter.

[0061] Furthermore, in this embodiment, the terminal device can also be a terminal device in an Internet of Things (IoT) system. IoT is an important component of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0062] The various terminal devices described above, if located in a vehicle (e.g., placed inside or installed inside a vehicle), can all be considered in-vehicle terminal devices, also known as on-board units (OBUs). The terminal device of this application can also be an in-vehicle module, in-vehicle component, in-vehicle chip, or in-vehicle unit built into a vehicle as one or more components or units. The vehicle can implement the methods of this application through the built-in in-vehicle module, in-vehicle component, in-vehicle chip, or in-vehicle unit.

[0063] The terminal equipment may sometimes be referred to as UE, terminal, access station, UE station, remote station, wireless communication equipment, or user equipment, etc.

[0064] In this application embodiment, the device for implementing the terminal device function can be a terminal device, which can be a terminal device or a device capable of supporting the terminal device in implementing the function, such as a chip system. This device can be installed in the terminal device. In the technical solutions provided in this application embodiment, the example of a terminal device being used to implement the terminal device function is used to describe the technical solutions provided in this application embodiment.

[0065] 2) Network equipment, including, for example, access network equipment (or access network elements) and / or core network equipment (or core network elements). The access network equipment is a device with wireless transceiver capabilities, used to communicate with the terminal equipment. The access network equipment includes, but is not limited to, base stations (base transceiver stations (BTS), Node B, evolved Node B (eNodeB) / eNB, or the next generation Node B (gNodeB) / gNB), transmission reception points (TRPs), base stations evolved from the 3rd generation partnership project (3GPP), access nodes in Wi-Fi systems, wireless relay nodes, wireless backhaul nodes, etc. The base station can be: macro base station, micro base station, pico base station, small cell, relay station, etc. Multiple base stations can support networks using the same access technology or networks using different access technologies. A base station can contain one or more co-located or non-co-located transmission and reception points. The access network equipment can also be a radio controller, centralized unit (CU), and / or distributed unit (DU) in a cloud radio access network (CRAN) scenario. The access network equipment can also be a server, etc. For example, the network equipment in V2X technology can be a roadside unit (RSU). The following description uses a base station as an example to illustrate the access network equipment. The base station can communicate with the terminal device, or it can communicate with the terminal device through a relay station. The terminal device can communicate with multiple base stations in different access technologies. The core network equipment is used to implement functions such as mobility management, data processing, session management, policy and billing. The names of the equipment implementing core network functions may differ in systems using different access technologies; this application does not limit this.Taking the 5th generation (5G) mobile communication technology system as an example, the core network equipment includes, for example, access and mobility management function (AMF), session management function (SMF), policy control function (PCF), or user plane function (UPF), etc.

[0066] In a CU-DU architecture, or in an open RAN (ORAN) system, access network equipment may include one or more logical network elements such as CU, DU, CU-control plane (CP), CU-user plane (UP), or radio unit (RU). CU and DU can be separate entities or included in the same network element, such as a baseband unit (BBU). RU may be included in radio equipment or radio units, such as a remote radio unit (RRU), active antenna unit (AAU), or remote radio head (RRH). One possible structure for access network equipment is shown in Figure 1A. In this structure, core network equipment and access network equipment can communicate via a backhaul link; within the access network equipment, CU and DU can communicate via a midhaul link, and DU and RU can communicate via a fronthaul link.

[0067] Alternatively, another architecture for the access network device can be seen in Figure 1B, which illustrates an access network device implemented using a chip, such as a RAN chip. The RAN chip may include a CU, DU, and RU. The CU can perform L2 and L3 functions, etc.; the DU can perform L1 functions and some L2 functions, etc.; and the RU can perform L1 computation and radio frequency (RF) digital functions, etc. The CU communicates with the core network device via a backhaul interface, which carries the traffic between the CU and the core network device. The CU may include a central processing unit (CPU) based on x86 or ARM architecture, and may include a field-programmable gate array (FPGA), graphics processing unit (GPU), or other accelerators. The CPU can communicate with the FPGA, GPU, or other accelerators via a peripheral component interconnect express (PCIe) interface.

[0068] The CU and DU communicate via a midhaul interface, which carries the traffic between the CU and DU. The DU may include an x86 or ARM architecture CPU, as well as FPGAs, GPUs, or other accelerators, which can communicate with the FPGA, GPU, or other accelerators via a PCIe interface.

[0069] The DU and RU communicate via a fronthaul interface, which carries the traffic between the DU and RU. If the access network equipment uses an integrated DU, the integrated DU can include the functions of both the DU and RU, and the RAN may no longer need to include a separate RU. The RU may include a RAN fronthaul (RAN FH) processing unit, a digital processing unit, and an RF processing unit. The RAN FH processing unit is implemented, for example, using an FPGA or an application-specific integrated circuit (ASIC). The digital processing unit is also implemented, for example, using an FPGA or an ASIC.

[0070] The RU can be connected to an antenna to communicate with the UE via the antenna.

[0071] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called an open CU (O-CU), DU can also be called an open DU (O-DU), CU-CP can also be called an open CU-CP (O-CU-CP), CU-UP can also be called an open CU-UP (O-CU-CP), and RU can also be called an open RU (O-RU). For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples in its embodiments. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in the embodiments of this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0072] The CU and DU can be configured according to the protocol layer functions of the wireless network they implement. For example, the CU can be configured to implement the functions of the Packet Data Convergence Protocol (PDCP) layer and above (such as the Radio Resource Control (RRC) layer and / or the Service Data Adaptation Protocol (SDAP) layer); the DU can be configured to implement the functions of protocol layers below the PDCP layer (such as one or more of the Radio Link Control (RLC) layer, Media Access Control (MAC) layer, or Physical (PHY) layer). As another example, the CU can be configured to implement the functions of protocol layers above the PDCP layer (such as the RRC and / or SDAP layers), and the DU can be configured to implement the functions of protocol layers below the PDCP layer (such as one or more of the RLC, MAC, or PHY layers).

[0073] The above CU and DU configurations are merely examples; the functions of the CU and DU can be configured as needed. For instance, the CU or DU can be configured to have more protocol layer functions, or only some protocol layer processing functions. For example, some RLC layer functions and protocol layer functions above the RLC layer can be placed in the CU, while the remaining RLC layer functions and protocol layer functions below the RLC layer can be placed in the DU. Furthermore, the functions of the CU or DU can be divided according to service type or other system requirements, such as by latency. Functions that require low latency can be placed in the DU, while functions that do not require low latency can be placed in the CU.

[0074] DU and RU can cooperate to implement the functions of the PHY layer. A DU can be connected to one or more RUs. The functions of DU and RU can be configured in various ways depending on the design. For example, a DU can be configured to implement baseband functions, and an RU can be configured to implement mid-RF functions. Another example is that a DU can be configured to implement higher-level functions in the PHY layer, and an RU can be configured to implement lower-level functions in the PHY layer, or to implement both lower-level and RF functions. Higher-level functions in the physical layer can include a portion of the physical layer's functions that are closer to the MAC layer, while lower-level functions in the physical layer can include another portion of the physical layer's functions that are closer to the mid-RF side.

[0075] In this application embodiment, the apparatus for implementing the functions of a network device can be referred to as a network apparatus. This network apparatus can be a network element, a network device, or an apparatus capable of supporting the network device or network element in implementing the function, such as a chip system. This apparatus can be installed within the network device. In the technical solutions provided in this application embodiment, the apparatus for implementing the functions of a network device is described as a network apparatus (for example, an apparatus for implementing the functions of an access network apparatus is an access network apparatus, and an apparatus for implementing the functions of a core network apparatus is a core network apparatus).

[0076] 3) In the embodiments of this application, "multiple" can refer to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two or more. For example, "including at least one" means including one, two or more. For example, including at least one of A, B and C, then it can include A, B, C, A and B, A and C, B and C, or A, B and C. "And / or" describes the association relationship of the associated objects. Specifically, there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0077] In the embodiments of this application, the terms "system" and "network" can be used interchangeably, and "according to" and "based on" can be used interchangeably.

[0078] The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects, and are not used to limit the order, timing, priority, or importance of multiple objects. For example, the first device and the second device involved in the embodiments of this application are used to distinguish different devices, and do not limit the order, timing, priority, or importance of these two devices.

[0079] The terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0080] In this application, "predefined" may include predefined terms, such as protocol definitions. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other means of indicating relevant information in the device (e.g., including various network elements), and this application does not limit the specific implementation method.

[0081] The term "storage" or "preservation" in this application can refer to storage in one or more memory devices. These memory devices can be separately configured or integrated into an encoder, decoder, processor, or communication device. Alternatively, some memory devices can be separately configured, while others can be integrated into the decoder, processor, or communication device. The type of memory can be any form of storage medium, and this is not limited.

[0082] In this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for the purpose of instructing A, it can be understood that the instruction information carries A, directly instructs A, or indirectly instructs A.

[0083] In this application, the information indicated by the instruction information is called the information to be instructed. In specific implementations, there are many ways to indicate the information to be instructed, such as, but not limited to, directly indicating the information to be instructed, such as the information to be instructed itself or its index. It can also indirectly indicate the information to be instructed by indicating other information, where there is a relationship between the other information and the information to be instructed. It can also indicate only a part of the information to be instructed, while the other parts are known or pre-agreed upon. For example, the instruction of specific information can be achieved by using a pre-agreed (e.g., protocol-defined) arrangement of various pieces of information, thereby reducing instruction overhead to some extent. Furthermore, the information to be instructed can be sent as a whole or divided into multiple sub-information pieces, and the sending period and / or timing of these sub-information pieces can be the same or different.

[0084] In this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which can include direct transmission via the air interface or indirect transmission via the air interface from other units or modules. "Receive information from YY" can be understood as the source of the information being YY, which can include direct reception from YY via the air interface or indirect reception from YY via the air interface from other units or modules. "Send" can also be understood as the "output" of a chip interface, and "receive" can also be understood as the "input" of a chip interface. In other words, sending and receiving can occur between devices, such as between network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via buses, traces, or interfaces.

[0085] In this application, the words "exemplarily," "for example," "e.g.," are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0086] This application will present embodiments relating to a system comprising multiple devices, components, modules, etc. It should be understood that the system may include other unmentioned devices, components, modules, etc., or may include only some of the devices, components, or modules mentioned in the embodiments. Optionally, the terms "component" and "part" in this application can be used interchangeably.

[0087] In this application, unless otherwise specified, the index is described using a numbering method starting from 0 and incrementing by 1 as an example. Accordingly, among X elements, the element with index x is the (x+1)th element among those X elements, where X is a positive integer and x belongs to {0, 1, ..., X-1}. Here, "..." represents a positive integer between "1" and "X-1". For example, if X is 5, then x belongs to {0, 1, 2, 3, 4}. Here, x belonging to {0, 1, ..., X-1} can be replaced with x∈{0, 1, ..., X-1}, or x∈[0, 1, ..., X-1]. Furthermore, this application does not limit the index numbering method to this. For example, the numbering method could also be: starting from 1 and incrementing by 1. Another example is that the numbering method could also be: starting from X and decrementing by 1, where X is an integer greater than 1.

[0088] The preceding text introduced some of the terms used in the embodiments of this application. The following text introduces the communication system to which the embodiments of this application are applicable.

[0089] The communication method provided in this application can be applied to fourth-generation (4G) communication systems, such as long-term evolution (LTE) communication systems, as well as fifth-generation (5G) communication systems, such as 5G new radio (NR) communication systems, or various communication systems evolving after 5G, such as future communication systems. The method provided in this application can also be applied to Bluetooth systems, wireless fidelity (Wi-Fi) systems, long-range radio (LoRa) systems, or vehicle-to-everything (V2X) systems. The method provided in this application can also be applied to terrestrial networks (TN) and non-terrestrial networks (NTN), such as satellite communication systems. For example, it can be applied to transparent satellite architectures, backhaul satellite architectures, or regenerative satellite architectures, etc., without limitation.

[0090] Figure 2 is a schematic diagram of a communication system provided in an embodiment of this application. The communication system may include at least one of the following: a first device or a second device. The first device is a signal transmitter, and the second device is a signal receiver. For example, the first device may send a signal to the second device using a sequence provided in an embodiment of this application; correspondingly, the second device may detect the signal according to the sequence provided in an embodiment of this application.

[0091] Optionally, the second device and the first device can also switch roles. That is, the second device can send a signal to the first device using the sequence provided in the embodiments of this application, and correspondingly, the first device can detect the signal according to the sequence provided in the embodiments of this application, as shown by the dashed line in Figure 2.

[0092] The first device is, for example, a first equipment, a functional module included in the first equipment, or a larger equipment including the first equipment. The first device is, for example, a terminal-side device or a network-side device. The second device is, for example, a second equipment, a functional module included in the second equipment, or a larger equipment including the second equipment. The second device is, for example, a terminal-side device or a network-side device. For instance, the first device is a terminal-side device and the second device is a network-side device; or, the first device is a network-side device and the second device is a terminal-side device; or, both the first device and the second device are terminal-side devices; or, both the first device and the second device are network-side devices.

[0093] The terminal-side device is also referred to as a terminal device or a terminal. This terminal device may be a terminal equipment or a component of a terminal equipment, such as a communication module, circuitry or chip responsible for communication functions (e.g., a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, a chip system, or a processor, etc.) or other functional module that can be applied within the terminal equipment. This chip system or functional module can implement the functions of the terminal equipment. For example, if the chip system or functional module is located within the terminal equipment, it can also be a logic module or software that can implement all or part of the functions of the terminal equipment.

[0094] The network-side device is also referred to as a network device. This network device is, for example, a network equipment, or a component of a network equipment, such as a communication module, circuitry or chip responsible for communication functions (e.g., a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, a chip system, or a processor, etc.) or other functional module that can be applied within the network equipment. This chip system or functional module can implement the functions of the network equipment. For example, the chip system or functional module is located within the network equipment, and can also be a logic module or software that can implement all or part of the functions of the network equipment. Optionally, the network equipment can be an ORAN architecture or an ORAN-based CU, DU, or RU. The network equipment is located on the ground, or it can be a non-ground device such as a satellite or an aircraft, or located on a non-ground device such as a satellite or an aircraft.

[0095] It should be understood that this application does not limit the implementation of the first and second devices. Furthermore, please refer to the foregoing explanations of terms for network equipment and terminal equipment; further elaboration is unnecessary.

[0096] The network architecture and communication process described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0097] This application provides a communication method and apparatus to reduce the time overhead of sequence generation, which is beneficial for adapting to communication scenarios with low latency requirements. The method and apparatus described in this application are based on the same technical concept. Since the principles by which the method and apparatus solve the problem are similar, the implementation of the apparatus and method can be referred to each other, and repeated details will not be repeated.

[0098] The method provided in the embodiments of this application is described below with reference to the accompanying drawings. The method provided in the embodiments of this application can be applied to the network architecture shown in FIG2. For example, the first device described in the embodiments of this application can be the first device shown in FIG2; the second device described in the embodiments of this application can be the second device shown in FIG2.

[0099] In this embodiment of the application, "sequence" is an array used to generate signals, such as the first sequence mentioned later, which is unrelated to transmission resources; "signal" refers to a signal emitted by the device, such as a signal with a cyclic prefix (CP) added.

[0100] In this embodiment of the application, the first device can generate a first signal based on a first sequence and send the first signal; correspondingly, the second device can generate (or determine, or acquire) the first sequence and detect the first signal based on the first sequence. The first sequence can be used to generate the first signal. The first sequence can include H elements, or the first sequence can be composed of H elements. H is a positive integer.

[0101] As an optional implementation, in this embodiment, the generation process of any element in the first sequence can be implemented by a sequence (e.g., original information bits) and a network; or, the value of any element in the first sequence can be determined by a sequence (e.g., original information bits) and a network. The network can be understood as a method for determining the value of an element (or an operation method, calculation method, or operational logic, etc.), and it can be represented in the form of a network, a table, or text, etc., which is not limited in this application. For ease of understanding, it will be described in the form of a network below.

[0102] Optionally, the H elements of the first sequence can be generated using H sequences and H networks; or, the values ​​of the H elements of the first sequence can be determined based on the H sequences and H networks, as shown in Figure 3. One element can be generated using a sequence and a network, thus generating H elements in parallel. Compared to generating H elements one by one through iterative operations, this effectively reduces the time overhead of sequence generation. Optionally, the H sequences can be understood as the original information bits. In Figure 3, X(0), X(1), ..., X(H-1) represent the H sequences, r(0), r(1), ..., r(H-1) represent the H elements of the first sequence, and the H networks are denoted as network 0, network 1, ..., network H-1. It can be understood that different elements in the first sequence can use the same network, or different networks can be sampled, or some elements can use the same network.

[0103] Taking the first element in the first sequence as an example, this first element can be generated by the second sequence and the first network, or the value of the first element can be determined by the second sequence and the first network. Optionally, the second sequence can be understood as the original information bits. The value of the first element can be the output of the first network, or the value of the first element can be determined by the output of the first network. The input of the first network can be the second sequence, or the input of the first network can be determined by the second sequence.

[0104] The first network will be introduced below. Other networks can refer to the implementation method of the first network.

[0105] The first network is a multi-layer network. For example, the first network may include (P+1) layers, or the first network consists of (P+1) layers, as shown in (1) of Figure 4. P is a positive integer. Optionally, if the first network also includes an input layer and / or an output layer (not shown in Figure 4), the (P+1) layers can be understood as (P+1) intermediate layers.

[0106] Each layer in the first network may include at least one node. A node may also be called a computation node, computation unit, or logic unit, and can be used to obtain an output based on the input. Along the input-to-output direction of the first network (as shown by the arrows in Figure 4), a node in the preceding layer of any two adjacent layers in the first network can be called an input node, and a node in the following layer can be called an output node (the descriptions of preceding and following layers in the following text refer to the descriptions here). It should be understood that input nodes and output nodes are relative; the same node can be an input node in one pair of adjacent layers and an output node in another pair of adjacent layers. For example, suppose the first network is a three-layer network, and along the input-to-output direction of the first network, the three layers are denoted as layer #1, layer #2, and layer #3; layer #1 and layer #2 are two adjacent layers in the first network, and a node in layer #2 can be called an output node relative to a node in layer #1; layer #2 and layer #3 are also two adjacent layers in the first network, and a node in layer #2 can be called an input node relative to a node in layer #3. Optionally, "previous layer" and "next layer" can be replaced with "current layer" and "next layer"; or replaced with "previous layer" and "current layer".

[0107] The number of nodes in each layer of the first network can be the same or different, and this application does not limit this. In an optional embodiment, along the input to output direction of the first network, the number of nodes (also called input nodes) in the preceding layer (denoted as K, where K is a positive integer) of any two adjacent layers in the first network is less than or equal to the number of nodes (also called output nodes) in the following layer (denoted as M, where M is a positive integer), that is, K is less than or equal to M, or M is greater than or equal to K.

[0108] In another optional implementation, along the input-to-output direction of the first network, the number of nodes (also called input nodes) in the preceding layer (denoted as K, where K is a positive integer) and the number of nodes (also called output nodes) in the following layer (denoted as M, where M is a positive integer) in any two adjacent layers of the first network can satisfy the following relationship: M = 2K-1, as shown in (2) of Figure 4. In (2) of Figure 4, the first network includes two layers, the first layer includes 3 nodes (i.e., K is 3), the second layer includes 5 nodes (i.e., M is 5), and the elements in the second sequence are denoted as x0, x1, and x2.

[0109] In one optional implementation, whether nodes in each adjacent pair of layers in the first network are related can be represented by a matrix. Whether nodes in each adjacent pair of layers in the first network are related can be replaced by: whether nodes in each adjacent pair of layers in the first network are unrelated; whether nodes in each adjacent pair of layers in the first network are connected; or whether nodes in each adjacent pair of layers in the first network have an edge; or whether input and output nodes in the first network are related; or whether input and output nodes in the first network are unrelated; or whether input and output nodes in the first network are connected; or whether input and output nodes in the first network have an edge. Wherein, nodes in adjacent pairs of layers are related can be understood as: the input of a node includes the output of at least one node related to that node; or as: the input of an output node includes the output of at least one input node related to that output node; or as: the output of at least one input node related to the output node serves as the input of that output node. The idea that nodes in adjacent layers are independent can be understood as follows: the input of a node does not include the output of at least one node that is independent of that node; or the input of an output node does not include the output of at least one input node that is independent of that output node; or the output of at least one input node that is independent of the output node is not used as the input of that output node.

[0110] For example, in two adjacent layers, the previous layer includes node #1 and the next layer includes node #2. If node #1 is related to node #2, the input of node #2 includes the output of node #1; conversely, if node #1 is not related to node #2, then the input of node #2 does not include the output of node #1.

[0111] Accordingly, whether nodes in two adjacent layers of the first network are related can be represented by P matrices. That is, P matrices can be used to indicate whether nodes in two adjacent layers of the first network are related, and one of the matrices can be used to indicate whether nodes in one adjacent layer of the first network are related.

[0112] Taking the first matrix among the P matrices as an example, this first matrix can be used to indicate whether nodes in two adjacent layers of the first network are related. Assuming the preceding layer includes K input nodes and the following layer includes M output nodes, the first matrix can be used to indicate whether the K input nodes and M output nodes are related. In an optional implementation, the value of the element in the m-th row and k-th column of the first matrix can be used to indicate whether the m-th output node is related to the k-th input node, where m is a positive integer belonging to {1, 2, ..., M}, and k is a positive integer belonging to {1, 2, ..., K}. Whether the m-th output node is related to the k-th input node can be replaced with: whether the m-th output node is unrelated to the k-th input node, whether the m-th output node is connected to the k-th input node, or whether there is an edge between the m-th output node and the k-th input node.

[0113] For example, the value of an element in the first matrix may include a sixth value and a seventh value. The sixth value can be used to indicate relevance, and the seventh value can be used to indicate independence. For instance, if the element in the m-th row and k-th column of the first matrix has the sixth value, it indicates that the m-th output node is related to the k-th input node; conversely, if the element in the m-th row and k-th column of the first matrix has the seventh value, it indicates that the m-th output node is unrelated to the k-th input node. For example, the sixth value can be 1 and the seventh value can be 0; or, the sixth value can be 0 and the seventh value can be 1. It is understood that this application does not limit the specific values ​​of the sixth and seventh values. Unless otherwise specified, the following description uses the sixth value of 1 and the seventh value of 0 as an example.

[0114] For example, if K is 2, the K input nodes are denoted as node 1-1, node 1-2, and node 1-3 respectively; if M is 5, the M output nodes are denoted as node 2-1, node 2-2, node 2-3, node 2-4, and node 2-5 respectively; if the first matrix is... This means that node 2-1 is related to node 1-1 (either connected or with an edge), node 2-2 is related to node 1-2, node 2-3 is related to node 1-3, node 2-4 is related to both node 1-1 and node 1-2, and node 2-5 is related to both node 1-2 and node 1-3, as shown in (2) of Figure 4. That is, the input of node 2-1 includes the output of node 1-1, the input of node 2-2 includes the output of node 1-2, the input of node 2-3 includes the output of node 1-3, the input of node 2-4 includes the output of both node 1-1 and node 1-2, and the input of node 2-5 includes the output of both node 1-2 and node 1-3.

[0115] It is understood that the implementation of the first matrix is ​​merely an example, and this application does not limit it. For example, the value of the element in the k-th row and m-th column of the first matrix can be used to indicate whether the m-th output node is related to the k-th input node. Taking the first network shown in (2) of Figure 4 as an example, the first matrix can also be...

[0116] In another alternative implementation, whether nodes in any two adjacent layers of the first network are related can be represented by a table. As an example, Table 1 can be referenced regarding whether nodes in two adjacent layers are related. In Table 1, the first network is the network structure shown in (2) of Figure 4. Wherein, "1" indicates that nodes in two adjacent layers are connected (or related), that is, the output of the node in the previous layer is used as the input of the node in the next layer; "0" indicates that nodes in two adjacent layers are not connected (or unrelated), that is, the output of the node in the previous layer is not used as the input of the node in the next layer. It should be understood that Table 1 is only an example, and this application is not limited thereto.

[0117] Table 1

[0118] It should be understood that whether nodes in adjacent layers are related can also be represented in other forms, such as text, and this application does not limit this. For ease of understanding, the following explanation uses a matrix as an example.

[0119] The following, with reference to Figure 5, describes the processes in the above procedure, including the first device generating the first signal according to the first sequence, sending the first signal, and the second device detecting the first signal according to the first sequence.

[0120] Figure 5 is a flowchart illustrating a communication method provided in an embodiment of this application. As shown in Figure 5, the method may include the following steps.

[0121] S501: The first device generates a first signal according to the first sequence.

[0122] The first signal can be an uplink signal from the terminal device to the network device, a downlink signal from the network device to the terminal device, a signal transmitted between terminal devices, or a signal transmitted between network devices. This application does not limit the implementation form of the first signal.

[0123] In one optional implementation, the first device may generate (or determine, or acquire) a first sequence and generate a first signal based on the sequence. In one example, the first device may generate the first sequence based on at least one sequence (e.g., H sequences) and at least one matrix; or, the first device may generate the first sequence based on at least one sequence (e.g., H sequences) and at least one network (e.g., H networks). The at least one sequence includes a second sequence. The at least one matrix may include P matrices. The at least one network may include a first network. For example, the first device may generate a first element in the first sequence based on the second sequence and P matrices; or, the first device may generate the first element in the first sequence based on the second sequence and the first network. The generation of other elements may refer to the generation method of the first element. Wherein, H and P are both positive integers.

[0124] Optionally, the P matrices can be predefined, preconfigured, or configured by the network device; this application does not impose any limitations on this.

[0125] Optionally, the second sequence may be predefined, preconfigured, or configured by the network device; this application does not limit this.

[0126] The first sequence may include H elements, the value of the first element of which can be determined by the second sequence and P matrices. The P matrices include a first matrix, which can be used to indicate whether K output nodes are related to M input nodes. For example, the value of an element in the first matrix can be used to indicate whether one of the K output nodes is related to one of the M input nodes. The value of the element in the m-th row and k-th column of the first matrix can be used to indicate whether the m-th output node is related to the k-th input node. m and k are both positive integers. For example, m belongs to {1, ..., M}. For example, k belongs to {1, ..., K}. K and M are positive integers. For example, K is greater than or equal to M. For example, K and M satisfy: M = 2^K - 1.

[0127] The terms such as first sequence, H elements, first element, second sequence, P matrices, first matrix, whether related, output node, and input node are not repeated here. Please refer to the previous content for details.

[0128] As mentioned above, the first matrix can be used to indicate whether the K output nodes are related to the M input nodes. For example, the first matrix can be used to indicate that the m-th output node among the K output nodes is related to at least one of the K input nodes (e.g., denoted as q input nodes, where q is a positive integer less than or equal to K). Furthermore, the output of the m-th output node can be implemented in any of the following ways.

[0129] Method 1: The output of the output node is determined by the output of the input node.

[0130] For example, if q is 1, the output of the m-th output node is the output of the q input nodes; or if q is greater than 1, the output of the m-th output node is the value obtained by modulo operation on a first value, where the first value is the product of the outputs of the q input nodes. In other words, if the m-th output node is related to only one input node, then the output of the m-th output node is the output of the input node related to it; if the m output nodes are related to multiple input nodes, then the output of the m-th output node is the value obtained by modulo operation on the product of the outputs of the multiple input nodes.

[0131] Taking (2) in Figure 4 as an example, assume that the outputs of node 1-1, node 1-2, node 1-3, node 2-1, node 2-2, node 2-3, node 2-4, and node 2-5 are recorded as c0, c1, c2, u0, u1, u2, u3, and u4 respectively. According to the above method 1, u0, u1, u2, u3, and u4 can satisfy the following formula (1).

[0132] In this application, mod represents modulo operation, and b represents the modulus. For example, b can be 2, 4, 8, etc. This application does not limit the value of the modulus.

[0133] As mentioned above, the second sequence is the input to the first network. In one optional implementation, the number of elements in the second sequence is equal to the number of nodes in the first layer of the first network, and at least one element in the second sequence corresponds one-to-one with at least one node in the first layer. The output of a node in the first layer can be the value of the element corresponding to that node in the second sequence. For example, assuming the first matrix is ​​the first matrix among P matrices, and the second sequence can include K elements, then the output of the k-th input node can be the value of the k-th element among the K elements, where k belongs to {[1, ..., K}. Here, the first matrix being the first matrix among P matrices can be understood as: the first matrix can be used to indicate whether the nodes between the first and second layers in the first network are related; or it can be understood as: the first matrix can be used to indicate whether the nodes between the first group of adjacent layers in the first network are related.

[0134] Taking (2) in Figure 4 as an example, assuming that the outputs of node 1-1, node 1-2 and node 1-3 are denoted as c0, c1 and c2 respectively, according to the above implementation method, c0, c1 and c2 can satisfy the following formula (1).

[0135] Here, x0, x1, and x2 are the values ​​of the three elements of the second sequence, respectively.

[0136] Method 2: The output of the output node is determined by the output of the input node and the weight of the output node.

[0137] For example, if q is 1, the output of the m-th output node is the value obtained by modulo operation on the second value, where the second value is the product of the outputs of the q input nodes and the weights (or weight coefficients, coefficients, or weighted coefficients, etc.) corresponding to the m-th output node; or if q is greater than 1, the output of the m-th output node is the value obtained by modulo operation on the third value, where the third value is the product of the first value and the weights (or weight coefficients, coefficients, or weighted coefficients, etc.) corresponding to the m-th output node, and the first value is the product of the outputs of the q input nodes. In other words, if the m-th output node is only related to one input node, then the output of the m-th output node is the value obtained by modulo operation on the product of the outputs of the related input nodes and the weights corresponding to the m-th output node; if the m output nodes are related to multiple input nodes, then the output of the m-th output node is the value obtained by modulo operation on the product of the outputs of the multiple input nodes and the weights corresponding to the m-th output node.

[0138] Taking (2) in Figure 4 as an example, assume that the outputs of node 1-1, node 1-2, node 1-3, node 2-1, node 2-2, node 2-3, node 2-4, and node 2-5 are recorded as c0, c1, c2, u0, u1, u2, u3, and u4 respectively. According to method 2 above, u0, u1, u2, u3, and u4 can satisfy the following formula (3).

[0139] Where mod represents modulo operation, b represents the modulus, and b can be, for example, 2, 4, 8, etc. This application does not limit the value of the modulus. α0 is the weight corresponding to node 2-1, α1 is the weight corresponding to node 2-2, α2 is the weight corresponding to node 2-3, α3 is the weight corresponding to node 2-4, and α4 is the weight corresponding to node 2-5.

[0140] As mentioned above, the output of a node in the first layer can be the value of the element corresponding to that node in the second sequence. Alternatively, the output of a node in the first layer can also be the value obtained by modulo operation on the product of the element corresponding to that node in the second sequence and the weight corresponding to that node. For example, assuming the first matrix is ​​the first matrix among P matrices, and the second sequence may include K elements, then the output of the k-th input node can be the value obtained by modulo operation on a fourth value, where the fourth value is the product of the value of the k-th element among the K elements and the weight corresponding to the k-th input node, and k belongs to {[1, ..., K}. The description of the first matrix as the first matrix among P matrices is provided above and will not be repeated here.

[0141] Taking (2) in Figure 4 as an example, assuming that the outputs of node 1-1, node 1-2 and node 1-3 are denoted as c0, c1 and c2 respectively, according to the above implementation method, c0, c1 and c2 can satisfy the following formula (4).

[0142] Where x0, x1, and x2 are the values ​​of the three elements of the second sequence, respectively. mod represents the modulo operation, and b represents the modulus, which can be, for example, 2, 4, 8, etc. This application does not limit the value of the modulus. β0 is the weight corresponding to node 1-1, β1 is the weight corresponding to node 1-2, and β2 is the weight corresponding to node 1-3.

[0143] Optionally, the weights corresponding to nodes can be predefined, preconfigured, or configured by the network device. For example, the first device can determine the weights corresponding to each node in the first network and generate the first element based on the second sequence, the weights corresponding to each node in the first network, and P matrices.

[0144] The value of the aforementioned first element is the output of the first network or determined by the output of the first network. In one optional implementation, the value of the first element can be the output of the output layer of the first network; or the value of the first element can be the value obtained by modulo operation on the sum of the outputs of the last layer of the first network. Here, the output of the output layer of the first network is the value obtained by modulo operation on the sum of the outputs of the last layer of the first network. For example, assuming the first matrix is ​​the Pth matrix among P matrices, the value of the first element can be the value obtained by modulo operation on the fifth value, which is the sum of the outputs of M output nodes. Here, the first matrix being the Pth matrix among P matrices can be understood as: the first matrix can be used to indicate whether the nodes between the last two layers in the first network are related; or it can be understood as: the first matrix can be used to indicate whether the nodes between the last pair of adjacent layers in the first network are related.

[0145] Taking (2) in Figure 4 as an example, assuming the outputs of nodes 2-1, 2-2, 2-3, 2-4, and 2-5 are denoted as u0, u1, u2, u3, and u4 respectively, according to the above implementation method, the value of the first element can satisfy the following formula (4). r(h-1)=(u0+u1+u2+u3+u4)mod b Formula (5)

[0146] Where r(h-1) represents the value of the first element, and h belongs to {0, ..., H}. mod represents the modulo operation, and b represents the modulus, which can be, for example, 2, 4, 8, etc. This application does not limit the value of the modulus.

[0147] It is understood that the modulo operations involved in the above formulas can be the same or different. Furthermore, the operational logic for nodes in this application is not limited to this.

[0148] In one optional implementation, the value of an element in the second sequence can be determined by the position of the first element among the H elements. As an example, assuming the first element is the (n+1)th element among the H elements, the value of the (i+1)th element in the second sequence can satisfy the following formula (6).

[0149] Where, x i Let be the value of the (i+1)th element in the second sequence, where I is the number of elements in the second sequence and I is a positive integer. For the floor operation, n belongs to {0, ..., H}, and i belongs to {0, ..., I}.

[0150] For example, the value of the first element can be referred to Table 2. In Table 2, the first network is the structure shown in (2) of Figure 4. The input of the first network is determined by formula (2), the value of [u0,u1,u2,u3,u4] is determined by formula (1), the modulus is 2, and the value of the element in the second sequence is determined by formula (6). It should be understood that Table 2 is only an example and this application is not limited thereto.

[0151] Table 2

[0152] For example, the values ​​of each element in the first sequence can be referred to Table 3. In Table 3, the first network is the structure shown in (2) of Figure 4. The input of the first network is determined by formula (2), the values ​​of [u0,u1,u2,u3,u4] are determined by formula (1), the modulus is 2, and the values ​​of the elements in the second sequence are determined by formula (6). It should be understood that Table 3 is only an example and this application is not limited thereto.

[0153] Table 3

[0154] As another example, suppose the first element is the (n+1)th element among H elements, and the value of the (i+1)th element in the second sequence satisfies the following formula (7).

[0155] Where, x i Let be the value of the (i+1)th element in the second sequence, where I is the number of elements in the second sequence and I is a positive integer. For the floor operation, n belongs to {0, ..., 2}. I -2}, i belongs to {0,...,I}.

[0156] For example, the value of the first element can be referred to Table 4. In Table 4, the first network is the structure shown in (2) of Figure 4. The input of the first network is determined by formula (2), the value of [u0,u1,u2,u3,u4] is determined by formula (1), the modulus is 2, and the value of the element in the second sequence is determined by formula (7). It should be understood that Table 4 is only an example and this application is not limited thereto.

[0157] Table 4

[0158] For example, the values ​​of each element in the first sequence can be referred to Table 5. In Table 5, the first network is the structure shown in (2) of Figure 4. The input of the first network is determined by formula (2), the values ​​of [u0,u1,u2,u3,u4] are determined by formula (1), the modulus is 2, and the values ​​of the elements in the second sequence are determined by formula (7). It should be understood that Table 5 is only an example and this application is not limited thereto.

[0159] Table 5

[0160] It is understood that this application does not limit the method of determining the second sequence to this. For example, the values ​​of the elements in the second sequence can also be generated in ways other than those described in formulas (6) and (7).

[0161] S502: The second device generates (or determines, or acquires) the first sequence.

[0162] The execution order of S502 is merely an example, and this application does not limit it. For example, the second device may generate the first sequence before the first device generates the first signal according to the first sequence, or it may generate the first sequence after the first device sends the first signal.

[0163] The first sequence can be referred to the foregoing description and will not be repeated here. Furthermore, the implementation method of the second device generating the first sequence can be referred to the implementation method of the first device generating the first sequence and will not be repeated here.

[0164] S503: The first device sends a first signal.

[0165] For example, the first device can send a first signal to the second device.

[0166] In this embodiment, a first device generates a first signal based on a first sequence and transmits the first signal. In an optional implementation, the first sequence can be used for frequency domain mapping. The first device can generate a time-domain baseband signal based on the first sequence used for mapping to the frequency domain. The method for generating the time-domain baseband signal may include: the first device performing an inverse fast fourier transform (IFFT) on the first sequence used for mapping to the frequency domain resource to obtain the time-domain baseband signal. Optionally, the method for generating the time-domain baseband signal may further include: the first device performing cyclic expansion on the IFFT-derived time-domain baseband signal, that is, adding a cyclic prefix (CP) to the IFFT-derived time-domain baseband signal. Further, the first device may perform frequency conversion, power amplification, etc., on the time-domain baseband signal (e.g., the IFFT-derived time-domain baseband signal, or the time-domain baseband signal with added CP) for transmission.

[0167] In another optional implementation, the first device can perform a Discrete Fourier Transform (DFT) on the first sequence to obtain a fourth sequence. This fourth sequence can be a sequence obtained after performing the DFT, and it can be a frequency domain signal sequence, meaning the fourth sequence can be used for frequency domain mapping. Further, the first device can generate a frequency domain signal based on the fourth sequence, and then generate a time-domain baseband signal based on the frequency domain signal. The method for generating the time-domain baseband signal may include: the first device performing an IFFT on the fourth sequence to be mapped to the frequency domain resource to obtain the time-domain baseband signal. Optionally, the method for generating the time-domain baseband signal may further include: the first device performing a cyclic expansion on the IFFT-derived time-domain baseband signal, i.e., adding a time-domain CP to the time-domain baseband signal. Further, the first device can perform frequency conversion, power amplification, etc., on the time-domain baseband signal (e.g., the IFFT-derived time-domain baseband signal, or the time-domain baseband signal with added CP) for transmission.

[0168] S504: The second device detects the first signal according to the first sequence.

[0169] Alternatively, S504 can also be expressed as: The second device receives the first signal according to the first sequence.

[0170] In one example, the second device may receive a first signal from the first device according to a first sequence, which may include detecting the first signal according to the first sequence. In another example, the second device may receive the first signal from the first device and then detect the first signal according to the first sequence. This application does not limit the specific implementation of the second device detecting the first signal according to the first sequence. Furthermore, this application does not limit the execution order of the second device generating the first sequence and receiving the first signal. For example, the second device may first generate the first sequence and then receive the first signal. Yet another example is that the second device may receive the first signal and then generate the first sequence.

[0171] In this embodiment, the value of the first element in the first sequence is determined by the second sequence and P matrices. The value of the first element is decoupled from the values ​​of other elements in the first sequence, or in other words, the generation of the first element is unrelated to the values ​​of other elements in the first sequence. Therefore, when storage resources are not limited, H elements in the first sequence can be generated (or determined, or obtained) in parallel, thereby reducing the time overhead of sequence generation. For example, the H elements may also include a second element, the value of which can be determined by the third sequence and D matrices. The D matrices include a fourth matrix, where the value of the element in the e-th row and f-th column of the fourth matrix is ​​used to indicate whether the e-th output node is related to the f-th input node; or, the value of the second element can be determined by the third sequence and the second network, and the D matrices can be used to indicate whether there is a relationship between nodes in each adjacent pair of layers in the second network. Here, D, e, and f are all positive integers. The third sequence, D matrices, fourth matrix, and second network can be referred to the descriptions of the second sequence, P matrices, first matrix, and first network, respectively, and will not be repeated here. The value of the second element is decoupled from (or unrelated to) the value of the first element, so the first device can generate the first element and the second element in parallel. Compared with generating the first element and the second element one by one through iterative operations, the time overhead of sequence generation can be reduced.

[0172] In one optional implementation, the first signal may consist of H sub-signals, all of which are received by the second device, or the H sub-signals may be received by multiple devices, including the second device. Exemplarily, the first device generating the first signal based on the first sequence may include: the first device determining (or constructing) a second matrix based on the first sequence, the second matrix consisting of the first sequence and zeros, where the h-th element of the first sequence is the element in the h-th row and h-th column of the second matrix, i.e., the second matrix is ​​a diagonal matrix constructed from the first sequence, as shown in Figure 6; and generating the first signal based on a third matrix, where the sequence in the h-th row of the third matrix is ​​used to generate the h-th sub-signal among the H sub-signals, i.e., one row of the third matrix is ​​used to generate one sub-signal. Here, h belongs to {1, ..., H}.

[0173] The third matrix is ​​determined by the second matrix. For example, the third matrix can be determined by the fifth matrix and the second matrix, such as by performing a dot product operation on the fifth and second matrices, as shown in Figure 6. The fifth matrix can include H rows and H columns. One row of the fifth matrix can be understood as a sequence (or an array). This sequence can be generated by the method provided in the embodiments of this application, or it can be generated by other methods; this application does not limit this. Through the above implementation methods, various types of sequences can be constructed to adapt to more communication scenarios.

[0174] Based on the same technical concept as the above-described method embodiments, this application provides a corresponding communication device that can be used to perform the functions of the relevant steps in the above-described method embodiments. This function can be implemented in hardware, software, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. The communication device can be a terminal or access network device, or a device within the terminal or access network device (e.g., a module, communication module, circuit or chip responsible for communication functions (such as a modem chip, or a SoC chip or SIP chip containing a modem core), chip system, or processor), or a logical node, logical module, or software capable of implementing all or part of the terminal or functions.

[0175] Figure 7 shows a schematic diagram of a communication device 700 provided in an embodiment of this application. This communication device 700 can implement the functions or steps performed by the first device or the second device in the above-described method embodiments.

[0176] For example, when the communication device 700 is used to implement the functions or steps implemented by the first device in the above method embodiments, the communication device 700 may be a network device or a component in a network device, or it may be a terminal device or a component in a terminal device.

[0177] For example, when the communication device 700 is used to implement the functions or steps implemented by the second device in the above method embodiments, the communication device 700 may be a network device or a component in a network device, or it may be a terminal device or a component in a terminal device.

[0178] In one embodiment, the communication device 700 may include a processing module 701 and a transceiver module 702; or it may include a processing module 701 but not a transceiver module 702; or it may include a transceiver module 702 but not a processing module 701. Wherein:

[0179] The processing module 701 can be used to support the communication device 700 in performing the processing actions in the above method embodiments. The processing module 701 can be implemented using one or more processors. For example, the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontroller units (MCUs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0180] In this application, the processing module 701 may also be referred to as a processing unit, etc., without limitation.

[0181] Transceiver module 702 is used for inputting and / or outputting information. Input information can be replaced by received information, and output information can be replaced by transmitted information. When outputting information, transceiver module 702 can output information to other devices outside of communication device 700, or to other units within communication device 700. In some embodiments, transceiver module 702 can be implemented through at least one of a physical interface, a communication module, a communication interface, and an input / output interface. In other embodiments, transceiver module 702 can be implemented through interface circuitry, such as a mobile communication module. The mobile communication module may include one or more of at least one antenna, at least one filter, a switch, a power amplifier, and a low-noise amplifier (LNA).

[0182] Optionally, the transceiver module 702 may include a sending module and / or a receiving module. The sending module is used to perform the sending operation in the above method embodiments. The receiving module is used to perform the receiving operation in the above method embodiments. It should be noted that the communication device 700 may include a sending module but not a receiving module. Alternatively, the communication device 700 may include a receiving module but not a sending module. Specifically, it depends on whether the above scheme performed by the communication device 700 includes both sending and receiving actions.

[0183] In this application, the transceiver module 702 may also be referred to as a communication interface, a communication module, a transceiver unit, an interface module, an interface unit, or a communication unit, etc., without limitation.

[0184] It should be noted that the communication device 700 may include a processing module 701, but not a transceiver module 702. Alternatively, the communication device 700 may include a transceiver module 702, but not a processing module 701. Specifically, it depends on whether the above-described scheme executed by the communication device 700 includes processing and transceiver actions.

[0185] Optionally, the communication device 700 may further include a storage module, not shown in FIG7. The storage module may be used to store instructions and / or data, and the processing module 701 may read the instructions and / or data in the storage module to enable the communication device 700 to implement the aforementioned method embodiment.

[0186] Optionally, the communication device 700 may be a chip system, the transceiver module 702 may be the input / output interface of the chip (e.g., a baseband chip), and the processing module 701 may be the processor of the chip system.

[0187] In one possible design, when the communication device 700 is a communication equipment or a communication module within a communication equipment, the functionality of the processing module 701 can be implemented by one or more processors. Exemplarily, the processor may include a modem chip (also known as a baseband chip), or a system-on-a-chip (SoC) chip or system-in-package (SIP) chip containing a modem core. The functionality of the transceiver module 702 can be implemented by transceiver circuitry. Optionally, the communication equipment can be a network device or a terminal device.

[0188] In one possible design, when the communication device 700 is a circuit or chip responsible for communication functions in a communication device, such as a modem chip or a SoC chip or SIP chip containing a modem core, the function of the processing module 701 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the transceiver module 702 can be implemented by the interface circuit or data transceiver circuit on the aforementioned chip. Optionally, the communication device can be a network device or a terminal device.

[0189] In the first implementation, the communication device 700 can perform the functions of the first device, executing the following: a processing module 701, used to generate a first signal according to a first sequence, the first sequence including H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m and k are all positive integers; and a transceiver module 702, used to transmit the first signal.

[0190] In one possible implementation, the first signal may consist of H sub-signals; when generating the first signal according to the first sequence, the processing module 701 is configured to determine a second matrix according to the first sequence, wherein the second matrix consists of the first sequence and zero, the h-th element in the first sequence is the element in the h-th row and h-th column of the second matrix, and h belongs to {1, ..., H}; and generate the first signal according to a third matrix, wherein the third matrix is ​​determined by the second matrix, and the sequence in the h-th row of the third matrix is ​​used to generate the h-th sub-signal among the H sub-signals.

[0191] In the second implementation, the communication device 700 can perform the functions of the second device, executing the following: a processing module 701 is used to generate a first sequence, the first sequence including H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m and k are all positive integers; and a first signal is detected according to the first sequence.

[0192] Detailed descriptions of the above-mentioned processing module 701 and transceiver module 702 can be obtained directly from the relevant descriptions in the foregoing method embodiments, and will not be repeated here.

[0193] Figure 8 shows a schematic diagram of another communication device 800 provided in an embodiment of this application. The communication device 800 may include a processor 820, used to implement or support the communication device 800 in implementing the functions of the first or second device in the aforementioned method embodiments. For details, please refer to the detailed descriptions in the aforementioned method embodiments, which will not be repeated here. For example, the processor 820 is used to read and execute program instructions through the communication interface 810, so that the communication device 800 implements the corresponding method. The processor 820 may include one or more processors, without limitation.

[0194] It should be noted that the aforementioned functional modules can be implemented by hardware or by a combination of hardware and software, without limitation. Furthermore, when the communication device 800 includes only the processor 820, the communication device 800 can be a chip or a chip system.

[0195] For example, the communication device 800 can be a chip system. The chip system can be composed of chips or can include chips and other discrete components, without limitation.

[0196] For example, when the communication device 800 is a chip, the communication interface 810 can be the chip's input / output interface, where input corresponds to receiving operations and output corresponds to sending operations.

[0197] Optionally, the communication device 800 may further include a memory 830 for storing program instructions and / or data. The memory 830 is coupled to the processor 820. This coupling can be understood as an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 820 may operate in conjunction with the memory 830; the processor 820 and the memory 830 may be integrated together or disposed separately.

[0198] Furthermore, the processor 820 is used to execute program instructions stored in the memory 830 so that the communication device 800 implements the corresponding method.

[0199] One or more of the memories in memory 830 may be included in the processor, or memory 830 may exist independently, such as off-chip memory, and be connected to processor 820 via a communication bus (represented by thick line 840 in Figure 8). Memory 830 and processor 820 may also be integrated together.

[0200] Optionally, the communication device 800 also includes a communication interface 810 (shown as dashed lines in FIG8) for communicating with other devices via a transmission medium, so that the device in the communication device 800 can communicate with other devices.

[0201] For example, when the communication device 800 is the first device, other devices can be second devices, etc. The processor 820 can use the communication interface 810 to send and receive data. For example, the processor 820 can be used to control the communication interface 810 to receive and / or send signals.

[0202] Specifically, the communication interface 810 can be a transceiver. In terms of hardware implementation, the transceiver can be used to implement the functions of the transceiver module 702 mentioned above, and the transceiver is integrated into the communication device 800 to form the communication interface 810.

[0203] Optionally, the transceiver may include a transmitter and / or a receiver to respectively implement the sending and receiving operations in the method embodiment; other operations besides sending and receiving may be implemented by the processor 820.

[0204] It should be noted that the communication interface 810 may have both sending and receiving functions, enabling the transmission and reception of signals; or it may have a sending function but no receiving function, used for transmitting signals; or it may have a receiving function but no sending function, used for receiving signals.

[0205] It should be noted that the specific connection medium between the communication interface 810, processor 820, and memory 830 is not limited in the embodiments of this application. Figure 8 shows the memory 830, processor 820, and communication interface 810 connected via a communication bus 840. The connection methods between other components are merely illustrative and not intended to be limiting. The communication bus 840 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 8, but this does not indicate that there is only one communication bus or one type of communication bus.

[0206] In the embodiments of this application, the processor 820 may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, or other programmable logic devices. The general-purpose processor may be a microprocessor or any conventional processor. The methods disclosed in the embodiments of this application may be executed by the hardware in the processor, or by a combination of hardware and software in the processor.

[0207] In this embodiment, the memory 830 can be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). The memory can also be any other medium used to carry or store program code in the form of instructions or data structures that can be accessed by a computer; or it can be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0208] In a first possible implementation, the communication device 800 may be a first device used to implement the relevant methods corresponding to the first device in the above embodiments. For specific functions, please refer to the descriptions in the above embodiments.

[0209] For example, the methods corresponding to the first device in the above embodiments include: generating a first signal according to a first sequence, the first sequence including H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, wherein the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m and k are all positive integers; and sending the first signal.

[0210] In a second possible implementation, the communication device 800 may be a second device used to implement the methods corresponding to the second device in the above embodiments. For specific functions, please refer to the descriptions in the above embodiments.

[0211] For example, the methods corresponding to the second device in the above embodiments include: generating a first sequence, the first sequence including H elements, wherein the value of the first element among the H elements is determined by a second sequence and P matrices, the P matrices including a first matrix, wherein the value of the element in the m-th row and k-th column of the first matrix is ​​used to indicate whether the m-th output node is related to the k-th input node, wherein H, P, m and k are all positive integers; and detecting a first signal according to the first sequence.

[0212] For the specific implementation process, please refer to the relevant content in the aforementioned embodiments; it will not be repeated here.

[0213] When the aforementioned communication device is a chip, Figure 9 shows a simplified schematic diagram of a chip 900 according to an embodiment of this application. The chip 900 includes an interface circuit 901 and one or more processors 902. Optionally, the chip 900 may also include a bus.

[0214] in:

[0215] Processor 902 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the hardware of processor 902 or by instructions in software form. Processor 902 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods and steps disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor.

[0216] The interface circuit 901 can be used to send or receive data, instructions or information. The processor 902 can use the data, instructions or other information received by the interface circuit 901 to process the data, instructions or other information, and can send the processed information out through the interface circuit 901.

[0217] Optionally, chip 900 also includes memory 903 (shown as dashed lines in Figure 9). Memory 903 may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of memory 903 may also include non-volatile random access memory (NVRAM).

[0218] Optionally, the memory 903 stores executable software modules or data structures, and the processor 902 can perform corresponding operations by calling the operation instructions stored in the memory 903 (which can be stored in the operating system).

[0219] Optionally, chip 900 can be used in the first or second device involved in the embodiments of this application. Optionally, interface circuit 901 can be used to output the execution result of processor 902. For the communication methods provided in the embodiments of this application, please refer to the foregoing embodiments, which will not be repeated here.

[0220] It should be noted that the functions of the interface circuit 901 and the processor 902 can be implemented through hardware design, software design, or a combination of hardware and software; no restrictions are imposed here.

[0221] It should be noted that the module division in the above embodiments of this application is illustrative and only represents a logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or have two or more units integrated into one unit. The integrated units can be implemented in hardware, as software functional units, or in a combination of hardware and software. Whether a function is executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0222] For example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as one or more ASICs, one or more CPUs, one or more MCUs, one or more DSPs, or one or more FPGAs, or a combination of at least two of these integrated circuit forms.

[0223] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0224] This application also provides a computer-readable storage medium for storing computer programs or instructions, which, when run, enable the methods or steps executed by the first or second device in the foregoing embodiments to be implemented.

[0225] This application also provides a computer program product, including a computer program, which, when run on a computer, causes the methods or steps executed by the first or second device in the foregoing embodiments to be implemented.

[0226] This application provides a chip system including a processor for implementing the functions of the first or second device in the aforementioned method (e.g., executing corresponding methods or steps). The chip system may be composed of a chip or may include a chip and other discrete devices.

[0227] Optionally, the chip system also includes a memory for storing program instructions that the processor can read and execute to implement the corresponding method.

[0228] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0229] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0230] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0231] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0232] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0233] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0234] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

[0235] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A communication method characterized by comprising: The method comprises: generating a first signal according to a first sequence, the first sequence comprising H elements, wherein a value of a first element in the H elements is determined by a second sequence and P matrices, the P matrices comprising a first matrix, a value of an element in an mth row and a kth column in the first matrix being used to indicate whether an mth output node is related to a kth input node, the H, the P, the m and the k being positive integers; sending the first signal.

2. The method of claim 1, wherein, The first signal is composed of H sub-signals; The first signal generated according to the first sequence comprises: determining a second matrix according to the first sequence, wherein the second matrix is composed of the first sequence and zero, an hth element in the first sequence being an element in an hth row and an hth column in the second matrix, the h belonging to {1, …, H}; generating the first signal according to a third matrix, wherein the third matrix is determined by the second matrix, a sequence in an hth row in the third matrix being used to generate an hth sub-signal in the H sub-signals.

3. A communication method characterized by comprising: The method comprises: generating a first sequence, the first sequence comprising H elements, wherein a value of a first element in H elements is determined by a second sequence and P matrices, the P matrices comprising a first matrix; a value of an element in an mth row and a kth column in the first matrix is used to indicate whether an mth output node is related to a kth input node, the first sequence, the P, the m and the k being positive integers; detecting a first signal according to the first sequence.

4. The method according to any one of claims 1 to 3, characterized in that, The first matrix is used to indicate that an mth output node in M output nodes is related to q input nodes in K input nodes, the M and the K being positive integers, the q being a positive integer less than or equal to the K, the m belonging to {1, …, M}.

5. The method according to claim 4, wherein, the q is 1, and an output of the mth output node is an output of the q input nodes; or the q is greater than 1, and the output of the mth output node is a value obtained by performing a modulo operation on a first value, the first value being a product of the outputs of the q input nodes; or the q is 1, and the output of the mth output node is a value obtained by performing a modulus operation on a second value, the second value being a product of the outputs of the q input nodes and a weight corresponding to the mth output node; or the q is greater than 1, and the output of the mth output node is the value obtained by performing a modulus operation on a third value, the third value being a product of a first value and a weight corresponding to the mth output node, the first value being a product of the outputs of the q input nodes.

6. The method according to claim 4 or 5, characterized in that, The M is greater than or equal to the K.

7. The method according to any one of claims 4 to 6, characterized in that, The K and the M satisfy the following relationship: M = 2K - 1.

8. The method according to any one of claims 4 to 7, characterized in that, The first matrix is a first matrix in the P matrices, and the second sequence comprises K elements, wherein: an output of the kth input node is a value of a kth element in the K elements; or An output of the kth input node is a value obtained by performing a modulo operation on a fourth value, the fourth value being a product of a value of a kth element in the K elements and a weight corresponding to the kth input node; wherein the k belongs to {1, …, K}.

9. The method according to any one of claims 4 to 8, characterized in that, The first matrix is a Pth matrix in the P matrices, and a value of the first element is a value obtained by performing a modulo operation on a fifth value, the fifth value being a sum of outputs of the M output nodes.

10. The method according to any one of claims 1 to 9, characterized in that, The first element is an (n+1)th element in the H elements, and a value of an (i+1)th element in the second sequence satisfies the following relationship: The n belongs to {0, …, H}; or, said n belongs to {0,..., 2 I -2}; wherein the x i is a value of an (i+1)th element in the second sequence, the I is a number of elements contained in the second sequence, is a floor operation.

11. The method according to any one of claims 1 to 10, characterized in that, The H elements further include a second element, and a value of the second element is determined by a third sequence and D matrices, the D matrices including a fourth matrix, a value of an element in an e-th row and an f-th column in the fourth matrix being used to indicate whether an e-th output node is related to an f-th input node, the D, the e, and the f being positive integers.

12. The method according to any one of claims 1 to 11, characterized in that, A value of the first element is determined by a second sequence and P matrices, including: A value of the first element is determined by the second sequence and a first network, the P matrices being used to indicate whether nodes between every two adjacent layers in the first network are related, an input of the first network being the second sequence, and an output of the first network being the value of the first element.

13. The method according to any one of claims 1 to 12, characterized in that, The second sequence is predefined, or the second sequence is preconfigured, or the second sequence is configured by a network device.

14. The method according to any one of claims 1 to 13, characterized in that, The P matrices are predefined, or the P matrices are preconfigured, or the P matrices are configured by a network device.

15. A communications device, characterized by The computer program product includes a computer program that, when executed on a computer, causes the method according to any one of claims 1 to 14 to be implemented.

16. A communications device, characterized by The computer program product includes at least one processor configured to execute the method according to any one of claims 1 to 14.

17. A communication system, characterized by The computer program product includes a first device and / or a second device, wherein: The first device is configured to execute the method according to any one of claims 1, 2, 4 to 14; The second device is configured to execute the method according to any one of claims 3 to 14.

18. A computer-readable storage medium, characterized in that, The computer program product includes a computer program or instructions that, when executed, cause the method according to any one of claims 1 to 14 to be implemented.

19. A computer program product, characterised in that, The computer readable medium includes a computer program that, when executed on a computer, causes the method according to any one claims 1 to 14 to be implemented.

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