Method and system for monitoring chip open-circuit failure of multi-chip IGBT module

Abstract

The present invention relates to the technical field of IGBT module monitoring. Specifically disclosed are a method and system for monitoring a chip open-circuit failure of a multi-chip IGBT module. The method comprises: first determining a health-sensitive parameter for monitoring a chip open-circuit failure of a multi-chip IGBT module; then, measuring a health-sensitive parameter value of the multi-chip IGBT module, and converting same into an analog voltage signal VPG; then, determining a failure threshold value VREF3 of the analog voltage signal VPG used for determining a chip open-circuit failure of the multi-chip IGBT module; and finally, comparing the actually measured analog voltage signal VPG and the failure threshold value VREF3 to determine whether the multi-chip IGBT module has had a chip open-circuit failure. In the present invention, monitoring a chip open-circuit failure of the multi-chip IGBT module is implemented without unpacking a package of the multi-chip IGBT module, and only a gate voltage signal needs to be acquired, such that affecting factors are few and measurement is easy; and non-invasive measurement is achieved, such that plug-and-play or integration in a drive circuit can be realized, and in-situ monitoring of chip open-circuit failures of multi-chip IGBT modules is easy to implement.

Description

Method and System for Detecting Open Circuit Failures in Multi-Chip IGBT Modules Technical Field

[0001] This invention relates to the field of IGBT module monitoring technology, and in particular to a method and system for monitoring open-circuit failures of multi-chip IGBT modules. Background Technology

[0002] Insulated-gate bipolar transistor (IGBT) modules are widely used in industrial fields such as rail transportation, electric vehicles, and new energy power generation. In high-power power electronic converters, multi-chip IGBT modules, composed of multiple IGBTs and diode chips connected in parallel, are typically used to improve the current-carrying capacity of the power module. Safety and long-term reliability have always been important concerns in the design of power electronic converters. However, surveys show that IGBT modules are the components with the highest failure probability in power electronic converters. Among these failures, bond wire failure is the main failure mode of IGBT modules. For multi-chip IGBT modules, due to differences in chip characteristics and packaging layout, the bond wires on the chips subjected to greater electrothermal stress fail first, accelerating the failure of the remaining bond wires on the chip, ultimately leading to open-circuit failure. Therefore, introducing condition monitoring technology to identify open-circuit failures in multi-chip IGBT modules has become an economical and effective method to improve the reliability of high-power power electronic converters.

[0003] Extensive research has been conducted on open-circuit failure monitoring of multi-chip IGBT modules. Existing methods can be categorized into sensor-based methods and health-sensitive parameter methods. Sensor-based methods require the installation of additional sensors within the module, significantly increasing monitoring costs and device operational risks; while health-sensitive parameter methods are widely used due to their fast response speed and low invasiveness. Based on the different mechanisms of bond wire failure, health-sensitive parameter methods can be further divided into resistance-inductance based monitoring methods and capacitance-based monitoring methods. While resistance-inductance based monitoring methods can identify open-circuit failures, their discrimination is relatively low and they are easily affected by partial bond wire failures. In contrast, capacitance-based monitoring methods can avoid interference from partial bond wire failures and have higher discrimination, making them the most promising open-circuit failure monitoring method currently available.

[0004] Currently, capacitance-based monitoring methods mainly include: turn-on delay time t don Shutdown delay time t doff Pre-threshold voltage V GE(pre-th) Gate charge Q G Crosstalk voltage V GEB , Turn-off voltage change rate dV CE / dt, gate voltage fall time tgf However, the above methods have drawbacks such as numerous influencing factors, high invasiveness, susceptibility to power circuit interference, and measurement difficulties, which are not conducive to in-situ monitoring of open-circuit failures in multi-chip IGBT modules. Summary of the Invention

[0005] This invention provides a method and system for monitoring open-circuit failures of multi-chip IGBT module chips. The technical problem it solves is that existing methods for monitoring open-circuit failures of multi-chip IGBT module chips are subject to many influencing factors, are highly invasive, easily interfered with, have low discrimination, and are difficult to measure.

[0006] To address the above technical problems, this invention provides a method for monitoring open-circuit failures in multi-chip IGBT modules, comprising the following steps:

[0007] Determine the health sensitivity parameter for monitoring open-circuit failure of multi-chip IGBT modules. This health sensitivity parameter is related to the number of effective chip branches n in the multi-chip IGBT module and is at least unaffected by bus voltage and load current.

[0008] Measure the health-sensitive parameter values ​​of the multi-chip IGBT module and convert them into an analog voltage signal V. PG ;

[0009] Determine the analog voltage signal V that indicates an open-circuit failure in a multi-chip IGBT module. PG Failure threshold V REF3 ;

[0010] Based on measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has experienced an open-circuit failure.

[0011] Furthermore, the health-sensitive parameter is determined as the gate voltage of the multi-chip IGBT module rising from 0 to a set voltage V. SET The time is the gate voltage precharge time t PG Set voltage V SET It is set below the flat band voltage when the multi-chip IGBT module operates at its maximum operating voltage.

[0012] Furthermore, by using the measured analog voltage signal V PG and failure threshold V REF3 For comparison, if V PG Below the failure threshold V REF3 If V PG Above the failure threshold V REF3 If so, it is determined that the multi-chip IGBT module has not experienced a chip open-circuit failure.

[0013] Furthermore, the measurement of the health-sensitive parameter values ​​of the multi-chip IGBT module and its conversion into an analog voltage signal V PG The specific steps include:

[0014] Capture the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of a multi-chip IGBT module;

[0015] The equivalent pulse representing the gate voltage precharge time t is obtained based on the captured turn-on and turn-off process of a multi-chip IGBT module. PG Digital pulses;

[0016] Gate voltage precharge time t PG The pulse of the turn-off process in the digital pulse is obtained, and the resulting pulse is converted into an amplitude representation t. PG The analog voltage signal V PG .

[0017] Furthermore, the capture of the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of the multi-chip IGBT module specifically includes the following steps:

[0018] Voltage matching is performed on the gate voltage signal of the multi-chip IGBT module by a voltage divider composed of voltage divider resistors R1 and R2.

[0019] The output voltage V of the resistor divider is converted by a non-inverting adder. ge Raise a DC voltage E C Ensure the output signal V of the in-phase adder gep Within the input voltage range allowed by the window comparator;

[0020] The output signal V of the in-phase adder gep The input is fed to the window comparator and compared with the input reference voltage V. REF1 and V REF2 Compare and output the corresponding comparison result V. a and V b V REF2 That is, set voltage V SET ;

[0021] Comparison result V a and V b The outputs are respectively sent to the logic sub-circuit through digital isolators U4 and U5 to obtain the equivalent pulses of the turn-on and turn-off process of the multi-chip IGBT module.

[0022] Furthermore, the equivalent pulse acquisition based on the captured multi-chip IGBT module's turn-on and turn-off process represents the gate voltage pre-charge time t. PG The digital pulse, specifically includes the following steps:

[0023] The output signal V of the window comparatora and V b The corresponding equivalent pulse is input to the logic AND gate U6 to obtain the digital pulse V represented by the pulse width. gg ;

[0024] The output signal V of the window comparator b The corresponding equivalent pulse is input to the RC delay circuit, and the output signal of the RC delay circuit is the same as V. b The corresponding equivalent pulses are input together to the logic AND gate U7 to obtain the enable signal OE.

[0025] Furthermore, the gate voltage pre-charge time t PG The pulse of the turn-off process in the digital pulse is obtained, and the resulting pulse is converted into an amplitude representation t. PG The analog voltage signal V PG The specific steps include:

[0026] The output signal V of the AND gate U6 gg The signal input terminal of the tri-state buffer U8 is input to the enable terminal of the tri-state buffer U8, and the output signal OE of the logic AND gate U7 is input to the enable terminal of the tri-state buffer U8.

[0027] The output signal V of the tri-state buffer U8 buf The input is fed into an RC integrator circuit consisting of resistor R8 and capacitor C3 to obtain the amplitude representative t. PG The analog voltage signal V PG .

[0028] Furthermore, the analog voltage signal V based on actual measurements PG and failure threshold V REF3 Determining whether a multi-chip IGBT module has experienced an open-circuit failure includes the following steps:

[0029] The enable signal OE is passed through an RC delay circuit and a NOT gate U. 10 Thus, the D flip-flop U is obtained. 11 The clock signal CLK;

[0030] Output signal V PG With input reference voltage V REF3 The input is compared with the high-speed comparator U9;

[0031] The output signal of high-speed comparator U9 is input to D flip-flop U. 11 Data input terminal;

[0032] D trigger U 11 Output voltage signal V that characterizes the health status of the IGBT module chip branch. dia ;

[0033] If the output voltage Vdia If the signal is low, the multi-chip IGBT module is in a healthy state.

[0034] If the output voltage V dia If the signal is high, the multi-chip IGBT module will experience an open-circuit failure.

[0035] This invention also provides a multi-chip IGBT module chip open-circuit failure monitoring system. The key feature of this system is that it includes a health-sensitive parameter determination module, a measurement module, a failure threshold determination module, and a diagnostic module. The health-sensitive parameter determination module determines the health-sensitive parameters for monitoring open-circuit failures in the multi-chip IGBT module. The measurement module measures the health-sensitive parameter values ​​of the multi-chip IGBT module and converts them into an analog voltage signal V. PG The failure threshold determination module is used to determine the analog voltage signal V that indicates an open-circuit failure in a multi-chip IGBT module. PG Failure threshold V REF3 The diagnostic module is based on the measured analog voltage signal V. PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has experienced an open-circuit failure.

[0036] Preferably, the measurement module employs a measurement circuit, which includes a signal processing sub-circuit, a logic sub-circuit, and a signal conversion sub-circuit.

[0037] The signal processing subcircuit includes a resistor divider composed of resistors R1 and R2, a non-inverting adder composed of a high-speed operational amplifier U1, resistors R3, R4, R5, R6, and capacitor C1, a window comparator composed of high-speed comparators U2 and U3, digital isolators U4 and U5, and an input reference voltage V. REF1 V REF2 DC voltage E C Voltage divider resistors R1 and R2 are connected in series and coupled between the gate G and auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the series connection of voltage divider resistors R1 and R2 is coupled to the non-inverting input terminal of the high-speed operational amplifier U1 via resistor R4. The DC voltage E C Resistor R5 is coupled to the non-inverting input of high-speed operational amplifier U1. Resistor R3 is coupled between the inverting input of high-speed operational amplifier U1 and reference ground. Resistor R6 and capacitor C1 are connected in parallel and coupled between the inverting input and output of high-speed operational amplifier U1. The output of high-speed operational amplifier U1 is coupled to the non-inverting input of high-speed comparator U2 and the inverting input of high-speed comparator U3, respectively. The input reference voltage V... REF1 V REF2The outputs of high-speed comparators U2 and U3 are respectively coupled to the inverting input of high-speed comparator U2 and the non-inverting input of high-speed comparator U3, and the outputs of high-speed comparators U2 and U3 are respectively coupled to the inputs of digital isolators U4 and U5.

[0038] The logic sub-circuit includes an RC delay circuit consisting of a resistor R7 and a capacitor C2, and two AND gates U6 and U7. The resistor R7 and capacitor C2 are connected in series and coupled between the output of the digital isolator U4 and the digital reference ground. The input of the AND gate U6 is coupled to the midpoint of the RC delay circuit and the output of the digital isolator U4, respectively. The input of the AND gate U7 is coupled to the output of the digital isolator U4 and the output of the digital isolator U5, respectively.

[0039] The signal conversion sub-circuit includes a tri-state buffer U8 and an RC integrator circuit composed of resistor R8 and capacitor C3. The enable terminal of the tri-state buffer U8 is coupled to the output terminal of AND gate U6, and the signal input terminal of the tri-state buffer U8 is coupled to the output terminal of AND gate U7. Resistor R8 and capacitor C3 are connected in series and coupled between the output terminal of the tri-state buffer U8 and the digital reference ground. The output voltage at the midpoint of the series connection of resistor R8 and capacitor C3 is V, which characterizes the gate voltage pre-charge time. PG .

[0040] The present invention provides a method and system for monitoring open-circuit failures of multi-chip IGBT modules. First, it determines the health-sensitive parameters for monitoring open-circuit failures in the multi-chip IGBT module. Then, it measures the health-sensitive parameter values ​​of the multi-chip IGBT module and converts them into an analog voltage signal V. PG Then, determine the analog voltage signal V that indicates an open-circuit failure in the multi-chip IGBT module. PG Failure threshold V REF3 Finally, the measured analog voltage signal V PG and failure threshold V REF3 The comparison is performed to determine whether the multi-chip IGBT module has experienced an open-circuit failure. This invention enables open-circuit failure monitoring of multi-chip IGBT modules without disassembling the module package. It only requires acquiring the gate voltage signal, is less affected by factors, is easy to measure, is non-invasive, and can be plug-and-play or integrated into the drive circuit. It facilitates in-situ monitoring of open-circuit failures in multi-chip IGBT modules and has strong practical application value. Attached Figure Description

[0041] Figure 1 is a flowchart of the multi-chip IGBT module chip open-circuit failure monitoring method provided in an embodiment of the present invention;

[0042] Figure 2 is a structural and circuit diagram of the multi-chip IGBT module provided in an embodiment of the present invention;

[0043] Figure 3 shows the collector-emitter voltage V during the turn-on process of the multi-chip IGBT module provided in this embodiment of the invention. CE Collector current i C Gate voltage v GE Gate current i G Waveform diagram;

[0044] Figure 4 is a circuit diagram of the measurement circuit provided in an embodiment of the present invention;

[0045] Figure 5 is an ideal waveform diagram of key nodes of the multi-chip IGBT module gate voltage precharge time measurement circuit provided in the embodiment of the present invention.

[0046] Figure 6 is a dual-pulse test circuit diagram of a multi-chip IGBT module provided in an embodiment of the present invention;

[0047] Figure 7 shows the multi-chip IGBT module under two operating conditions with different bus voltages V provided in the embodiments of the present invention. DC V below PG Resulting image;

[0048] Figure 8 shows the multi-chip IGBT module under two different operating conditions with different load currents I0 according to the embodiments of the present invention. L V below PG Resulting image;

[0049] Figure 9 shows the multi-chip IGBT module under two operating conditions at different junction temperatures T according to the embodiments of the present invention. j V below PG Resulting image;

[0050] Figure 10 is a circuit diagram of the diagnostic circuit provided in an embodiment of the present invention;

[0051] Figure 11 shows the waveforms of the intermediate nodes and output signals of the diagnostic circuit under different operating conditions provided in the embodiments of the present invention. Detailed Implementation

[0052] The embodiments of the present invention are described in detail below with reference to the accompanying drawings. The embodiments are given for illustrative purposes only and should not be construed as limiting the present invention. The accompanying drawings are for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0053] The multi-chip IGBT module chip open-circuit failure monitoring method provided in this embodiment of the invention, as shown in the flowchart of Figure 1, includes the following steps:

[0054] Determine the health sensitivity parameter for monitoring open-circuit failure of multi-chip IGBT modules. This health sensitivity parameter is related to the number of effective chip branches n in the multi-chip IGBT module and is at least unaffected by bus voltage and load current.

[0055] Measure the health-sensitive parameter values ​​of the multi-chip IGBT module and convert them into an analog voltage signal V. PG ;

[0056] Determine the analog voltage signal V that indicates an open-circuit failure in a multi-chip IGBT module. PG Failure threshold V REF3 ;

[0057] Based on measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has experienced an open-circuit failure.

[0058] Figure 2 shows the structure and circuit of a specific multi-chip IGBT module. This module is an FF150R12ME3G soldered IGBT module. Figure 2(a) shows the internal structure of the FF150R12ME3G soldered IGBT module, and Figure 2(b) shows the equivalent circuit of the FF150R12ME3G soldered IGBT module. The FF150R12ME3G soldered IGBT module contains two switches connected in series to form a half-bridge structure. Each switch consists of three chip branches, each branch consisting of one IGBT chip and one FWD chip. In Figure 2(a), the first capital letter of the parameter label means: Q represents the IGBT chip, D represents the diode chip, G represents the gate, AE represents the auxiliary emitter, C represents the collector, and E represents the emitter. The first subscript of the parameter label means: T represents the top, and B represents the bottom. The second subscript (if present) specifies the chip number. In Figure 2(b), R gint L g C GC C GE and C CE These are the internal gate resistance, gate circuit parasitic inductance, gate-collector capacitance, gate-emitter capacitance, and collector-emitter capacitance for each chip branch. T For the parasitic inductance of the upper power supply terminal, L C For the parasitic inductance of the midpoint power supply terminal, L B This is the parasitic inductance of the lower tube power supply terminal.

[0059] Collector-emitter voltage V during the turn-on process of a multi-chip IGBT module CE Collector current i C Gate voltage v GE Gate current i GThe waveform diagram is shown in Figure 3, where V DC I L V PO V FB V TH V GP V GON V GOFF and I GP These are, respectively, the DC bus voltage, load current, gate spike voltage, flat-band voltage, threshold voltage, Miller plateau voltage, turn-on gate voltage, turn-off gate voltage, and Miller plateau current. Based on the characteristics of the collector current, this invention divides the turn-on process of a multi-chip IGBT module into two stages:

[0060] (1) Pre-charge stage (t0~t3): During this stage, the gate control signal flips from 0 to 1, and the gate voltage v GE It starts to rise from time t0 and rises to V at times t1, t2, and t3 respectively. PO V FB and V TH During the pre-charging phase, the conductive channel has not yet been formally formed, and the collector current i C and collector-emitter voltage v CE There will be no major changes.

[0061] (2) Fast conduction phase (t>t3): When v GE Exceeding the threshold voltage V TH The conductive channel is formally formed, and the multi-chip IGBT module officially enters the fast conduction stage, with the collector current i C It begins to rise rapidly, collector-emitter voltage v CE It began to decline rapidly.

[0062] The expression for the gate voltage during the pre-charge phase is:

[0063]

[0064] Where n is the number of effective chip branches in the multi-chip IGBT module, R gint R is the internal gate resistance of a single chip branch. gext R is the external gate resistor. gint C is the gate resistance inside a single chip branch. GE For a single chip gate-emitter capacitance, V GON To turn on the gate voltage, V GOFF To turn off the gate voltage, V SET To define t PG The voltage at the end, where t represents time and e represents the natural base.

[0065] Increase the gate voltage from 0 to the set voltage VSET The time is defined as the pre-charge time t PG Then the pre-charging time t PG The relationship between the number of parallel chip branches n and the number of parallel chip branches n can be expressed as:

[0066]

[0067] When an open-circuit failure occurs, the number of parallel chip branches n inside the module decreases, and the gate voltage precharge time t... PG Decrease, therefore t PG It can be used as a health-sensitive parameter for monitoring open-circuit failure of chips.

[0068] Further analysis of t is needed. PG The relationship between bus voltage, load current and junction temperature.

[0069] (1)t PG With bus voltage V DC The relationship between the gate-emitter capacitance C during switching: GE The expression is:

[0070]

[0071] Among them, C OXD This is the gate oxide capacitance, which is independent of the bus voltage. C dep The depletion layer capacitance is inversely proportional to the bus voltage. Therefore, t PG The final voltage V SET Set at flat band voltage V FB The following can eliminate the influence of bus voltage variations. Furthermore, the flat-band voltage V FB Due to the influence of bus voltage and the short-channel effect, V increases with the rise of bus voltage. FB Reduced. Therefore, the present invention reduces V. SET The voltage is set below the flat band voltage at the maximum operating voltage of the multi-chip IGBT module, thereby eliminating the influence of bus voltage variations.

[0072] (2)t PG With load current I L The relationship between the two phases: During the pre-charging phase, the conductive channel in the IGBT gate region has not yet been formally formed. Regardless of changes in the load current, the collector current i flowing through the multi-chip IGBT module... C Since the current is 0, therefore, t PG With load current I L Irrelevant.

[0073] (3)t PG With junction temperature T j The relationship between t PGIn the expression, only R gint Affected by changes in junction temperature, t PG Regarding R gint Differentiation yields:

[0074]

[0075] Among them, R gint Its temperature sensitivity is very small, only 1-2 mV / ℃. Furthermore, the external gate resistor R... gext The presence of R further inhibited gint The effect of changes in junction temperature on t PG It has only a slight impact.

[0076] Therefore, in this embodiment, the health-sensitive parameter is determined as the gate voltage pre-charge time t of the multi-chip IGBT module. PG The health-sensitive parameter can also be set to other parameters, but it must be related to the number of effective chip branches n in the multi-chip IGBT module and be at least unaffected by the bus voltage and load current.

[0077] To effectively measure the health-sensitive parameters (gate voltage, precharge time t) of multi-chip IGBT modules... PG It converts it into an analog voltage signal V. PG The specific steps adopted in this embodiment are as follows:

[0078] Capture the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of a multi-chip IGBT module;

[0079] The equivalent pulse representing the gate voltage precharge time t is obtained based on the captured turn-on and turn-off process of a multi-chip IGBT module. PG Digital pulses;

[0080] Gate voltage precharge time t PG The pulse of the turn-off process in the digital pulse is obtained, and the resulting pulse is converted into an amplitude representation t. PG The analog voltage signal V PG .

[0081] This embodiment designs a measurement circuit to implement the above three steps. As shown in the circuit diagram of the measurement circuit in Figure 4, the measurement circuit specifically includes a signal processing subcircuit, a logic subcircuit, and a signal conversion subcircuit, which are used to implement the above three steps respectively.

[0082] The main function of the signal processing sub-circuit is to capture t PGThe start and end times. As shown in Figure 4, the signal processing sub-circuit includes a resistor divider composed of voltage divider resistors R1 and R2, a non-inverting adder composed of high-speed operational amplifier (OPA) U1, resistors R3, R4, R5, R6 and capacitor C1, a window comparator composed of high-speed comparators (CMP) U2 and U3, digital isolators (ISO) U4 and U5, and an input reference voltage V. REF1 V REF2 (Input reference voltage V) REF2 V represents SET DC voltage E C Voltage divider resistors R1 and R2 are connected in series and coupled between the gate G and auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the series connection of voltage divider resistors R1 and R2 is coupled to the non-inverting input terminal of the high-speed operational amplifier U1 via resistor R4. The DC voltage E C Resistor R5 is coupled to the non-inverting input of high-speed operational amplifier U1. Resistor R3 is coupled between the inverting input of high-speed operational amplifier U1 and reference ground. Resistor R6 and capacitor C1 are connected in parallel and coupled between the inverting input and output of high-speed operational amplifier U1. The output of high-speed operational amplifier U1 is coupled to the non-inverting input of high-speed comparator U2 and the inverting input of high-speed comparator U3, respectively. The input reference voltage V... REF1 V REF2 The outputs of high-speed comparators U2 and U3 are coupled to the inverting input of high-speed comparator U2 and the non-inverting input of high-speed comparator U3, respectively. The outputs of high-speed comparators U2 and U3 are coupled to the inputs of digital isolators U4 and U5, respectively.

[0083] The workflow of the signal processing sub-circuit is as follows:

[0084] Voltage matching is performed on the gate voltage signal of the multi-chip IGBT module by a voltage divider composed of voltage divider resistors R1 and R2.

[0085] The output voltage V of the resistor divider is converted by a non-inverting adder. ge Raise a DC voltage E C Ensure the output signal V of the in-phase adder gep Within the input voltage range allowed by the window comparator, and suppressing gate spike voltage V PO Interference;

[0086] The output signal V of the in-phase adder gep The input is fed to the window comparator and compared with the input reference voltage V. REF1 and V REF2 Compare and output the corresponding comparison result V. a and V b ;

[0087] Compare the results V a and Vb The outputs are respectively sent to the logic sub-circuit through digital isolators U4 and U5 to obtain the equivalent pulses of the turn-on and turn-off process of the multi-chip IGBT module.

[0088] It should be noted that the parallel capacitor C1 in the feedback loop of the in-phase adder mainly functions to perform phase compensation and form a low-pass filter to suppress the gate voltage spike V. PO The capacitance design principle for interference with measurements is as follows:

[0089]

[0090] Among them, t r_PG The duration of the gate voltage pre-charge phase.

[0091] The main function of the logic sub-circuit is to convert the comparison result of the window comparator into a pulse width representation t. PG The digital pulses are generated, and an enable signal for the signal conversion sub-circuit is produced. As shown in Figure 4, the logic sub-circuit includes an RC delay circuit consisting of resistor R7 and capacitor C2, and two AND gates U6 and U7. Resistor R7 and capacitor C2 are connected in series and coupled between the output of digital isolator U4 and digital reference ground. The input of AND gate U6 is coupled to the midpoint of the RC delay circuit and the output of digital isolator U4, respectively. The input of AND gate U7 is coupled to the outputs of digital isolator U4 and digital isolator U5, respectively.

[0092] The workflow of the logic sub-circuit is as follows:

[0093] The output signal V of the window comparator a and V b The corresponding equivalent pulse is input to the logic AND gate U6 to obtain the digital pulse V represented by the pulse width. gg ;

[0094] The output signal V of the window comparator b The corresponding equivalent pulse is input to the RC delay circuit, and the output signal of the RC delay circuit is the same as V. b The corresponding equivalent pulses are input together to the logic AND gate U7 to obtain the enable signal OE.

[0095] The main function of the signal conversion sub-circuit is to eliminate the pulse during the turn-off process and convert t PG Converted into analog voltage signal V PGAs shown in Figure 4, the signal conversion sub-circuit includes a three-state buffer (3S-buf) U8 and an RC integrator circuit composed of resistor R8 and capacitor C3. The enable terminal of the three-state buffer U8 is coupled to the output terminal of the AND gate U6, and the signal input terminal of the three-state buffer U8 is coupled to the output terminal of the AND gate U7. Resistor R8 and capacitor C3 are connected in series and coupled between the output terminal of the three-state buffer U8 and the digital reference ground. The output voltage at the midpoint of the series connection of resistor R8 and capacitor C3 is V, which characterizes the gate voltage precharge time. PG .

[0096] The working process of the signal conversion sub-circuit is as follows:

[0097] The output signal V of the AND gate U6 gg The signal input terminal of the tri-state buffer U8 is input to the enable terminal of the tri-state buffer U8, and the output signal OE of the logic AND gate U7 is input to the enable terminal of the tri-state buffer U8.

[0098] The output signal V of the tri-state buffer U8 buf The input is fed into an RC integrator circuit consisting of resistor R8 and capacitor C3 to obtain the amplitude representative t. PG The analog voltage signal V PG .

[0099] The design principle of the RC integrator circuit in the signal conversion sub-circuit is based on the allowable input voltage range of the microprocessor ADC. Taking a microprocessor with an allowable input voltage range of 3.3V as an example, and ensuring a 20% safety margin, the principle for selecting the value of the RC integrator circuit is as follows:

[0100]

[0101] Figure 5 shows the ideal waveform of the key node of the multi-chip IGBT module gate voltage precharge time measurement circuit, where t delay The delay time introduced by the RC delay circuit in the logic sub-circuit is HI-Z, which is the high-impedance state. The gate voltage of the multi-chip IGBT module, after signal processing and logic sub-circuit operation, yields a pulse width of t. PG Digital pulse V gg and enable signal OE. At t PG Within the range (t0~t1), OE is high, and the output signal V of U8 is high. buf At time t0, the voltage level transitions from low to high, and capacitor C3 begins charging. The voltage V across C3 is... PG It rises exponentially from 0. During the t1 to t5 phase, OE flips to a low level, and V... buf In a high-resistivity state, V PG The value at time t1 remains unchanged. This state continues until time t5, when OE toggles high again, and V... PGDischarge begins to 0. It should be noted that the t1 to t5 stages include the turn-off process of the multi-chip IGBT module, thus eliminating the influence of digital pulses during the turn-off process.

[0102] This embodiment constructs a dual-pulse test circuit for a multi-chip IGBT module as shown in Figure 6. It performs full-condition tests on a healthy multi-chip IGBT module and a multi-chip IGBT module with an open-circuit failure in one chip branch, recording the Vt values ​​under all operating conditions. PG Based on the experimental results, a failure threshold V was set to determine whether a multi-chip IGBT module experienced an open-circuit failure. REF3 In Figure 6, the upper IGBT device is always in the off state, while the lower IGBT device is in the normal switching state, and the load inductance L... load Connected in parallel across the upper IGBT device, V DC DC power supply voltage, C DC For DC side support capacitor, R gext V is the external gate resistor. GG This is the gate control signal.

[0103] In a specific experiment, this embodiment of the invention uses a multi-chip IGBT module FF150R12ME3G with three parallel chip branches, as shown in Figure 2, to test under healthy operating conditions and an open-circuit failure condition where one chip branch experiences an open-circuit failure. The experimental circuit is configured according to Figure 6. The relevant parameter settings for the experimental circuit are shown in Table 1 below. The open-circuit failure of the multi-chip IGBT module chip is achieved by cutting the Q branch shown in Figure 2. B1 Simulations were performed on all emitter bond lines.

[0104] Table 1

[0105]

[0106] Figure 7 shows the multi-chip IGBT module under two operating conditions at different bus voltages V. DC V below PG The results are shown in the following figures: (a) is the time-domain waveform, and (b) is the waveform at different bus voltages V. DC V below PG Overview diagram. Figure 7 shows V under healthy operating conditions and open-circuit failure conditions. PG With bus voltage V DC Irrelevant, V under both operating conditions PG The value remains basically unchanged under healthy operating conditions. PG The average value is approximately 2.669V, the highest value is 2.675V, and the lowest value is 2.655V. This is the V value under open-circuit failure conditions. PG The average value is approximately 1.733V, the highest value is 1.738V, and the lowest value is 1.729V.

[0107] Figure 8 shows the multi-chip IGBT module under two different operating conditions with different load currents I0. L V below PG The results are shown in the following figures: (a) is the time-domain waveform, and (b) is the waveform at different bus voltages V. DC V below PG Overview diagram. Figure 8 shows V under healthy operating conditions and open-circuit failure conditions. PG With load current I L Irrelevant, V under both operating conditions PG The value remains basically unchanged under healthy operating conditions. PG The average value is approximately 2.672V, the highest value is 2.675V, and the lowest value is 2.671V. This is the V value under open-circuit failure conditions. PG The average value is approximately 1.732V, the highest value is 1.735V, and the lowest value is 1.729V.

[0108] Figure 9 shows the multi-chip IGBT module under two operating conditions at different junction temperatures. j V below PG The results are shown in the figure, where (a) is the time-domain waveform and (b) is the waveform at different junction temperatures T. j V below PG Overview diagram. Figure 9 shows V under healthy operating conditions and open-circuit failure conditions. PG With junction temperature T j The correlation is not significant; V under both operating conditions PG The changes are not significant; V under healthy operating conditions PG The average value is approximately 2.675V, the highest value is 2.707V, and the lowest value is 2.643V. This is the V value under open-circuit failure conditions. PG The average value is approximately 1.729V, the highest value is 1.783V, and the lowest value is 1.673V.

[0109] As can be seen from Figures 7 to 9, V under both operating conditions PG Both are relatively stable, and V under both operating conditions PG There are significant differences; using rounding, the results will vary depending on the bus voltage V. DC Different load currents I L Different junction temperatures T j V under healthy working conditions PG Both are 2.7V (V) He ), while V under open-circuit failure condition PG Both are 1.7V (V) Fa To accurately distinguish between these two operating conditions, this embodiment determines the failure threshold V for open-circuit failure in a multi-chip IGBT module. REF3 Set to:

[0110] VREF3 ∈[V Fa +α(V He -V Fa ),V Fa -α(V He -V Fa )](7)

[0111] The value of the coefficient factor α must satisfy V Fa +α(V He -V Fa () is greater than V under all open-circuit failure conditions PG The maximum value, V Fa -α(V He -V Fa () less than V under all healthy operating conditions PG The minimum value.

[0112] To accurately distinguish between healthy operating conditions and open-circuit failure conditions, α should not be too small. In this embodiment, α is selected between (0.1, 0.5). Ultimately, this embodiment determines that α equals 0.4, and the failure threshold V is determined accordingly. REF3 The value is selected from [2.1, 2.3]V. In this example, the failure threshold V is selected. REF3 It is 2.3V.

[0113] By measuring the analog voltage signal V PG and failure threshold V REF3 For comparison, if V PG Below the failure threshold V REF3 If V PG Above the failure threshold V REF3 If so, it is determined that the multi-chip IGBT module has not experienced a chip open-circuit failure.

[0114] In addition to testing multi-chip IGBT modules with open-circuit failure in one chip branch, it is also possible to test multi-chip IGBT modules with open-circuit failure in two or more chip branches. By setting a failure threshold sufficient to distinguish between the healthy operating condition and the open-circuit failure condition in one chip branch, two chip branches to n-1 chip branches, the number of chip branches with open-circuit failure can be obtained.

[0115] In order to convert the measured analog voltage signal V PG and failure threshold V REF3 By comparing and obtaining diagnostic results, this embodiment of the invention designs a diagnostic circuit, as shown in the circuit diagram of Figure 10. The diagnostic circuit mainly includes a high-speed comparator U9, an RC delay circuit composed of resistor R9 and capacitor C4, and a logic NOT gate U. 10D flip-flop U 11 Input reference voltage V REF3 (Failure threshold). The input terminals of the high-speed comparator U9 are respectively connected to the input reference voltage V. REF3 and the measurement circuit output V PG Coupling. Resistor R9 and capacitor C4 are connected in series and coupled between the output of AND gate U6 and digital reference ground, and the NOT gate U6 is also connected in series. 10 The input terminal is coupled at the midpoint of resistor R9 and capacitor C4 in series. The D flip-flop U... 11 The input terminals are respectively connected to the output terminal of the high-speed comparator U9 and the logic NOT gate U 10 Output coupling. D flip-flop U 11 The output is a voltage signal V that characterizes the health status of the chip branch of the multi-chip IGBT module. dia .

[0116] The diagnostic circuit works as follows:

[0117] The enable signal OE is passed through an RC delay circuit and a NOT gate U. 10 Thus, the D flip-flop U is obtained. 11 The clock signal CLK;

[0118] The output signal V of the measurement circuit PG With input reference voltage V REF3 The input is compared with the high-speed comparator U9;

[0119] The output signal of high-speed comparator U9 is input to D flip-flop U. 11 Data input terminal;

[0120] D trigger U 11 Output voltage signal V that characterizes the health status of the IGBT module chip branch. dia .

[0121] If the output voltage V of the diagnostic circuit dia If the signal is low, the multi-chip IGBT module is in a healthy state.

[0122] If the output voltage V of the diagnostic circuit dia If the signal is high, the multi-chip IGBT module will experience an open-circuit failure.

[0123] Figure 11 shows the intermediate nodes and output signal waveforms of the diagnostic circuit under different operating conditions, where (a) represents the healthy operating condition and (b) represents the open-circuit failure operating condition. As can be seen from Figure 11, when the multi-chip IGBT module does not experience an open-circuit failure, the D flip-flop U... 11 Output signal V dia The level is low. When a chip open-circuit failure occurs in the multi-chip IGBT module, the D flip-flop U... 11 Output signal Vdia The signal level is high, which verifies the effectiveness of the diagnostic circuit.

[0124] It should also be noted that the above-described measurement circuit and diagnostic circuit are only one preferred implementation method, and other circuits and implementation methods that can achieve the same function can also be used.

[0125] This invention also provides a multi-chip IGBT module chip open-circuit failure monitoring system, which applies the above-described multi-chip IGBT module chip open-circuit failure monitoring method. The system includes a health-sensitive parameter determination module, a measurement module, a failure threshold determination module, and a diagnostic module. The health-sensitive parameter determination module determines the health-sensitive parameters for monitoring open-circuit failures in the multi-chip IGBT module. The measurement module measures the health-sensitive parameter values ​​of the multi-chip IGBT module and converts them into an analog voltage signal V. PG The failure threshold determination module is used to determine the analog voltage signal V that indicates an open-circuit failure in a multi-chip IGBT module. PG Failure threshold V REF3 The diagnostic module is based on the measured analog voltage signal V. PG and failure threshold V REF3 This determines whether a multi-chip IGBT module has experienced an open-circuit failure. These modules are electronic modules capable of performing the corresponding functions, and the measurement and diagnostic modules can utilize the aforementioned measurement and diagnostic circuits.

[0126] In summary, the multi-chip IGBT module chip open-circuit failure monitoring method and system provided in this embodiment of the invention first determines the health-sensitive parameters for monitoring open-circuit failures of the multi-chip IGBT module, then measures the health-sensitive parameter values ​​of the multi-chip IGBT module and converts them into an analog voltage signal V. PG Then, determine the analog voltage signal V that indicates an open-circuit failure in the multi-chip IGBT module. PG Failure threshold V REF3 Finally, the measured analog voltage signal V PG and failure threshold V REF3 The comparison is performed to determine whether the multi-chip IGBT module has experienced an open-circuit failure. This invention enables open-circuit failure monitoring of multi-chip IGBT modules without disassembling the module package. It only requires acquiring the gate voltage signal, is less affected by factors, is easy to measure, is non-invasive, and can be plug-and-play or integrated into the drive circuit. It facilitates in-situ monitoring of open-circuit failures in multi-chip IGBT modules and has strong practical application value.

[0127] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for detecting open-circuit failures in multi-chip IGBT module chips, characterized in that, Including the following steps: A health-sensitive parameter for monitoring open-circuit failure of multi-chip IGBT modules is determined. This health-sensitive parameter is related to the number of effective chip branches n in the multi-chip IGBT module and is at least unaffected by bus voltage and load current. The health-sensitive parameter is determined as the rise of the gate voltage of the multi-chip IGBT module from 0 to a set voltage V. SET The time is the gate voltage precharge time t PG Set voltage V SET Set below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module; Measure the health-sensitive parameter values ​​of the multi-chip IGBT module and convert them into an analog voltage signal V. PG ; Determine the analog voltage signal V that indicates an open-circuit failure in a multi-chip IGBT module. PG Failure threshold V REF3 ; Based on measured analog voltage signal V PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has experienced an open-circuit failure.

2. The method for monitoring open-circuit failure of multi-chip IGBT module chips according to claim 1, characterized in that: By measuring the analog voltage signal V PG and failure threshold V REF3 For comparison, if V PG Below the failure threshold V REF3 If V PG Above the failure threshold V REF3 If so, it is determined that the multi-chip IGBT module has not experienced an open-circuit failure.

3. The method for monitoring open-circuit failure of multi-chip IGBT module chips according to claim 2, characterized in that, The health-sensitive parameter values ​​of the multi-chip IGBT module are measured and converted into an analog voltage signal V. PG The specific steps include: Capture the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of a multi-chip IGBT module; The equivalent pulse representing the gate voltage precharge time t is obtained based on the captured turn-on and turn-off process of a multi-chip IGBT module. PG Digital pulses; Gate voltage precharge time t PG The pulse of the turn-off process in the digital pulse is obtained, and the resulting pulse is converted into an amplitude representation t. PG The analog voltage signal V PG .

4. The method for monitoring open-circuit failure of multi-chip IGBT module chips according to claim 3, characterized in that, The capture of the equivalent pulse of the gate voltage signal during the turn-on and turn-off process of the multi-chip IGBT module specifically includes the following steps: Voltage matching is performed on the gate voltage signal of the multi-chip IGBT module by a voltage divider composed of voltage divider resistors R1 and R2. The output voltage V of the resistor divider is converted by a non-inverting adder. ge Raise a DC voltage E C Ensure the output signal V of the in-phase adder gep Within the input voltage range allowed by the window comparator; The output signal V of the in-phase adder gep The input is fed to the window comparator and compared with the input reference voltage V. REF1 and V REF2 Compare and output the corresponding comparison result V. a and V b V REF2 That is, set voltage V SET ; Comparison result V a and V b The outputs are respectively sent to the logic sub-circuit through digital isolators U4 and U5 to obtain the equivalent pulses of the turn-on and turn-off process of the multi-chip IGBT module.

5. The method for monitoring open-circuit failure of multi-chip IGBT module chips according to claim 4, characterized in that, The equivalent pulse acquisition of the turn-on and turn-off process of the multi-chip IGBT module based on the captured signal represents the gate voltage precharge time t. PG The digital pulse, specifically includes the following steps: The output signal V of the window comparator a and V b The corresponding equivalent pulse is input to the logic AND gate U7 to obtain the digital pulse V represented by the pulse width. gg ; The output signal V of the window comparator b The corresponding equivalent pulse is input to the RC delay circuit, and the output signal of the RC delay circuit is the same as V. b The corresponding equivalent pulses are input together to the logic AND gate U6 to obtain the enable signal OE.

6. The method for monitoring open-circuit failure of multi-chip IGBT module chips according to claim 5, characterized in that, The gate voltage precharge time t PG The pulse of the turn-off process in the digital pulse is obtained, and the resulting pulse is converted into an amplitude representation t. PG The analog voltage signal V PG The specific steps include: The output signal V of the AND gate U7 gg The signal input terminal of the tri-state buffer U8 is input to the enable terminal of the tri-state buffer U8, and the output signal OE of the logic AND gate U6 is input to the enable terminal of the tri-state buffer U8. The output signal V of the tri-state buffer U8 buf The input is fed into an RC integrator circuit consisting of resistor R8 and capacitor C3 to obtain the amplitude representative t. PG The analog voltage signal V PG .

7. The method for monitoring open-circuit failure of multi-chip IGBT module chips according to claim 6, characterized in that, The analog voltage signal V based on actual measurements PG and failure threshold V REF3 Determining whether a multi-chip IGBT module has experienced an open-circuit failure includes the following steps: The enable signal OE is passed through an RC delay circuit and a NOT gate U. 10 Thus, the D flip-flop U is obtained. 11 The clock signal CLK; Output signal V PG With failure threshold V REF3 The input is compared with the high-speed comparator U9; The output signal of high-speed comparator U9 is input to D flip-flop U. 11 Data input terminal; D trigger U 11 Output voltage signal V that characterizes the health status of the IGBT module chip branch. dia ; If the output voltage V dia If the signal is low, the multi-chip IGBT module is in a healthy state. If the output voltage V dia If the signal is high, the multi-chip IGBT module will experience an open-circuit failure.

8. A multi-chip IGBT module chip open-circuit failure monitoring system, using the multi-chip IGBT module chip open-circuit failure monitoring method according to any one of claims 1 to 7, characterized in that: The system includes a health-sensitive parameter determination module, a measurement module, a failure threshold determination module, and a diagnostic module. The health-sensitive parameter determination module is used to determine the health-sensitive parameters for monitoring open-circuit failures of multi-chip IGBT module chips. The health-sensitive parameter is determined as the gate voltage of the multi-chip IGBT module rising from 0 to a set voltage V. SET The time is the gate voltage precharge time t PG Set voltage V SET The voltage is set below the flat-band voltage at the maximum operating voltage of the multi-chip IGBT module; the measurement module is used to measure the health-sensitive parameter values ​​of the multi-chip IGBT module and convert them into an analog voltage signal V. PG The failure threshold determination module is used to determine the analog voltage signal V that indicates an open-circuit failure in a multi-chip IGBT module. PG Failure threshold V REF3 The diagnostic module is based on the measured analog voltage signal V. PG and failure threshold V REF3 Determine whether a multi-chip IGBT module has experienced an open-circuit failure.

9. The multi-chip IGBT module chip open-circuit failure monitoring system according to claim 8, characterized in that: The measurement module employs a measurement circuit, which includes a signal processing sub-circuit, a logic sub-circuit, and a signal conversion sub-circuit. The signal processing subcircuit includes a resistor divider composed of resistors R1 and R2, a non-inverting adder composed of a high-speed operational amplifier U1, resistors R3, R4, R5, R6, and capacitor C1, a window comparator composed of high-speed comparators U2 and U3, digital isolators U4 and U5, and an input reference voltage V. REF1 V REF2 DC voltage E C Voltage divider resistors R1 and R2 are connected in series and coupled between the gate G and auxiliary emitter AE of the multi-chip IGBT module. The midpoint of the series connection of voltage divider resistors R1 and R2 is coupled to the non-inverting input terminal of the high-speed operational amplifier U1 via resistor R4. The DC voltage E C Resistor R5 is coupled to the non-inverting input of high-speed operational amplifier U1. Resistor R3 is coupled between the inverting input of high-speed operational amplifier U1 and reference ground. Resistor R6 and capacitor C1 are connected in parallel and coupled between the inverting input and output of high-speed operational amplifier U1. The output of high-speed operational amplifier U1 is coupled to the non-inverting input of high-speed comparator U2 and the inverting input of high-speed comparator U3, respectively. The input reference voltage V... REF1 V REF2 The outputs of high-speed comparators U2 and U3 are respectively coupled to the inverting input of high-speed comparator U2 and the non-inverting input of high-speed comparator U3, and the outputs of high-speed comparators U2 and U3 are respectively coupled to the inputs of digital isolators U4 and U5. The logic sub-circuit includes an RC delay circuit consisting of a resistor R7 and a capacitor C2, and two AND gates U6 and U7. The resistor R7 and capacitor C2 are connected in series and coupled between the output of the digital isolator U4 and the digital reference ground. The input of the AND gate U6 is coupled to the midpoint of the RC delay circuit and the output of the digital isolator U4, respectively. The input of the AND gate U7 is coupled to the output of the digital isolator U4 and the output of the digital isolator U5, respectively. The signal conversion sub-circuit includes a tri-state buffer U8 and an RC integrator circuit composed of resistor R8 and capacitor C3. The enable terminal of the tri-state buffer U8 is coupled to the output terminal of AND gate U6, and the signal input terminal of the tri-state buffer U8 is coupled to the output terminal of AND gate U7. Resistor R8 and capacitor C3 are connected in series and coupled between the output terminal of the tri-state buffer U8 and the digital reference ground. The output voltage at the midpoint of the series connection of resistor R8 and capacitor C3 is V, which characterizes the gate voltage pre-charge time. PG。

Images