Semiconductor chopper device
By connecting IGBT chips in parallel on two copper-clad ceramic substrates and combining them with an external drive control circuit in a semiconductor chopper device, the problem of grid disconnection caused by voltage fluctuations in wind turbine units is solved, improving chopping capability and power density while reducing costs.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- NANJING NARI SEMICON CO LTD
- Filing Date
- 2025-12-01
- Publication Date
- 2026-07-30
AI Technical Summary
Existing semiconductor chopper devices cannot effectively cope with voltage fluctuations caused by sudden rises in grid voltage in wind turbines, leading to wind turbine disconnection from the grid, and their power density and chopper capability are insufficient.
The design employs a copper-clad ceramic substrate, in which IGBT chips are connected in parallel on two copper-clad ceramic substrates and then connected by bonding wire bundles. Combined with an external drive control circuit, this achieves the parallel connection of IGBT chips and the electrical connection of FRD chips, thereby improving chopping capability and power density.
This significantly improves the chopping capability and power density of the chopper device, reduces costs, and ensures the heat dissipation performance and reliability of the IGBT chip, preventing wind turbines from disconnecting from the grid.
Smart Images
Figure CN2025139036_30072026_PF_FP_ABST
Abstract
Description
Semiconductor chopper device
[0001] This disclosure claims priority to Chinese patent application No. 202510098817.5, filed on January 22, 2025, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This disclosure relates to power semiconductor devices, and more particularly to a semiconductor chopper device. Background Technology
[0003] Large-scale development of wind power is a crucial support for achieving the "dual carbon" goals. As the installed capacity of wind power continues to increase, the inherent random fluctuations of wind power and disturbances from the external power grid can cause significant voltage fluctuations within wind turbine clusters. Especially when the grid voltage suddenly spikes, voltage fluctuations in the turbines can easily cause cascading voltage fluctuations throughout the entire wind turbine cluster, potentially leading to large-scale grid disconnection and substantial economic losses. Summary of the Invention
[0004] This disclosure provides a semiconductor chopper device, including a device heat dissipation substrate, on which a first copper-clad ceramic substrate and a second copper-clad ceramic substrate are disposed. The device also includes an upper bridge circuit and a lower bridge circuit. The upper bridge circuit includes one or more parallel-connected fast recovery diode (FRD) chips, which are disposed in parallel on the second copper-clad ceramic substrate or the first copper-clad ceramic substrate, or simultaneously on both substrates. The lower bridge circuit includes multiple parallel-connected insulated-gate bipolar transistor (IGBT) chips, with some IGBT chips disposed on the first copper-clad ceramic substrate and others on the second copper-clad ceramic substrate.
[0005] In some embodiments, the lower bridge circuit includes a first IGBT chip, a second IGBT chip, a third IGBT chip, a fourth IGBT chip, a fifth IGBT chip, a sixth IGBT chip, a first FRD chip, a second FRD chip, and a third FRD chip;
[0006] The collectors of the first IGBT chip, the second IGBT chip, and the third IGBT chip are soldered to the cathodes of the first FRD chip, the second FRD chip, and the third FRD chip on the first copper-clad ceramic substrate.
[0007] The collectors of the fourth, fifth, and sixth IGBT chips are soldered onto the second copper-clad ceramic substrate.
[0008] In some embodiments, a first bonding wire cluster is connected between the first copper-clad ceramic substrate and the second copper-clad ceramic substrate, and the collectors of the first IGBT chip, the second IGBT chip, and the third IGBT chip are connected in parallel with the collectors of the fourth IGBT chip, the fifth IGBT chip, and the sixth IGBT chip through the first bonding wire cluster.
[0009] In some embodiments, the emitter of the first IGBT chip is connected to the anode of the first FRD chip via a second bonding wire cluster;
[0010] The emitter of the second IGBT chip is connected to the anode of the second FRD chip via a third bonding wire bundle;
[0011] The emitter of the third IGBT chip and the anode of the third FRD chip are connected by a fourth bonding wire cluster.
[0012] In some embodiments, the emitter of the fourth IGBT chip is connected in parallel with the emitters of the first IGBT chip, the second IGBT chip, and the third IGBT chip through the fifth bonding wire cluster and the eighth bonding wire cluster;
[0013] The emitter of the fifth IGBT chip is connected in parallel with the emitters of the first, second, and third IGBT chips through the sixth and eighth bonding wire clusters.
[0014] The emitter of the sixth IGBT chip is connected in parallel with the emitters of the first, second, and third IGBT chips through the seventh and eighth bonding wire clusters.
[0015] The eighth bonding wire bundle is connected between the first copper-clad ceramic substrate and the second copper-clad ceramic substrate, and the second copper-clad ceramic substrate is electrically connected to the negative terminal.
[0016] In some embodiments, the gates of the first IGBT chip, the second IGBT chip, the third IGBT chip, the fourth IGBT chip, the fifth IGBT chip, and the sixth IGBT chip are connected to an external drive control circuit via signal terminals.
[0017] The emitters of the first, second, third, fourth, fifth, and sixth IGBT chips are connected to an external drive control circuit via return terminals.
[0018] In some embodiments, the bridge circuit includes a plurality of FRD chips connected in parallel, wherein the cathodes of the fourth FRD chip and the fifth FRD chip are soldered onto the second copper-clad ceramic substrate and electrically connected to the positive terminal.
[0019] In some embodiments, the anode of the fourth FRD chip is connected between the collectors of multiple parallel-connected IGBT chips and the cathode of the FRD chip in the lower bridge circuit via a first chip bonding wire cluster and a first bonding wire cluster.
[0020] The anode of the fifth FRD chip is connected between the collector of multiple parallel-connected IGBT chips and the cathode of the FRD chip in the lower bridge circuit through the second chip bonding wire cluster and the first bonding wire cluster.
[0021] In some embodiments, the lower bridge circuit includes a first IGBT chip, a second IGBT chip, a third IGBT chip, a fourth IGBT chip, a first FRD chip, a second FRD chip, and a third FRD chip;
[0022] The collectors of the first IGBT chip and the second IGBT chip are soldered to the cathodes of the first FRD chip and the second FRD chip on the first copper-clad ceramic substrate.
[0023] The collectors of the third IGBT chip and the fourth IGBT chip are welded to the cathode of the third FRD chip on the second copper-clad ceramic substrate.
[0024] The emitter of the first IGBT chip is connected to the anode of the first FRD core through a second bonding wire cluster and a third bonding wire cluster;
[0025] The emitter of the second IGBT chip is connected to the anode of the second FRD chip via a fourth bonding wire cluster;
[0026] The emitter of the third IGBT chip is connected to the anode of the third FRD chip through the fifth and seventh bonding wire clusters;
[0027] The emitter of the fourth IGBT chip is connected to the anode of the third FRD chip via the sixth and seventh bonding wire clusters.
[0028] In some embodiments, the lower bridge circuit includes a fourth FRD chip, a fifth FRD chip, a sixth FRD chip, and a seventh FRD chip; wherein the fourth FRD chip and the fifth FRD chip are configured according to the current requirements of the FRD chip.
[0029] The cathodes of the fourth and fifth FRD chips are welded onto the second copper-clad ceramic substrate and electrically connected to the positive terminal.
[0030] The cathodes of the sixth FRD chip and the seventh FRD chip are soldered onto the first copper-clad ceramic substrate.
[0031] The cathodes of the fourth and fifth FRD chips are connected in parallel with the cathodes of the sixth and seventh FRD chips through the ninth bonding wire cluster. Attached Figure Description
[0032] Figure 1 is a schematic diagram of the structure of chopper devices in some technologies.
[0033] Figure 2 shows the circuit topology of chopper devices in some technologies.
[0034] Figure 3 is a schematic diagram of the structure of a semiconductor chopper device according to some embodiments.
[0035] Figure 4 is a schematic diagram of another semiconductor chopper device according to some embodiments.
[0036] Figure 5 is a schematic diagram of the structure of another semiconductor chopper device according to some embodiments. Detailed Implementation
[0037] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
[0039] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "more than one" means two or more.
[0040] Large-scale development of wind power is a crucial support for achieving the "dual carbon" goal. With the continuous increase in installed wind power capacity, the inherent random fluctuations of wind power and disturbances from the external power grid can cause significant voltage fluctuations within wind turbine clusters. Especially when the grid voltage suddenly rises, voltage fluctuations in the turbines can easily cause cascading voltage fluctuations throughout the entire wind turbine cluster, potentially leading to large-scale wind turbine disconnections and substantial economic losses. For example, large-scale wind turbine disconnection incidents occurred at the Zhangjiakou wind power base in Hebei and Guazhou in Gansu, both caused by excessively low voltage within the wind farm after an external grid fault or by the failure to promptly remove reactive power compensation devices, resulting in excessively high voltage. The high-voltage ride-through capability of wind turbines refers to their ability to maintain continuous operation without disconnection within a certain voltage rise range and time interval when a grid fault or disturbance causes a voltage rise at the grid connection point. Chopper IGBT semiconductor power devices, as core components in chopper devices used in high-voltage ride-through applications, play a vital role in protecting wind turbines from short-term voltage fluctuations that could cause them to stop operating, thus preventing large-scale wind turbine disconnections. Currently, major manufacturers have integrated chopper devices into wind power converters to improve the reliability and stability of wind power generation. As the power output of individual wind turbines gradually increases, higher demands are being placed on the chopper capability and power density of chopper semiconductor devices.
[0041] The chip layout of a traditional chopper device is shown in Figure 1. The lower bridge circuit is placed on the first copper-clad ceramic substrate 61, and the upper bridge circuit is placed on the second copper-clad ceramic substrate 62. The first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62 are soldered to the device heat dissipation substrate 7. The lower bridge circuit consists of multiple IGBT chips and FRD chips connected in antiparallel. The collectors of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 are soldered to the cathodes of the first FRD chip 91, the second FRD chip 92, and the third FRD chip 93 on the first copper-clad ceramic substrate 61 and electrically connected to the output terminal 3. The emitters of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 are connected to the anodes of the first FRD chip 91, the second FRD chip 92, and the third FRD chip 93 through bonding wire bundles 101, 102, and 103, and are electrically connected to the negative terminal 2 through the bonding wire bundle 11 between the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62. The upper bridge circuit consists of multiple FRDs connected in parallel. The cathodes of the upper bridge circuit FRD chips 121, 122, and 123 are soldered onto the second copper-clad ceramic substrate 62 and electrically connected to the positive terminal 1. The anodes of the upper bridge circuit FRD chips 121, 122, and 123 are electrically connected to the collector of the lower bridge circuit IGBT chip group and the cathode of the lower bridge circuit FRD chip through chip bonding wire clusters 131, 132, and 133 and bonding wire cluster 14 between the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62. The gates of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 of the lower bridge circuit are connected to the external drive control circuit through the lower bridge circuit gate signal terminal 4 and the lower bridge gate return terminal 5. The implemented circuit topology is shown in Figure 2, where 1 is the positive terminal, 2 is the negative terminal, 3 is the output terminal, 4 is the gate-level signal terminal of the lower bridge circuit, 5 is the gate-level return terminal of the lower bridge circuit, 6 is the IGBT chip of the lower bridge circuit, 7 is the anti-parallel FRD chip of the lower bridge circuit, and 8 is the FRD chip of the upper bridge circuit.
[0042] The above technologies involve soldering two copper-clad ceramic substrates onto the heat dissipation substrate of a semiconductor chopper. The upper-bridge chip and the lower-bridge chip are each located on one of the copper-clad ceramic substrates, and electrical connection is achieved through the circuit design of the copper-clad ceramic substrates and the connection of bonding wire bundles. Compared to traditional half-bridge IGBT devices, the existing technology topology only removes the IGBT chip from the upper-bridge circuit. The chopping capability is not improved compared to conventional half-bridge devices; it only reduces device cost to a limited extent, and the power density is limited.
[0043] In view of the above, this disclosure provides a semiconductor chopper device, including a device heat dissipation substrate (7), on which a first copper-clad ceramic substrate (61) and a second copper-clad ceramic substrate (62) are disposed. The semiconductor chopper device further includes an upper bridge circuit and a lower bridge circuit. The upper bridge circuit includes one or more parallel fast recovery diode chips (FRD chips), which are disposed in parallel on the second copper-clad ceramic substrate (62) or the first copper-clad ceramic substrate (61), or simultaneously on the first copper-clad ceramic substrate (61) and the second copper-clad ceramic substrate (62). The lower bridge circuit includes multiple parallel insulated gate bipolar transistor (IGBT) chips, with some IGBT chips disposed on the first copper-clad ceramic substrate (61) and other IGBT chips disposed on the second copper-clad ceramic substrate (62).
[0044] The technical solution of this disclosure will now be described in detail with reference to specific embodiments and accompanying drawings.
[0045] Example 1
[0046] As shown in Figure 3, the semiconductor chopper device disclosed herein includes the following components: a positive terminal 1, a negative terminal 2, an output terminal 3, a signal terminal 4, a return terminal 5, a first copper-clad ceramic substrate 61, a second copper-clad ceramic substrate 62, a device heat dissipation substrate 7, a first IGBT chip 81, a second IGBT chip 82, a third IGBT chip 83, a fourth IGBT chip 84, a fifth IGBT chip 85, a sixth IGBT chip 86, a first FRD chip 91, a second FRD chip 92, a third FRD chip 93, a first bonding wire cluster 10, a second bonding wire cluster 111, a third bonding wire cluster 112, a fourth bonding wire cluster 113, a fifth bonding wire cluster 114, a sixth bonding wire cluster 115, a seventh bonding wire cluster 116, an eighth bonding wire cluster 12, a fourth FRD chip 131, a fifth FRD chip 132, a first chip bonding wire cluster 141, and a second chip bonding wire cluster 142.
[0047] Positive terminal 1, negative terminal 2, and output terminal 3 are connected to external circuits, and signal terminal 4 and return terminal 5 are connected to external drive control circuits. The first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62 are welded or sintered onto the device heat dissipation substrate 7.
[0048] The downbridge circuit consists of a group of IGBT chips and an anti-parallel FRD chip. Multiple IGBT chips are connected in parallel. Some IGBT chips are disposed on a first copper-clad ceramic substrate 61, and others are disposed on a second copper-clad ceramic substrate 62. The IGBT chips are soldered or sintered onto the first and second copper-clad ceramic substrates 61 and 62. For example, the downbridge circuit includes a first IGBT chip 81, a second IGBT chip 82, a third IGBT chip 83, a fourth IGBT chip 84, a fifth IGBT chip 85, a sixth IGBT chip 86, a first FRD chip 91, a second FRD chip 92, and a third FRD chip 93.
[0049] The collectors of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 are soldered to the cathodes of the first FRD chip 91, the second FRD chip 92, and the third FRD chip 93, respectively, onto the first copper-clad ceramic substrate 61. The collectors of the fourth IGBT chip 84, the fifth IGBT chip 85, and the sixth IGBT chip 86 are soldered to the second copper-clad ceramic substrate 62. A first bonding wire bundle 10 connects the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62. The collectors of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 are connected in parallel with the collectors of the fourth IGBT chip 84, the fifth IGBT chip 85, and the sixth IGBT chip 86 through the first bonding wire bundle 10, and are electrically connected to the output terminal 3. The first copper-clad ceramic substrate 61 is electrically connected to the output terminal 3.
[0050] The emitter of the first IGBT chip 81 is connected to the anode of the first FRD chip 91 via a second bonding wire bundle 111. The emitter of the second IGBT chip 82 is connected to the anode of the second FRD chip 92 via a third bonding wire bundle 112. The emitter of the third IGBT chip 83 is connected to the anode of the third FRD chip 93 via a fourth bonding wire bundle 113. The emitter of the fourth IGBT chip 84 is connected in parallel with the emitters of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 via a fifth bonding wire bundle 114 and an eighth bonding wire bundle 12, and is electrically connected to the negative terminal 2. The emitter of the fifth IGBT chip 85 is connected in parallel with the emitters of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 via a sixth bonding wire bundle 115 and an eighth bonding wire bundle 12, and is electrically connected to the negative terminal 2. The emitter of the sixth IGBT chip 86 is connected in parallel with the emitters of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 via the seventh bonding wire cluster 116 and the eighth bonding wire cluster 12, and is electrically connected to the negative terminal 2. The eighth bonding wire cluster 12 is connected between the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62, and the second copper-clad ceramic substrate 62 is electrically connected to the negative terminal 2.
[0051] The above method enables the IGBT chip on the first copper-clad ceramic substrate 61 to be connected in parallel with the IGBT chip on the second copper-clad ceramic substrate 62.
[0052] After being connected in parallel, the gates of the first IGBT chip 81, the second IGBT chip 82, and the third IGBT chip 83 disposed on the first copper-clad ceramic substrate 61, and the fourth IGBT chip 84, the fifth IGBT chip 85, and the sixth IGBT chip 86 disposed on the second copper-clad ceramic substrate 62, are connected to the external drive control circuit through signal terminal 4. The emitters of the first IGBT chip 81, the second IGBT chip 82, the third IGBT chip 83, the fourth IGBT chip 84, the fifth IGBT chip 85, and the sixth IGBT chip 86 are connected to the external drive control circuit through return terminal 5.
[0053] The upper bridge circuit is disposed on the second copper-clad ceramic substrate 62. The upper bridge circuit includes multiple FRD chips connected in parallel. In this embodiment, the upper bridge circuit includes a fourth FRD chip 131 and a fifth FRD chip 132. The cathodes of the fourth FRD chip 131 and the fifth FRD chip 132 are soldered to the second copper-clad ceramic substrate 62 and electrically connected to the positive terminal 1. The anode of the fourth FRD chip 131 is connected between the collector of the multiple parallel IGBT chips and the cathode of the FRD chip in the lower bridge circuit through the first chip bonding wire bundle 141 and the first bonding wire bundle 10, realizing the electrical connection between the fourth FRD chip 131 and the collector of the IGBT chip group in the lower bridge circuit and the cathode of the FRD chip in the lower bridge circuit. The anode of the fifth FRD chip 132 is connected between the collector of multiple parallel IGBT chips and the cathode of the FRD chip in the lower bridge circuit through the second chip bonding wire cluster 142 and the first bonding wire cluster 10, thereby realizing the electrical connection between the fifth FRD chip 132 and the collector of the IGBT chip group in the lower bridge circuit and the cathode of the FRD chip in the lower bridge circuit.
[0054] In summary, the technical solution disclosed herein achieves parallel connection of IGBT chips on two copper-clad ceramic substrates through circuit design and bonding wire cluster connection of the copper-clad ceramic substrate. The circuit design of the copper-clad ceramic substrate mainly involves the design of the copper layer pattern on the copper-clad substrate. The final result is that the gate terminal 4 is connected in parallel with the gates of all IGBT chips on the copper-clad ceramic substrate 1 and the copper-clad ceramic substrate 2, and the return terminal 5 is connected to the emitters of all IGBT chips.
[0055] The lower-bridge circuit consists of a group of IGBT chips and an anti-parallel FRD chip. The collectors of the IGBT chips and the cathodes of the FRD chips are soldered to a copper-clad ceramic substrate and electrically connected to the output terminals. The emitters of the IGBT chips and the anodes of the FRD chips are connected front-side via bonding wire bundles and electrically connected to the negative terminal. Through the drive circuit design on the copper-clad ceramic substrate, the gates and emitters of all the lower-bridge IGBT chips on multiple copper-clad ceramic substrates are connected to the external drive control circuit via signal terminals and their return terminals. The upper-bridge circuit consists of one or a group of FRDs connected in parallel. The cathodes of the upper-bridge FRD chips are soldered to a copper-clad ceramic substrate and electrically connected to the anode terminal. The anodes of the upper-bridge FRD chips are electrically connected to the collectors of the lower-bridge IGBT chips and the cathodes of the lower-bridge FRD chips via bonding wire bundles.
[0056] The semiconductor chopper device disclosed herein, through circuit design on copper-clad ceramic substrates, simultaneously arranges the IGBT chip of the lower-bridge circuit on the first and second copper-clad ceramic substrates and connects them in parallel. The rated current carrying capacity of the module can be more than doubled, and the chopping capability is significantly improved compared with current chopper devices, achieving a substantial increase in power density. At the same time, since the IGBT chip is set on two copper-clad ceramic substrates respectively, on the basis of doubling the rated current, the IGBT chip on each copper-clad ceramic substrate is heat-dissipated independently, the thermal resistance of the IGBT chip is not increased, and the junction temperature of the IGBT chip can be maintained at the same level as traditional chopper devices, ensuring normal heat dissipation of the module. It can realize one-to-two replacement at the application end, significantly reducing costs.
[0057] Example 2
[0058] As shown in Figure 4, the difference between this embodiment and Embodiment 1 is that the FRD chip of the upper bridge circuit is simultaneously arranged on the first copper-clad ceramic substrate and the second copper-clad ceramic substrate, which can increase the number of FRD chips and further increase the rated current of the upper bridge FRD chip, improve the surge resistance of the device, and ensure the safe and reliable freewheeling of the upper bridge circuit FRD chip when operating at high current. At the same time, the FRD chips are arranged on the first copper-clad ceramic substrate and the second copper-clad ceramic substrate respectively, which reduces the thermal coupling between the FRD chips, helps to reduce the junction temperature of the FRD chip, and ensures the safe operation of the device.
[0059] In this embodiment, the lower bridge circuit includes a first IGBT chip 81, a second IGBT chip 82, a third IGBT chip 83, a fourth IGBT chip 84, a first FRD chip 91, a second FRD chip 92, and a third FRD chip 93.
[0060] The collectors of the first IGBT chip 81 and the second IGBT chip 82 are soldered to the cathodes of the first FRD chip 91 and the second FRD chip 92, respectively, on the first copper-clad ceramic substrate 61. The collectors of the third IGBT chip 83 and the fourth IGBT chip 84 are soldered to the cathode of the third FRD chip 93, respectively, on the second copper-clad ceramic substrate 62. The collectors of the first IGBT chip 81 and the second IGBT chip 82, and the collectors of the third IGBT chip 83 and the fourth IGBT chip 84 are connected in parallel through a bonding wire bundle 10 disposed between the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62, and are electrically connected to the output terminal 3.
[0061] The emitter of the first IGBT chip 81 is connected to the anode of the first FRD chip 91 via the second bonding wire bundle 111 and the third bonding wire bundle 112. The emitter of the second IGBT chip 82 is connected to the anode of the second FRD chip 92 via the fourth bonding wire bundle 113. The emitter of the third IGBT chip 83 is connected to the anode of the third FRD chip 93 via the fifth bonding wire bundle 114 and the seventh bonding wire bundle 116. The emitter of the fourth IGBT chip 84 is connected to the anode of the third FRD chip 93 via the sixth bonding wire bundle 115 and the seventh bonding wire bundle 116. Based on the fact that the emitters of the first IGBT chip 81, the second IGBT chip 82, the third IGBT chip 83, and the fourth IGBT chip 84 are connected to the anodes of the first FRD chip 91, the second FRD chip 92, and the third FRD chip 93 through corresponding bonding wire clusters, the emitters of the first IGBT chip 81 and the second IGBT chip 82 are also connected in parallel with the emitters of the third IGBT chip 83 and the fourth IGBT chip 84 through the eighth bonding wire cluster 12 between the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62, and are electrically connected to the negative terminal 2.
[0062] The above method enables the parallel connection of IGBT chips on the first copper-clad ceramic substrate 61 and the second copper-clad ceramic substrate 62. The gates and emitters of the first IGBT chip 81 and the second IGBT chip 82 on the first copper-clad ceramic substrate 61, and the third IGBT chip 83 and the fourth IGBT chip 84 on the second copper-clad ceramic substrate 62 are connected to the external drive control circuit through signal terminals 4 and their return terminals 5.
[0063] The upper bridge circuit consists of a group of FRD chips connected in parallel. In this embodiment, the upper bridge circuit includes a fourth FRD chip 131, a fifth FRD chip 132, a sixth FRD chip 133, and a seventh FRD chip 134. The cathodes of the fourth FRD chip 131 and the fifth FRD chip 132 are soldered onto the second copper-clad ceramic substrate 62 and are electrically connected to the positive terminal 1. The cathodes of the sixth FRD chip 133 and the seventh FRD chip 134 are soldered onto the first copper-clad ceramic substrate 61. The cathodes of the fourth FRD chip 131 and the fifth FRD chip 132 are connected in parallel with the cathodes of the sixth FRD chip 133 and the seventh FRD chip 134 through the ninth bonding wire cluster 14 between the copper-clad ceramic substrate 61 and the copper-clad ceramic substrate 62. The anodes of the fourth FRD chip 131 and the fifth FRD chip 132 are connected in parallel with the anodes of the sixth FRD chip 133 and the seventh FRD chip 134 through the third chip bonding wire cluster 151, the fourth chip bonding wire cluster 152, the fifth chip bonding wire cluster 153, the sixth chip bonding wire cluster 154 and the first bonding wire cluster 10 between the ceramic copper-clad substrate 61 and the ceramic copper-clad substrate 62, and are electrically connected to the collector of the IGBT chip in the lower bridge circuit and the cathode of the FRD chip in the lower bridge circuit.
[0064] Example 3
[0065] As shown in Figure 5, the difference between this embodiment and Embodiment 2 is that, according to the current requirements of the FRD chip, the FRD chips 131 and 132 on the second copper-clad ceramic substrate 62, as well as the corresponding bonding wire clusters 151 and 152, can be removed. The upper bridge circuit only includes the sixth FRD chip 133 and the seventh FRD chip 134, which are only arranged on the first copper-clad ceramic substrate 61. In this embodiment, the upper bridge FRD chip is further away from the output terminal 3 that requires a large current flow for a long time, which can further reduce the thermal coupling between the upper bridge FRD chip and the output terminal and ensure the safe and reliable operation of the upper bridge FRD chip.
[0066] Beneficial effects: Compared with the prior art, the significant technical effects of the present invention are as follows:
[0067] By using a copper-clad ceramic substrate circuit design and bonding wire bundle connection, IGBT chips on two copper-clad ceramic substrates in the semiconductor chopper device are connected in parallel.
[0068] Through the circuit design on the copper-clad ceramic substrate, the external drive control circuit can simultaneously control the first copper-clad ceramic substrate and all IGBT chips on the first copper-clad ceramic substrate through the gate signal terminal and the return line terminal. Compared with traditional chopper devices that only set IGBT chips on the lower bridge ceramic copper-clad substrate, the device utilization rate is greatly improved, the chopping capability can be doubled, the device power density is significantly increased, and the device cost is effectively reduced.
Claims
1. A semiconductor chopper device, comprising a device heat dissipation substrate (7), wherein a first copper-clad ceramic substrate (61) and a second copper-clad ceramic substrate (62) are disposed on the device heat dissipation substrate (7), wherein: The semiconductor chopper device further includes an upper bridge circuit and a lower bridge circuit; wherein, the upper bridge circuit includes one or more fast recovery diode chips (FRD chips) connected in parallel, and the one or more FRD chips are arranged in parallel on the second copper-clad ceramic substrate (62) or the first copper-clad ceramic substrate (61), or simultaneously on the first copper-clad ceramic substrate (61) and the second copper-clad ceramic substrate (62); the lower bridge circuit includes multiple insulated gate bipolar transistor (IGBT) chips connected in parallel, some of the IGBT chips are arranged on the first copper-clad ceramic substrate (61), and the other part of the IGBT chips are arranged on the second copper-clad ceramic substrate (62).
2. The semiconductor chopper device according to claim 1, wherein: The lower bridge circuit includes a first IGBT chip (81), a second IGBT chip (82), a third IGBT chip (83), a fourth IGBT chip (84), a fifth IGBT chip (85), a sixth IGBT chip (86), a first FRD chip (91), a second FRD chip (92), and a third FRD chip (93); The collectors of the first IGBT chip (81), the second IGBT chip (82), and the third IGBT chip (83) are soldered to the cathodes of the first FRD chip (91), the second FRD chip (92), and the third FRD chip (93) on the first copper-clad ceramic substrate (61). The collectors of the fourth IGBT chip (84), the fifth IGBT chip (85), and the sixth IGBT chip (86) are soldered onto the second copper-clad ceramic substrate (62).
3. The semiconductor chopper device according to claim 2, wherein: A first bonding wire cluster (10) is connected between the first copper-clad ceramic substrate (61) and the second copper-clad ceramic substrate (62). The collectors of the first IGBT chip (81), the second IGBT chip (82), and the third IGBT chip (83) are connected in parallel with the collectors of the fourth IGBT chip (84), the fifth IGBT chip (85), and the sixth IGBT chip (86) through the first bonding wire cluster (10).
4. The semiconductor chopper device according to claim 2, wherein: The emitter of the first IGBT chip (81) is connected to the anode of the first FRD chip (91) through a second bonding wire cluster (111); The emitter of the second IGBT chip (82) is connected to the anode of the second FRD chip (92) through a third bonding wire cluster (112); The emitter of the third IGBT chip (83) and the anode of the third FRD chip (93) are connected by a fourth bonding wire cluster (113).
5. The semiconductor chopper device according to claim 2, wherein: The emitter of the fourth IGBT chip (84) is connected in parallel with the emitters of the first IGBT chip (81), the second IGBT chip (82), and the third IGBT chip (83) through the fifth bonding wire cluster (114) and the eighth bonding wire cluster (12); The emitter of the fifth IGBT chip (85) is connected in parallel with the emitters of the first IGBT chip (81), the second IGBT chip (82), and the third IGBT chip (83) through the sixth bonding wire cluster (115) and the eighth bonding wire cluster (12); The emitter of the sixth IGBT chip (86) is connected in parallel with the emitters of the first IGBT chip (81), the second IGBT chip (82), and the third IGBT chip (83) through the seventh bonding wire cluster (116) and the eighth bonding wire cluster (12); The eighth bonding wire cluster (12) is connected between the first copper-clad ceramic substrate (61) and the second copper-clad ceramic substrate (62), and the second copper-clad ceramic substrate (62) is electrically connected to the negative terminal (2).
6. The semiconductor chopper device according to claim 2, wherein: The gates of the first IGBT chip (81), the second IGBT chip (82), the third IGBT chip (83), the fourth IGBT chip (84), the fifth IGBT chip (85), and the sixth IGBT chip (86) are connected to an external drive control circuit through signal terminals (4); The emitters of the first IGBT chip (81), the second IGBT chip (82), the third IGBT chip (83), the fourth IGBT chip (84), the fifth IGBT chip (85), and the sixth IGBT chip (86) are connected to the external drive control circuit through the return line terminal (5).
7. The semiconductor chopper device according to claim 1, wherein: The bridge circuit includes multiple FRD chips connected in parallel, wherein the cathodes of the fourth FRD chip (131) and the fifth FRD chip (132) are soldered on the second copper-clad ceramic substrate (62) and electrically connected to the positive terminal (1).
8. The semiconductor chopper device according to claim 7, wherein: The anode of the fourth FRD chip (131) is connected between the collector of multiple parallel IGBT chips and the cathode of the FRD chip of the lower bridge circuit through the first chip bonding wire cluster (141) and the first bonding wire cluster (10). The anode of the fifth FRD chip (132) is connected between the collector of a plurality of parallel IGBT chips and the cathode of the FRD chip of the lower bridge circuit through the second chip bonding wire cluster (142) and the first bonding wire cluster (10).
9. The semiconductor chopper device according to claim 1, wherein: The lower bridge circuit includes a first IGBT chip (81), a second IGBT chip (82), a third IGBT chip (83), a fourth IGBT chip (84), a first FRD chip (91), a second FRD chip (92), and a third FRD chip (93); The collectors of the first IGBT chip (81) and the second IGBT chip (82) are soldered to the cathodes of the first FRD chip (91) and the second FRD chip (92) on the first copper-clad ceramic substrate (61). The collectors of the third IGBT chip (83) and the fourth IGBT chip (84) are soldered to the cathode of the third FRD chip (93) on the second copper-clad ceramic substrate (62); The emitter of the first IGBT chip (81) is connected to the anode of the first FRD chip (91) through the second bonding wire cluster (111) and the third bonding wire cluster (112); The emitter of the second IGBT chip (82) is connected to the anode of the second FRD chip (92) via a fourth bonding wire cluster (113); The emitter of the third IGBT chip (83) is connected to the anode of the third FRD chip (93) through the fifth bonding wire cluster (114) and the seventh bonding wire cluster (116); The emitter of the fourth IGBT chip (84) is connected to the anode of the third FRD chip (93) via the sixth bonding wire cluster (115) and the seventh bonding wire cluster (116).
10. The semiconductor chopper device according to claim 9, wherein: The lower bridge circuit includes a fourth FRD chip (131), a fifth FRD chip (132), a sixth FRD chip (133), and a seventh FRD chip (134); wherein the fourth FRD chip (131) and the fifth FRD chip (132) are configured according to the current requirements of the FRD chip. The cathodes of the fourth FRD chip (131) and the fifth FRD chip (132) are soldered onto the second copper-clad ceramic substrate (62) and electrically connected to the positive terminal (1); The cathodes of the sixth FRD chip (133) and the seventh FRD chip (134) are soldered onto the first copper-clad ceramic substrate (61); The cathodes of the fourth FRD chip (131) and the fifth FRD chip (132) are connected in parallel with the cathodes of the sixth FRD chip (133) and the seventh FRD chip (134) through the ninth bonding wire cluster (14).