Signal generation circuit, signal generation method, electronic device and storage medium

Abstract

Provided in the embodiments of the present disclosure are a signal generation circuit, a signal generation method, an electronic device and a storage medium. The signal generation circuit comprises a clock module, a control module and a frequency division module; the clock module is configured to generate a first clock signal on the basis of an input reference clock signal, wherein the first clock signal is at least used for generating a working clock signal of the control module; the control module is configured to send to the frequency division module a first frequency division reset signal, and trigger start of a timer in the control module associated with the first frequency division reset signal, the timer performing timing on the basis of the working clock signal; the frequency division module is configured to perform frequency division on an input clock signal on the basis of the first frequency division reset signal, so as to output a frequency-divided signal, the input clock signal being generated on the basis of the first clock signal, and the first frequency division reset signal being configured to control the starting time of outputting the frequency-divided signal by the frequency division module to be separated from the start time of the timer by a first predetermined duration.

Description

Signal generation circuits, signal generation methods, electronic devices, and storage media

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on January 23, 2025, with application number 202510112160.3, entitled “Signal generation circuit, signal generation method, electronic device and storage medium”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of signal measurement technology, and in particular to a signal generation circuit, a signal generation method, an electronic device, and a storage medium. Background Technology

[0004] In some applications, devices typically require time delay calibration and multi-channel synchronization calibration every time they are powered on. After power-on, the device usually undergoes a series of calibrations to ensure that the timing relationships between different channels and modules meet the device's performance requirements. For example, signal source devices require a fixed time delay from trigger to output after each power-on, with a time delay variation deviation of less than 10 ps. Calibration signals are commonly used for calibration between channels and / or modules. Generating calibration signals with a fixed phase relationship to the control module's operating clock and improving calibration accuracy is a pressing issue that needs to be addressed. Summary of the Invention

[0005] In view of the above, embodiments of this disclosure provide a signal generation circuit, a signal generation method, an electronic device, and a storage medium.

[0006] According to a first aspect of the present disclosure, a signal generation circuit is provided, the signal generation circuit comprising: a clock module, a control module, and a frequency divider module, wherein,

[0007] The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module.

[0008] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0009] The frequency divider module is configured to divide the input clock signal based on a first frequency divider reset signal to output a frequency divider signal, wherein the input clock signal is generated based on the first clock signal; the first frequency divider reset signal is used to control the interval between the start time of the frequency divider module outputting the frequency divider signal and the start time of the timer for a first predetermined time.

[0010] In some embodiments, the signal generation circuit further includes a low-pass filter configured to perform low-pass filtering on the frequency division signal to obtain a calibration signal, wherein the start time of the calibration signal is spaced apart from the start time of the timer by a second predetermined duration.

[0011] In some embodiments, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider;

[0012] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0013] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0014] The signal delay submodule is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0015] The first frequency divider is configured to be triggered by the second frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0016] In some embodiments, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0017] The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal;

[0018] The second synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0019] The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0020] The second frequency divider is configured to be triggered by the first frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0021] In some embodiments, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal;

[0022] The third synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0023] The startup time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal;

[0024] The counting divider is configured to be triggered by the first frequency division reset signal at a predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

[0025] According to a second aspect of the present disclosure, a signal generation method is provided, applied to a signal generation circuit, the signal generation circuit comprising: a clock module, a control module, and a frequency division module, wherein the method comprises:

[0026] The clock module generates a first clock signal based on the input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module;

[0027] The control module sends a first frequency division reset signal to the frequency division module and triggers the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0028] The frequency divider module divides the input clock signal based on the first frequency divider reset signal to output a frequency divider signal, wherein the input clock signal is generated based on the first clock signal; the first frequency divider reset signal is used to control the interval between the start time of the frequency divider module outputting the frequency divider signal and the start time of the timer for a first predetermined time.

[0029] In some embodiments, the signal generation circuit further includes: a low-pass filter;

[0030] The method further includes: performing low-pass filtering on the frequency division signal through the low-pass filter to obtain a calibration signal, wherein the start time of the calibration signal is spaced apart from the start time of the timer by a second predetermined time interval.

[0031] In some embodiments, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider; the method further includes:

[0032] The working clock signal and the input clock signal are generated based on the first clock signal using the first clock buffer;

[0033] The first frequency division reset signal is sent to the frequency division module through the first synchronous reset control module;

[0034] The first frequency-divided reset signal is delayed by a predetermined time by the signal delay submodule to obtain a second frequency-divided reset signal, so that the second frequency-divided reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0035] The first frequency divider is triggered by the second frequency divider reset signal at the predetermined trigger edge, and the frequency divider signal is generated based on the input clock signal.

[0036] In some embodiments, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0037] The method further includes:

[0038] The second clock buffer generates a second clock signal and the input clock signal based on the first clock signal;

[0039] The second synchronous reset control module generates a first frequency-divided reset signal based on the working clock signal;

[0040] The phase of the second clock signal is adjusted by the phase adjustment module to obtain the working clock signal, so that the first frequency division reset signal triggered by the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0041] The second frequency divider is triggered by the first frequency divider reset signal at the predetermined trigger edge, and the frequency divider signal is generated based on the input clock signal.

[0042] In some embodiments, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal;

[0043] The method further includes:

[0044] The third synchronous reset control module generates a first frequency-divided reset signal based on the working clock signal; the start time includes a predetermined edge of the working clock signal after the generation time of the first frequency-divided reset signal.

[0045] The counting divider is triggered by the first frequency division reset signal at a predetermined edge, counts the working clock signal from the predetermined edge, and generates the frequency division signal based on the counting result.

[0046] According to a third aspect of the present disclosure, an electronic device is provided, including a signal generation circuit as described in the first aspect.

[0047] According to a fourth aspect of the present disclosure, an electronic device is provided, including a processor, a memory, and an executable program stored in the memory and executable by the processor, wherein the processor executes the steps of the signal generation method as described in the second aspect when running the executable program.

[0048] According to a fifth aspect of the present disclosure, a storage medium is provided that stores an executable program thereon, which, when executed by a processor, implements the steps of the signal generation method as described in the second aspect.

[0049] This disclosure provides a signal generation circuit, a signal generation method, an electronic device, and a storage medium. The signal generation circuit includes a clock module, a control module, and a frequency divider module. The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate a working clock signal for the control module. The control module is configured to send a first frequency divider reset signal to the frequency divider module and trigger the start of a timer associated with the first frequency divider reset signal in the control module, wherein the timer counts based on the working clock signal. The frequency divider module is configured to divide the input clock signal based on the first frequency divider reset signal to output a divided frequency signal, wherein the input clock signal is generated based on the first clock signal. The first frequency divider reset signal is used to control the start time of the frequency divider module outputting the divided frequency signal to be spaced apart from the start time of the timer by a first predetermined duration. Thus, by adjusting the start time of the frequency division signal based on the first frequency division reset signal, and determining the correspondence between the first frequency division reset signal and the start time of the timer, the control of the time interval between the start time of the frequency division signal and the start time of the timer is determined, so that the frequency division signal can be used for time delay calibration comparison, thereby realizing the calibration of the signal to be calibrated. Attached Figure Description

[0050] Figure 1 is a schematic diagram of a signal generation device according to an exemplary embodiment;

[0051] Figure 2 is a schematic diagram of a signal generation timing according to an exemplary embodiment;

[0052] Figure 3 is a schematic diagram of another signal generation device according to an exemplary embodiment;

[0053] Figure 4 is a schematic diagram of another signal generation timing according to an exemplary embodiment;

[0054] Figure 5 is a schematic flowchart of a signal generation method according to an exemplary embodiment;

[0055] Figure 6 is a schematic diagram of the structure of another signal generation device according to an exemplary embodiment;

[0056] Figure 7 is a schematic diagram of another signal generation timing according to an exemplary embodiment;

[0057] Figure 8 is a schematic flowchart of another signal generation method according to an exemplary embodiment;

[0058] Figure 9 is a schematic diagram of the structure of another signal generation device according to an exemplary embodiment;

[0059] Figure 10 is a schematic diagram of another signal generation timing according to an exemplary embodiment;

[0060] Figure 11 is a schematic flowchart of another signal generation method according to an exemplary embodiment;

[0061] Figure 12 is a schematic flowchart of another signal generation method according to an exemplary embodiment. Detailed Implementation

[0062] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0063] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0064] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0065] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0066] In this embodiment of the disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0067] In the embodiments of this disclosure, "multiple" refers to two or more.

[0068] In some embodiments, the terms “at least one of”, “one or more”, “aplurality of”, “multiple”, etc., may be used interchangeably.

[0069] In some embodiments, the notation "at least one of A and B", "A and / or B", "A in one case, B in another", "A in one case, B in another", etc., may include the following technical solutions depending on the situation: in some embodiments, A (A is executed regardless of B); in some embodiments, B (B is executed regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, A and B (both A and B are executed). The same applies when there are more branches such as A, B, C, etc.

[0070] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execution of A regardless of B); in some embodiments, B (execution of B regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, C, etc.

[0071] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects should be found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the value of the descriptive object is not limited by ordinal numbers and can be one or more. For example, in "first device," the value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0072] In some embodiments, “including A,” “containing A,” “for indicating A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0073] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably.

[0074] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0075] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0076] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0077] Figure 1 illustrates a signal generation circuit according to an embodiment of the present disclosure. The signal generation circuit includes a clock module, a control module, and a frequency divider module.

[0078] The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module.

[0079] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0080] The frequency divider module is configured to divide the input clock signal based on a first frequency divider reset signal to output a frequency divider signal, wherein the input clock signal is generated based on the first clock signal; the first frequency divider reset signal is used to control the interval between the start time of the frequency divider module outputting the frequency divider signal and the start time of the timer for a first predetermined time.

[0081] In one possible implementation, the signal generation circuit can be implemented by an integrated circuit, or by a combination of at least one integrated circuit and at least one discrete component.

[0082] Here, the signal generation circuit can be applied to signal source electronic devices such as Arbitrary Waveform Generator (AWG) signal sources, Arbitrary Function Generator (AFG) signal sources, i.e., signal sources, radio frequency signal sources, vector signal sources, etc., and can also be applied to electronic devices such as oscilloscopes and spectrum analyzers. The signal generation circuit can exist as an independent functional module, such as an independent functional module in the PXIe architecture; it can also be combined with other functional circuits to achieve composite functions. For example, the signal generation circuit and the Analog-to-Digital Converter (ADC) circuit can reside on the same board to provide specific signals to the ADC circuit.

[0083] Here, the reference clock signal can be a clock signal generated by a reference clock signal source. For example, the reference clock signal can be a crystal oscillator clock signal, or it can be a clock signal sent by the motherboard to each functional module board in the PXIe architecture.

[0084] The control module can be implemented using components with signal processing and / or data computation capabilities, such as a Field Programmable Gate Array (FPGA). Alternatively, it can be implemented using a Microprocessor (MCU).

[0085] The clock module is configured to buffer and divide the reference clock at least once to generate a clock signal at the frequency required for the operation of each module.

[0086] In one possible implementation, the first clock signal is used to generate at least one of the operating clock signal and the input clock signal. For example, the first clock signal can generate the operating clock signal and the input clock signal by fan-out or other methods.

[0087] Here, the control module can control the frequency divider module to reset and / or perform frequency division operation via a reset signal. For example, the control module can control the frequency divider module to enter the reset state and perform frequency division operation through two levels of the reset signal, respectively. The first frequency divider reset signal can be the level that triggers the frequency divider module to divide the input clock signal. As shown in Figure 2, the first frequency divider reset signal is the low-level state of the reset signal in Figure 2.

[0088] In one possible implementation, the frequency divider module is in a reset state before dividing the input clock signal.

[0089] In one possible implementation, the first frequency divider reset signal is triggered based on the edge of the operating level.

[0090] In one possible implementation, the control module triggering the start of a timer associated with the first frequency divider reset signal may include: the control module triggering the timer at a predetermined edge (rising edge or falling edge) of the operating clock signal after the first frequency divider reset signal is generated.

[0091] In one possible implementation, the predetermined edge is the first rising edge after the start time of the first frequency division reset signal (as indicated by arrow A in Figure 2).

[0092] In one possible implementation, the timer's start time (as indicated by arrow B in Figure 2) is the edge time of a predetermined edge of the working clock signal.

[0093] Since the timer operates based on the operating clock signal, its timing is synchronized with the operating clock signal. For example, the timer counts once for each period of the operating clock signal.

[0094] Both the operating clock signal and the input clock signal are generated from the first clock signal, therefore they are correlated. In one possible implementation, the operating clock signal and the input clock signal have a fixed phase difference.

[0095] In one possible implementation, the start time of the frequency divider module's output frequency divider signal can be adjusted by changing the time-domain position of the first frequency divider reset signal's start time. For example, the frequency divider module can be triggered to output the frequency divider signal at the edge of the input clock signal by the first frequency divider reset signal. Therefore, the start time of the frequency divider module's output frequency divider signal triggered by the first frequency divider reset signal can be determined based on the time-domain position of the first frequency divider reset signal's start time and the time-domain position of the input clock signal's edge. Since the operating clock signal and the input clock signal have a fixed phase difference, the time interval between the start time of the frequency divider signal triggered by the input clock signal and the timer's start time is fixed, which means the time interval between the start time of the frequency divider signal and the timer's start time can be determined, i.e., the first predetermined duration (as shown by T1 in Figure 2).

[0096] Since the time interval between the start time of the frequency divider signal and the start time of the timer, i.e. the first predetermined duration, is known, that is, the phase difference between the start time of the frequency divider signal and the working clock is known (e.g., the phase difference between the start time of the frequency divider signal and the predetermined edge of the working clock is known), the frequency divider signal can be used for time delay comparison. For example, by comparing the signal to be calibrated with the frequency divider signal, the time interval between the signal to be calibrated and the start time of the timer can be determined, and thus the time delay of the signal to be calibrated relative to the start time of the timer can be determined.

[0097] In one possible implementation, the frequency divider module can be configured to divide the input clock signal by N to output a divided signal. Here, N is a positive integer greater than or equal to 1.

[0098] Thus, by adjusting the start time of the frequency division signal based on the first frequency division reset signal, and determining the correspondence between the first frequency division reset signal and the start time of the timer, the control of the time interval between the start time of the frequency division signal and the start time of the timer is determined, so that the frequency division signal can be used for time delay calibration comparison, thereby realizing the calibration of the signal to be calibrated.

[0099] In some embodiments, as shown in FIG1, the signal generation circuit further includes: a low-pass filter configured to perform low-pass filtering on the frequency division signal to obtain a calibration signal, wherein the start time of the calibration signal is spaced apart from the start time of the timer by a second predetermined duration.

[0100] As shown in Figure 2, the frequency-divided signal obtained after passing through the frequency divider module is approximately a square wave and contains high-frequency harmonic components. These can be filtered using a low-pass filter to obtain a smooth calibration signal, thereby improving the accuracy of phase calculation. The low-pass filter can be set based on the frequency of the frequency-divided signal, filtering out harmonic components with frequencies higher than the frequency of the frequency-divided signal.

[0101] As shown in Figure 2, there is a filtering delay when the low-pass filter performs filtering (as shown by T2 in Figure 2). Therefore, the second predetermined duration (as shown by T in Figure 2) between the calibration signal obtained after filtering and the start time of the timer is the sum of the first predetermined duration and the filtering delay.

[0102] Therefore, when comparing the calibration signal with the signal to be calibrated, the phase difference between the signal to be calibrated and the start time of the timer can be determined based on the phase difference T3 between the signal to be calibrated and the calibration signal and the second predetermined duration.

[0103] In some embodiments, as shown in FIG3, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider;

[0104] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0105] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0106] The signal delay submodule is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0107] The first frequency divider is configured to be triggered by the second frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0108] The first clock buffer is configured to generate two clock signals—a working clock signal and an input clock signal—from a single first clock signal through frequency replication or other methods. The phase of the working clock signal input to the control module can be determined based on the transmission path of the working clock signal through the control module, and the phase of the input clock signal input to the first frequency divider can be determined based on the transmission path of the input clock signal through the first frequency divider. In other words, since the circuit for converting the first clock signal into the working clock signal and the input clock signal is fixed, the phase difference between the input clock signal and the working clock signal is known.

[0109] Here, the first synchronous reset control module in the control module can send the first frequency division reset signal to the frequency division module. The timer in the control module can start timing after the first frequency division reset signal.

[0110] Figure 4 is a timing diagram of the signal generation circuit shown in Figure 3. The timer can be triggered to start at a predetermined edge of the operating clock signal after the first frequency divider reset signal. As shown in Figure 4, the predetermined edge after the first frequency divider reset signal may include the first rising edge after the first frequency divider reset signal.

[0111] In one possible implementation, the predetermined trigger edge of the input clock signal (shown as C in Figure 4) may include the Mth trigger edge (e.g., a rising edge) after the timer's start time. M is a positive integer greater than or equal to 1. As shown in Figure 4, the predetermined trigger edge may be the first rising edge after the timer's start time. Since the phase difference between the input clock signal and the operating clock signal is known, the time interval between the predetermined trigger edge and the timer's start time can be determined.

[0112] In one possible implementation, the predetermined delay duration can be determined based on the time interval between the start time of the first frequency-divided reset signal and the predetermined trigger edge. The predetermined delay duration can be determined based on at least one of the following: the establishment time of the second frequency-divided reset signal after the delay is satisfied (as shown in t in Figure 4); the second frequency-divided reset signal does not trigger the edge of the input clock signal before the predetermined trigger edge.

[0113] In one possible implementation, the predetermined delay duration can be pre-written into the signal delay submodule. In an FPGA, the signal delay submodule can be implemented using input / output delay (IOdelay) circuitry.

[0114] The second frequency divider reset signal enables the first frequency divider to perform frequency division and output a divided frequency signal when triggered at a predetermined trigger edge. In Figure 4, the time interval T1 between the start time of the divided frequency signal and the start time of the timer may include the response time of the first frequency divider.

[0115] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response time of the first frequency divider can be determined based on the first frequency divider. Therefore, the first predetermined time interval between the start time of the frequency division signal and the start time of the timer is fixed.

[0116] The calibration signal is obtained by filtering the frequency-divided signal. The filtering delay is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the second predetermined time interval T between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phase of the calibration signal and the signal to be calibrated, thereby achieving the calibration of the signal to be calibrated.

[0117] In practical applications, the start time of the timer, the start time of the frequency divider signal, and the time when the first frequency divider is triggered at a predetermined trigger edge are all related to the release time of the second frequency divider reset signal. That is, the falling edge of the second reset signal needs to be sampled by both the working clock signal and the input clock signal, requiring sufficient setup and hold time between the falling edge of the second reset signal and its sampling time. Since the timer's start time is triggered by the edge of the working clock signal, and the start time of the frequency divider signal and the first frequency divider are triggered by the input clock signal, and the working clock signal and the input clock signal have a fixed phase relationship, the deviations between the timer's start time, the start time of the frequency divider signal, and the time when the first frequency divider is triggered at the predetermined trigger edge are fixed, thus enabling high-precision calibration.

[0118] For example, as shown in Figure 5, the specific steps of the calibration signal generation method include:

[0119] Step 501: Power on and initialize each module in the signal generation process.

[0120] Step 502: Configure the clock module to generate the input clock signal of the first frequency divider and the working clock signal of the FPGA (control module).

[0121] Step 503: Synchronize the first synchronous reset control module to control the first frequency divider to be in the reset state and the timer to be in the reset state.

[0122] Step 504: Configure the delay value (predetermined delay duration) of the signal delay submodule. The delay value can be a factory calibration value used to control the setup / hold time of the second frequency divider reset signal and the input clock signal.

[0123] Step 505: The control module determines whether a calibration signal needs to be generated. If yes, proceed to step 506; otherwise, proceed to step 505.

[0124] Step 506: Issue the second frequency divider reset signal to release the first frequency divider.

[0125] Step 507: Start the FPGA's internal timer (to count the start reference time of the calibration signal).

[0126] Step 508: The frequency-divided signal passes through a low-pass filter.

[0127] Step 509: The output signal of the low-pass filter is the calibration signal.

[0128] In the above steps, the signal delay submodule uses the delay value obtained during factory calibration. This delay value is used to control the second frequency divider reset signal output by the FPGA to have sufficient setup / hold timing with the input clock signal, ensuring that the frequency divider signal output by the first frequency divider and the start time of the FPGA's internal timer have a fixed delay relationship each time power is powered on. This guarantees that the calibration signal output by the low-pass filter has a fixed delay relationship with the start time of the FPGA's internal timer.

[0129] In some embodiments, as shown in FIG6, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0130] The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal;

[0131] The second synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0132] The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0133] The second frequency divider is configured to be triggered by the first frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0134] The first clock buffer is configured to generate two clock signals: a second clock signal and an input clock signal, from a first clock signal through frequency replication or other means.

[0135] Here, the first frequency divider reset signal and the timer have a corresponding relationship. The corresponding relationship between the first frequency divider reset signal and the timer includes the following: the start time of the first frequency divider reset signal and the start time of the timer have a predetermined interval; the first frequency divider reset signal and the timer are triggered based on a predetermined edge of the same working clock signal.

[0136] The phase adjustment module can be configured to adjust the phase of the second clock signal to obtain the working clock signal. The phase adjustment module can be implemented by at least one of the following to adjust the phase of the clock signal: phase-locked loop (PLL), delay-locked loop (DLL), or digital clock manager (DCM).

[0137] In one possible implementation, the phase adjustment module can be configured to adjust the phase of the second clock signal by a pre-set amount.

[0138] The phase of the second clock signal can be determined based on the transmission path of the control module transmitting the second clock signal, and the phase of the input clock signal can be determined based on the path of the input clock signal transmitted to the first frequency divider. That is, the phase difference between the second clock signal and the input clock signal is known. Therefore, the phase difference between the operating clock signal and the input clock signal can be determined based on the phase adjustment amount of the phase adjustment module.

[0139] Figure 7 is a timing diagram of the signal generation circuit shown in Figure 6. The predetermined trigger edge (shown as C in Figure 7) can include the Mth trigger edge (e.g., a rising edge) after the timer's start time. M is a positive integer greater than or equal to 1. As shown in Figure 7, the predetermined trigger edge can be the first rising edge after the timer's start time. Since the phase difference between the input clock signal and the operating clock signal is known, the time interval between the predetermined trigger edge and the timer's start time can be determined.

[0140] Here, the phase adjustment amount can be determined based on at least one of the following: the first frequency divider reset signal satisfies the setup time of the predetermined trigger edge (as shown by t in Figure 7); the second frequency divider reset signal does not trigger the edge of the input clock signal before the predetermined trigger edge.

[0141] Thus, the second frequency divider can be triggered at a predetermined trigger edge to perform frequency division and output a divided frequency signal. In Figure 7, the time interval T1 between the divided frequency signal and the start time of the timer may include the response time of the first frequency divider.

[0142] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response time of the second frequency divider can be determined based on the second frequency divider. Therefore, the first predetermined time interval T1 between the start time of the frequency division signal and the start time of the timer is fixed.

[0143] The calibration signal is obtained by filtering the frequency-divided signal. The filtering delay is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the second predetermined time interval T between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phase of the calibration signal and the signal to be calibrated, thereby achieving the calibration of the signal to be calibrated.

[0144] In practical applications, the start time of the timer is determined by the edge of the working clock signal (such as the rising edge), and the start time of the frequency divider signal is determined by the edge of the input clock signal (such as the rising edge). The working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviation between the start time of the timer and the start time of the frequency divider signal is fixed, thereby enabling high-precision calibration.

[0145] For example, as shown in Figure 8, the specific steps of the calibration signal generation method include:

[0146] Step 801: Power on and initialize each module in the signal generation process.

[0147] Step 802: Configure the clock module to generate the input clock signal and the second clock signal for the frequency divider.

[0148] Step 803: Synchronous reset control module, controls the second frequency divider to be in reset state, and the timer to be in reset state.

[0149] Step 804: Configure the parameters of the phase adjustment module in the FPGA (control module) to adjust the phase of the second clock signal. The phase adjustment amount can be a factory calibration value, used to control the setup / hold time of the first divider reset signal and the second divider input clock.

[0150] Step 805: The control module determines whether a calibration signal needs to be generated. If yes, proceed to step 806; otherwise, proceed to step 805.

[0151] Step 806: Issue the first frequency divider reset signal to release the second frequency divider.

[0152] Step 807: Start the FPGA's internal timer. This count serves as the reference time for the start of the calibration signal.

[0153] Step 808: The frequency-divided signal passes through a low-pass filter.

[0154] Step 809: The output signal of the low-pass filter is the calibration signal.

[0155] In the above steps, the phase adjustment module (such as PLL, DLL, DCM, etc.) of the FPGA's internal clock unit is used to adjust the phase of the FPGA's operating clock signal, thereby ensuring sufficient setup / hold timing for the first frequency divider reset signal and the input clock of the second frequency divider. This ensures that the output signal of the second frequency divider and the start time of the FPGA's internal timer have a fixed time delay relationship each time power is applied.

[0156] In some embodiments, as shown in FIG9, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal;

[0157] The third synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0158] The startup time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal;

[0159] The counting divider is configured to be triggered by the first frequency division reset signal at a predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

[0160] Here, the clock module outputs a first clock signal based on a reference clock signal, which serves as the operating clock signal for the control module. Inside the control module, the operating clock signal is transmitted to a counter divider as an input clock signal.

[0161] In one possible implementation, the counter divider is configured to count the input clock signal and reverse the level when the count value reaches a counting threshold, thereby generating a periodic divided signal.

[0162] For example, if the required frequency division signal is an N-division signal of the working clock signal, then the counting threshold can be set to N / 2. When the frequency divider counts the working clock signal, the level is reversed when the count value reaches N / 2, thus generating the N-division signal.

[0163] Figure 10 is a timing diagram of the signal generation circuit shown in Figure 9. As shown in Figure 10, the first frequency divider reset signal and the timer have a corresponding relationship. The timer starts at a predetermined edge of the working clock signal after the generation of the first frequency divider reset signal.

[0164] In one possible implementation, the predetermined edge may include the first edge (rising edge or falling edge) of the operating clock signal after the generation time of the first frequency divider reset signal.

[0165] The counting divider counts based on the triggering of the first frequency division reset signal, thereby outputting the frequency division signal.

[0166] Here, the frequency divider is triggered at the start time of the timer; therefore, the time interval between the start time of the divided signal and the start time of the timer is fixed. For example, the start time of the divided signal is the same as the start time of the timer. The filtering delay of the low-pass filter is fixed; therefore, the interval T between the start time of the calibration signal generated by the divided signal and the start time of the timer is a fixed value.

[0167] For example, as shown in Figure 11, the specific steps of the calibration signal generation method include:

[0168] Step 1101: Power on and initialize each module in the signal generation process.

[0169] Step 1102: The third synchronous reset control module controls the counter divider to be in the reset state and the timer to be in the reset state.

[0170] Step 1103: The control module determines whether a calibration signal needs to be generated. If yes, proceed to step 1104; otherwise, proceed to step 1103.

[0171] Step 1104: Issue the first frequency divider reset signal to release the frequency divider.

[0172] Step 1105: Start the FPGA (control module) internal timer to count the start reference time of the calibration signal.

[0173] Step 1106: The frequency-divided signal passes through a low-pass filter.

[0174] Step 1107: The output signal of the low-pass filter is the calibration signal.

[0175] In the above steps, this scheme does not use an external frequency divider, nor does it require adjusting the phase of the third synchronous reset control module and the input clock signal of the external frequency divider. This scheme directly starts the internal frequency divider counter based on the FPGA working clock signal, realizes the N-fold frequency division signal, and obtains the calibration signal by passing the signal output through a low-pass filter, which is simple and easy to implement.

[0176] Figure 12 illustrates a signal generation method according to an embodiment of the present disclosure. The signal generation circuit, as shown in Figure 1, includes a clock module, a control module, and a frequency divider module.

[0177] The method includes:

[0178] Step 1201: The clock module generates a first clock signal based on the input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module;

[0179] Step 1202: The control module sends a first frequency division reset signal to the frequency division module and triggers the start of the timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0180] Step 1203: The frequency divider module divides the input clock signal based on the first frequency divider reset signal to output a frequency divider signal, wherein the input clock signal is generated based on the first clock signal; the first frequency divider reset signal is used to control the interval between the start time of the frequency divider module outputting the frequency divider signal and the start time of the timer for a first predetermined time.

[0181] In one possible implementation, the signal generation circuit can be implemented by an integrated circuit, or by a combination of at least one integrated circuit and at least one discrete component.

[0182] Here, the signal generation circuit can be applied to signal source electronic devices such as Arbitrary Waveform Generator (AWG) signal sources, Arbitrary Function Generator (AFG) signal sources, i.e., signal sources, radio frequency signal sources, vector signal sources, etc., and can also be applied to electronic devices such as oscilloscopes and spectrum analyzers. The signal generation circuit can exist as an independent functional module, such as an independent functional module in the PXIe architecture; it can also be combined with other functional circuits to achieve composite functions. For example, the signal generation circuit and the Analog-to-Digital Converter (ADC) circuit can reside on the same board to provide specific signals to the ADC circuit.

[0183] In one possible implementation, the signal generation method can be executed by a controller or similar device in an electronic device.

[0184] Here, the reference clock signal can be a clock signal generated by a reference clock signal source. For example, the reference clock signal can be a crystal oscillator clock signal, or it can be a clock signal sent by the motherboard to each functional module board in the PXIe architecture.

[0185] The control module can be implemented using components with signal processing and / or data computation capabilities, such as a Field Programmable Gate Array (FPGA). Alternatively, it can be implemented using a Microprocessor (MCU).

[0186] The clock module is configured to buffer and divide the reference clock at least once to generate a clock signal at the frequency required for the operation of each module.

[0187] In one possible implementation, the first clock signal is used to generate at least one of the operating clock signal and the input clock signal. For example, the first clock signal can generate the operating clock signal and the input clock signal by fan-out or other methods.

[0188] Here, the control module can control the frequency divider module to reset and / or perform frequency division operation via a reset signal. For example, the control module can control the frequency divider module to enter the reset state and perform frequency division operation through two levels of the reset signal, respectively. The first frequency divider reset signal can be the level that triggers the frequency divider module to divide the input clock signal. As shown in Figure 2, the first frequency divider reset signal is the low-level state of the reset signal in Figure 2.

[0189] In one possible implementation, the frequency divider module is in a reset state before dividing the input clock signal.

[0190] In one possible implementation, the first frequency divider reset signal is triggered based on the edge of the operating level.

[0191] In one possible implementation, the control module triggering the start of a timer associated with the first frequency divider reset signal may include: the control module triggering the timer at a predetermined edge (rising edge or falling edge) of the operating clock signal after the first frequency divider reset signal is generated.

[0192] In one possible implementation, the predetermined edge is the first rising edge after the start time of the first frequency division reset signal (as indicated by arrow A in Figure 2).

[0193] In one possible implementation, the timer's start time (as indicated by arrow B in Figure 2) is the edge time of a predetermined edge of the working clock signal.

[0194] Since the timer operates based on the operating clock signal, its timing is synchronized with the operating clock signal. For example, the timer counts once for each period of the operating clock signal.

[0195] Both the operating clock signal and the input clock signal are generated from the first clock signal, therefore they are correlated. In one possible implementation, the operating clock signal and the input clock signal have a fixed phase difference.

[0196] In one possible implementation, the start time of the frequency divider module's output frequency divider signal can be adjusted by changing the time-domain position of the first frequency divider reset signal's start time. For example, the frequency divider module can be triggered to output the frequency divider signal at the edge of the input clock signal by the first frequency divider reset signal. Therefore, the start time of the frequency divider module's output frequency divider signal triggered by the first frequency divider reset signal can be determined based on the time-domain position of the first frequency divider reset signal's start time and the time-domain position of the input clock signal's edge. Since the operating clock signal and the input clock signal have a fixed phase difference, the time interval between the start time of the frequency divider signal triggered by the input clock signal and the timer's start time is fixed, which means the time interval between the start time of the frequency divider signal and the timer's start time can be determined, i.e., the first predetermined duration (as shown by T1 in Figure 2).

[0197] Since the time interval between the start time of the frequency divider signal and the start time of the timer, i.e. the first predetermined duration, is known, that is, the phase difference between the start time of the frequency divider signal and the working clock is known (e.g., the phase difference between the start time of the frequency divider signal and the predetermined edge of the working clock is known), the frequency divider signal can be used for time delay comparison. For example, by comparing the signal to be calibrated with the frequency divider signal, the time interval between the signal to be calibrated and the start time of the timer can be determined, and thus the time delay of the signal to be calibrated relative to the start time of the timer can be determined.

[0198] In one possible implementation, the frequency divider module can be configured to divide the input clock signal by N to output a divided signal. Here, N is a positive integer greater than or equal to 1.

[0199] Thus, by adjusting the start time of the frequency division signal based on the first frequency division reset signal, and determining the correspondence between the first frequency division reset signal and the start time of the timer, the control of the time interval between the start time of the frequency division signal and the start time of the timer is determined, so that the frequency division signal can be used for time delay calibration comparison, thereby realizing the calibration of the signal to be calibrated.

[0200] In some embodiments, as shown in FIG1, the signal generation circuit further includes a low-pass filter;

[0201] The method further includes: performing low-pass filtering on the frequency division signal through the low-pass filter to obtain a calibration signal, wherein the start time of the calibration signal is spaced apart from the start time of the timer by a second predetermined time interval.

[0202] As shown in Figure 2, the frequency-divided signal obtained after passing through the frequency divider module is approximately a square wave and contains high-frequency harmonic components. These can be filtered using a low-pass filter to obtain a smooth calibration signal, thereby improving the accuracy of phase calculation. The low-pass filter can be set based on the frequency of the frequency-divided signal, filtering out harmonic components with frequencies higher than the frequency of the frequency-divided signal.

[0203] As shown in Figure 2, there is a filtering delay when the low-pass filter performs filtering (as shown by T2 in Figure 2). Therefore, the second predetermined duration (as shown by T in Figure 2) between the calibration signal obtained after filtering and the start time of the timer is the sum of the first predetermined duration and the filtering delay.

[0204] Therefore, when comparing the calibration signal with the signal to be calibrated, the phase difference between the signal to be calibrated and the start time of the timer can be determined based on the phase difference T3 between the signal to be calibrated and the calibration signal and the second predetermined duration.

[0205] In some embodiments, as shown in FIG3, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider; the method further includes:

[0206] The working clock signal and the input clock signal are generated based on the first clock signal using the first clock buffer;

[0207] The first frequency division reset signal is sent to the frequency division module through the first synchronous reset control module;

[0208] The first frequency-divided reset signal is delayed by a predetermined time by the signal delay submodule to obtain a second frequency-divided reset signal, so that the second frequency-divided reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0209] The first frequency divider is triggered by the second frequency divider reset signal at the predetermined trigger edge, and the frequency divider signal is generated based on the input clock signal.

[0210] The first clock buffer is configured to generate two clock signals—a working clock signal and an input clock signal—from a single first clock signal through frequency replication or other methods. The phase of the working clock signal input to the control module can be determined based on the transmission path of the working clock signal through the control module, and the phase of the input clock signal input to the first frequency divider can be determined based on the transmission path of the input clock signal through the first frequency divider. In other words, since the circuit for converting the first clock signal into the working clock signal and the input clock signal is fixed, the phase difference between the input clock signal and the working clock signal is known.

[0211] Here, the first synchronous reset control module in the control module can send the first frequency division reset signal to the frequency division module. The timer in the control module can start timing after the first frequency division reset signal.

[0212] Figure 4 is a timing diagram of the signal generation circuit shown in Figure 3. The timer can be triggered to start at a predetermined edge of the operating clock signal after the first frequency divider reset signal. As shown in Figure 4, the predetermined edge after the first frequency divider reset signal may include the first rising edge after the first frequency divider reset signal.

[0213] In one possible implementation, the predetermined trigger edge of the input clock signal (shown as C in Figure 4) may include the Mth trigger edge (e.g., a rising edge) after the timer's start time. M is a positive integer greater than or equal to 1. As shown in Figure 4, the predetermined trigger edge may be the first rising edge after the timer's start time. Since the phase difference between the input clock signal and the operating clock signal is known, the time interval between the predetermined trigger edge and the timer's start time can be determined.

[0214] In one possible implementation, the predetermined delay duration can be determined based on the time interval between the start time of the first frequency-divided reset signal and the predetermined trigger edge. The predetermined delay duration can be determined based on at least one of the following: the establishment time of the second frequency-divided reset signal after the delay is satisfied (as shown in t in Figure 4); the second frequency-divided reset signal does not trigger the edge of the input clock signal before the predetermined trigger edge.

[0215] In one possible implementation, the predetermined delay duration can be pre-written into the signal delay submodule. In an FPGA, the signal delay submodule can be implemented using input / output delay (IOdelay) circuitry.

[0216] The second frequency divider reset signal enables the first frequency divider to be triggered at a predetermined trigger edge to perform frequency division and output a divided frequency signal. In Figure 4, the time interval T1 between the start time of the divided frequency signal and the start time of the timer may include the response time of the first frequency divider.

[0217] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response time of the first frequency divider can be determined based on the first frequency divider. Therefore, the first predetermined time interval between the start time of the frequency division signal and the start time of the timer is fixed.

[0218] The calibration signal is obtained by filtering the frequency-divided signal. The filtering delay is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the second predetermined time interval T between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phase of the calibration signal and the signal to be calibrated, thereby achieving the calibration of the signal to be calibrated.

[0219] In practical applications, the start time of the timer, the start time of the frequency divider signal, and the time when the first frequency divider is triggered at a predetermined trigger edge are all related to the release time of the second frequency divider reset signal. That is, the falling edge of the second reset signal needs to be sampled by both the working clock signal and the input clock signal, requiring sufficient setup and hold time between the falling edge of the second reset signal and its sampling time. Since the timer's start time is triggered by the edge of the working clock signal, and the start time of the frequency divider signal and the first frequency divider are triggered by the input clock signal, and the working clock signal and the input clock signal have a fixed phase relationship, the deviations between the timer's start time, the start time of the frequency divider signal, and the time when the first frequency divider is triggered at the predetermined trigger edge are fixed, thus enabling high-precision calibration.

[0220] In some embodiments, as shown in FIG6, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0221] The method further includes:

[0222] The second clock buffer generates a second clock signal and the input clock signal based on the first clock signal;

[0223] The second synchronous reset control module generates a first frequency-divided reset signal based on the working clock signal;

[0224] The phase of the second clock signal is adjusted by the phase adjustment module to obtain the working clock signal, so that the first frequency division reset signal triggered by the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0225] The second frequency divider is triggered by the first frequency divider reset signal at the predetermined trigger edge, and the frequency divider signal is generated based on the input clock signal.

[0226] The first clock buffer is configured to generate two clock signals: a second clock signal and an input clock signal, from a first clock signal through frequency replication or other means.

[0227] Here, the first frequency divider reset signal and the timer have a corresponding relationship. The corresponding relationship between the first frequency divider reset signal and the timer includes the following: the start time of the first frequency divider reset signal and the start time of the timer have a predetermined interval; the first frequency divider reset signal and the timer are triggered based on a predetermined edge of the same working clock signal.

[0228] The phase adjustment module can be configured to adjust the phase of the second clock signal to obtain the working clock signal. The phase adjustment module can be implemented by at least one of the following to adjust the phase of the clock signal: phase-locked loop (PLL), delay-locked loop (DLL), or digital clock manager (DCM).

[0229] In one possible implementation, the phase adjustment module can be configured to adjust the phase of the second clock signal by a pre-set amount.

[0230] The phase of the second clock signal can be determined based on the transmission path of the control module transmitting the second clock signal, and the phase of the input clock signal can be determined based on the path of the input clock signal transmitted to the first frequency divider. That is, the phase difference between the second clock signal and the input clock signal is known. Therefore, the phase difference between the operating clock signal and the input clock signal can be determined based on the phase adjustment amount of the phase adjustment module.

[0231] Figure 7 is a timing diagram of the signal generation circuit shown in Figure 6. The predetermined trigger edge (shown as C in Figure 7) can include the Mth trigger edge (e.g., a rising edge) after the timer's start time. M is a positive integer greater than or equal to 1. As shown in Figure 7, the predetermined trigger edge can be the first rising edge after the timer's start time. Since the phase difference between the input clock signal and the operating clock signal is known, the time interval between the predetermined trigger edge and the timer's start time can be determined.

[0232] Here, the phase adjustment amount can be determined based on at least one of the following: the first frequency divider reset signal satisfies the setup time of the predetermined trigger edge (as shown by t in Figure 7); the second frequency divider reset signal does not trigger the edge of the input clock signal before the predetermined trigger edge.

[0233] Thus, the second frequency divider can be triggered at a predetermined trigger edge to perform frequency division and output a divided frequency signal. In Figure 7, the time interval T1 between the divided frequency signal and the start time of the timer may include the response time of the first frequency divider.

[0234] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response time of the second frequency divider can be determined based on the second frequency divider. Therefore, the first predetermined time interval T1 between the start time of the frequency division signal and the start time of the timer is fixed.

[0235] The calibration signal is obtained by filtering the frequency-divided signal. The filtering delay is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the second predetermined time interval T between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phase of the calibration signal and the signal to be calibrated, thereby achieving the calibration of the signal to be calibrated.

[0236] In practical applications, the deviations in the timer's start time, the start time of the frequency divider signal, and the time when the second frequency divider is triggered at the predetermined trigger edge originate from the edge setup times of the operating clock signal and the input clock signal. Since the edge setup times are relatively short, the deviations in these parameters are small, thus enabling high-precision calibration. The timer's start time is determined by the edge of the operating clock signal (e.g., the rising edge), and the frequency divider signal's start time is determined by the edge of the input clock signal (e.g., the rising edge). The operating clock signal and the input clock signal have a fixed phase relationship; therefore, the deviations between the timer's start time and the frequency divider signal's start time are fixed, allowing for high-precision calibration.

[0237] In some embodiments, as shown in FIG9, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronization bit control module and the counting frequency divider; the working clock is used to input the counting frequency divider as the input clock;

[0238] The method further includes:

[0239] The third synchronous reset control module generates a first frequency-divided reset signal based on the working clock signal; the start time includes a predetermined edge of the working clock signal after the generation time of the first frequency-divided reset signal.

[0240] The counting divider is triggered by the first frequency division reset signal at a predetermined edge, counts the working clock signal from the predetermined edge, and generates the frequency division signal based on the counting result.

[0241] Here, the clock module outputs a first clock signal based on a reference clock signal, which serves as the operating clock signal for the control module. Inside the control module, the operating clock signal is transmitted to a counter divider as an input clock signal.

[0242] In one possible implementation, the counter divider is configured to count the input clock signal and reverse the level when the count value reaches a counting threshold, thereby generating a periodic divided signal.

[0243] For example, if the required frequency division signal is an N-division signal of the working clock signal, then the counting threshold can be set to N / 2. When the frequency divider counts the working clock signal, the level is reversed when the count value reaches N / 2, thus generating the N-division signal.

[0244] Figure 10 is a timing diagram of the signal generation circuit shown in Figure 9. As shown in Figure 10, the first frequency divider reset signal and the timer have a corresponding relationship. The timer starts at a predetermined edge of the working clock signal after the generation of the first frequency divider reset signal.

[0245] In one possible implementation, the predetermined edge may include the first edge (rising edge or falling edge) of the operating clock signal after the generation time of the first frequency divider reset signal.

[0246] The counting divider counts based on the triggering of the first frequency division reset signal, thereby outputting the frequency division signal.

[0247] Here, the frequency divider is triggered at the start time of the timer; therefore, the time interval between the start time of the divided signal and the start time of the timer is fixed. For example, the start time of the divided signal is the same as the start time of the timer. The filtering delay of the low-pass filter is fixed; therefore, the interval T between the start time of the calibration signal generated by the divided signal and the start time of the timer is a fixed value.

[0248] This disclosure also proposes an electronic device, including a processor, a memory, and an executable program stored in the memory and executable by the processor, wherein the processor executes the steps of the signal generation method described in any of the above embodiments when running the executable program.

[0249] In this disclosure, the processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction read and execute capabilities, such as a Central Processing Unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a type of microprocessor), or a digital signal processor (DSP). In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. The logical relationships of the aforementioned hardware circuits are fixed or reconfigurable. For example, the processor is a hardware circuit implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units or modules. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a Neural Network Processing Unit (NPU), a Tensor Processing Unit (TPU), a Deep Learning Processing Unit (DPU), etc.

[0250] The computer-readable storage medium provided in this embodiment can execute the signal generation method of the above embodiment. Its implementation principle and technical effect are similar to those of the above embodiment, and will not be described again here.

[0251] The aforementioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0252] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in an electronic device or a host device.

[0253] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0254] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0255] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0256] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A signal generation circuit, wherein, The signal generation circuit includes: a clock module, a control module, and a frequency divider module, wherein, The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module. The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal; The frequency divider module is configured to divide the input clock signal based on a first frequency divider reset signal to output a frequency divider signal, wherein the input clock signal is generated based on the first clock signal; the first frequency divider reset signal is used to control the interval between the start time of the frequency divider module outputting the frequency divider signal and the start time of the timer for a first predetermined time.

2. The signal generation circuit according to claim 1, wherein, The signal generation circuit further includes a low-pass filter configured to perform low-pass filtering on the frequency division signal to obtain a calibration signal, wherein the start time of the calibration signal is spaced apart from the start time of the timer by a second predetermined duration.

3. The signal generation circuit according to claim 1 or 2, wherein, The signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider; The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal; The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module; The signal delay submodule is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The first frequency divider is configured to be triggered by the second frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

4. The signal generation circuit according to claim 1 or 2, wherein, The signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider; The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal; The second synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal; The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The second frequency divider is configured to be triggered by the first frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

5. The signal generation circuit according to claim 1 or 2, wherein, The first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes a third synchronous reset control module and the counting frequency divider; the working clock signal is used as input to the counting frequency divider as the input clock signal; The third synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal; The startup time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal; The counting divider is configured to be triggered by the first frequency division reset signal at a predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

6. A signal generation method, wherein, The method is applied to a signal generation circuit, which includes a clock module, a control module, and a frequency divider module, wherein the method includes: The clock module generates a first clock signal based on the input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module; The control module sends a first frequency division reset signal to the frequency division module and triggers the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal; The frequency divider module divides the input clock signal based on the first frequency divider reset signal to output a frequency divider signal, wherein the input clock signal is generated based on the first clock signal; the first frequency divider reset signal is used to control the interval between the start time of the frequency divider module outputting the frequency divider signal and the start time of the timer for a first predetermined time.

7. The signal generation method according to claim 6, wherein, The signal generation circuit further includes: a low-pass filter; The method further includes: performing low-pass filtering on the frequency division signal through the low-pass filter to obtain a calibration signal, wherein the start time of the calibration signal is spaced apart from the start time of the timer by a second predetermined time interval.

8. The signal generation method according to claim 6 or 7, wherein, The signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider; the method further includes: The working clock signal and the input clock signal are generated based on the first clock signal using the first clock buffer; The first frequency division reset signal is sent to the frequency division module through the first synchronous reset control module; The first frequency-divided reset signal is delayed by a predetermined time by the signal delay submodule to obtain a second frequency-divided reset signal, so that the second frequency-divided reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The first frequency divider is triggered by the second frequency divider reset signal at the predetermined trigger edge, and the frequency divider signal is generated based on the input clock signal.

9. The signal generation method according to claim 6 or 7, wherein, The signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider; The method further includes: The second clock buffer generates a second clock signal and the input clock signal based on the first clock signal; The second synchronous reset control module generates a first frequency-divided reset signal based on the working clock signal; The phase of the second clock signal is adjusted by the phase adjustment module to obtain the working clock signal, so that the first frequency division reset signal triggered by the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The second frequency divider is triggered by the first frequency divider reset signal at the predetermined trigger edge, and the frequency divider signal is generated based on the input clock signal.

10. The signal generation method according to claim 6 or 7, wherein, The first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes a third synchronous reset control module and the counting frequency divider; the working clock signal is used as input to the counting frequency divider as the input clock signal; The method further includes: The third synchronous reset control module generates a first frequency-divided reset signal based on the working clock signal; the start time includes a predetermined edge of the working clock signal after the generation time of the first frequency-divided reset signal. The counting divider is triggered by the first frequency division reset signal at a predetermined edge, counts the working clock signal from the predetermined edge, and generates the frequency division signal based on the counting result.

11. An electronic device, wherein, Includes the signal generation circuit as described in any one of claims 1 to 5.

12. An electronic device comprising a processor, a memory, and an executable program stored in the memory and executable by the processor, wherein, When the processor runs the executable program, it performs the steps of the signal generation method as described in any one of claims 6 to 10.

13. A storage medium having an executable program stored thereon, wherein, When the executable program is executed by a processor, it implements the steps of the signal generation method as described in any one of claims 6 to 10.

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