Calibration circuit, signal processing device, and signal processing system

Abstract

Provided in the embodiments of the present disclosure are a calibration circuit, a signal processing device, and a signal processing system. The calibration circuit comprises a signal generation circuit, the signal generation circuit comprising: a clock module, which generates a first clock signal, wherein the first clock signal is at least used for generating an operating clock signal for a control module and an input clock signal for a frequency-division module; the control module, which sends a first frequency-division reset signal to the frequency-division module and triggers the startup of a timer in the control module, wherein the timer performs timing on the basis of the operating clock signal, and the first frequency-division reset signal controls an interval between an initial moment at which the frequency-division module outputs a frequency-division signal and a startup moment of the timer to be a first predetermined duration; and a low-pass filter, which filters the frequency-division signal to obtain a first calibration signal, wherein an interval between an initial moment of the first calibration signal and the startup moment of the timer is a second predetermined duration, and the first calibration signal is used for analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between an initial moment of the first digital signal and the startup moment of the timer.

Description

Calibration circuits, signal processing equipment, and signal processing systems

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 202510112061.5, filed on January 23, 2025, entitled "Calibration Circuit, Signal Processing Apparatus and Signal Processing System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of signal measurement technology, and in particular to a calibration circuit, signal processing device, and signal processing system. Background Technology

[0004] In some applications, devices typically require time delay calibration and multi-channel synchronization calibration each time they are powered on. After power-on, the device usually undergoes a series of calibrations to ensure that the timing relationships between different channels and modules meet the device's performance requirements. For example, signal source devices require a fixed time delay from trigger to output after each power-on, with a time delay variation deviation of less than 10 ps. The first calibration signal is usually used for calibration between different channels and / or modules. How to generate a first calibration signal with a fixed phase relationship to the control module's operating clock and improve calibration accuracy is a pressing issue that needs to be addressed. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a calibration circuit, a signal processing device, and a signal processing system.

[0006] According to a first aspect of the present disclosure, a calibration circuit is provided, the calibration circuit including a signal generation circuit; the signal generation circuit includes: a clock module, a control module, a frequency division module, and a low-pass filter, wherein...

[0007] The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module and the input clock signal of the frequency divider module.

[0008] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0009] The first frequency division reset signal is used to control the frequency division module to output the frequency division signal at a time interval of a first predetermined duration between the start time of the frequency division signal and the start time of the timer;

[0010] A low-pass filter is configured to perform low-pass filtering on the frequency division signal to obtain a first calibration signal, wherein the start time of the first calibration signal is spaced apart from the start time of the timer by a second predetermined time interval.

[0011] The first calibration signal is used at least for the analog-to-digital conversion module to perform analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between the initial time of the first digital signal and the start time of the timer, wherein the first measurement duration is used at least to determine the transmission delay associated with the first calibration signal.

[0012] In some embodiments, the calibration circuit includes the analog-to-digital conversion module.

[0013] The control module is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer.

[0014] The control module is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

[0015] In some embodiments, the calibration circuit includes a selection switch configured to select one of the first calibration signal and N signals to be calibrated as input to the analog-to-digital converter module; wherein,

[0016] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated.

[0017] The control module is configured to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated.

[0018] The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

[0019] In some embodiments, the calibration circuit includes a selection switch configured to select a second calibration signal external to the calibration circuit as input to the analog-to-digital converter module; wherein...

[0020] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0021] The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0022] In some embodiments, the signal generation circuit further includes a fan-out module;

[0023] The fan-out module is connected to the low-pass filter and is configured to fan out at least one of the first calibration signals.

[0024] In some embodiments, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider;

[0025] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0026] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0027] The signal delay submodule is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0028] The first frequency divider is configured to be triggered by the second frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0029] In some embodiments, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0030] The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal;

[0031] The second synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0032] The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0033] The second frequency divider is configured to be triggered by the first frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0034] In some embodiments, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes a third synchronous reset control module and the counting frequency divider; the working clock is used to input the counting frequency divider as the input clock;

[0035] The third synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0036] The startup time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal;

[0037] The counting divider is configured to be triggered by the first frequency division reset signal at a predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

[0038] According to a second aspect of the present disclosure, a signal processing apparatus is provided, the signal processing apparatus including at least one calibration circuit as described in the first aspect.

[0039] In some embodiments, the calibration circuit includes a first calibration circuit, wherein the first calibration circuit includes the analog-to-digital conversion module.

[0040] The control module of the first calibration circuit is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer.

[0041] The control module of the first calibration circuit is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

[0042] In some embodiments, the signal processing device further includes N channels to be calibrated, wherein each channel to be calibrated is configured to output a signal to be calibrated;

[0043] The first calibration circuit includes a selection switch configured to select one of the first calibration signal and at least one signal to be calibrated as input to the analog-to-digital converter module; wherein,

[0044] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated.

[0045] The control module is configured to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated.

[0046] The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the first calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

[0047] In some embodiments, the first calibration circuit includes a selection switch configured to select a second calibration signal external to the first calibration circuit as input to the analog-to-digital conversion module; wherein...

[0048] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0049] The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0050] In some embodiments, the calibration circuit further includes a second calibration circuit, and the signal generation circuit of the second calibration circuit further includes a fan-out module;

[0051] The fan-out module is connected to the low-pass filter and is configured to fan out at least one first calibration signal from the second calibration circuit.

[0052] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal of the second calibration circuit.

[0053] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal sent by an external signal processing device.

[0054] According to a third aspect of the present disclosure, a signal processing system is provided, the signal processing system including at least one signal processing device as described in the second aspect.

[0055] This disclosure provides a calibration circuit, a signal processing device, and a signal processing system. The calibration circuit includes a signal generation circuit; the signal generation circuit includes a clock module, a control module, a frequency divider module, and a low-pass filter, wherein the clock module is used to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module and the input clock signal of the frequency divider module; the control module is configured to send a first frequency divider reset signal to the frequency divider module and trigger the start of a timer associated with the first frequency divider reset signal in the control module, wherein the timer counts based on the operating clock signal; the first frequency divider reset signal is used to control the frequency divider module to output the frequency divider signal at a first predetermined time interval between the start time of the frequency divider and the start time of the timer; the low-pass filter is configured to perform low-pass filtering on the frequency divider signal to obtain a first calibration signal, wherein the start time of the first calibration signal is used at least to determine the transmission delay associated with the first calibration signal by an analog-to-digital conversion module to obtain a first digital signal, thereby determining a first measurement duration between the initial time of the first digital signal and the start time of the timer, wherein the first measurement duration is used at least to determine the transmission delay associated with the first calibration signal. Thus, by adjusting the start time of the frequency division signal based on the first frequency division reset signal and establishing the correspondence between the first frequency division reset signal and the start time of the timer, the time interval between the start position of the first calibration signal and the start time of the timer can be controlled. Furthermore, based on the fixed positional relationship between the first calibration signal and the start time of the timer, the signal transmission delay can be determined and calibrated to improve calibration accuracy. Attached Figure Description

[0056] Figure 1 is a schematic diagram of a calibration circuit according to an exemplary embodiment;

[0057] Figure 2 is a schematic diagram of a signal generation timing according to an exemplary embodiment;

[0058] Figure 3 is a schematic diagram of another calibration circuit according to an exemplary embodiment;

[0059] Figure 4 is a schematic diagram of another signal generation timing according to an exemplary embodiment;

[0060] Figure 5 is a schematic flowchart of a signal generation method according to an exemplary embodiment;

[0061] Figure 6 is a schematic diagram of the structure of another calibration circuit according to an exemplary embodiment;

[0062] Figure 7 is a schematic diagram of another signal generation timing according to an exemplary embodiment;

[0063] Figure 8 is a schematic flowchart of another signal generation method according to an exemplary embodiment;

[0064] Figure 9 is a schematic diagram of another calibration circuit according to an exemplary embodiment;

[0065] Figure 10 is a schematic diagram of another signal generation timing according to an exemplary embodiment;

[0066] Figure 11 is a schematic flowchart of another signal generation method according to an exemplary embodiment;

[0067] Figure 12 is a schematic flowchart of another signal generation method according to an exemplary embodiment;

[0068] Figure 13 is a schematic flowchart of a time delay calibration method according to an exemplary embodiment;

[0069] Figure 14 is a schematic diagram of a delay calibration timing according to an exemplary embodiment;

[0070] Figure 15 is a schematic diagram of another calibration circuit according to an exemplary embodiment;

[0071] Figure 16 is a schematic diagram of the structure of a signal processing device according to an exemplary embodiment;

[0072] Figure 17 is a schematic diagram of another delay calibration timing according to an exemplary embodiment;

[0073] Figure 18 is a schematic diagram of another calibration circuit according to an exemplary embodiment;

[0074] Figure 19 is a schematic diagram of another calibration circuit according to an exemplary embodiment;

[0075] Figure 20 is a schematic diagram of the structure of a signal processing device according to an exemplary embodiment;

[0076] Figure 21 is a schematic diagram of the structure of a signal processing system according to an exemplary embodiment. Detailed Implementation

[0077] To make the technical solution and beneficial effects of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0078] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0079] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0080] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0081] In this embodiment of the disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0082] In the embodiments disclosed herein, "multiple" refers to two or more.

[0083] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0084] In some embodiments, the notation "at least one of A and B", "A and / or B", "A in one case, B in another", "A in one case, B in another", etc., may include the following technical solutions depending on the situation: in some embodiments, A (A is executed regardless of B); in some embodiments, B (B is executed regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, A and B (both A and B are executed). The same applies when there are more branches such as A, B, C, etc.

[0085] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execution of A regardless of B); in some embodiments, B (execution of B regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, C, etc.

[0086] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects should be found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the value of the descriptive object is not limited by ordinal numbers and can be one or more. For example, in "first device," the value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0087] In some embodiments, “including A,” “containing A,” “for indicating A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0088] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably.

[0089] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0090] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0091] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0092] Figure 1 illustrates a calibration circuit according to an embodiment of the present disclosure. The calibration circuit includes a signal generation circuit; the signal generation circuit includes: a clock module, a control module, a frequency divider module, and a low-pass filter, wherein...

[0093] The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module and the input clock signal of the frequency divider module.

[0094] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0095] The first frequency division reset signal is used to control the frequency division module to output the frequency division signal at a time interval of a first predetermined duration between the start time of the frequency division signal and the start time of the timer;

[0096] A low-pass filter is configured to perform low-pass filtering on the frequency division signal to obtain a first calibration signal, wherein the start time of the first calibration signal is spaced apart from the start time of the timer by a second predetermined time interval.

[0097] The first calibration signal is used at least for the analog-to-digital conversion module to perform analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between the initial time of the first digital signal and the start time of the timer, wherein the first measurement duration is used at least to determine the transmission delay associated with the first calibration signal.

[0098] In one possible implementation, the calibration circuit can be implemented by an integrated circuit, or by a combination of at least one integrated circuit and at least one discrete component.

[0099] Here, calibration circuits can be applied to signal processing equipment, such as arbitrary waveform generator (AWG) signal sources, arbitrary function generator (AFG) signal sources (i.e., signal sources, radio frequency signal sources, vector signal sources, etc.), and also to electronic devices such as oscilloscopes and spectrum analyzers. Calibration circuits can exist as independent functional modules, such as independent functional modules in the PXIe architecture; they can also be combined with other functional circuits to achieve composite functions.

[0100] In one possible implementation, the calibration circuitry may be carried on a module card within the PXIe architecture.

[0101] Here, the reference clock signal can be a clock signal generated by a reference clock signal source. For example, the reference clock signal can be a crystal oscillator clock signal, or it can be a clock signal sent by the motherboard to each functional module board in the PXIe architecture.

[0102] The control module can be implemented using components with signal processing and / or data computation capabilities, such as a Field Programmable Gate Array (FPGA). Alternatively, it can be implemented using a Microprocessor (MCU).

[0103] The clock module is configured to buffer and divide the reference clock signal at least once to generate a clock signal at the frequency required for the operation of each module.

[0104] In one possible implementation, the first clock signal is used to generate at least one of the operating clock signal and the input clock signal. For example, the first clock signal can generate the operating clock signal and the input clock signal by fan-out or other methods.

[0105] Here, the control module can control the frequency divider module to reset and / or perform frequency division operation via a reset signal. For example, the control module can control the frequency divider module to enter the reset state and / or perform frequency division operation through two levels of the reset signal. The first frequency divider reset signal can be the level that triggers the frequency divider module to divide the input clock signal. As shown in Figure 2, the first frequency divider reset signal is the low-level state of the reset signal in Figure 2.

[0106] In one possible implementation, the frequency divider module is in a reset state before dividing the input clock signal.

[0107] In one possible implementation, the first frequency divider reset signal is triggered based on the edge of the operating level.

[0108] In one possible implementation, the control module triggering the start of a timer associated with the first frequency divider reset signal may include: the control module triggering the timer at a predetermined edge (rising edge or falling edge) of the input working clock signal after the first frequency divider reset signal is generated.

[0109] In one possible implementation, the predetermined edge is the first rising edge after the start time of the first frequency division reset signal (as indicated by arrow A in Figure 2).

[0110] In one possible implementation, the timer's start time (as indicated by arrow B in Figure 2) is the edge time of a predetermined edge.

[0111] Since the timer operates based on the operating clock signal, its timing is synchronized with the operating clock signal. For example, the timer counts once for each period of the operating clock signal.

[0112] Both the operating clock signal and the input clock signal are generated from the first clock signal, therefore they are correlated. In one possible implementation, the operating clock signal and the input clock signal have a fixed phase difference.

[0113] In one possible implementation, the start time of the frequency divider module's output frequency divider signal can be adjusted by changing the time-domain position of the first frequency divider reset signal's start time. For example, the frequency divider module can be triggered to output the frequency divider signal at the edge of the input clock signal by the first frequency divider reset signal. Therefore, the start time of the frequency divider module's output frequency divider signal triggered by the first frequency divider reset signal can be determined based on the time-domain position of the first frequency divider reset signal's start time and the time-domain position of the input clock signal's edge. Since the operating clock signal and the input clock signal have a fixed phase difference, the time interval between the start time of the frequency divider signal triggered by the input clock signal and the timer's start time is fixed, which means the time interval between the start time of the frequency divider signal and the timer's start time can be determined, i.e., the first predetermined duration (as shown by T1 in Figure 2).

[0114] In one possible implementation, the frequency divider module can be configured to divide the input clock signal by N to output a divided signal. Here, N is a positive integer greater than or equal to 1.

[0115] As shown in Figure 2, the frequency-divided signal obtained after the frequency division module is approximately a square wave and contains high-frequency harmonic components. These can be filtered using a low-pass filter to obtain a smooth first calibration signal, thereby improving the accuracy of phase calculation. The low-pass filter can be set based on the frequency of the frequency-divided signal, filtering out harmonic components with frequencies higher than the frequency of the frequency-divided signal.

[0116] As shown in Figure 2, there is a filtering delay when the low-pass filter performs filtering (as shown by T2 in Figure 2). Therefore, the second predetermined duration of the interval between the first calibration signal obtained after filtering and the start time of the timer (the sum of T1 and T2 in Figure 2) is the sum of the first predetermined duration and the filtering delay.

[0117] In one possible implementation, the analog-to-digital conversion module can be located either inside or outside the calibration circuit.

[0118] The first calibration signal reaches the analog-to-digital converter (ADC) through the transmission path, and is then converted from analog to digital by the ADC to obtain the first digital signal. Here, the first digital signal may include the digitized first calibration signal. The first calibration signal can be an analog signal, which is then converted from analog to digital to obtain the digitized first calibration signal.

[0119] In one possible implementation, the analog-to-digital converter module can transmit the first digital signal to the control module connected to the analog-to-digital converter module via a digital signal transmission channel such as a data bus.

[0120] In one possible implementation, the control module connected to the analog-to-digital conversion module may include a control module within the calibration circuit, or a control module outside the calibration circuit.

[0121] In one possible implementation, the analog-to-digital converter (ADC) can perform the conversion in a streaming manner, with the first digital signal transmitted to the control module connected to the ADC via streaming. That is, the first digital signal is sent directly to the control module connected to the ADC without passing through a data buffer.

[0122] The control module connected to the analog-to-digital conversion module can determine the moment when the first digital signal is received, that is, the start time of the first digital signal. It then determines the first measurement duration between the start time of the first digital signal and the start time of the timer.

[0123] The transmission delay associated with the first calibration signal may include the transmission delay of part or all of the transmission paths for transmitting the first calibration signal. For example, the transmission delay associated with the first calibration signal may include at least one of the following: the sampling delay of the analog-to-digital converter performing analog-to-digital conversion; the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital converter; and the transmission delay of at least one of the cables, connectors, and selector switches for transmitting the first calibration signal.

[0124] For example, if the transmission path of the first calibration signal from the low-pass filter to the analog-to-digital converter (ADC) is short or the transmission delay is known, then the sampling delay of the ADC can be determined based on the first measurement duration. If the sampling delay of the ADC can be determined based on the components used in the ADC, then the transmission delay from the low-pass filter to the ADC can be determined based on the first measurement duration.

[0125] Thus, by adjusting the start time of the frequency division signal based on the first frequency division reset signal and establishing the correspondence between the first frequency division reset signal and the start time of the timer, the time interval between the start position of the first calibration signal and the start time of the timer can be controlled. Furthermore, based on the fixed positional relationship between the first calibration signal and the start time of the timer, the signal transmission delay can be determined and calibrated to improve calibration accuracy.

[0126] In some embodiments, as shown in FIG3, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider;

[0127] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0128] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0129] The signal delay submodule is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0130] The first frequency divider is configured to be triggered by the second frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0131] The first clock buffer is configured to generate two clock signals—a working clock signal and an input clock signal—from a single first clock signal through frequency replication or other methods. The phase of the working clock signal input to the control module can be determined based on the transmission path of the working clock signal through the control module, and the phase of the input clock signal input to the first frequency divider can be determined based on the transmission path of the input clock signal through the first frequency divider. In other words, since the circuit for converting the first clock signal into the working clock signal and the input clock signal is fixed, the phase difference between the input clock signal and the working clock signal is known.

[0132] Here, the first synchronous reset control module in the control module can send the first frequency division reset signal to the frequency division module. The timer in the control module can start timing after the first frequency division reset signal.

[0133] Figure 4 is a timing diagram of the signal generation circuit shown in Figure 3. The timer can be triggered to start at a predetermined edge of the operating clock signal after the first frequency divider reset signal. As shown in Figure 4, the predetermined edge after the first frequency divider reset signal may include the first rising edge after the first frequency divider reset signal.

[0134] In one possible implementation, the predetermined trigger edge of the input clock signal (shown as C in Figure 4) may include the Mth trigger edge (e.g., a rising edge) after the timer's start time. M is a positive integer greater than or equal to 1. As shown in Figure 4, the predetermined trigger edge may be the first rising edge after the timer's start time. Since the phase difference between the input clock signal and the operating clock signal is known, the time interval between the predetermined trigger edge and the timer's start time can be determined.

[0135] In one possible implementation, the predetermined delay duration can be determined based on the time interval between the start time of the first frequency-divided reset signal and the predetermined trigger edge. The predetermined delay duration can be determined based on at least one of the following: the establishment time of the second frequency-divided reset signal after the delay is satisfied (as shown in t in Figure 4); the second frequency-divided reset signal does not trigger the edge of the input clock signal before the predetermined trigger edge.

[0136] In one possible implementation, the predetermined delay duration can be pre-written into the signal delay submodule. In an FPGA, the signal delay submodule can be implemented using input / output delay (IOdelay) circuitry.

[0137] The second frequency divider reset signal enables the first frequency divider to be triggered at a predetermined trigger edge to perform frequency division and output a divided frequency signal. In Figure 4, the time interval T1 between the start time of the divided frequency signal and the start time of the timer may include the response time of the first frequency divider.

[0138] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response time of the first frequency divider can be determined based on the first frequency divider. Therefore, the first predetermined time interval between the start time of the frequency division signal and the start time of the timer is fixed.

[0139] The first calibration signal is obtained by filtering the frequency-divided signal. The filtering delay is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the second predetermined time interval T between the start time of the first calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phase of the first calibration signal and the signal to be calibrated, thereby achieving the calibration of the signal to be calibrated.

[0140] In practical applications, the start time of the timer, the start time of the frequency divider signal, and the time when the first frequency divider is triggered at a predetermined trigger edge are all related to the release time of the second frequency divider reset signal. That is, the falling edge of the second reset signal needs to be sampled by both the working clock signal and the input clock signal, requiring sufficient setup and hold time between the falling edge of the second reset signal and its sampling time. Since the timer's start time is triggered by the edge of the working clock signal, and the start time of the frequency divider signal and the first frequency divider are triggered by the input clock signal, and the working clock signal and the input clock signal have a fixed phase relationship, the deviations between the timer's start time, the start time of the frequency divider signal, and the time when the first frequency divider is triggered at the predetermined trigger edge are fixed, thus enabling high-precision calibration.

[0141] For example, as shown in Figure 5, the specific steps of the first calibration signal generation method include:

[0142] Step 501: Power on and initialize each module in the signal generation process.

[0143] Step 502: Configure the clock module to generate the input clock signal of the first frequency divider and the working clock signal of the FPGA (control module).

[0144] Step 503: Synchronize the first synchronous reset control module to control the first frequency divider to be in the reset state and the timer to be in the reset state.

[0145] Step 504: Configure the delay value (predetermined delay duration) of the signal delay submodule. The delay value can be a factory calibration value used to control the setup / hold time of the second frequency divider reset signal and the input clock signal.

[0146] Step 505: The control module determines whether a first calibration signal needs to be generated. If yes, proceed to step 506; otherwise, proceed to step 505.

[0147] Step 506: Issue the second frequency divider reset signal to release the first frequency divider.

[0148] Step 507: Start the FPGA internal timer (to count the start reference time of the first calibration signal).

[0149] Step 508: The frequency-divided signal passes through a low-pass filter.

[0150] Step 509: The output signal of the low-pass filter is the first calibration signal.

[0151] In the above steps, the signal delay submodule uses the delay value obtained during factory calibration. This delay value is used to control the second frequency divider reset signal output by the FPGA to have sufficient setup / hold timing with the input clock signal, ensuring that the frequency divider signal output by the first frequency divider and the start time of the FPGA's internal timer have a fixed delay relationship each time power is powered on. This guarantees that the first calibration signal output by the low-pass filter has a fixed delay relationship with the start time of the FPGA's internal timer.

[0152] In some embodiments, as shown in FIG6, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0153] The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal;

[0154] The second synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0155] The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0156] The second frequency divider is configured to be triggered by the first frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

[0157] The first clock buffer is configured to generate two clock signals: a second clock signal and an input clock signal, from a first clock signal through frequency replication or other means.

[0158] Here, the first frequency divider reset signal and the timer have a corresponding relationship. The corresponding relationship between the first frequency divider reset signal and the timer includes the following: the start time of the first frequency divider reset signal and the start time of the timer have a predetermined interval; the first frequency divider reset signal and the timer are triggered based on a predetermined edge of the same working clock signal.

[0159] The phase adjustment module can be configured to adjust the phase of the second clock signal to obtain the working clock signal. The phase adjustment module can be implemented by at least one of the following to adjust the phase of the clock signal: phase-locked loop (PLL), delay-locked loop (DLL), or digital clock manager (DCM).

[0160] In one possible implementation, the phase adjustment module can be configured to adjust the phase of the second clock signal by a pre-set amount.

[0161] The phase of the second clock signal can be determined based on the transmission path of the control module transmitting the second clock signal, and the phase of the input clock signal can be determined based on the path of the input clock signal transmitted to the first frequency divider. That is, the phase difference between the second clock signal and the input clock signal is known. Therefore, the phase difference between the operating clock signal and the input clock signal can be determined based on the phase adjustment amount of the phase adjustment module.

[0162] Figure 7 is a timing diagram of the signal generation circuit shown in Figure 6. The predetermined trigger edge (shown as C in Figure 7) can include the Mth trigger edge (e.g., a rising edge) after the timer's start time. M is a positive integer greater than or equal to 1. As shown in Figure 7, the predetermined trigger edge can be the first rising edge after the timer's start time. Since the phase difference between the input clock signal and the operating clock signal is known, the time interval between the predetermined trigger edge and the timer's start time can be determined.

[0163] Here, the phase adjustment amount can be determined based on at least one of the following: the first frequency divider reset signal satisfies the setup time of the predetermined trigger edge (as shown by t in Figure 7); the second frequency divider reset signal does not trigger the edge of the input clock signal before the predetermined trigger edge.

[0164] Thus, the second frequency divider can be triggered at a predetermined trigger edge to perform frequency division and output a divided frequency signal. In Figure 7, the time interval T1 between the divided frequency signal and the start time of the timer may include the response time of the first frequency divider.

[0165] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response time of the second frequency divider can be determined based on the second frequency divider. Therefore, the first predetermined time interval T1 between the start time of the frequency division signal and the start time of the timer is fixed.

[0166] The first calibration signal is obtained by filtering the frequency-divided signal. The filtering delay is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the second predetermined time interval T between the start time of the first calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phase of the first calibration signal and the signal to be calibrated, thereby achieving the calibration of the signal to be calibrated.

[0167] In practical applications, the start time of the timer is determined by the edge of the working clock signal (such as the rising edge), and the start time of the frequency divider signal is determined by the edge of the input clock signal (such as the rising edge). The working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviation between the start time of the timer and the start time of the frequency divider signal is fixed, thereby enabling high-precision calibration.

[0168] For example, as shown in Figure 8, the specific steps of the first calibration signal generation method include:

[0169] Step 801: Power on and initialize each module in the signal generation process.

[0170] Step 802: Configure the clock module to generate the input clock signal and the second clock signal for the frequency divider.

[0171] Step 803: Synchronous reset control module, controls the second frequency divider to be in reset state, and the timer to be in reset state.

[0172] Step 804: Configure the parameters of the phase adjustment module in the FPGA (control module) to adjust the phase of the second clock signal. The phase adjustment amount can be a factory calibration value, used to control the setup / hold time of the first divider reset signal and the second divider input clock.

[0173] Step 805: The control module determines whether a first calibration signal needs to be generated. If yes, proceed to step 806; otherwise, proceed to step 805.

[0174] Step 806: Issue the first frequency divider reset signal to release the second frequency divider.

[0175] Step 807: Start the FPGA's internal timer. Count the time as the starting reference time for the first calibration signal.

[0176] Step 808: The frequency-divided signal passes through a low-pass filter.

[0177] Step 809: The output signal of the low-pass filter is the first calibration signal.

[0178] In the above steps, the phase adjustment module (such as PLL, DLL, DCM, etc.) of the FPGA's internal clock unit is used to adjust the phase of the FPGA's operating clock signal, thereby ensuring sufficient setup / hold timing for the first frequency divider reset signal and the input clock of the second frequency divider. This ensures that the output signal of the second frequency divider and the start time of the FPGA's internal timer have a fixed time delay relationship each time power is applied.

[0179] In some embodiments, as shown in FIG9, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal;

[0180] The third synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal;

[0181] The startup time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal;

[0182] The counting divider is configured to be triggered by the first frequency division reset signal at a predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

[0183] Here, the clock module outputs a first clock signal based on a reference clock signal, which serves as the operating clock signal for the control module. Inside the control module, the operating clock signal is transmitted to a counter divider as an input clock signal.

[0184] In one possible implementation, the counter divider is configured to count the input clock signal and reverse the level when the count value reaches a counting threshold, thereby generating a periodic divided signal.

[0185] For example, if the required frequency division signal is an N-division signal of the working clock signal, then the counting threshold can be set to N / 2. When the frequency divider counts the working clock signal, the level is reversed when the count value reaches N / 2, thereby generating the N-division signal.

[0186] Figure 10 is a timing diagram of the signal generation circuit shown in Figure 9. As shown in Figure 10, the first frequency divider reset signal and the timer have a corresponding relationship. The timer starts at a predetermined edge of the working clock signal after the generation of the first frequency divider reset signal.

[0187] In one possible implementation, the predetermined edge may include the first edge (rising edge or falling edge) of the operating clock signal after the generation time of the first frequency divider reset signal.

[0188] The counting divider counts based on the triggering of the first frequency division reset signal, thereby outputting the frequency division signal.

[0189] Here, the frequency divider is triggered at the start time of the timer; therefore, the time interval between the start time of the divided signal and the start time of the timer is fixed. For example, the start time of the divided signal is the same as the start time of the timer. The filtering delay of the low-pass filter is fixed; therefore, the interval T between the start time of the first calibration signal generated by the divided signal and the start time of the timer is a fixed value.

[0190] For example, as shown in Figure 11, the specific steps of the first calibration signal generation method include:

[0191] Step 1101: Power on and initialize each module in the signal generation process.

[0192] Step 1102: The third synchronous reset control module controls the counter divider to be in the reset state and the timer to be in the reset state.

[0193] Step 1103: The control module determines whether a first calibration signal needs to be generated. If yes, proceed to step 1104; otherwise, proceed to step 1103.

[0194] Step 1104: Issue the first frequency divider reset signal for the release counter frequency divider.

[0195] Step 1105: Start the FPGA (control module) internal timer to count the start reference time of the first calibration signal.

[0196] Step 1106: The frequency-divided signal passes through a low-pass filter.

[0197] Step 1107: The output signal of the low-pass filter is the first calibration signal.

[0198] In the above steps, this scheme does not use an external frequency divider, nor does it require adjusting the phase of the third synchronous reset control module and the input clock signal of the external frequency divider. This scheme directly starts the internal frequency divider counter based on the FPGA working clock signal, realizes the N-fold frequency division signal, and obtains the first calibration signal by passing the signal output through a low-pass filter, which is simple and easy to implement.

[0199] In some embodiments, as shown in FIG12, the calibration circuit includes the analog-to-digital conversion module.

[0200] The control module is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer.

[0201] The control module is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

[0202] It is understandable that the signal generation circuit in Figure 12, which consists of a control module, a clock module, a first clock buffer, a first frequency divider, and a low-pass filter, is one implementation of the signal generation circuit. Unless otherwise specified, the signal generation circuit may include the signal generation circuit in any of the above embodiments.

[0203] Here, the sampling delay associated with the analog-to-digital conversion module may include at least one of the following: the delay of the analog-to-digital conversion module in performing analog-to-digital conversion, the response delay of the analog-to-digital conversion module, and the transmission delay between the analog-to-digital conversion module and the control module.

[0204] In related technologies, the analog-to-digital converter (ADC) module in a calibration circuit may be affected by various factors upon each power-on, leading to changes in the sampling delay of the ADC module's sampling link. These factors include: re-establishing the internal timing of the ADC chip; re-establishing the timing of the data transmission interface between the ADC chip and the control module (such as an FPGA); cross-clock domain signal conversion within the FPGA; and changes in the phase relationship between the sampling clock and the FPGA operating clock. In other words, the sampling delay of the ADC module may change with each power-on, thus affecting the calibration progress of the calibration circuit. In certain application scenarios, the ADC module needs to have stable delay characteristics upon each power-on, such as when using the ADC module to sample external trigger signals or using an ADC chip to achieve synchronous output calibration of multi-channel, multi-machine signal source devices. In these application scenarios, the delay deviation of the ADC sampling circuit upon each power-on may need to be controlled within 5 ps. Therefore, it is necessary to determine the sampling delay of the ADC module in a timely manner to improve the calibration accuracy of the calibration circuit.

[0205] In one possible implementation, the analog-to-digital converter (ADC) can transmit the first digital signal to the control module connected to it via a digital signal transmission channel such as a data bus. The ADC and the control module are located in the same calibration circuit.

[0206] In one possible implementation, the analog-to-digital converter (ADC) can perform the conversion in a streaming manner, with the first digital signal transmitted to the control module connected to the ADC via streaming. That is, the first digital signal is sent directly to the control module connected to the ADC without passing through a data buffer.

[0207] The control module can determine the moment when the first digital signal is received, that is, the start time of the first digital signal. It can then determine the first measurement duration between the start time of the first digital signal and the start time of the timer.

[0208] In one possible implementation, as shown in Figure 2, after receiving the first digital signal, the control module can first search for the peak value of the first digital signal. After determining the peak value, it can extract the data at the position of 1 / 4 cycle before the peak value and perform phase calculation of the first digital signal based on the data, thereby determining the first measurement duration.

[0209] As shown in Figure 2, the interval between the start time of the first calibration signal and the start time of the timer is the second predetermined duration (the sum of T1 and T2 in Figure 2). The interval between the start time of the first digital signal and the start time of the timer is the first measurement duration T. Therefore, based on the first measurement duration T and the second predetermined duration, the total delay of the sampling delay of the analog-to-digital conversion module for analog-to-digital conversion and the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital conversion module can be determined.

[0210] Since the transmission path of the first calibration signal from the low-pass filter to the analog-to-digital converter module is fixed, the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital converter module can be determined. Therefore, the sampling delay of the analog-to-digital converter module for analog-to-digital conversion is determined by subtracting the transmission delay of the first calibration signal from the low-pass filter to the analog-to-digital converter module from the first measurement duration T.

[0211] In one possible implementation, the determined sampling delay can be used to compensate for the delay in the analog-to-digital conversion module.

[0212] For example, taking the calibration circuit in Figure 12 as an example, the control module can be an FPGA. Referring to the timing diagram of the calibration circuit in Figure 14, the specific steps for the calibration circuit to perform time delay calibration on the analog-to-digital conversion module are shown in Figure 13, including:

[0213] Step 1301: Power on and initialize each module in the signal generation process.

[0214] Step 1302: Configure the clock module to generate the input clock signal of the first frequency divider and the operating clock signal of the control module (FPGA).

[0215] Step 1303: Configure the delay value (predetermined delay duration) of the signal delay submodule (such as FPGA IODelay) to ensure a stable setup / hold timing relationship between the second frequency divider reset signal and the input clock of the frequency divider module (first frequency divider). The delay value can be a factory calibration value.

[0216] Step 1304: Determine whether to measure the delay of the analog-to-digital converter (ADC). If yes, proceed to step 1305; otherwise, proceed to step 1304.

[0217] Step 1305: Switch the selection switch so that it is used to acquire the first calibration signal.

[0218] Step 1306: Synchronize the first synchronous reset control module, control the frequency divider module (first frequency divider) to be in the reset state, and the timer to be in the reset state.

[0219] Step 1307: Issue the second frequency divider reset signal to release the first frequency divider.

[0220] Step 1308: Start the internal timer of the control module. Count the time as the starting reference time for the first calibration signal. Since the synchronous reset control signal and the input clock of the N divider have a stable setup / hold timing relationship, the frequency division calibration signal output by the N divider and the release time of the FPGA internal reset signal have a stable time phase relationship, recorded as T1.

[0221] Step 1309: The frequency-divided signal is passed through a low-pass filter to obtain the first calibration signal. After the frequency-divided calibration signal passes through the low-pass filter, the harmonic components are filtered out, and only the fundamental component is retained, which generates the ADC time delay calibration signal. The filter time delay is recorded as T2.

[0222] Step 1310: The first calibration signal is processed by ADC sampling, First In First Out (FIFO), and time delay adjustment module.

[0223] Step 1311: Calculate the precise delay value T3 of the analog-to-digital converter (ADC).

[0224] Step 13111: Search for the peak of the first sine wave of the first digital signal and record the current timer time, converting it into a time delay t0.

[0225] Step 13112: Extract a segment of data from the first digital signal and send it to the calibration data delay calculation module.

[0226] Step 13113: The calibration data delay calculation module calculates the precise phase based on the intercepted data and converts it into a delay value t1.

[0227] Step 13114: The delay value of the analog-to-digital conversion module is T3 = t0 + t1.

[0228] Step 1312: Determine whether the delay of the analog-to-digital converter module needs to be compensated. If so, determine the difference between the precise delay value T3 and the reference delay Tr of the analog-to-digital converter module: delta; otherwise, the precise delay value T3 can be recorded.

[0229] Step 1313: Determine whether the difference delata is less than the error threshold. If it is, the time delay calibration process ends; otherwise, compensation is performed based on the difference delata.

[0230] It is understandable that different signal generation circuits have different signal generation steps, which will not be elaborated here.

[0231] In practical applications, as shown in Figure 12, at the beginning of each calibration circuit power-on, the first calibration signal enters the ADC sampling circuit. After passing through the analog-to-digital converter (ADC) module and asynchronous clock domain conversion, the delay value of the first calibration signal is calculated. This delay value can be recorded and processed in other ways to eliminate the impact of changes in the link delay of the analog-to-digital converter module; alternatively, a delay adjustment module can be used to adjust the delay of the data converted by the analog-to-digital converter module to ensure that the delay entering the signal processing module remains a fixed value.

[0232] Thus, based on the fixed time-domain positional relationship between the first calibration signal and the start time of the timer, the sampling delay associated with the analog-to-digital conversion module can be determined by the time when the control module receives the first digital signal, thereby achieving delay compensation for the analog-to-digital conversion module and improving the accuracy of the signal processing equipment when calibrating the signal to be calibrated.

[0233] In some embodiments, as shown in FIG15, the calibration circuit includes a selection switch configured to select one of the first calibration signal and N signals to be calibrated as input to the analog-to-digital converter module; wherein,

[0234] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated.

[0235] The control module is configured to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated.

[0236] The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

[0237] It is understood that Figure 15 is only a schematic diagram. The signal generation circuit composed of the control module, clock module, frequency divider module and low-pass filter in Figure 15 and any of the following embodiments is one implementation of the signal generation circuit. Unless otherwise specified, the signal generation circuit may include the signal generation circuit in any of the above embodiments. Unless otherwise specified, the internal structure of the control module is as described in any of the above embodiments.

[0238] Here, N is a positive integer greater than or equal to 1.

[0239] In one possible implementation, a selection switch is used to select one of N signals to be calibrated and a first calibration signal as input to the analog-to-digital converter module. Here, the selection switch can be implemented as an electronic switch such as a relay switch. When the selection switch selects the first calibration signal as input to the analog-to-digital converter module, it can be used to calibrate the module, as shown in the above embodiment.

[0240] When the selector switch selects the signal to be calibrated to be input into the analog-to-digital conversion module, it can be used to determine the time delay of the channel to be calibrated corresponding to the signal to be calibrated.

[0241] In this embodiment, the function of the signal to be calibrated is not limited. For example, the signal to be calibrated can be an external trigger signal or a signal specifically used for channel calibration emitted by other channels to be calibrated.

[0242] In one possible implementation, the channel to be calibrated may include a signal source channel in a signal processing device. The channel to be calibrated may convert the digital signal into an analog signal for output based on digital-to-analog conversion.

[0243] In one possible implementation, the calibration circuit and the channel to be calibrated can output a first calibration signal and a signal to be calibrated, respectively, based on the same reference signal. For example, Figure 16 is a schematic diagram of a signal processing device (such as a signal generator), which includes a calibration circuit and a channel to be calibrated. As shown in Figure 16, the signal processing device can be implemented using a modular architecture such as the PXIe architecture. The calibration circuit and the channel to be calibrated can be respectively carried on daughter cards in the modular architecture. The modular architecture can include a backplane, and the daughter cards are connected to the backplane via slots, etc. The backplane is equipped with a backplane clock module and a backplane control module (which can be implemented by an FPGA and / or a processor, etc.). The backplane clock module can be used to provide a reference clock signal to each daughter card, and the backplane control module is configured to manage and control the daughter cards via communication and control lines.

[0244] As shown in Figure 16, the channel to be calibrated may include a signal source daughter card, which can act as a signal source to output signals to the outside. The signal source daughter card includes a daughter card clock module, a daughter card FPGA, DAC, AFE, relay switches, and channel output ports (CH1~CH4), etc. The daughter card clock module is configured to output clock signals to the daughter card FPGA and DAC based on a reference clock. The FPGA is configured to output digital signals to the DAC. The DAC performs digital-to-analog conversion to obtain analog signals, which are then output to the outside via the AFE and relay switches. When the signal source daughter card is configured to output the signal to be calibrated, the relay can connect to the selection switch, allowing the signal to be calibrated to be input to the selection switch.

[0245] It is understandable that, in Figure 16, each functional module in the control module is only one implementation method, and the implementation method of the control module can include the control module in any of the above embodiments. The signal generation circuit shown in Figure 16 is only one implementation method of the signal generation circuit, and can be replaced by the signal generation circuit in any of the above embodiments if there is no contradiction.

[0246] The signal to be calibrated is converted into a digital signal to be calibrated by the analog-to-digital conversion module, and the arrival time of the digital signal to be calibrated to the control module is determined by the control module.

[0247] Here, the predetermined signal transmission delay for the channel to be calibrated can include a predetermined delay between the generation of the signal to be calibrated by the waveform generator of the FPGA in the signal source daughter card and the receipt of the digital signal to be calibrated by the control module of the calibration circuit. Since the transmission path from the waveform generator to the control module of the calibration circuit is known, the transmission delay for the predetermined signal can be determined in advance. This is because the sampling delay of the analog-to-digital conversion module in the control module is determined based on the first calibration signal.

[0248] In one possible implementation, the predetermined signal transmission delay can be calibrated using a sampling delay to obtain a calibrated signal transmission delay. In another possible implementation, the calibrated signal transmission delay is used to synchronize the timer of the signal to be calibrated and the timer of the calibration circuit.

[0249] The channel to be calibrated can include a timer to record the generation time of the signal to be calibrated generated by the FPGA's waveform generator. Therefore, the channel to be calibrated can be synchronized based on the arrival time of the digital signal to be calibrated, the transmission delay of the calibrated signal, and the generation time of the signal to be calibrated. For example, the generation time of the signal to be calibrated can be updated by subtracting the transmission delay of the calibrated signal from the arrival time of the digital signal to be calibrated, thus synchronizing the timer in the calibration circuit with the timer in the channel to be calibrated.

[0250] For example, taking the calibration circuit in Figure 16 as an example, the specific steps for time delay calibration of the channel to be calibrated are shown in Figure 17, including:

[0251] Step 1701: Power on and initialize each module in the signal generation circuit.

[0252] Step 1702: The control module issues a command to synchronously reset the frequency divider module and start the timer.

[0253] Step 1703: Switch the selection switch of the calibration circuit and acquire the first calibration signal.

[0254] Step 1704: Calculate the precise delay value of the analog-to-digital conversion module relative to the start timer and record the delay value Tr.

[0255] Step 1705: Calculate the time delay difference Td that the analog-to-digital converter module needs to compensate; (the time delay value recorded by the analog-to-digital converter module during factory calibration is Ta, then Td = Ta - Tr).

[0256] Step 1706: Calculate the reference delay value for each channel to be calibrated (the channel to be calibrated is represented by Chi, and i represents the sequence number of the channel to be calibrated).

[0257] CHi reference delay value = DAC channel fixed reference delay + user-set CHi offset (skew) value + CHi delay compensation value - Td. The DAC channel fixed reference delay can be a parameter value recorded in the factory calibration; it is calculated and saved at the factory based on the delay values ​​of all channels. The user-set CHi skew value can be the delay value set by the user to fine-tune each channel; the CHi delay compensation value can be the compensation value recorded in the factory calibration; Td is the delay compensation value calculated by the analog-to-digital converter module each time the device is powered on.

[0258] Step 1707: Determine if all channels to be calibrated have been synchronously calibrated and compensated; if so, end the calibration process; otherwise, proceed to step 1708.

[0259] Step 1708: Select the next channel to be calibrated.

[0260] Step 1709: Switch the selection switch inside the calibration circuit to select the signal to be calibrated from the CHi channel.

[0261] Step 1710: Calculate the channel delay value from the CHi channel to the synchronization calibration card.

[0262] Step 1711: Is abs(CHi channel delay - CHi reference delay) less than the error threshold? If yes, proceed to step 1707; otherwise, proceed to step 1712.

[0263] Step 1712: Calculate the delay difference value to be adjusted for CHi, where the delay difference value to be adjusted for CHi = CHi reference delay value - CHi channel delay value.

[0264] Step 1713: Calculate the coarse delay value (integer sampling period) of CHi and the fine delay value (fractional sampling period) of CHi.

[0265] Step 1714: 1. Adjust the coarse and fine delay of the CHi channel.

[0266] In some embodiments, as shown in FIG18, the calibration circuit includes a selection switch configured to select a second calibration signal external to the calibration circuit as input to the analog-to-digital conversion module; wherein...

[0267] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0268] The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0269] In one possible implementation, the second calibration signal is generated by an external signal generation circuit. Here, the first and second calibration signals are used to distinguish between the calibration signals generated by the calibration circuit and those generated by the external signal generation circuit. The second calibration signal is received externally relative to the calibration circuit; relative to the external signal generation circuit, the second calibration signal is also the first calibration signal.

[0270] It is understood that the signal generation circuit shown in Figure 18 is only one implementation of the signal generation circuit, and can be replaced by the signal generation circuit in any of the above embodiments if there is no contradiction.

[0271] In one possible implementation, the external signal generation circuit is similar to the signal generation circuit disclosed in any of the above embodiments. The start time of the second calibration signal associated timer includes the start time of the timer of the control module in the external signal generation circuit. That is, the time interval between the start time of the second calibration signal and the start time of the timer of the control module in the external signal generation circuit can be determined. For example, the time interval between the start time of the second calibration signal and the start time of the timer of the control module in the external signal generation circuit can also be a second predetermined duration.

[0272] Here, the transmission path of the second calibration signal to the signal calibration circuit is determinable (e.g., cables, connectors, selector switches, etc. in the transmission path). Therefore, the transmission delay of the second calibration signal to the analog-to-digital converter in the calibration circuit, to be converted into a second digital signal by the analog-to-digital converter in the calibration circuit, and to reach the calibration circuit control module is determinable.

[0273] Here, the transmission delay of the second calibration signal to the calibration circuit control module (second digital signal arrival control module) can be preset based on the transmission path. This transmission delay includes the preset delay of the analog-to-digital conversion module in the calibration circuit. After determining the sampling delay of the analog-to-digital conversion module in the calibration circuit, the calibration circuit can calibrate the transmission delay. This improves the accuracy of the calibrated transmission delay.

[0274] By determining the arrival time of the second digital signal, the start time of the second calibration signal, and the transmission delay after calibration through the calibration circuit, the delay between the start time of the control module's timer and the start time of the timer associated with the second calibration signal can be determined, thereby achieving synchronization between the control module's timer and the timer associated with the second calibration signal.

[0275] In some embodiments, as shown in FIG19, the signal generation circuit further includes a fan-out module;

[0276] The fan-out module is connected to the low-pass filter and is configured to fan out at least one of the first calibration signals.

[0277] It is understood that the signal generation circuit shown in Figure 19 is only one implementation of the signal generation circuit, and can be replaced by the signal generation circuit in any of the above embodiments if there is no contradiction.

[0278] Here, the fan-out module is configured to copy the signal output by the low-pass filter to obtain multiple first calibration signals.

[0279] In one possible implementation, the fan-out module can adjust the level of the first calibration signal to meet the requirements of the first calibration signal receiver.

[0280] In one possible implementation, the first calibration signal can be received by an external calibration circuit. Here, the external calibration circuit can be implemented as any of the calibration circuits described above that includes an analog-to-digital conversion module. The external calibration circuit can determine the arrival time of the received first calibration signal based on its own timer. Here, the arrival time of the first calibration signal can include the start time when the control module of the external calibration circuit receives the digital signal obtained by converting the first calibration signal.

[0281] In one possible implementation, the first calibration signal is used to calibrate the timer of the control module and the timer of the external calibration circuit that receives the first calibration signal. It is understood that the external calibration circuit can also determine the sampling delay of its analog-to-digital conversion module to calibrate the transmission delay of the first calibration signal when it is transmitted to the external calibration circuit. The calibrated transmission delay, the determined arrival time of the first calibration signal at the external calibration circuit, and the start time of the first calibration signal determined by the control module in the calibration circuit can determine the delay between the start time of the timer of the control module in the calibration circuit that sends the first calibration signal and the start time of the timer of the control module in the external calibration circuit, thereby achieving synchronization of timers between different calibration circuits.

[0282] In one possible implementation, the external calibration circuit may include a calibration circuit belonging to the same signal processing device as the calibration circuit that sends the first calibration signal, and / or a calibration circuit belonging to a different signal processing device than the calibration circuit that sends the first calibration signal.

[0283] This disclosure discloses a signal processing device, as shown in FIG20, which includes at least one calibration circuit as described in any of the above embodiments. The specific implementation of the calibration circuit is as described in any of the above embodiments and will not be repeated here.

[0284] Here, the signal processing device may include multiple calibration circuits, each of which may be the same or different, and are used to perform different functions. For example, as shown in Figure 20, the signal processing device may include a first calibration circuit and a second calibration circuit.

[0285] In some embodiments, as shown in FIG20, the calibration circuit includes a first calibration circuit, wherein the first calibration circuit includes the analog-to-digital conversion module.

[0286] The control module of the first calibration circuit is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer.

[0287] The control module of the first calibration circuit is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

[0288] It is understood that the signal generation circuit in Figure 20, consisting of a control module, a clock module, a frequency divider module, and a low-pass filter, is one implementation of the signal generation circuit. Unless otherwise specified, the signal generation circuit may include the signal generation circuit from any of the above embodiments. That is, in Figure 20, the signal generation circuit in the first calibration circuit and the second calibration circuit may include one of the embodiments shown in Figures 1, 3, 6, or 9.

[0289] Here, the implementation method of determining the sampling delay associated with the analog-to-digital conversion module in the first calibration circuit is similar to that in the above embodiment (as shown in the calibration circuit embodiment disclosed in Figure 12), and will not be repeated here.

[0290] In some embodiments, as shown in FIG20, the signal processing device further includes N channels to be calibrated, wherein the channels to be calibrated are respectively configured to output signals to be calibrated;

[0291] The first calibration circuit includes a selection switch configured to select one of the first calibration signal and at least one signal to be calibrated as input to the analog-to-digital converter module; wherein,

[0292] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated.

[0293] The control module is configured to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated.

[0294] The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the first calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

[0295] Here, N is a positive integer greater than or equal to 1.

[0296] As shown in Figure 20, the channel to be calibrated can be carried on a signal source daughter card. One signal source daughter card can carry one or more channels to be calibrated.

[0297] The implementation methods for the first calibration circuit to determine the arrival time of the digital signal to be calibrated, and the implementation methods for synchronizing the timer of the first calibration circuit and the timer of the channel to be calibrated by the arrival time of the digital signal to be calibrated, are as described in any of the above embodiments, and will not be repeated here.

[0298] In some embodiments, as shown in FIG20, the calibration circuit further includes a second calibration circuit, and the signal generation circuit of the second calibration circuit further includes a fan-out module;

[0299] The fan-out module is connected to the low-pass filter and is configured to fan out at least one first calibration signal from the second calibration circuit.

[0300] Here, the signal processing device may include a first calibration circuit and a second calibration circuit.

[0301] In one possible implementation, the first calibration circuit and the second calibration circuit can be carried on different daughter cards. For example, the first calibration circuit and the second calibration circuit can be carried on different daughter cards of a PXIe architecture signal processing device.

[0302] In one possible implementation, the fan-out module can adjust the level of the first calibration signal to meet the requirements of the first calibration signal receiver.

[0303] In one possible implementation, the first calibration signal may be received by an external calibration circuit. The external calibration circuit may include a calibration circuit belonging to a different signal processing device than the first calibration circuit, and / or the calibration circuit itself.

[0304] Here, the external calibration circuit can be implemented in any of the aforementioned calibration circuits that include an analog-to-digital conversion module. The external calibration circuit can determine the arrival time of the received first calibration signal based on its own timer. Here, the arrival time of the first calibration signal can include the start time when the control module of the external calibration circuit receives the digital signal obtained by converting the first calibration signal.

[0305] In one possible implementation, the first calibration signal is used to calibrate the timer of the control module and the timer of the external calibration circuit that receives the first calibration signal. It is understood that the external calibration circuit can also determine the sampling delay of its analog-to-digital conversion module to calibrate the transmission delay of the first calibration signal when it is transmitted to the external calibration circuit. The calibrated transmission delay, the determined arrival time of the first calibration signal at the external calibration circuit, and the start time of the first calibration signal determined by the control module in the calibration circuit can determine the delay between the start time of the timer of the control module in the calibration circuit that sends the first calibration signal and the start time of the timer of the control module in the external calibration circuit, thereby achieving synchronization of timers between different calibration circuits.

[0306] In some embodiments, the first calibration circuit includes a selection switch configured to select a second calibration signal external to the first calibration circuit as input to the analog-to-digital conversion module; wherein...

[0307] The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal;

[0308] The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

[0309] The implementation method for the first calibration circuit to determine the arrival time of the second digital signal, and the implementation method for determining the delay between the start time of the timer of the control module in the first calibration circuit and the start time of the timer associated with the second calibration signal based on the arrival time of the second digital signal, are as described in any of the above embodiments and will not be repeated here.

[0310] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal of the second calibration circuit.

[0311] As shown in Figure 20, the first calibration signal of the second calibration circuit is used as the input signal of the selection switch of the first calibration circuit as the second calibration signal input to the first calibration circuit. This determines the time delay between the start time of the timer in the first calibration circuit and the start time of the timer in the second calibration circuit, thereby achieving synchronization between the timers in the first and second calibration circuits.

[0312] In some embodiments, the second calibration signal selected by the first calibration circuit includes the first calibration signal sent by an external signal processing device.

[0313] Understandably, the second calibration signal can also be sent by an external signal processing device other than the signal processing device of the first calibration circuit. By using the arrival time of the second digital signal determined by the calibration circuit, the start time of the second calibration signal determined by the external signal processing device, and the transmission delay of the calibrated second calibration signal, the delay between the start time of the control module's timer and the start time of the timer associated with the second calibration signal can be determined, thereby achieving synchronization between the control module's timer and the timer associated with the second calibration signal.

[0314] As shown in Figure 21, the first calibration circuit of the second signal processing device receives the calibration signal from the second calibration circuit of the first signal processing device. The method by which the first calibration circuit of the second signal processing device and the second calibration circuit of the first signal processing device determine the time delay through the calibration signal is similar to the method by which the time delay is determined between calibration circuits within the signal processing device, and will not be described in detail here.

[0315] An embodiment of this disclosure illustrates a signal processing system, as shown in FIG21, which includes at least one signal processing device as described in any of the above embodiments.

[0316] As shown in Figure 21, a signal processing system may include multiple signal processing devices, such as a first signal processing device and a second signal processing device.

[0317] The specific implementation of the signal processing device is as described in any of the above embodiments.

[0318] As can be understood, the signal source sub-card in the second signal processing device in Figure 21 is a simplified block diagram, and its implementation can include the implementation of the signal source sub-card in any of the above embodiments. The signal processing system can have multiple second signal processing devices.

[0319] In one possible implementation, the first signal processing device can act as the master device, and the second signal processing device can act as the auxiliary device. The first signal processing device can send a reference signal to the second signal processing device via an electrical connection to achieve clock frequency synchronization, etc. The first signal processing device can also control the second signal processing device via an electrical connection to perform operations in the synchronization delay determination.

[0320] In a signal processing system, a first signal processing device can synchronize the timer of the first calibration circuit in each signal processing device (including the first signal processing device and the second signal processing device) with the timer of the second calibration circuit in the first signal processing device through a second calibration circuit.

[0321] The signal processing device determines the start time delay of the timer by transmitting a calibration signal, thereby achieving synchronization between timers as described in the above embodiments, and will not be repeated here.

[0322] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0323] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0324] In the description of this specification, references to "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0325] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A calibration circuit, wherein, The calibration circuit includes a signal generation circuit; The signal generation circuit includes: a clock module, a control module, a frequency divider module, and a low-pass filter, wherein, The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is used at least to generate the operating clock signal of the control module and the input clock signal of the frequency divider module. The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal; The first frequency division reset signal is used to control the frequency division module to output the frequency division signal at a time interval of a first predetermined duration between the start time of the frequency division signal and the start time of the timer; A low-pass filter is configured to perform low-pass filtering on the frequency division signal to obtain a first calibration signal, wherein the start time of the first calibration signal is spaced apart from the start time of the timer by a second predetermined time interval. The first calibration signal is used at least for the analog-to-digital conversion module to perform analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between the initial time of the first digital signal and the start time of the timer, wherein the first measurement duration is used at least to determine the transmission delay associated with the first calibration signal.

2. The calibration circuit according to claim 1, wherein, The calibration circuit includes the analog-to-digital conversion module. The control module is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer. The control module is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

3. The calibration circuit according to claim 2, wherein, The calibration circuit includes a selection switch configured to select one of the first calibration signal and N signals to be calibrated as input to the analog-to-digital conversion module; wherein... The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated. The control module is configured to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated. The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

4. The calibration circuit according to claim 2, wherein, The calibration circuit includes a selection switch configured to select a second calibration signal from outside the calibration circuit as input to the analog-to-digital conversion module; wherein... The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal; The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

5. The calibration circuit according to any one of claims 1 to 4, wherein, The signal generation circuit also includes a fan-out module; The fan-out module is connected to the low-pass filter and is configured to fan out at least one of the first calibration signals.

6. The calibration circuit according to claim 1, wherein, The signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay submodule; the frequency division module includes a first frequency divider; The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal; The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module; The signal delay submodule is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The first frequency divider is configured to be triggered by the second frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

7. The calibration circuit according to claim 1, wherein, The signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider; The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal; The second synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal; The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal satisfies the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The second frequency divider is configured to be triggered by the first frequency divider reset signal at the predetermined trigger edge, and to generate the frequency divider signal based on the input clock signal.

8. The calibration circuit according to claim 1, wherein, The first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes a third synchronous reset control module and the counting frequency divider; the working clock is used as the input clock to the counting frequency divider. The third synchronous reset control module is configured to generate a first frequency-divided reset signal based on the working clock signal; The startup time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal; The counting divider is configured to be triggered by the first frequency division reset signal at a predetermined edge, count the operating clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

9. A signal processing device, wherein, The signal processing device includes at least one calibration circuit as described in any one of claims 1 to 7.

10. The signal processing apparatus according to claim 9, wherein, The calibration circuit includes a first calibration circuit, wherein the first calibration circuit includes the analog-to-digital conversion module. The control module of the first calibration circuit is configured to receive the first digital signal and determine a first measurement duration between the initial time of the first digital signal and the start time of the timer. The control module of the first calibration circuit is configured to determine the sampling delay associated with the analog-to-digital conversion module based at least on the second predetermined duration and the first measurement duration.

11. The signal processing apparatus according to claim 10, wherein, The signal processing device further includes N channels to be calibrated, wherein each channel to be calibrated is configured to output a signal to be calibrated; The first calibration circuit includes a selection switch configured to select one of the first calibration signal and at least one signal to be calibrated as input to the analog-to-digital converter module; wherein, The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the selected signal to be calibrated to obtain a digital signal to be calibrated. The control module is configured to receive the digital signal to be calibrated and determine the arrival time of the digital signal to be calibrated. The arrival time of the digital signal to be calibrated, the sampling delay, and the predetermined signal transmission delay of the channel to be calibrated corresponding to the selected signal to be calibrated are used to synchronize the timer of the first calibration circuit and the timer of the channel to be calibrated corresponding to the selected signal to be calibrated, wherein the signal to be calibrated is output from the channel to be calibrated.

12. The signal processing apparatus according to claim 11, wherein, The first calibration circuit includes a selection switch configured to select a second calibration signal external to the first calibration circuit as input to the analog-to-digital conversion module; wherein... The analog-to-digital conversion module is configured to perform analog-to-digital conversion on the second calibration signal to obtain a second digital signal; The control module is configured to receive the second digital signal and determine the arrival time of the second digital signal, wherein the arrival time of the second digital signal is used to determine the time delay between the start time of the timer of the control module and the start time of the timer associated with the second calibration signal.

13. The signal processing apparatus according to any one of claims 9 to 12, wherein, The calibration circuit further includes a second calibration circuit, and the signal generation circuit of the second calibration circuit further includes a fan-out module. The fan-out module is connected to the low-pass filter and is configured to fan out at least one first calibration signal from the second calibration circuit.

14. The signal processing apparatus according to claim 13, wherein, The second calibration signal selected by the first calibration circuit includes the first calibration signal of the second calibration circuit.

15. The signal processing apparatus according to claim 12, wherein, The second calibration signal selected by the first calibration circuit includes the first calibration signal sent by an external signal processing device.

16. A signal processing system, wherein, The signal processing system includes at least one signal processing device as described in any one of claims 9 to 15.

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