Memory fault location method and related apparatus

Abstract

A memory fault location method and a related apparatus, which relate to the technical field of computers. The memory fault location method may comprise: when reading data from a memory, determining, with respect to a memory error, a location where a fault occurs in the memory, wherein the location where the fault occurs in the memory comprises some or all of the following: a faulty dual in-line memory module, a faulty memory rank, a faulty memory chip, a faulty memory bank, a faulty memory cell, a faulty row in a memory bank, a faulty column in a memory bank, a faulty bit, a faulty data input / output channel, a faulty burst or a faulty sub-channel. In the memory fault location method provided in the embodiments of the present application, fault location can be performed at multiple granularities, so as to accurately locate a location where a fault occurs in a memory, thereby facilitating the rapid repair of memory faults.

Description

A method and related apparatus for locating memory faults

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510114702.0, filed on January 23, 2025, with the State Intellectual Property Office of the People's Republic of China, entitled "A Memory Fault Location Method and Related Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a method and apparatus for locating memory faults. Background Technology

[0004] Memory, also known as random access memory (RAM), is internal storage that directly exchanges data with the central processing unit (CPU). It typically serves as temporary data storage for the operating system or other running programs. When memory is active, information can be written to or read from any specified memory address at any time.

[0005] As memory architecture has evolved, in order to fit more storage cells into the same area of ​​silicon wafer and achieve faster read and write speeds, memory manufacturing processes have become smaller and operating frequencies have become higher. To control heat generation, operating voltages have been forced to continuously decrease, leading to a continuous decline in memory reliability and an increasing failure rate. Currently, memory failure has become one of the most common sources of failure in computing devices. When memory fails, it affects the stable operation of services, and in severe cases, it can cause abnormal restarts or system crashes of computing devices.

[0006] Accurately locating memory faults is a problem that urgently needs to be solved. Summary of the Invention

[0007] This application provides a memory fault location method and related apparatus, which can accurately locate memory faults.

[0008] In a first aspect, embodiments of this application provide a memory fault location method, which can be executed by a computing device, or a chip, chip system, or circuit within the computing device. The method may include: when reading data from memory, determining the location of the fault in the memory in response to a memory error; the location of the fault in the memory includes some or all of the following: a faulty memory module (Dimm), a faulty memory column (Rank), a faulty memory chip (Chip), a faulty storage array (Bank), a faulty storage cell (Cell), a faulty row in the storage array, a faulty column in the storage array, a faulty bit, a faulty input / output channel (DQ), a faulty read unit (burst), or a faulty subchannel.

[0009] The memory fault location method provided in this application can locate memory errors at multiple granularities such as Dimm, Rank, Chip, Bank, Cell, Row, bit, Column, DQ, burst, and subchannel, accurately pinpointing the location of the fault in the memory, which is beneficial for quickly repairing memory faults.

[0010] In one possible implementation, the computing device can also generate and save memory fault information based on the location of the fault in memory. This memory fault information can help maintenance personnel quickly grasp relevant information about the memory fault, which is beneficial for repairing the memory fault.

[0011] In one possible implementation, for a correctable error (CE) or an uncorrectable error (UCE) occurring in memory, the computing device can acquire raw data and expected data; by comparing the raw data with the expected data, the location of the fault in memory can be determined. Here, the raw data is data read from memory, and the expected data is data obtained by correcting the raw data.

[0012] In one possible implementation, for a UCE occurring in the memory, the computing device can determine the location of the fault in the memory by writing test data into the memory multiple times.

[0013] In one possible implementation, the computing device can compare the original data with the expected data, determine the difference bits, and based on the difference bits, determine the location of the fault in the memory.

[0014] In one possible implementation, the location of the memory failure includes the faulty memory module, subchannel, memory column, storage array, faulty row in the storage array, and faulty column in the storage array. The computing device can determine the faulty memory module, subchannel, memory column, storage array, faulty row in the storage array, and faulty column in the storage array based on the interrupt status of the memory controller and the error information recorded in the error address register.

[0015] Secondly, embodiments of this application provide a memory fault location device, which can be applied to a computing device. The memory fault location device may include:

[0016] The data reading module is used to read data from memory;

[0017] The data analysis module is used to determine the location of the fault in memory in response to memory errors. The location of the fault in memory includes some or all of the following: the faulty memory module (Dimm), the faulty memory column (Rank), the faulty memory chip (Chip), the faulty storage array (Bank), the faulty storage cell (Cell), the faulty row in the storage array, the faulty column in the storage array, the faulty bit, the faulty input / output channel (DQ), the faulty read unit (burst), or the faulty subchannel.

[0018] In one possible implementation, the data analysis module can also be used for:

[0019] Memory fault information is generated and saved based on the location of the fault in memory.

[0020] In one possible implementation, the data analysis module can specifically be used for:

[0021] For correctable errors (CE) or uncorrectable errors (UCE) occurring in memory, obtain the original data and the expected data; the original data is the data read from memory, and the expected data is the data obtained by correcting the original data.

[0022] By comparing the raw data with the expected data, the location of the fault in the memory can be determined.

[0023] In one possible implementation, the data analysis module can specifically be used for:

[0024] For uncorrectable errors (UCEs) occurring in memory, the location of the fault in the memory is determined by writing test data into the memory multiple times.

[0025] In one possible implementation, the data analysis module can be used to: compare the raw data with the expected data to determine the difference bits; and based on the difference bits, determine the location of the fault in memory.

[0026] In one possible implementation, the locations of memory failures include the faulty memory module, subchannel, memory column, storage array, faulty row in the storage array, and faulty column in the storage array; the data analysis module can specifically be used for:

[0027] Based on the interrupt status of the memory controller and the error information recorded in the error address register, the faulty memory module, subchannel, memory column, storage array, faulty row in the storage array, and faulty column in the storage array are determined.

[0028] Thirdly, embodiments of this application provide a chip including a processor and a power supply circuit; the power supply circuit is used to supply power to the processor, and the processor is used to execute a computer program to implement any of the memory fault location methods provided in the first aspect above.

[0029] Fourthly, embodiments of this application provide a computing device, which includes memory and a chip provided by a third aspect.

[0030] Fifthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which are used to cause a computer to execute any of the memory fault location methods provided in the first aspect above.

[0031] Sixthly, embodiments of this application provide a computer program product comprising computer-executable instructions, the computer-executable instructions being used to cause a computer to execute any of the memory fault location methods provided in the first aspect above.

[0032] The technical effects that can be achieved by any of the second to sixth aspects mentioned above can be referred to the description of the beneficial effects in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0033] Figure 1 is a schematic diagram of the structure of a computing device provided in an embodiment of this application;

[0034] Figure 2 is a schematic diagram of a memory structure provided in an embodiment of this application;

[0035] Figure 3 is a flowchart of a memory fault location method provided in an embodiment of this application;

[0036] Figure 4 is a schematic diagram of reading data according to an embodiment of this application;

[0037] Figure 5 is a schematic diagram of another data reading method provided in an embodiment of this application;

[0038] Figure 6 is an interactive diagram of a memory fault location method provided in an embodiment of this application;

[0039] Figure 7 is a schematic diagram of an error correction process provided in an embodiment of this application;

[0040] Figure 8 is an interaction diagram of another memory fault location method provided in an embodiment of this application;

[0041] Figure 9 is an interaction diagram of another memory fault location method provided in an embodiment of this application;

[0042] Figure 10 is a schematic diagram of a memory fault location device provided in an embodiment of this application;

[0043] Figure 11 is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments of this application and is not intended to limit this application.

[0045] Before introducing the specific solutions provided in the embodiments of this application, some terms used in this application will be explained to facilitate understanding by those skilled in the art, but the terms used in this application are not limited.

[0046] (1) Error Checking and Correcting (ECC) Algorithm: The memory inside the computing device has a certain error detection and correction capability, which can correct errors in the data in memory to a certain extent. When the memory controller needs to write data into memory, it calls the ECC algorithm to generate a checksum for the data. The memory controller then writes the data and the checksum into memory. The ECC algorithm does not refer to a specific algorithm, but rather to a class of algorithms that can implement ECC.

[0047] (2) Correctable error (CE): When the memory controller reads data under the instruction of the processor, in addition to reading the data from memory, the memory controller also reads the checksum of the data from memory, calls the ECC algorithm to verify the read data based on the checksum, and determines whether there is an error in the data. If the read data contains an error, the memory controller will use the checksum to correct the error; if the correction is successful, the corrected data will be fed back to the processor. This type of error that can be corrected by the memory controller is called a correctable error.

[0048] (3) Uncorrectable Error (UCE): The larger the data volume of the checksum, the stronger its error correction capability. A strong error-correcting code can correct a large number of erroneous data points. Considering the limited storage space within memory, in practical applications, checksums cannot occupy a large amount of storage space; they must be concentrated in a small number of memory chips. This limits the ECC capability of the memory itself. Therefore, there will always be some errors that the memory controller cannot correct; these errors are called uncorrectable errors.

[0049] In this application embodiment, "multiple" refers to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0050] Unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the order, sequence, priority or importance of multiple objects.

[0051] The memory fault location method provided in this application embodiment can be applied to the computing device shown in FIG1. ​​This computing device can be a computer or a server, such as a general-purpose computing server, a general-purpose storage server, or a data center server. As shown in FIG1, the hardware of the computing device 100 may include a processor 110, memory 120, a baseboard management controller (BMC) 130, and a power module 140. The power module 140 can supply power to the processor 110, memory 120, and baseboard management controller 130. The power module 140, processor 110, memory 120, and baseboard management controller 130 can be connected via a bus.

[0052] The processor 110 is the core of computing and control in the computing device 100. The processor 110 may include a central processing unit (CPU) 111, a microcontroller unit (MCU) 112, and a memory controller 113, etc. The CPU 111 can access the memory 120 through the memory controller 113. The processor 110 is mounted on the motherboard.

[0053] The baseboard management controller 130 is an off-band, independent management chip and a server management component. It can be integrated into the motherboard of the computing device 100 or connected to the motherboard as a separate management module. It can perform firmware upgrades, manage the operating status of the computing device 100, and troubleshoot faults even when the computing device 100 is not powered on. The baseboard management controller 130 can maintain the program code in the memory 120 of the computing device 100, including upgrading or restoring it. The baseboard management controller 130 can also control the power supply circuits or clock circuits within the computing device 100.

[0054] The software portion of the computing device 100 may include an operating system, which is divided into kernel mode and user mode. The kernel mode supports the operation of hardware drivers such as display drivers, camera drivers, audio drivers, and sensor drivers. The user mode supports the operation of third-party applications installed on the computing device 100, as well as the operation of business functions.

[0055] The computing device 100 may also include firmware. For example, the processor 110 may have multiple processor cores, including a main processor and a coprocessor. The firmware in the computing device 100 may include main processor firmware and coprocessor firmware, and may also include a basic input / output system (BIOS). The BIOS is firmware that performs hardware initialization during the power-on startup phase and provides runtime services to the operating system. The BIOS is usually stored on a flash memory chip for easy updates.

[0056] Memory 120 refers to the internal memory that directly exchanges data with processor 110, and can also be called a memory module. Processor 110 can read and write data to memory at any time, and at a very high speed, serving as temporary data storage for the operating system or other running applications running on the processor. Memory 120 may include volatile memory, such as random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR-SDRAM), etc., and may also include non-volatile memory, such as storage class memory (SCM), or a combination of volatile and non-volatile memory. DRAM is a semiconductor memory, and like most RAM, it is a type of volatile memory device. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard drives, but its access speed is slower than DRAM, and it is also cheaper than DRAM. DRAM, SDRAM, DDR-SDRAM, and SCM are merely illustrative examples in this embodiment. Memory 120 may also include other random access memories, such as read-only memories, for example, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), etc. Additionally, memory 120 may also be a dual in-line memory module (DIMM), i.e., a module composed of DRAM.

[0057] There can be one or more memory modules 120, and multiple memory modules 120 can be memory modules of different types. This application embodiment does not limit the number or type of memory in a node. Furthermore, the user can configure the memory to have a power-saving function. A power-saving function means that when the system experiences a power outage and is then powered on again, the data stored in the memory will not be lost. Memory with a power-saving function is called non-volatile memory.

[0058] In some embodiments, as shown in FIG2, memory 120 may include multiple memory modules (Dimm), which can be inserted into slots on the motherboard. Each memory module may include two or more memory rows (Ranks). FIG2 only illustrates memory module 1 as an example. Each Rank includes multiple memory chips (Chip or DRAM device), and each memory chip includes multiple memory banks. Each memory bank may include multiple memory cells. Exemplarily, each memory bank may include multiple rows of memory cells and multiple columns of memory cells. The position where any row intersects any column is called a memory cell. In some embodiments, each memory bank may have 4 input / output channels, i.e., data quality (DQ); in other embodiments, each memory bank may have 8 input / output channels; in other embodiments, each memory bank may have 16 input / output channels; and in other embodiments, each memory bank may have 64 input / output channels.

[0059] In other embodiments, the memory 120 may also be mounted on the motherboard or packaged inside the processor 110. The memory 120 may include multiple Ranks, each Rank may include multiple Chips, each Chip may include multiple Banks, and each Bank may include multiple Cells.

[0060] Memory 120 serves as a temporary data storage medium for the operating system or other running programs. When Memory 120 is operational, information can be written to or read from any specified memory address at any time. A failure in Memory 120 can impact the stable operation of services, and in severe cases, may cause the computing device to restart abnormally or crash.

[0061] Based on this, embodiments of this application provide a memory fault location method. This method may include: when reading data from memory, determining the location of the fault in the memory in response to a memory error. The location of the fault in the memory may include some or all of the following: a faulty memory module, a faulty memory column, a faulty memory chip, a faulty storage array, a faulty storage cell, a faulty row in the storage array, a faulty column in the storage array, a faulty bit, a faulty input / output channel, a faulty read unit, or a faulty sub-channel. Embodiments of this application can perform fault location at multiple granularities, accurately pinpointing the location of the fault in the memory, which is beneficial for rapid memory fault repair.

[0062] Figure 3 illustrates a flowchart of a memory fault location method provided in an embodiment of this application. This memory fault location method can be executed by the computing device 100 shown in Figure 1. As shown in Figure 3, the memory fault location method may include the following steps:

[0063] S301 reads data from memory.

[0064] During the operation of a computing device, or during a memory fault test, the computing device accesses memory and reads data from it. For example, when reading data from memory, the computing device can read one cache line of data at a time. One cache line can include 64 bytes of data and may also include 8 bytes of parity data.

[0065] A cacheline can be divided into 8 or 16 bursts, reading a total of 64 bytes of data from multiple memory chips in parallel. For example, in some embodiments, a computing device may read data from a cacheline from memory from 8 memory chips, reading 64 bits of data from each chip, for a total of 64 bytes of data. In other embodiments, a computing device may read data from memory from memory from 16 memory chips, reading 32 bits of data from each chip, for a total of 64 bytes of data. The original data contains the aforementioned 64 bytes of data.

[0066] For DDR5 memory, it provides two sub-channels, such as sub-channel 0 and sub-channel 1. For example, as shown in Figure 4, when reading data from memory at one time, 16 bursts of data (one cache line) can be read from eight consecutive memory chips through sub-channel 0, and parity data can also be read from the parity chip. Each bit of data has a corresponding storage unit and DQ information. For DDR4 memory, as shown in Figure 5, when reading data from memory at one time, eight bursts of data (one cache line) can be read from 16 consecutive memory chips, and parity data can also be read from the parity chip.

[0067] S302, for memory errors, determines the location of the fault in the memory.

[0068] During the process of reading data from memory, it is checked whether errors have occurred in the read data. If an error is found, the location of the fault in memory is determined for the memory error. The location of the fault in memory includes one or more of the following: the faulty memory module, the faulty Rank, the faulty memory chip, the faulty storage array, the faulty row in the storage array, the faulty column in the storage array, the faulty storage cell, the faulty bit, the faulty input / output channel, the faulty burst, or the faulty subchannel.

[0069] For example, in response to a faulty memory operation (CE) in memory, a computing device can acquire raw data and expected data. The raw data is data read from memory, and the expected data is data obtained by correcting the raw data. If the raw data includes 64 bytes of data, the expected data also includes 64 bytes of data. Any bit in the expected data has a corresponding bit in the raw data. By comparing the raw data and the expected data, the computing device can determine the location of the fault in memory. The location of the fault in memory can include the faulty memory chip, the faulty storage unit, the faulty bit, the faulty input / output channel, and the faulty burst unit. Based on the interrupt status of the memory controller and the error information recorded in the error address register, the computing device can determine the faulty memory module, the faulty subchannel, the faulty memory column, the faulty storage array, the faulty row in the storage array, and the faulty column in the storage array.

[0070] In some embodiments, for a UCE occurring in memory, the computing device can acquire raw data and expected data; wherein the raw data is data read from memory, and the expected data is data obtained by correcting the raw data. By comparing the raw data with the expected data, the computing device can determine the location of the fault in memory, which may include the faulty memory chip, the faulty storage unit, the faulty bit, the faulty input / output channel, and the faulty burst unit. In other embodiments, for a UCE occurring in memory, the computing device can determine the location of the fault in memory by writing test data to memory multiple times, which may include the faulty memory chip, the faulty storage unit, the faulty bit, the faulty input / output channel, and the faulty burst unit. The computing device can determine the faulty memory module, the faulty subchannel, the faulty memory column, the faulty storage array, the faulty row in the storage array, and the faulty column in the storage array based on the interrupt status of the memory controller and the error information recorded in the error address register in the memory controller.

[0071] S303 generates and saves memory fault information based on the location of the fault in memory.

[0072] Computing devices can store memory fault information, which includes the location of the fault in the memory. This allows for precise location of memory faults and can be used to locate poor contact in memory DQ or predict memory faults, thus facilitating accurate memory repair.

[0073] The following descriptions focus on CE and UCE respectively. Figure 6 shows an interaction diagram between the components of the computing device during a fault location process for CE. As shown in Figure 6, the process may include the following steps:

[0074] S601, the memory controller successfully corrected the CE error and recorded the original data before the error correction and the expected data after the error correction.

[0075] The memory controller is a hardware device located between the processor core and the bus connecting the cache and memory. The memory controller is often considered part of the processor, in which case the operations performed by the memory controller can be considered operations performed by the processor. The memory controller can also be a separate hardware device; in this embodiment, we will use a separate hardware device as an example. The memory controller is primarily used to handle access requests initiated by the processor to memory and to read data from memory according to these requests.

[0076] During the operation of a computing device, or during a memory fault test, the central processing unit of the computing device can read data from memory through the memory controller, reading one cacheline (64 bytes) of data at a time.

[0077] The data read from memory can also include checksum data. The memory controller can use this checksum data and an ECC error correction algorithm to determine if the read data is error-free. If the ECC error correction algorithm determines that the original data is error-free, the memory controller can then confirm that the read data is correct.

[0078] If an error is detected in the original data based on the ECC error correction algorithm, for example, a cacheline includes 64 bytes of data. The ECC error correction algorithm performs error detection and correction in units of half a cacheline, that is, in units of 32 bytes. For DDR4 memory, as shown in Figure 7, data is read from 16 memory chips DRAM0 to DRAM15. Each memory chip needs to provide 16 bits of data for 32 bytes. The 32 bytes of data are divided into 16 groups, so that each of the 16 groups contains only 1 bit of data from one memory chip. In other words, the 16 bits of data provided by each of the 16 memory chips are evenly distributed among the 16 groups. Each of the 16 groups also contains check data: a cyclic redundancy check (CRC) code and a parity check (PTY) bit. The CRC code and PTR of each group of check data are used to check the 16-bit data of the group. For the group of data with parity error, the bits are flipped sequentially starting from DRAM0, and the CRC of the flipped data is calculated. If the calculated CRC does not match the CRC code contained in the group of data, the next bit is flipped. If the calculated CRC matches the CRC code contained in the group of data, the error correction is successful.

[0079] Through the above process, single-chip errors (CEs) can be corrected, and the specific memory chip causing the error can be identified. The memory controller can divide the data in a cache line into two 32-byte segments. After executing the above process twice, the CE in the data can be successfully corrected. Upon successful CE correction, the memory controller can record the original data before correction and the expected data after correction.

[0080] S602, the memory controller sends an interrupt notification to the BIOS.

[0081] After the memory controller successfully corrects a CE error, it can send an interrupt notification to the BIOS. In some embodiments, for DDR5, the interrupt notification carries information about the sub-channel that reported the interrupt.

[0082] S603, the BIOS responds to the interrupt notification, reads the original data before error correction and the expected data after error correction, and generates error information.

[0083] The error message contains the original data before correction and the expected data after correction.

[0084] In some embodiments, the BIOS may also record the interrupt status of the memory controller in a register based on information from the sub-channel that reported the interrupt notification. The register is a memory in the processor used to temporarily store instructions, data, status, and addresses. The interrupt status of the memory controller indicates the faulty sub-channel; for example, an interrupt status of "01" indicates that the faulty sub-channel is sub-channel 1; an interrupt status of "10" indicates that the faulty sub-channel is sub-channel 0. The error message may also include the interrupt status of the memory controller and the error information recorded in the error address register. When a memory error occurs, corresponding error information is recorded in the error address register, indicating the faulty memory module, sub-channel, memory column, memory array, faulty row in the memory array, and faulty column in the memory array, etc.

[0085] S604, the BIOS sends an error message to the BMC.

[0086] S605, BMC compares the raw data with the expected data to determine the location of the fault in memory.

[0087] The BIOS sends error information to the BMC. The BMC retrieves the original and expected data from the received error information, compares them, and records the location of the differing bit. This allows it to determine the burst in the cacheline to which the differing bit belongs. Based on the cacheline data distribution shown in Figure 4 and a reference record format of the differing bit location, the BMC can determine the memory cell to which the differing bit belongs, the memory chip to which that memory cell belongs, and the input / output channel corresponding to the differing bit. Therefore, it can identify the faulty memory chip, the faulty memory cell, the faulty bit, the faulty input / output channel, and the faulty burst.

[0088] In some embodiments, the error message may also include the interrupt status of the memory controller and the error information recorded in the error address register. The BMC may also determine the faulty subchannel, the faulty memory module, the faulty memory column, the faulty storage array, the faulty row in the storage array, and the faulty column in the storage array based on the error information recorded in the interrupt status error address register of the memory controller.

[0089] S606, BMC generates and saves memory fault information based on the location of the fault in memory.

[0090] BMC can save the generated memory fault information to the log.

[0091] In the above embodiments, the step of determining the location of the memory fault is performed by the BMC in the computing device. In other embodiments, the step of determining the location of the memory fault may also be performed by the BIOS or other execution entities. If performed by the BIOS or other execution entities, the BIOS or other execution entities can transmit the fault location information to the BMC for recording.

[0092] Figure 8 illustrates the interaction between components of a computing device during a fault location process for UCE. In some embodiments, as shown in Figure 8, the process may include the following steps:

[0093] S801, memory controller failed to correct UCE error.

[0094] During memory fault testing, the central processing unit of the computing device can read data from memory through the memory controller, reading one cache line (64 bytes) of data at a time.

[0095] The data read from memory can also include checksum data. The memory controller can use the checksum data and an ECC error correction algorithm to determine if the read data contains errors. If the ECC error correction algorithm determines that the original data is error-free, the memory controller can confirm that the read data is correct. If the ECC error correction algorithm determines that the original data contains errors, but the correct data after error correction cannot be obtained (i.e., correction cannot be achieved), the memory controller can record the original data before error correction if UCC error correction fails.

[0096] S802, the memory controller sends an interrupt notification to the BIOS.

[0097] When the memory controller fails to correct a UCE error, it can send an interrupt notification to the BIOS. In some embodiments, for DDR5, the interrupt notification carries information about the sub-channel that reported the interrupt.

[0098] S803, the BIOS sends an error location request to the microprocessor.

[0099] The BIOS responds to the interrupt notification by sending an error location request to the microprocessor. The BIOS can also disable error correction and verification for the faulty memory path.

[0100] The S804 microprocessor determines the location result based on the error location request.

[0101] The microprocessor can randomly generate test data. For example, it can generate test data like 0x5555 5555 AAAA AAAA 5555 5555 AAAA AAAA 5555 5555 AAAA AAAA 5555 5555 AAAA AAAA 5555 5555 AAAA AAAA. The test data is written to the fault address through the memory controller. The fault address is the memory address that stores the original data. The memory controller then reads the test data from memory and compares the read data with the generated test data to determine the faulty bit, thus obtaining the location result.

[0102] To avoid positioning errors, the microprocessor can generate different test data and repeat the above process multiple times, using at least two consistent results as the positioning result.

[0103] S805, the microprocessor sends the location result to the BIOS.

[0104] S806, the BIOS determines the error message based on the location results.

[0105] The location results include the faulty bit, the faulty memory chip, the faulty storage unit, the faulty input / output channel, and the faulty read unit burst. The error message includes the faulty memory chip, the faulty storage unit, the faulty bit, the faulty input / output channel, and the faulty read unit burst.

[0106] In some embodiments, the BIOS may also record the memory controller's interrupt status in a register based on information from the sub-channel that reported the interrupt notification. The register is a memory in the processor used to temporarily store instructions, data, status, and addresses. The memory controller's interrupt status indicates the faulty sub-channel; for example, an interrupt status of "01" indicates that sub-channel 1 has failed, and an interrupt status of "10" indicates that sub-channel 0 has failed. The error message may also include the memory controller's interrupt status and the error information recorded in the error address register, which may be obtained by the BIOS in response to the interrupt notification.

[0107] S807, the BIOS sends an error message to the BMC.

[0108] The S808 BMC determines the location of the fault in memory based on the error information.

[0109] The BIOS sends error information to the BMC. This error information includes the faulty memory chip, the faulty memory cell, the faulty bit, the faulty input / output channel, and the faulty burst. The error information may also include the memory controller's interrupt status and error information recorded in the error address register. Based on the error information recorded in the memory controller's interrupt status and error address register, the BMC can determine the faulty memory module, the faulty subchannel, the faulty memory column, the faulty memory array, the faulty row within the memory array, and the faulty column within the memory array. Therefore, based on the error information, the BMC can determine the faulty memory module, the faulty Rank, the faulty memory chip, the faulty memory array, the faulty row within the memory array, the faulty column within the memory array, the faulty subchannel, the faulty memory cell, the faulty bit, the faulty input / output channel, and the faulty burst.

[0110] S809, BMC generates and saves memory fault information based on the location of the fault in memory.

[0111] BMC can save the generated memory fault information to the log.

[0112] In the above embodiments, the step of determining the location of the memory fault is performed by the BMC in the computing device. In other embodiments, the step of determining the location of the memory fault may also be performed by the BIOS or other execution entities. If performed by the BIOS or other execution entities, the BIOS or other execution entities can transmit the fault location information to the BMC for recording.

[0113] In the above embodiments, the error location step is executed by the microprocessor in the computing device. In other embodiments, the error location step may also be executed by the BIOS, memory controller, or other execution entities; this application does not limit this approach.

[0114] Figure 9 illustrates the interaction diagram between the components of a computing device during a fault location process for UCE. In some embodiments, as shown in Figure 9, the process may include the following steps:

[0115] S901, the memory controller, records the original data before error correction when UCE error correction fails.

[0116] During memory fault testing, the central processing unit of the computing device can read data from memory through the memory controller, reading one cache line (64 bytes) of data at a time.

[0117] The data read from memory can also include checksum data. The memory controller can use the checksum data and an ECC error correction algorithm to determine if the read data contains errors. If the ECC error correction algorithm determines that the original data is error-free, the memory controller can confirm that the read data is correct. If the ECC error correction algorithm determines that the original data contains errors, but the correct data after error correction cannot be obtained (i.e., correction cannot be achieved), the memory controller can record the original data before error correction if UCC error correction fails.

[0118] S902, the memory controller sends an interrupt notification to the BIOS.

[0119] When the memory controller fails to correct a UCE error, it can send an interrupt notification to the BIOS. In some embodiments, for DDR5, the interrupt notification carries information about the sub-channel that reported the interrupt.

[0120] S903, BIOS responds to interrupt notification and reads the original data before error correction.

[0121] S904, the BIOS sends an error correction request to the microprocessor.

[0122] The error correction request may include the original data before the error correction or the storage address information of the original data.

[0123] The S905 microprocessor corrects the original data before correction based on the error correction request, and obtains the expected data after correction.

[0124] The microprocessor can obtain the original data in the error correction request, or obtain the original data based on the storage address information of the original data in the error correction request, perform secondary error correction on the original data, and obtain the expected data after error correction.

[0125] S906, the microprocessor sends the desired data to the BIOS.

[0126] S907, the BIOS generates an error message containing both the raw data and the expected data.

[0127] After receiving the expected data sent by the microprocessor, the BIOS can generate error messages for both the original data and the expected data.

[0128] In some embodiments, the BIOS may also record the memory controller's interrupt status in a register based on information from the sub-channel that reported the interrupt notification. The register is a memory in the processor used to temporarily store instructions, data, status, and addresses. The memory controller's interrupt status indicates the faulty sub-channel; for example, an interrupt status of "01" indicates that sub-channel 1 has failed, and an interrupt status of "10" indicates that sub-channel 0 has failed. The error message may also include the memory controller's interrupt status and the error information recorded in the error address register. When a memory error occurs, corresponding error information is recorded in the error address register, indicating the faulty memory module, sub-channel, memory column, memory array, faulty row in the memory array, and faulty column in the memory array.

[0129] S908, the BIOS sends an error message to the BMC.

[0130] In this embodiment, after the microprocessor determines the expected data, it sends the expected data to the BIOS, and the BIOS then sends error information to the BMC. In other embodiments, after the microprocessor determines the expected data, it can also generate error information containing the original data and the expected data, and send the error information to the BMC. In still other embodiments, the BIOS can perform a secondary error correction step on the original data to obtain the corrected expected data, and generate error information based on the original data and the expected data, and send the error information to the BMC. This application does not limit the execution entity for determining the expected data or the execution entity for sending the error information to the BMC.

[0131] S909, BMC compares the raw data with the expected data to determine the location of the fault in memory.

[0132] The BIOS sends error information to the BMC. The BMC retrieves the original and expected data from the received error information, compares them, and records the location of the differing bit. This allows it to determine the burst in the cacheline to which the differing bit belongs. Based on the cacheline data distribution shown in Figure 4 and a reference record format of the differing bit location, the BMC can determine the memory cell to which the differing bit belongs, the memory chip to which that memory cell belongs, and the input / output channel corresponding to the differing bit. Therefore, it can identify the faulty memory chip, the faulty memory cell, the faulty bit, the faulty input / output channel, and the faulty burst.

[0133] In some embodiments, the error message may also include the interrupt status of the memory controller and the error information recorded in the error address register. The BMC may also determine the faulty subchannel, the faulty memory module, the faulty memory column, the faulty storage array, the faulty row in the storage array, and the faulty column in the storage array based on the error information recorded in the interrupt status error address register of the memory controller.

[0134] S910, BMC generates and saves memory fault information based on the location of the fault in memory.

[0135] BMC can save the generated memory fault information to the log.

[0136] In the above embodiments, the step of determining the location of the memory fault is performed by the BMC in the computing device. In other embodiments, the step of determining the location of the memory fault may also be performed by the BIOS or other execution entities. If performed by the BIOS or other execution entities, the BIOS or other execution entities can transmit the fault location information to the BMC for recording.

[0137] This application's embodiments address memory errors and can identify one or more of the following: faulty memory module, faulty memory column, faulty memory chip, faulty storage array, faulty row in the storage array, faulty column in the storage array, faulty storage cell, faulty bit, faulty input / output channel, faulty cacheline, faulty burst, or faulty subchannel. The fault localization is more granular, allowing identification of whether an error occurred in each bit within each cacheline, and pinpointing the specific subchannel, memory chip, burst, DQ, and storage cell where the error occurred. For cachelines and bursts, fault features can be extracted in the time dimension; for faulty memory modules, columns, chips, storage arrays, rows, columns, cells, and bits, features can be extracted in the spatial dimension. Furthermore, it allows for more precise determination of whether a DQ contact failure is the cause. Memory fault information generated from faulty input / output channels is beneficial for supporting accurate fault localization and prediction.

[0138] In some embodiments, if CE and UCE are present in the original data, memory fault location can be performed according to the fault location process for UCE, and the memory fault information can be saved. Saving memory fault information is crucial for monitoring the health status of memory modules, allowing for early identification of faulty memory and fault repair, thus reducing the risk of system downtime.

[0139] Based on the same design concept as the above-described method embodiments, this application also provides a memory fault location device. This memory fault location device can be applied to the computing device shown in FIG1, and can be disposed in the processor or the baseboard management controller of the computing device. Alternatively, a portion of the memory fault location device modules can be disposed in the processor of the computing device, and another portion of the modules can be disposed in the baseboard management controller of the computing device. This memory fault location device can be used to implement the functions of the above-described method embodiments, and therefore can achieve the beneficial effects possessed by the above-described method embodiments. As shown in FIG10, the memory fault location device 1000 may include a data reading module 1001 and a data analysis module 1002.

[0140] The data reading module 1001 can be used to read data from memory;

[0141] The data analysis module 1002 can be used to determine the location of the fault in memory in response to memory errors. The location of the fault in memory includes some or all of the following: the faulty memory module Dimm, the faulty memory column Rank, the faulty memory chip Chip, the faulty storage array Bank, the faulty row in the storage array, the faulty column in the storage array, the faulty storage cell, the faulty bit, the faulty input / output channel DQ, the faulty read unit burst, or the faulty subchannel.

[0142] Both the data reading module 1001 and the data analysis module 1002 can be implemented in software or hardware. For example, the implementation of the data analysis module 1002 will be described below. Similarly, the implementation of the data reading module 1001 can refer to the implementation of the data analysis module 1002.

[0143] As an example of a software functional module, the data analysis module 1002 may include code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, or a container. Furthermore, the aforementioned computing instance may be one or more. For example, the data analysis module 1002 may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ including one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0144] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0145] As an example of a hardware functional unit, the data analysis module 1002 may include at least one computing device, such as a server. Alternatively, the data analysis module 1002 may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0146] The data analysis module 1002 includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the multiple computing devices included in the data analysis module 1002 can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the multiple computing devices included in the data analysis module 1002 can be distributed within the same Virtual Private Cloud (VPC) or in multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0147] It should be noted that, in some embodiments, the data reading module 1001 can be used to execute any step in the service operation method, and the data analysis module 1002 can also be used to execute any step in the memory fault location method. The steps implemented by the data reading module 1001 and the data analysis module 1002 can be specified as needed. The data reading module 1001 and the data analysis module 1002 respectively implement different steps in the memory fault location method to achieve all the functions of the memory fault location device. The memory fault location device 1000 can also employ more or fewer functional modules to implement its functions.

[0148] This application also provides a chip, which may be the substrate management controller or processor chip shown in FIG1. ​​This chip can be used to implement the functions of the above method embodiments, and therefore can achieve the beneficial effects of the above method embodiments.

[0149] In some embodiments, the structure of the chip 1100 can be as shown in FIG11, including a processor 1101 and a power supply circuit 1102 connected to the processor 1101. The processor 1101 and the power supply circuit 1102 can be interconnected via a bus. The processor 1101 can be a digital signal processor (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or other specific integrated circuits. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The power supply circuit 1102 is used to supply power to the processor 1101 through the bus.

[0150] The processor 1101 can be connected to a memory located outside the chip or to a memory located inside the chip, and run software programs and modules stored in the memory to perform various functional applications and data processing of the chip 1100, such as the model training method provided in the embodiments of this application, or the memory fault location method provided in the embodiments of this application.

[0151] In some embodiments, the processor 1101 may include one or more processing units, which may be independent devices or integrated into one or more processors. The processor 1101 may also include a controller, which can generate operation control signals according to the instruction opcode and timing signals to control the instruction fetching and execution.

[0152] This application also provides a computing device, the structure of which can be as shown in Figure 1, and will not be described in detail here.

[0153] This application also provides a computer program product comprising computer-executable instructions. In one embodiment, the computer-executable instructions are used to cause a computer to perform the functions described in the method embodiments above.

[0154] Computer-executable instructions can be stored in a computer-readable storage medium. This application also provides a computer-readable storage medium storing executable instructions. In one embodiment, the computer-executable instructions are used to cause a computer to perform the functions described in the method embodiments above.

[0155] The computer-readable storage medium provided in the embodiments of this application may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, portable hard disk, CD-ROM, or any other form of computer-readable storage medium known in the art.

[0156] Computer-executable instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0157] In the various embodiments of this application, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments are consistent and can be referenced mutually. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0158] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative examples of the solutions defined by the appended claims and are to be considered as covering any and all modifications, variations, combinations, or equivalents within the scope of this application.

[0159] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A method for locating a memory fault, the method comprising: The method includes: When reading data from memory, for memory errors, the location of the fault in the memory is determined; the location of the fault in the memory includes some or all of the following: the faulty memory module (Dimm), the faulty memory column (Rank), the faulty memory chip (Chip), the faulty storage array (Bank), the faulty storage cell (Cell), the faulty row in the storage array, the faulty column in the storage array, the faulty bit, the faulty input / output channel (DQ), the faulty read unit (burst), or the faulty subchannel.

2. The method according to claim 1, characterized in that, The method further includes: Based on the location of the fault in the memory, memory fault information is generated and saved.

3. The method according to claim 1 or 2, characterized in that, The step of determining the location of the fault in the memory in response to a memory error includes: For correctable errors (CE) or uncorrectable errors (UCE) occurring in the memory, obtain raw data and expected data; the raw data is data read from memory, and the expected data is data obtained by correcting the raw data; The location of the fault in the memory is determined by comparing the original data with the expected data.

4. The method according to claim 1 or 2, characterized in that, The step of determining the location of the fault in the memory in response to a memory error includes: For the UCE occurring in the memory, the location of the fault in the memory is determined by writing test data into the memory multiple times.

5. The method according to claim 3, characterized in that, The step of determining the location of the fault in the memory by comparing the original data with the expected data includes: The original data is compared with the expected data to determine the difference bits; Based on the difference bits, the location of the fault in the memory is determined.

6. The method according to any one of claims 1 to 5, characterized in that, The locations where the memory failure occurs include the memory module that failed, the sub-channel, the memory column, the storage array, the row in the storage array that failed, and the column in the storage array that failed. Determining the location of the fault in the memory includes: Based on the interrupt status of the memory controller and the error information recorded in the error address register, the faulty memory module, subchannel, memory column, storage array, faulty row in the storage array, and faulty column in the storage array are determined.

7. A memory fault location device, characterized in that, The device includes: The data reading module is used to read data from memory; The data analysis module is used to determine the location of the fault in the memory in response to memory errors. The location of the fault in the memory includes some or all of the following: the faulty memory module (Dimm), the faulty memory column (Rank), the faulty memory chip (Chip), the faulty storage array (Bank), the faulty storage cell (Cell), the faulty row in the storage array, the faulty column in the storage array, the faulty bit, the faulty input / output channel (DQ), the faulty read unit (burst), or the faulty subchannel.

8. The apparatus according to claim 7, characterized in that, The data analysis module is also used for: Based on the location of the fault in the memory, memory fault information is generated and saved.

9. The apparatus according to claim 7 or 8, characterized in that, The data analysis module is specifically used for: For correctable errors (CE) or uncorrectable errors (UCE) occurring in the memory, obtain raw data and expected data; the raw data is data read from memory, and the expected data is data obtained by correcting the raw data; The location of the fault in the memory is determined by comparing the original data with the expected data.

10. The apparatus of claim 7 or 8, wherein, The data analysis module is also used for: For the UCE occurring in the memory, the location of the fault in the memory is determined by writing test data into the memory multiple times.

11. A chip, characterized in that, It includes a processor and a power supply circuit; the power supply circuit is used to supply power to the processor, and the processor is used to execute a computer program to implement the method as described in any one of claims 1 to 6.

12. A computing device, characterized in that, Includes memory and the chip as described in claim 11.

13. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for causing a computer to perform the method as described in any one of claims 1 to 6.

14. A computer program product, characterized in that, It includes computer-executable instructions for causing a computer to perform the method as described in any one of claims 1 to 6.

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