Circuit mainboard, circuit mainboard operating method and electronic device

Abstract

Provided in the embodiments of the present application are a circuit mainboard, a circuit mainboard operating method and an electronic device. The circuit mainboard comprises a main control system, a level holding circuit and a memory, wherein when the main control system operates, the main control system outputs a first control signal to the level holding circuit, and the level holding circuit outputs the first control signal to the memory; under the action of the first control signal, the main control system exchanges operation data with the memory; when the main control system is in a powered-off standby state, the main control system stops outputting the first control signal to the level holding circuit and stops exchanging the operation data; and the level holding circuit outputs a second control signal to the memory, so as to control the memory to refresh and store the currently stored operation data. In the embodiments of the present application, a main control system chip having no constant-power functional region related to the self-refresh control of a memory is used to resume the operation of a previous processing scenario after a main control system is powered on again.

Description

A circuit motherboard, a circuit motherboard operating method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202510126728.7, filed on January 27, 2025, entitled "A Circuit Board, Circuit Board Operation Method and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip design technology, and in particular to a circuit board, a circuit board operation method, and an electronic device. Background Technology

[0003] Electronic devices based on embedded system applications include a circuit motherboard. The circuit motherboard houses a main control system and a memory. The memory stores the operating data of the main control system during power-on. When the main control system is powered on, it processes the operating data in the memory to execute various application functions. Typically, in embedded system applications, when the main control system is continuously powered on for extended periods, most electronic devices experience power consumption issues, especially those powered by energy storage devices (such as batteries). Prolonged continuous power-on reduces the operational time of the electronic device. To reduce power consumption, one existing improvement is to periodically or intermittently power down the main control system, depending on the actual application scenario, to reduce the continuous power-on of the main control system without affecting the operation of the electronic device. However, after the main control system is powered down, the data stored in the memory, being volatile, will gradually be lost. This means that after power-on, the main control system cannot restore the processing scenario before power-down (i.e., the running program and related functional operations before power-down).

[0004] One improvement involves integrating a constant-power functional area within the main control system. When the main control system is powered down, this area remains powered on and operational. The constant-power functional area controls the memory to keep data refreshed, allowing the main control system to resume previously executed processing scenarios upon power-up. However, this approach requires a dedicated chip for the main control system designed specifically for this application scenario and is not universally applicable to main control system chips that do not have a corresponding constant-power functional area. Summary of the Invention

[0005] This application provides a circuit motherboard, a circuit motherboard operation method, and an electronic device. Based on a main control system chip without a related constant power functional area, it enables the restoration of the processing scenario in the previous power-on stage after the main control system is powered on again.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a circuit board is provided, comprising a main control system, a level holding circuit, and a memory. When the main control system is operating, it outputs a first control signal to the level holding circuit, which in turn outputs a first control signal to the memory. Under the action of the first control signal, the main control system and the memory exchange operational data, which is the data required for the main control system's operation. When the main control system is powered down and in standby mode, it stops outputting the first control signal to the level holding circuit and ceases the data exchange. The level holding circuit outputs a second control signal to the memory, which, under the action of the second control signal, refreshes and saves the currently stored operational data.

[0008] This embodiment of the application designs a level-holding circuit external to the main control system. When the main control system is in a powered-on operating state, it needs to perform data processing operations on the memory based on the executed program or instructions. At this time, the main control system outputs a first control signal of corresponding level to the memory. The first control signal is a data processing-related control signal for interaction at the control link level. Based on the interactive control of the first control signal, the main control system can interact with the memory for operating data through the data link level. Therefore, in the powered-on operating state of the main control system, the level-holding circuit acts as a pathway, serving as a device for forwarding the actual data processing control signal (i.e., the first control signal) of the main control system. When the main control system switches to a powered-off standby state, it does not operate. At this time, the level-holding circuit isolates the main control system side and provides a second control signal to the memory. The second control signal is a control signal related to the memory's self-refresh. Based on the function of the second control signal, the memory can be controlled in the powered-off state to keep the memory in a self-refresh state. In the self-refresh state, the memory continuously refreshes the operating data stored in the memory array. By continuously refreshing the running data in the storage array through self-refresh operations, the running data is prevented from becoming invalid and can be used by the main control system to resume operation after power-on. In this embodiment, there is no need to design and integrate a constant-power function area related to memory self-refresh control in the main control system, so that the main control system can resume operation of previously processed scenarios after power-on.

[0009] In one possible implementation, the level holding circuit includes a controller and a level holding switch assembly. The input terminal of the level holding switch assembly is connected to the level holding circuit, and the output terminal of the level holding switch assembly is connected to the memory. Specifically, when the main control system is running, the controller outputs an on control signal to the level holding switch assembly, causing the input and output terminals of the level holding switch assembly to conduct. When the main control system is in standby mode, the controller outputs a off control signal to the level holding switch assembly, causing the input and output terminals of the level holding switch assembly to turn off, and the output terminal of the level holding switch assembly outputs a second control signal to the memory. In this embodiment, the level holding circuit controls the level holding switch assembly through the controller. When the main control system is powered on, the level holding switch assembly is in the on state to forward the first control signal. When the main control system is in standby mode, the controller controls the level holding switch assembly to turn off the control transmission link (related to the self-refresh control signal) between the main control system and the memory based on the off control signal, and the level holding switch assembly outputs a second control signal to maintain the self-refresh state of the memory.

[0010] In one possible implementation, after the main control system is powered down and in standby mode, the controller outputs a conduction control signal to the level holding switch assembly and a power-on indication signal to the main control system. Under the action of the power-on indication signal, the main control system enters the recovery power-on operation state. When the main control system enters the recovery power-on operation state, the main control system outputs a first control signal to the input terminal of the level holding switch assembly, and the output terminal of the level holding switch assembly outputs a first control signal to the memory. Under the action of the first control signal, the main control system and the memory perform data interaction on the currently stored operating data in the memory. In this embodiment, the controller can also switch the power-on and power-off states of the main control system. The controller controls the main control system to power on through the power-on indication signal and instructs the main control system to enter the recovery power-on operation mode. The recovery power-on operation state is different from the cold start power-on operation state. The cold start power-on operation state means that the memory is reset to zero, and the main control system restarts the currently required program or instruction from zero after power-on. The recovery power-on operation state means that the main control system continues to run the program or instruction corresponding to the function executed in the last power-on state and processes the operating data in the memory.

[0011] For example, the controller can be designed to periodically control the power-on and power-off of the main control system. In this case, after the duration of the main control system's power-off standby state reaches a preset value, the controller outputs a power-on indication signal to the level-holding switch assembly.

[0012] For example, the controller can be designed to control the power-on and power-off of the main control system based on preset trigger conditions. In response to the preset trigger conditions, the controller outputs a power-on indication signal to the level-holding switch component. For instance, taking a camera as an example, several related sensors can be designed within the electronic device, such as liveness sensors, motion sensors, and brightness sensors. Taking a motion sensor as an example, when a moving object appears within the image acquisition area, the controller outputs a power-on indication signal based on the information collected by the sensor, controlling the main control system to resume its power-on operation.

[0013] In one possible implementation, the level-holding switch assembly includes a first analog switch and a second analog switch. The two ends of the first analog switch are connected to the first input and first output of the level-holding switch assembly, respectively. The two ends of the second analog switch are connected to the second input and second output of the level-holding switch assembly, respectively. The main control system is connected to the first and second inputs, respectively, and the memory is connected to the first and second outputs, respectively. The first control signal includes a first reset control signal and a first clock enable signal. Specifically, when the main control system is running, it outputs the first reset control signal to the first input of the level-holding switch assembly and the first clock enable signal to the second input of the level-holding switch assembly. Under the action of the first reset control signal at different levels, the memory changes its reset state. Under the action of the first clock enable signal at different levels, the main control system and the memory begin or stop data interaction of running data. In this embodiment, the first control signal includes a first reset control signal and a first clock enable signal. When the main control system is running, under the action of the first reset control signal at different levels, the memory changes its reset state; under the action of the first clock enable signal at different levels, the main control system and the memory begin or stop data interaction of running data.

[0014] In one possible implementation, the second control signal includes a second reset control signal and a second clock enable signal, wherein the second reset control signal is high and the second clock enable signal is low. The level holding switch assembly further includes a level pull-up component and a level pull-down component. The first terminal of the level pull-up component is connected to the power supply, and the second terminal of the level pull-up component is connected to the first output terminal of the level holding switch assembly to provide the second reset control signal. The first terminal of the level pull-down component is connected to the second output terminal of the level holding switch assembly, and the second terminal of the level pull-down component is grounded. In this embodiment, the second control signal includes a second reset control signal and a second clock enable signal. When the main control system is in a power-down state, the high-level second reset control signal can control the memory not to be reset and cleared. The low-level clock enable signal controls the memory to be in a data waiting state and not to perform data interaction. By combining the second reset control signal and the second clock enable signal, the memory can be controlled to remain in a data holding state and the internal data can be refreshed periodically to avoid the loss of stored running data due to prolonged lack of refresh.

[0015] For example, electronic devices can be smart door locks, video doorbells, always-on video (AOV) cameras in the security field, talking cameras, multimedia televisions, set-top boxes, and cameras, etc.

[0016] For example, the main control system can be a system on chip (SoC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0017] Exemplarily, the memory is a memory memory based on a volatile memory architecture. Exemplarily, the volatile memory can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0018] For example, taking DDR SDRAM as an example, DDR can design the first and second control signals based on the DDR JEDEC protocol defined by the JEDEC Solid State Technology Association. In this case, the control signals may include a reset not (RESETN) signal and a clock enable (CKE) signal as specified in the DDR JEDEC protocol. For instance, the first and second reset control signals are the RESETN signals specified in the JEDEC protocol, and the first and second clock signals are the CKE signals specified in the JEDEC protocol.

[0019] For example, the levels of the first reset control signal and the first clock enable signal vary according to the processing requirements of the main control system in actual application. In the DDR SDRAM memory scenario, the second reset control signal is high and the second clock enable signal is low.

[0020] Secondly, this application provides a circuit board operation method, applied to a circuit board including a main control system, a level holding circuit, and a memory. The method includes: when the main control system is operating, the main control system outputs a first control signal to the level holding circuit, and the level holding circuit outputs a first control signal to the memory. Under the action of the first control signal, the main control system and the memory exchange operating data, which is the data required for the main control system to operate. When the main control system is powered down and in standby mode, the main control system stops outputting the first control signal to the level holding circuit and stops exchanging operating data. The level holding circuit outputs a second control signal to the memory, and under the action of the second control signal, the memory refreshes and saves the currently stored operating data.

[0021] In one possible implementation, the level holding circuit includes a level holding switch assembly; the input terminal of the level holding switch assembly is connected to the level holding circuit, and the output terminal of the level holding switch assembly is connected to a memory; wherein...

[0022] When the main control system is running, it outputs an on control signal to the level holding switch assembly. Under the action of the on control signal, the input and output terminals of the level holding switch assembly are connected. When the main control system is in standby mode, it outputs an off control signal to the level holding switch assembly. Under the action of the off control signal, the input and output terminals of the level holding switch assembly are turned off, and the output terminal of the level holding switch assembly outputs a second control signal to the memory.

[0023] In one possible implementation, after the main control system is powered down and in standby mode, the method further includes: outputting a conduction control signal to a level holding switch assembly and outputting a power-on indication signal to the main control system; under the action of the power-on indication signal, the main control system enters a power-on recovery state. When the main control system enters the power-on recovery state, the main control system outputs a first control signal to the input terminal of the level holding switch assembly, and the output terminal of the level holding switch assembly outputs a first control signal to the memory. Under the action of the first control signal, the main control system and the memory perform data interaction on the currently stored operating data in the memory.

[0024] In one possible implementation, the above-mentioned output of a power-on indication signal to the level holding switch assembly includes: after the duration of the power-off standby state of the main control system reaches a preset value, the controller outputs a power-on indication signal to the level holding switch assembly; or, in response to a preset trigger condition, the controller outputs a power-on indication signal to the level holding switch assembly.

[0025] In one possible implementation, the level-holding switch assembly includes a first analog switch and a second analog switch. The two ends of the first analog switch are connected to the first input and first output of the level-holding switch assembly, respectively. The two ends of the second analog switch are connected to the second input and second output of the level-holding switch assembly, respectively. The main control system is connected to the first and second inputs, respectively, and the memory is connected to the first and second outputs, respectively. The first control signal includes a first reset control signal and a first clock enable signal. When the main control system is running, the first and second analog switches are turned on under the action of the conduction control signal. The main control system outputs the first reset control signal to the first input of the level-holding switch assembly and the first clock enable signal to the second input of the level-holding switch assembly. Under the action of the first reset control signal at different levels, the memory changes its reset state. Under the action of the first clock enable signal at different levels, the main control system and the memory begin or stop data interaction.

[0026] In one possible implementation, the second control signal includes a second reset control signal and a second clock enable signal, wherein the second reset control signal is high and the second clock enable signal is low. The level-holding switch assembly further includes a level-pull-high component and a level-pull-low component. A first terminal of the level-pull-high component is connected to a power supply, and a second terminal of the level-pull-high component is connected to a first output terminal of the level-holding switch assembly to provide the second reset control signal. A first terminal of the level-pull-low component is connected to a second output terminal of the level-holding switch assembly, and a second terminal of the level-pull-low component is grounded.

[0027] Thirdly, embodiments of this application also provide an electronic device, which includes a device housing and a circuit board as described in the first aspect, the circuit board being installed inside the device housing.

[0028] Fourthly, embodiments of this application also provide a computer-readable storage medium including instructions that, when executed on a circuit board, cause the circuit board to perform the circuit board operation method as described in the second aspect above.

[0029] For a description of the technical principles and effects of the second, third and fourth aspects mentioned above, please refer to the relevant records of the first aspect, which will not be repeated here. Attached Figure Description

[0030] Figure 1 is a schematic diagram of a circuit motherboard;

[0031] Figure 2 is a schematic diagram of the structure of a first circuit board;

[0032] Figure 3 is a schematic diagram of the structure of a second circuit motherboard provided in an embodiment of this application;

[0033] Figure 4 is a schematic diagram of the structure of a second circuit motherboard provided in an embodiment of this application;

[0034] Figure 5 is a schematic diagram of the structure of a second circuit motherboard provided in an embodiment of this application;

[0035] Figure 6 is a schematic diagram of the structure of a second circuit motherboard provided in an embodiment of this application;

[0036] Figure 7 is a schematic flowchart of a circuit motherboard operation method provided in an embodiment of this application;

[0037] Figure 8 is a schematic flowchart of a circuit motherboard operation method provided in an embodiment of this application;

[0038] Figure 9 is a schematic flowchart of a circuit motherboard operation method provided in an embodiment of this application;

[0039] Figure 10 is a schematic flowchart of a circuit motherboard operation method provided in an embodiment of this application;

[0040] Figure 11 is a schematic flowchart of a circuit motherboard operation method provided in an embodiment of this application. Detailed Implementation

[0041] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0042] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0043] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0044] First, some basic concepts involved in the embodiments of this application will be explained:

[0045] Volatile memory, also known as non-persistent memory, refers to a type of memory where data is lost once power is off. Typically, data stored in volatile memory arrays is only retained during power supply; when power is off, the information is not automatically saved and requires backup via battery or other power sources for persistence. Although this type of memory cannot achieve persistent data storage, its high access speed makes it commonly designed as a main memory device, connected to the processing unit (CPU) to temporarily store data such as instructions and variable values ​​from the running program, enabling the CPU to execute programs quickly.

[0046] With the development of electronic technology, embedded system applications have become ubiquitous in people's lives. This application provides an example of an electronic device. The electronic device includes a circuit board and a device housing. The circuit board is disposed within the device housing. As shown in Figure 1, the circuit board 1000 includes a main control system 100 and a memory 200. The first input / output (IO) interface IO1 of the main control system 100 is connected to the second input / output interface IO2 of the memory 200. When the main control system 100 is powered on, it needs to execute preset function-related programs and instructions to complete the corresponding device function operations. During the execution of these related programs and instructions by the main control system 100, some related operational data needs to be processed. At this time, the main control system 100 needs to send control signals at the control link level to the control-related interface or pin of the second input / output interface IO2 of the memory 200 based on the control-related interface or pin of the first input / output interface IO1. Under the influence of control signals, the main control system 100 performs data processing of operational data at the data link layer based on the data transmission related interfaces or pins of the first input / output interface 101 and the data related interfaces or pins of the second input / output interface 102 of the memory 200. This data processing includes operations such as data writing, data reading, and data refreshing.

[0047] For example, the main control system 100 may be a system on chip (SoC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0048] Exemplarily, memory 200 is a memory memory based on a volatile memory architecture. Exemplarily, the volatile memory can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the hardware systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0049] Low power consumption is a requirement in many electronic devices, including the circuit board 1000 with the architecture shown in Figure 1. These devices can be smart locks, video doorbells, always-on video (AOV) cameras in the security field, interactive cameras, multimedia televisions, set-top boxes, and camcorders. Typically, in embedded system applications, power consumption is a problem when the main control system 100 is continuously powered on for extended periods. This is especially true for electronic devices powered by energy storage devices (such as batteries), where prolonged continuous power consumption reduces the device's operating time.

[0050] To reduce the power consumption of electronic devices during prolonged use and thus increase their operating time, one improvement is to periodically or intermittently power down the main control system 100, depending on the actual application scenario of the electronic device. This reduces the continuous power-on time of the main control system 100 without affecting the operation of the electronic device. However, after the main control system 100 is powered down, the operating data stored in the memory 200, which is volatile memory, will gradually be lost. This will result in the main control system being unable to restore the processing scenario before power-down (i.e., the running program and related functional processing before power-down) after power-on.

[0051] To address the issue that the main control system 100 cannot resume its previous processing state during the power-on cycle after a power-down, the circuit board 1000 shown in Figure 1 can be a first circuit board integrating a constant-power functional area within the main control system 100. As shown in Figure 2, the first circuit board 1000A includes a first main control system 100A and a memory 200. The first main control system 100A integrates a first input / output interface IO1, a constant-power functional area 110A, and a power-down functional area 120A. The constant-power functional area 110A and the power-down functional area 120A are connected to the second control interface K2 within the second input / output interface IO2 of the memory 200 via the first control interface K1 within the first input / output interface IO1. The power-down functional area 120A is connected to the second data interface D2 within the second input / output interface IO2 of the memory 200 via the first data interface D1 within the first input / output interface IO1.

[0052] In the embodiment shown in Figure 2, when the first main control system 100A is powered on, the power-off functional area 120A within the first main control system 100A executes relevant instructions and programs, and generates a first control signal related to data processing according to actual operational needs. The power-off functional area 120A outputs the first control signal through the first control interface K1, and performs data interaction processing operations related to the first control signal on the data link. Upon receiving the first control signal, the second control interface K2 of the memory 200, under the action of the first control signal, responds with corresponding data processing operations based on the second data interface D2. For example, when the power-off functional area 120A of the first main control system 100A outputs a first control signal related to reading data, the power-off functional area 120A waits to receive the relevant operational data to be read at the first data interface 110A. When the memory 200 receives the corresponding first control signal at the second control interface K2, it sends the corresponding operational data from the second data interface D2 to the first data interface D1.

[0053] When the first main control system 100A is powered down and in standby mode, the power-down function area 120A within the first main control system 100A is powered down and ceases operation. There is no data interaction between the first data interface D1 of the first main control system 100A and the second data interface D2 of the memory 200. However, the constant-power function area 110A within the first main control system 100A remains in the power-on operating state. At this time, the constant-power function area 110A outputs a second control signal to the second control interface K2 of the memory 200 through the first control interface K1. Under the action of the second control signal, the memory 200 refreshes (e.g., periodically refreshes) the currently stored operating data. In this case, when the first main control system 100A powers on again, the operating data processed during the previous power-on phase is still stored in the memory 200. At this time, the first main control system 100A can interact with the memory 200 to exchange data on the currently stored operating data, thereby resuming the execution of the functions or application scenarios performed during the last power-on phase.

[0054] In the embodiment shown in Figure 2, the first main control system 100A of the electronic device can enter a low-power power-down state during a predefined period of non-operation to reduce power consumption. Furthermore, after the first main control system 100A is powered on again, it can retain the operational data related to the functions performed in the previous power-on state. However, this approach requires product designers and manufacturers to design dedicated chips for the main control system in this application scenario. This increases chip design complexity, and integrating the constant-power functional area 110A internally increases chip area overhead. Most importantly, the embodiment shown in Figure 2 is not universally applicable to main control system 100 chips that do not have the relevant constant-power functional area 110A. Typically, for a type of embedded application product, product manufacturers may design different models of main control systems 200 depending on the configuration and application scenario. For main control systems 200 that are not the first main control system 200A, manufacturers cannot use these models of related inventory chips to implement products for this application scenario.

[0055] To enable the main control system to resume operation of previously processed scenarios after power-on, based on a main control system chip without associated constant-power functional areas, the circuit motherboard 1000 shown in Figure 1 can be a second circuit motherboard based on peripheral devices. As shown in Figure 3, the second circuit motherboard 1000B includes a second main control system 100B, a level holding circuit 300B, and a memory 200. The second main control system 100B includes a first input / output interface IO1. The first input / output interface IO1 includes a first data interface D1 and a first control interface K1. The memory 200 includes a storage array 210 and a second input / output interface IO2. The second input / output interface IO2 includes a second data interface D2 and a second control interface K1. The first data interface D1 is connected to the second data interface D2, the first control interface K1 is connected to the level holding circuit 300B, and the level holding circuit 300B is connected to the second control interface D2. As shown in Figure 3(a), when the second main control system 100B is in the power-on operation state, it outputs a first control signal to the level holding circuit 300B, which in turn outputs a first control signal to the memory 200. Under the action of the first control signal, the second main control system 100B and the memory 200 exchange operating data, which is the data required for the operation of the second main control system 100B. As shown in Figure 3(b), when the second main control system 100B is in the power-off standby state, it stops outputting the first control signal to the level holding circuit 300B and stops exchanging operating data. The level holding circuit 300B outputs a second control signal to the memory 200, which refreshes and saves the currently stored operating data.

[0056] For example, by designing a level-holding circuit 300B externally to the second main control system 100B, when the second main control system 100B is in a powered-on operating state, the second main control system 100B needs to perform data processing operations on the memory 200 based on the executed program or instructions. At this time, the second main control system 100B outputs a first control signal of corresponding level to the memory 200. The first control signal is a data processing-related control signal for interaction at the control link level. Based on the interactive control of the first control signal, the second main control system 100B can interact with the memory 200 to exchange operating data through the data link level. Therefore, in the powered-on operating state of the second main control system 100B, the level-holding circuit 300B acts as a pathway, serving as a device for forwarding the actual data processing control signal (i.e., the first control signal) of the second main control system 100B. When the second main control system 100B switches to the power-down standby state, it does not operate. At this time, the level holding circuit 300B isolates the second main control system 100B from the system and provides a second control signal to the memory 200. This second control signal is related to the self-refreshing of the memory 200. Based on the function of this second control signal, the memory 200 can be controlled even when the second main control system 100B is powered off, maintaining its self-refreshing state. In the self-refreshing state, the memory 200 continuously refreshes the operating data stored in the storage array 210. This continuous self-refreshing operation prevents the data from becoming invalid, ensuring it can be used when the second main control system 100B is powered on again and resumes operation.

[0057] In the embodiment shown in Figure 3, there is no need to design and integrate a constant power function area related to the self-refresh control of the memory 200 in the second main control system 100B, so that the main control system can resume the operation of the previously processed scenario after power-on.

[0058] In some possible implementations, as shown in FIG4, the level holding circuit 300B includes a controller 310B and a level holding switch assembly 320B; the input terminal of the level holding switch assembly 320B is connected to the level holding circuit 300B, and the output terminal of the level holding switch assembly 320B is connected to the memory 200. As shown in FIG4(a), when the second main control system 100B is powered on and running, the controller 310B outputs a conduction control signal to the level holding switch assembly 320B. Under the action of the conduction control signal, the input terminal and the output terminal of the level holding switch assembly 320B are connected. When the second main control system 100B is powered off and in standby mode, the controller 310B outputs a shutdown control signal to the level holding switch assembly 320B. Under the action of the shutdown control signal, the input terminal and the output terminal of the level holding switch assembly 320B are turned off, and the output terminal of the level holding switch assembly 320B outputs a second control signal to the memory 200. In this embodiment, the level holding circuit 300B controls the level holding switch component 320B through the controller 310B. When the second main control system 100B is powered on, the level holding switch component 320B is controlled to be in the on state to forward the first control signal. As shown in Figure 4(b), when the second main control system 100B is in the power-off standby state, the controller 310B controls the level holding switch component 320B to turn off the control transmission link (related to the self-refresh control signal) between the second main control system 100B and the memory 200 based on the shutdown control signal. The level holding switch component 320B outputs the second control signal to maintain the self-refresh state of the memory 200.

[0059] In some possible implementations, the controller 310B can also switch the power-on and power-off states of the second main control system 100B. For example, the controller 310B controls the second main control system 100B to resume power-on. After the second main control system 100B is powered off and in standby mode, the controller 310B outputs a conduction control signal to the level holding switch assembly 320B and a power-on indication signal to the second main control system 100B. Under the action of the power-on indication signal, the second main control system 100B enters the power-on resumption operation state. When the second main control system 100B enters the power-on resumption operation state, the second main control system 100B outputs a first control signal to the input terminal of the level holding switch assembly 320B, and the output terminal of the level holding switch assembly 320B outputs a first control signal to the memory 200; under the action of the first control signal, the second main control system 100B and the memory 200 interact with the currently stored operating data in the memory 200.

[0060] In some possible implementations, depending on the memory technology and type of the memory 200, the first control signal and the second control signal are control signals under the corresponding protocol of the memory 200. For example, taking a double data rate synchronous dynamic random access memory (DDR SDRAM) of type DRAM as an example, the DDR can design the first and second control signals based on the DDR JEDEC protocol defined by the JEDEC Solid State Technology Association. In this case, the control signals may include a reset not (RESETN) signal and a clock enable (CKE) signal as specified in the DDR JEDEC protocol.

[0061] For example, the RESETN signal is typically an active low pulse. When the system initializes or a soft reset of the memory module is required, RESETN is pulled low, causing the DDR chip's internal operating state to return to zero, reverting to its initial configuration. Once the reset is complete, the signal returns to a high level, allowing the memory to enter normal operating mode. Therefore, a high-level control signal is needed when the DDR needs to remain in a non-zero operating state and retain data; a low-level active control signal is needed when the DDR needs to return to a zero operating state.

[0062] For example, the CKE signal is a clock enable signal used to control when the DDR memory receives and sends data. When CKE is high, it indicates that the memory is in a data transfer cycle and can receive and send data within two clock cycles; when CKE is low, it indicates that the memory is in a waiting state and does not perform data exchange, mainly used for the transmission of command signals or other non-data operations.

[0063] For example, the first control signal includes a first reset control signal and a first clock enable signal. When the second main control system 100B is running, the memory 200 changes its reset state under the action of the first reset control signal at different levels; under the action of the first clock enable signal at different levels, the second main control system 100B and the memory 200 exchange running data at the start or stop.

[0064] For example, the second control signal includes a second reset control signal and a second clock enable signal. When the second main control system 100B is powered down, the high-level second reset control signal can control the memory 200 not to be reset and cleared. The low-level clock enable signal controls the memory 200 to be in a data waiting state and not to perform data interaction. By combining the second reset control signal and the second clock enable signal, the memory 200 can be controlled to maintain a data-holding state and periodically refresh the internal data to avoid the loss of stored operating data due to prolonged lack of refresh.

[0065] In some possible implementations, as shown in FIG5, the second main control system 100B includes a first input / output interface IO1, which includes a first control interface K1 and a first data interface D1. The memory 200 includes a second input / output interface IO2, which includes a second control interface K2 and a second data interface D2. The input terminals of the level-holding switch assembly 320B include a first input terminal I1 and a second input terminal I2, and the output terminals of the level-holding switch assembly 320B include a first output terminal O1 and a second output terminal O2. The first control interface K1 includes a first reset control pin RESETN1 and a first clock pin CKE1; the second control interface includes a second reset control pin RESETN2 and a second clock pin CKE2. The level-holding switch assembly 320B includes a first analog switch S1 and a second analog switch S2. The first terminal of the first analog switch S1 is connected to the first reset control pin RESETN1, and the second terminal of the first analog switch S1 is connected to the second reset control pin RESETN2. The two ends of the first analog switch S1 are connected to the first input terminal I1 and the first output terminal O1 of the level holding switch assembly 320B, respectively. The two ends of the second analog switch S2 are connected to the second input terminal I2 and the second output terminal O2 of the level holding switch assembly 320B, respectively.

[0066] For example, as shown in Figure 5, when the second main control system 100B is operating, the controller 310B outputs a conduction control signal to the first analog switch S1 and the second analog switch S2. The second main control system 100B outputs a first reset control signal to the first input terminal I1 of the level holding switch assembly 320B and a first clock enable signal to the second input terminal I2 of the level holding switch assembly 320B. The level holding switch assembly 320B outputs the first reset control signal and the first clock enable signal to the memory 200 through the conducting first analog switch S1 and the second analog switch S2, respectively, to complete the normal processing between the second main control system 100B and the memory 200. Depending on the actual operating requirements of the second main control system 100B, it may control the memory 200 to reset to zero or hold data. It may perform operations such as reading data, writing data, and refreshing data on the memory 200. Therefore, the level of the first control signal will also be different depending on the relevant control requirements.

[0067] In some possible implementations, as shown in FIG6, the level holding switch assembly 320B further includes a level pull-up assembly 321B and a level pull-down assembly 322B; the first end of the level pull-up assembly 321B is connected to the power supply, and the second end of the level pull-up assembly 321B is connected to the first output terminal O1 of the level holding switch assembly 320B.

[0068] For example, as shown in FIG6, when the second main control system 100B is powered down and in standby mode, the controller 310B outputs a shutdown control signal to the first analog switch S1 and the second analog switch S2. At this time, the power-down state of the second main control system 100B does not affect the operation of the memory 200. Furthermore, a high-level second reset control signal is provided by the level pull-up component 321B to keep the memory 200 from entering the reset zero state; the grounded level pull-down component 322B pulls down the potential at the second output terminal O2 to provide a low-level second clock enable signal to keep the memory 200 in a state of not transmitting data and to retain data.

[0069] For example, the first analog switch S1 and the second analog switch S2 can be transistors, analog switches, and single-pole single-throw switches. In this embodiment, because the transmission between the second main control system 100B and the memory 200 is a high-speed signal with a transmission delay accuracy on the nanosecond level, prior art typically does not consider placing switching elements between the main control chip and the memory chip. However, this application uses transistors, analog switches, and single-pole single-throw switches, and adapts the wiring length between the second main control system 100B and the memory 200 to avoid glitches in the transmission of control signals between the memory 200 and the second main control system 100B, ensuring steady-state signal transmission. This achieves the design function of the above embodiment without affecting the normal operation and interaction between the second main control system 100B and the memory 200. Generally, it is not recommended to use gating circuits and single-pole multi-throw switches as switching components in this embodiment, as these devices are prone to causing glitches in the control signals, greatly increasing design complexity.

[0070] For example, the pull-high component 321B and the pull-low component 322B can be resistive elements. For example, the pull-high component 321B and the pull-low component 322B can be transistors.

[0071] For example, when the second main control system 100B is in a power-down state, it can be a fully power-down state. A fully power-down state means that all internal devices of the second main control system 100B are not powered on. For example, when the second main control system 100B is in a power-down state, most modules can be in a power-down state. In this case, the second main control system 100B can be a chip with constantly powered functional areas independent of the self-refresh control of the memory 200. These non-self-refresh control related functional areas can also remain operational when the second main control system 100B is powered down.

[0072] Based on the second circuit board 1000B, which includes the structures shown in Figures 3, 4, 5 and 6 above, the circuit board operation method including steps S100-S200 shown in Figure 7 can be executed.

[0073] S100 and the second main control system 100B are powered on and run. Under the action of the first control signal, they interact with the memory 200 to run data.

[0074] For example, according to actual design requirements, engineers can adapt the controller 310B to control the switching of the power-on and power-off states of the second main control system 100B. For instance, the controller 310B can wake up and power on the second main control system 100B based on user power-on operation, preset detection trigger condition operation, periodic power-on control operation, or predefined timed automatic power-on operation.

[0075] In some possible implementations, as shown in FIG8, step S100 further includes the following sub-operations from steps S110 to S130:

[0076] S110, the second main control system 100B outputs the first control signal to the level holding circuit 300B.

[0077] During the operation of the second main control system 100B, programs or instructions for related functions are executed. Based on the execution of these programs or instructions, related operational data processing operations need to be performed on the memory 200, such as writing data, reading data, refreshing data, and clearing data. Depending on the specific operational data processing operation to be performed, the second main control system 100B needs to generate a corresponding first control signal. The operational data is the data required for the operation of the second main control system 100B. For details regarding the first control signal, please refer to the relevant descriptions in the above hardware embodiments; they will not be repeated here.

[0078] S120, the level holding circuit 300B outputs the first control signal to the memory 200.

[0079] For example, as shown in FIG4, when the second main control system 100B is running, the controller 310B outputs a conduction control signal to the level holding switch assembly 320B. Under the action of the conduction control signal, the input terminal of the level holding switch assembly 320B is connected to the output terminal of the level holding switch assembly 320B.

[0080] For example, the first control signal includes a first reset control signal and a first clock enable signal. As shown in FIG5, the first analog switch S1 and the second analog switch S2 in the level holding switch assembly 320B are turned on by the turn-on control signal to realize the interaction of control signals between the second main control system 100B and the memory 200.

[0081] S130, the second main control system 100B and the memory 200 exchange operating data.

[0082] After the memory 200 receives the first control signal, the second main control system 100B interacts with the memory 200 to exchange operational data under the action of the first control signal. The interaction of operational data here should be interpreted broadly, including bidirectional data transmission (i.e., reading data and writing data), as well as data refresh control and data clearing control of the memory 200 by the second main control system 100B.

[0083] S200 and the second main control system 100B are powered down and in standby mode. Under the action of the second control signal output by the level holding circuit 300B, the stored calculation data is refreshed and held.

[0084] In some possible implementations, as shown in FIG9, step S200 further includes the following sub-operations: steps S210-S220.

[0085] S210, the second main control system 100B stops outputting the first control signal to the level holding circuit 300B and stops data interaction of running data.

[0086] S220 and the level holding circuit 300B output a second control signal to the memory 200.

[0087] For example, as shown in FIG4, when the second main control system 100B is powered down and in standby mode, it outputs a shutdown control signal to the level holding switch assembly 320B. Under the action of the shutdown control signal, the input terminal and the output terminal of the level holding switch assembly 320B are turned off, and the output terminal of the level holding switch assembly 320B outputs a second control signal to the memory 200.

[0088] For example, the second control signal includes a second reset control signal and a second clock enable signal. As shown in FIG6, when the memory 200 is DDR, the high-level second reset control signal and the low-level second clock enable signal are provided by the high-level pull-up component 321B and the low-level pull-down component 322B in the level holding switch component 320B, respectively.

[0089] In this embodiment, the power-down state of the second main control system 100B is isolated from the memory 200 by the level holding circuit 300B. The level holding circuit 300B provides a second control signal to control the memory 200 to self-refresh and retain the stored operating data. The specific details of the second control signal can be found in the descriptions in the above hardware embodiments, and will not be repeated here.

[0090] In some possible implementations, as shown in FIG10, the circuit board operation method further includes the following step S300:

[0091] S300 and the second main control system 100B have resumed power-on operation.

[0092] In some possible implementations, depending on the application scenario of the electronic device, the controller 310B can periodically control the second main control system 100B to power on and off to reduce power consumption. Alternatively, the controller 310B can also control the second main control system 100B to power on or off according to preset trigger conditions.

[0093] In some examples, after the second main control system 100B is powered down and in standby mode, the controller 310B outputs a conduction control signal to the level holding switch assembly 320B and a power-on indication signal to the second main control system 100B. Under the action of the power-on indication signal, the second main control system 100B enters the recovery power-on operation state. The recovery power-on operation state is different from the cold start power-on operation state. The cold start power-on operation state means that the memory 200 is reset to zero, and the second main control system 100B restarts the currently required program or instruction from scratch after power-on. The recovery power-on operation state means that the second main control system 100B continues to run the program or instruction corresponding to the function executed in the last power-on state and processes the running data in the memory 200.

[0094] For example, taking a camera as an example, the controller 310B inside the camera periodically controls the second main control system 100B inside the camera to power on and operate. After the second main control system 100B controls the relevant imaging acquisition components of the camera to acquire a frame of image, the controller 310B controls the second main control system 100B to power off and enter standby mode. After the second main control system 100B has been in standby mode for a period of time, the controller 310B controls the second main control system 100B to power on again, and the second main control system 100B continues to run the previous imaging and capturing related differential programs or instructions, and captures a frame of image based on the operating data stored in the memory 200, and based on the capturing mode or shooting parameters or imaging function of the last power-on operating state.

[0095] In some possible implementations, as shown in FIG11, step S300 includes sub-operations of steps S310-S330:

[0096] S310 and controller 310B output a conduction control signal to level holding switch assembly 320B and a power-on indication signal to second main control system 100B.

[0097] For example, the controller 310B can be designed to periodically control the power-on and power-off of the second main control system 100B. At this time, after the duration of the power-off standby state of the second main control system 100B reaches a preset value, the controller 310B outputs a power-on indication signal to the level holding switch assembly 320B.

[0098] For example, the controller 310B can be designed to control the power-on and power-off of the second main control system 100B according to a preset trigger condition. In this case, in response to the preset trigger condition, the controller 310B outputs a power-on indication signal to the level-holding switch assembly 320B. For instance, taking a camera as an example, some related sensors, such as liveness sensors, motion sensors, and brightness sensors, can be designed within the electronic device. Taking a motion sensor as an example, when a moving object appears within the image acquisition area, the controller 310B outputs a power-on indication signal based on the information collected by the sensor, controlling the second main control system 100B to resume its power-on operation.

[0099] In this embodiment, the controller 310B controls the second main control system 100B to power on via a power-on indication signal and instructs the second main control system 100B to enter a power-on recovery operation mode. The second main control system 100B determines, based on the power-on indication signal, that it is currently in a power-on recovery operation mode, rather than a power-on operation mode following a cold start. Simultaneously, the controller 310B controls the level holding switch assembly 320B to remain on based on a conduction control signal, ensuring that the second main control system 100B can perform normal control operations with the memory 200 after power-on recovery.

[0100] S320, the second main control system 100B outputs a first control signal to the level holding switch assembly 320B, and the level holding switch assembly 320B outputs a first control signal to the memory 200.

[0101] In this embodiment, when the second main control system 100B enters the power-on recovery state, the input and output terminals of the level holding switch assembly 320B are in a conducting state. The second main control system 100B outputs a first control signal to the input terminal of the level holding switch assembly 320B, and the output terminal of the level holding switch assembly 320B outputs a first control signal to the memory 200.

[0102] S330, the second main control system 100B and the memory 200 exchange data on the currently saved operating data.

[0103] In this embodiment, the memory 200 responds to the first control signal and, under the action of the first control signal, performs data interaction processing with the second main control system 100B. Specifically, the data interaction processing in step S330 refers to the second main control system 100B processing the currently stored operating data in the memory 200 after power-on.

[0104] This application provides a circuit board, a circuit board operation method, and an electronic device. The electronic device includes a circuit board. A main control system, a level holding circuit, and a memory are configured on the circuit board. When the main control system is powered on, the level holding circuit primarily functions to conduct data transmission, enabling the interaction of control signals at the control link level between the main control system and the memory. When the main control system is powered off and in standby mode, the level holding circuit isolates the memory from the influence of the power-off state and controls the memory to remain in a data self-refresh state, ensuring that the running data within the volatile memory is not lost, so that the main control system can resume processing after power-on. Through this implementation, it is unnecessary to design and integrate a constant-power functional area related to the self-refresh control of the memory 200 in the second main control system 100B, thus enabling the main control system to resume operation of previously processed scenarios after power-on.

[0105] This application also provides a computer-readable storage medium including instructions. When the instructions are executed on a circuit board, the circuit board performs a circuit board operation method (e.g., the circuit board operation method shown in Figures 7, 8, 9, 10, and 11 above).

[0106] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0107] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0108] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0110] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0111] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0112] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0113] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, This includes the main control system, level holding circuit, and memory; among which, When the main control system is running, the main control system outputs a first control signal to the level holding circuit, and the level holding circuit outputs the first control signal to the memory; under the action of the first control signal, the main control system and the memory exchange operating data, and the operating data is the data required for the main control system to operate; When the main control system is powered down and in standby mode, the main control system stops outputting the first control signal to the level holding circuit and stops data interaction of the running data; the level holding circuit outputs a second control signal to the memory, and under the action of the second control signal, the memory refreshes and saves the currently stored running data.

2. The circuit board according to claim 1, characterized in that, The level-holding circuit includes a controller and a level-holding switch assembly; the input terminal of the level-holding switch assembly is connected to the level-holding circuit, and the output terminal of the level-holding switch assembly is connected to the memory; wherein... When the main control system is running, the controller outputs a conduction control signal to the level holding switch assembly. Under the action of the conduction control signal, the input terminal of the level holding switch assembly is connected to the output terminal of the level holding switch assembly. When the main control system is powered down and in standby mode, the controller outputs a shutdown control signal to the level holding switch assembly. Under the action of the shutdown control signal, the input terminal and the output terminal of the level holding switch assembly are turned off, and the output terminal of the level holding switch assembly outputs the second control signal to the memory.

3. The circuit board according to claim 2, characterized in that, After the main control system is powered down and in standby mode, the controller outputs the conduction control signal to the level holding switch assembly and outputs a power-on indication signal to the main control system; under the action of the power-on indication signal, the main control system enters the power-on recovery operation state. When the main control system enters the power-on recovery state, the main control system outputs the first control signal to the input terminal of the level holding switch component, and the output terminal of the level holding switch component outputs the first control signal to the memory; under the action of the first control signal, the main control system and the memory perform data interaction on the currently stored operating data in the memory.

4. The circuit board according to claim 3, characterized in that, The step of outputting the power-on indication signal to the level-holding switch assembly includes: After the duration of the power-down standby state of the main control system reaches a preset value, the controller outputs the power-on indication signal to the level holding switch assembly; or, In response to a preset trigger condition, the controller outputs the power-on indication signal to the level holding switch assembly.

5. The circuit board according to any one of claims 2-4, characterized in that, The level-holding switch assembly includes a first analog switch and a second analog switch; the two ends of the first analog switch are connected to the first input terminal and the first output terminal of the level-holding switch assembly; the two ends of the second analog switch are connected to the second input terminal and the second output terminal of the level-holding switch assembly; the main control system is connected to the first input terminal and the second input terminal respectively, and the memory is connected to the first output terminal and the second output terminal respectively; the first control signal includes a first reset control signal and a first clock enable signal; wherein, When the main control system is running, it outputs the first reset control signal to the first input terminal of the level holding switch assembly and the first clock enable signal to the second input terminal of the level holding switch assembly. Under the action of the first reset control signal at different levels, the memory changes its reset state. Under the action of the first clock enable signal at different levels, the main control system and the memory start or stop data interaction of the running data.

6. The circuit board according to claim 5, characterized in that, The second control signal includes a second reset control signal and a second clock enable signal, wherein the second reset control signal is at a high level and the second clock enable signal is at a low level; the level holding switch assembly further includes a level pull-up assembly and a level pull-down assembly; the first terminal of the level pull-up assembly is connected to the power supply, and the second terminal of the level pull-up assembly is connected to the first output terminal of the level holding switch assembly to provide the second reset control signal; The first terminal of the pull-low component is connected to the second output terminal of the level holding switch component, and the second terminal of the pull-low component is grounded.

7. A method for operating a circuit motherboard, characterized in that, The method is applied to a circuit board, the circuit board including a main control system, a level holding circuit, and a memory; the method includes: When the main control system is running, the main control system outputs a first control signal to the level holding circuit, and the level holding circuit outputs the first control signal to the memory; under the action of the first control signal, the main control system and the memory exchange operating data, and the operating data is the data required for the main control system to operate; When the main control system is powered down and in standby mode, the main control system stops outputting the first control signal to the level holding circuit and stops data interaction of the running data; the level holding circuit outputs a second control signal to the memory, and under the action of the second control signal, the memory refreshes and saves the currently stored running data.

8. The circuit board operation method according to claim 7, characterized in that, The level holding circuit includes a level holding switch assembly; the input terminal of the level holding switch assembly is connected to the level holding circuit, and the output terminal of the level holding switch assembly is connected to the memory; wherein... When the main control system is running, it outputs a conduction control signal to the level holding switch assembly. Under the action of the conduction control signal, the input terminal of the level holding switch assembly is connected to the output terminal of the level holding switch assembly. When the main control system is powered down and in standby mode, it outputs a shutdown control signal to the level holding switch assembly. Under the action of the shutdown control signal, the input terminal and the output terminal of the level holding switch assembly are turned off, and the output terminal of the level holding switch assembly outputs the second control signal to the memory.

9. The circuit board operation method according to claim 8, characterized in that, After the main control system is powered down and put into standby mode, the method further includes: The system outputs the conduction control signal to the level holding switch assembly and a power-on indication signal to the main control system; under the action of the power-on indication signal, the main control system enters the power-on recovery operation state. When the main control system enters the power-on recovery state, the main control system outputs the first control signal to the input terminal of the level holding switch component, and the output terminal of the level holding switch component outputs the first control signal to the memory; under the action of the first control signal, the main control system and the memory perform data interaction on the currently stored operating data in the memory.

10. The circuit board operation method according to claim 9, characterized in that, The step of outputting the power-on indication signal to the level-holding switch assembly includes: After the duration of the power-down standby state of the main control system reaches a preset value, the controller outputs the power-on indication signal to the level holding switch assembly; or, In response to a preset trigger condition, the controller outputs the power-on indication signal to the level holding switch assembly.

11. The circuit board operation method according to any one of claims 8-10, characterized in that, The level-holding switch assembly includes a first analog switch and a second analog switch; the two ends of the first analog switch are connected to the first input terminal and the first output terminal of the level-holding switch assembly; the two ends of the second analog switch are connected to the second input terminal and the second output terminal of the level-holding switch assembly; the main control system is connected to the first input terminal and the second input terminal respectively, and the memory is connected to the first output terminal and the second output terminal respectively; the first control signal includes a first reset control signal and a first clock enable signal; wherein, When the main control system is running, under the action of the conduction control signal, the first analog switch and the second analog switch are turned on; the main control system outputs the first reset control signal to the first input terminal of the level holding switch assembly and outputs the first clock enable signal to the second input terminal of the level holding switch assembly; under the action of the first reset control signal at different levels, the memory changes its reset state; under the action of the first clock enable signal at different levels, the main control system and the memory start or stop data interaction of the running data.

12. The circuit board operation method according to claim 11, characterized in that, The second control signal includes a second reset control signal and a second clock enable signal, wherein the second reset control signal is at a high level and the second clock enable signal is at a low level; the level holding switch assembly further includes a level pull-up assembly and a level pull-down assembly; the first terminal of the level pull-up assembly is connected to the power supply, and the second terminal of the level pull-up assembly is connected to the first output terminal of the level holding switch assembly to provide the second reset control signal; The first terminal of the pull-low component is connected to the second output terminal of the level holding switch component, and the second terminal of the pull-low component is grounded.

13. An electronic device, characterized in that, It includes a device housing and a circuit board as described in any one of claims 1-6, the circuit board being mounted within the device housing.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on the circuit board, cause the circuit board to perform the circuit board operation method as described in any one of claims 7-12.

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