Data processing method and apparatus, storage medium and program product

Abstract

Embodiments of the present disclosure relate to the technical field of communications, and provide a data processing method and apparatus, a storage medium, and a program product, which can improve the quality of data transmission. The method comprises: encoding a plurality of information bit sequences to obtain a plurality of encoded bit sequences; performing interleaving processing on X encoded bit sequences among the plurality of encoded bit sequences to obtain an interleaved bit sequence, wherein X is an integer greater than 1; modulating the interleaved bit sequence to obtain a modulated symbol sequence; and sending the modulated symbol sequence.

Description

Data processing methods, devices, storage media and software products

[0001] This disclosure claims priority to Chinese patent application No. 202510113612.X, filed on January 22, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of communication technology, and in particular to a data processing method, apparatus, storage medium, and program product. Background Technology

[0003] With the gradual development of communication networks, the number of devices in wireless communication networks is increasing, and the requirements for data transmission quality are also becoming more stringent. However, data transmission may suffer from various problems such as data loss due to factors like channel attenuation and noise, which will reduce the quality of data transmission. Summary of the Invention

[0004] On one hand, a data processing method is provided, comprising: encoding multiple information bit sequences to obtain multiple coded bit sequences; interleaving X coded bit sequences among the multiple coded bit sequences to obtain an interleaved bit sequence, wherein X is an integer greater than 1; modulating the interleaved bit sequence to obtain a modulation symbol sequence; and transmitting the modulation symbol sequence.

[0005] In another aspect, a data processing method is provided, comprising: receiving a modulation symbol sequence; demodulating the modulation symbol sequence to obtain a soft bit sequence; deinterleaving all soft bits of X coded bit sequences in the soft bit sequence to obtain multiple coded soft bit sequences, wherein X is an integer greater than 1; and decoding based on the multiple coded soft bit sequences to obtain multiple information bit sequences.

[0006] In another aspect, a data processing apparatus is provided, comprising: a processing unit and a transmitting unit; the processing unit is used to encode multiple information bit sequences to obtain multiple coded bit sequences; the processing unit is further used to perform interleaving processing on X coded bit sequences among the multiple coded bit sequences to obtain an interleaved bit sequence, wherein X is an integer greater than 1; the processing unit is further used to modulate the interleaved bit sequence to obtain a modulation symbol sequence; and the transmitting unit is used to transmit the modulation symbol sequence.

[0007] In another aspect, a data processing apparatus is provided, comprising: a receiving unit and a processing unit; the receiving unit is configured to receive a modulation symbol sequence; the processing unit is configured to demodulate the modulation symbol sequence to obtain a soft bit sequence; the processing unit is further configured to deinterleave all soft bits of X coded bit sequences in the soft bit sequence to obtain multiple coded soft bit sequences, wherein X is an integer greater than 1; the processing unit is further configured to decode based on the multiple coded soft bit sequences to obtain multiple information bit sequences.

[0008] In another aspect, a communication device is provided, comprising: a memory and a processor; the memory and the processor are coupled; the memory is used to store a computer program; and the processor implements the above-described data processing method when executing the computer program.

[0009] In another aspect, a computer-readable storage medium is provided, including a non-transitory computer-readable storage medium on which computer program instructions are stored, which, when executed by a processor, implement the above-described data processing method.

[0010] In another aspect, a computer program product is provided, which includes computer program instructions that, when executed by a processor, implement the aforementioned data processing method. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings.

[0012] Figure 1 is an architecture diagram of a communication system according to some embodiments.

[0013] Figure 2 is a flowchart of a data processing method according to some embodiments.

[0014] Figure 3 is a schematic diagram of a basic graph matrix according to some embodiments.

[0015] Figure 4 is a flowchart of an interleaving process according to some embodiments.

[0016] Figure 5 is a diagram of a different bit sequence according to some embodiments.

[0017] Figure 6 is a schematic diagram of the reliability of a soft bit according to some embodiments.

[0018] Figure 7 is a schematic diagram of the reliability of another soft bit according to some embodiments.

[0019] Figure 8 is a flowchart of another interleaving process according to some embodiments.

[0020] Figure 9 is a flowchart of another interleaving process according to some embodiments.

[0021] Figure 10 is a flowchart of another interleaving process according to some embodiments.

[0022] Figure 11 is a flowchart of another interleaving process according to some embodiments.

[0023] Figure 12 is a schematic diagram of writing to a first matrix according to some embodiments.

[0024] Figure 13 is a schematic diagram of a cyclic shift interleaving according to some embodiments.

[0025] Figure 14 is a schematic diagram of a soft bit position according to some embodiments.

[0026] Figure 15 is a schematic diagram of another soft bit position according to some embodiments.

[0027] Figure 16 is a schematic diagram of another soft bit position according to some embodiments.

[0028] Figure 17 is a flowchart of another data processing method according to some embodiments.

[0029] Figure 18 is a block diagram of a communication device according to some embodiments.

[0030] Figure 19 is a block diagram of another communication device according to some embodiments.

[0031] Figure 20 is a block diagram of another communication device according to some embodiments.

[0032] Figure 21 is a block diagram of another communication device according to some embodiments.

[0033] Figure 22 is a block diagram of another communication device according to some embodiments. Detailed Implementation

[0034] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] It should be noted that, in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0037] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "more than one" means two or more.

[0038] With the rapid development of technologies such as big data, cloud computing, and latency-sensitive networks, the number of user devices in wireless communication networks is growing rapidly. Wireless communication networks will carry diverse applications and massive amounts of data, placing high demands on data processing throughput, reliability, and latency. With the development of intelligent transportation, intelligent industrial control, and intelligent logistics, users have increasingly strong requirements for ultra-low latency and ultra-reliable communication, meaning they need to send and successfully receive large volumes of data in a short period. In ultra-high throughput scenarios, data can be transmitted after encoding based on low-density parity check (LDPC). However, LDPC encoding results in a large number of coded blocks, which are not interconnected. Furthermore, when combined with higher-order modulation, the performance of the coded blocks is poor when passing through fading channels. This leads to poor performance and resistance to burst errors in LDPC encoding, reducing the quality of data transmission.

[0039] The coding and modulation process during data transmission will be described below.

[0040] In wireless communication systems, the transmitting end performs channel coding on the data to be transmitted to obtain a coded bit sequence (also known as a coded block). This coded bit sequence is then mapped to modulation symbols in a constellation diagram and transmitted to the receiving end. During data transmission through the channel, errors (such as bit loss) may occur due to factors like multipath propagation, noise, and interference. To address this, the transmitting end can add redundant information to the data to be transmitted through channel coding. This way, even if errors occur during transmission, the receiving end can recover the original data using this redundant information, thus eliminating distortion introduced during transmission. Furthermore, the receiving end needs to demodulate and decode the received modulation symbols to recover the data to be transmitted.

[0041] Currently, commonly used channel coding methods include LDPC coding, polar coding, turbo coding, and convolutional coding. LDPC coding uses a sparse (or low-density) parity-check matrix, and its decoding performance can be improved through iterative decoding, such as using confidence-transfer decoding.

[0042] LDPC coding is a type of forward error correction coding. LDPC coding can be defined as a linear block code using a parity check matrix and boost values. Because the parity check matrix is ​​very sparse, decoding can be achieved with low complexity. The parity check matrix H of LDPC coding is an mb×Z matrix with nb×Z columns, composed of mb×nb submatrices. Each submatrix is ​​either a different power of the Z×Z standard permutation matrix P (corresponding to a cyclic shift matrix of the identity matrix) or a Z×Z all-zero square matrix, and the standard permutation matrix can be determined from the elements of the fundamental graph matrix. The parity check matrix H has the following form:

[0043] Here, h ij Let represent the elements in the matrix, i and j represent the row index and column index respectively, mb be the number of rows in the matrix, and nb be the number of columns in the matrix. Let P be a power of a standard permutation matrix, and let the submatrix in the i-th row and j-th column of the parity-check matrix H be... H b A simplified representation of the entire matrix H, usually representing a certain structure or property of matrix H.

[0044] like but That is, a Z×Z all-zero square matrix; if If the integer is greater than or equal to 0, then the corresponding submatrix is ​​the standard permutation matrix P. The power of the power (i.e., the cyclic shift of the identity matrix). The standard permutation matrix P of the above Z×Z is shown below (the standard permutation matrix is ​​formed by cyclically shifting the identity matrix one bit to the right):

[0045] so, This allows each submatrix or standard permutation matrix to be uniquely identified. If a submatrix is ​​a square matrix consisting entirely of zeros, the corresponding... Using -1 (or null values ​​or other representations), if a submatrix is ​​obtained by cyclic shift 's' of the identity matrix, then... Equals s, therefore all This can form a fundamental matrix, a parity check matrix, a coefficient matrix, or a shift matrix. The parity check matrix includes two types of elements: elements indicating an all-zero square matrix (which can be called -1 elements) and elements indicating cyclic shifts of the identity matrix (which can be called non--1 elements). By changing the elements indicating an all-zero square matrix to 0 and the elements indicating cyclic shifts of the identity matrix to 1, the fundamental graph matrix is ​​obtained. The fundamental graph matrix generally includes only two types of elements: 0 and 1. 0 indicates an all-zero square matrix, and 1 indicates cyclic shifts of the identity matrix (the number of shifts is determined by the parity check matrix).

[0046] Z is the dimension of the standard permutation matrix (submatrix) mentioned above, and can be called the lifting size. For ease of description, only the elements of the parity check matrix that indicate the cyclic shift of the identity matrix and the row and column indices of these elements can be described, while the remaining row and column indices are assumed to indicate the elements of the all-zero square matrix. Alternatively, the elements indicating the cyclic shift of the identity matrix can be represented by their cyclic shift values, while the elements indicating the all-zero square matrix can be described by -1, null, or empty values.

[0047] To address this, this disclosure provides a data processing method. A first node can encode multiple information bit sequences to obtain multiple coded bit sequences. Interleaving X coded bit sequences among these sequences yields an interleaved bit sequence, thereby increasing the coupling between the X coded bit sequences. Furthermore, in higher-order modulation, information bits in the coded bit sequences are mapped to high-reliability bits of the modulation symbols, providing greater protection for the information bits, improving reception performance, and enhancing data transmission reliability. Thus, interleaving can distribute errors in certain coded bit sequences across all X coded bit sequences, reducing the probability of these errors being concentrated in one or a few sequences, leading to decoding failure in those sequences. This increases the robustness of signal transmission and improves data transmission quality.

[0048] The data processing method provided in this disclosure can be applied to systems with various communication standards. For example, the systems to which the data processing provided in this disclosure is applicable include, but are not limited to, long-term evolution (LTE) systems, various versions based on LTE evolution, 5th generation mobile communication technology (5G) systems, 5G-Advanced (5G-A) communication systems, future mobile communication networks (such as 6th generation mobile communication technology (6G) or 7th generation mobile communication technology (7G)), or multiple converged communication systems. Furthermore, the data processing method provided in this disclosure can also be applied to future-oriented communication systems.

[0049] For example, the above data processing method can be applied to the communication system shown in FIG1. ​​As shown in FIG1, the communication system includes: a first node 101 and a second node 102.

[0050] Here, the first node 101 can be a terminal-side device, such as an IoT device, a mobile phone, or an in-vehicle device. The second node 102 can be a network-side device, such as a communication base station or a sensing base station. Alternatively, the first node 101 can be a network-side device, and the second node 102 can be a terminal-side device.

[0051] In some embodiments, the first node 101 can interleave X coded bit sequences from multiple coded bit sequences to obtain an interleaved bit sequence. Then, the first node 101 can modulate the interleaved bit sequence to obtain a modulated symbol sequence. Afterwards, the first node 101 can transmit the modulated symbol sequence. Correspondingly, the second node 102 can receive the modulated symbol sequence and demodulate it to obtain a soft bit sequence. Then, the second node 102 can deinterleave the soft bit sequence to obtain multiple coded soft bit sequences. Thus, because the interleaving process can distribute burst errors in some of the X coded bit sequences across the X coded bit sequences, the original data can be better recovered during decoding, thereby improving the error resistance of the coded bit sequences, enhancing the robustness of data transmission, and improving the quality of data transmission.

[0052] In some embodiments, the terminal can be a device with wireless transceiver capabilities, which can be deployed on land, including indoors or outdoors, handheld, wearable, or vehicle-mounted; it can also be deployed on water (such as on ships); and it can also be deployed in the air (e.g., on airplanes, balloons, and satellites). The terminal can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, virtual reality (VR) terminal, augmented reality (AR) terminal, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical care, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. The embodiments of this application do not limit the application scenarios. The term "terminal" can sometimes also refer to a user, user equipment (UE), access terminal, UE unit, UE station, mobile station, mobile station, remote station, remote terminal, mobile device, UE terminal, wireless communication device, UE agent, or UE device, etc., but the embodiments of this application do not limit this to these terms.

[0053] In one possible implementation, the various types of UEs can also be mobile stations, user stations, mobile units, user cells, radio units, remote units, mobile devices, radio devices, wireless communication devices, remote devices, mobile user stations, access terminals, mobile terminals, radio terminals, remote terminals, handheld devices, user agents, mobile clients, clients, passive tags, or some other suitable term. Furthermore, the various types of UEs can also be cellular phones, personal digital assistants (PDAs), wireless modems, wireless communication devices, handheld devices, tablet computers, laptop computers, cordless phones, wireless local loop (WLL) stations, etc. The various types of UEs can communicate with various types of base stations and network equipment (including macro eNBs, small cell eNBs, relay base stations, etc.).

[0054] In some embodiments, the base station may be a base station in Long Term Evolution (LTE), Long Term Evolution Advanced (LTEA), or an evolved Node B (eNB, eNodeB, or gNodeB), a base station device in a 5G, 6G, or 7G network, or a base station in a future communication system, etc. The base station may include various macro base stations, micro base stations, femtocell base stations, wireless remote extensions, reconfigurable intelligent surfaces (RISs), routers, wireless fidelity (WIFI) devices, or various network-side devices such as primary cells and secondary cells.

[0055] It should be noted that Figure 1 is only an exemplary framework diagram. The number of devices included in Figure 1 and the names of each device are not limited. In addition to the devices shown in Figure 1, the communication system may also include other devices, such as relay nodes.

[0056] The application scenarios of the embodiments disclosed herein are not limited. The system architecture and business scenarios described in the embodiments of this disclosure are for the purpose of more clearly illustrating the technical solutions of the embodiments of this disclosure, and do not constitute a limitation on the technical solutions provided by the embodiments of this disclosure. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of this disclosure are also applicable to similar technical problems.

[0057] The data processing method provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0058] The data processing method provided in this embodiment can be applied to the first node 101 in the communication system shown in FIG1. ​​FIG2 shows a flowchart of a data processing method, which includes S201, S202, S203 and S204.

[0059] In S201, multiple information bit sequences are encoded to obtain multiple encoded bit sequences.

[0060] The first node can perform code block segmentation on the long original information to obtain multiple information bit sequences (also known as code block information bit sequences). After performing LDPC encoding on the multiple information bit sequences respectively, multiple encoded bit sequences can be obtained. In this way, the segmented code block information bit sequences can be adapted to LDPC encoding, thereby improving the encoding efficiency.

[0061] In one possible implementation, the multiple coded bit sequences are C coded bit sequences obtained based on LDPC encoding, where C is a positive integer greater than or equal to 1, and X is less than or equal to C. In this way, the first node can select X coded bit sequences from all C coded bit sequences for interleaving, thereby reducing the number of bit sequences to be processed and improving data processing efficiency. For example, the X coded bit sequences can be multiple consecutive coded bit sequences from the C coded bit sequences.

[0062] In S202, X coded bit sequences from multiple coded bit sequences are interleaved to obtain an interleaved bit sequence.

[0063] Here, X is an integer greater than 1. The interleaved bit sequence can be a single bit sequence (also called a bit stream), or it can consist of multiple sub-bit sequences. For example, the maximum value of X is one of the following: 2, 4, 6, 8, 10, 12, 16, 20, 24, or 32.

[0064] The purpose of interleaving is to rearrange the order of bits so that burst errors occurring during transmission can be dispersed, making them easier to correct with error-correcting codes (such as convolutional codes, Turbo codes, LDPC codes, etc.). In traditional methods, interleaving is usually performed within each coded block (i.e., the encoded bit sequence) to distribute errors at different locations within that block.

[0065] However, in this embodiment, the first node can perform interleaving between the X coded bit sequences (i.e., between the X coded blocks), distributing burst errors in each coded bit sequence across different coded bit sequences. This avoids situations where some coded bit sequences contain a large number of burst errors, making it impossible to reconstruct the original data. Thus, because burst errors in a few coded bit sequences are distributed across more coded bit sequences, the impact of burst errors is reduced during decoding, leading to better reconstruction of the original data. This improves the error resistance of the coded bit sequences, enhances the robustness of data transmission, and improves the quality of data transmission.

[0066] In S203, the interleaved bit sequence is modulated to obtain the modulated symbol sequence.

[0067] Here, modulation can also be called modulation mapping. A modulation symbol sequence includes multiple modulation symbols. For example, modulation methods for interleaved bit sequences can include binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), and quadrature amplitude modulation (QAM).

[0068] In one possible implementation, the modulation order of the modulation scheme can be equal to at least one of the following: 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16.

[0069] In S204, the modulation symbol sequence is transmitted.

[0070] After obtaining the interleaved bit sequence, it can be modulated and mapped based on the modulation order corresponding to the modulation scheme to obtain the modulation symbol sequence. This allows the first node to transmit the modulation symbol sequence, thus enhancing its resistance to burst errors during transmission, increasing transmission robustness, and improving signal transmission quality.

[0071] The above-mentioned coded bit sequence and modulation symbols will be described below.

[0072] I. Encoded Bit Sequence

[0073] In some embodiments, the index of the information bits (also called system bits) in the X coded bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence is less than or equal to the index of the parity bits in the X coded bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence. That is, the information bits are mapped to high-reliability bits in the mapping bit sequence of the modulation symbols, or bits with a bit error rate below a bit error rate threshold, or the index of the information bit in the mapping bit sequence is less than the index of the parity bit in the mapping bit sequence. For example, the information bits in each coded bit sequence can be preferentially mapped to the bit positions of high-reliability bits in the modulation symbols in the modulation symbol sequence (i.e., the bit positions with bit error rates below the bit error rate threshold mentioned above). In one example, the first S bits in the X coded bit sequences can be preferentially mapped to target bits in the modulation symbols in the modulation symbol sequence, where S is a positive integer. This can also be understood as the first S bits in the X coded bit sequences being information bits.

[0074] It should be noted that during modulation, the first node can divide all bits in the coded bit sequence into multiple mapped bit sequences. One mapped bit sequence, after modulation, yields a modulation symbol. Therefore, high-reliability bits in the mapped bit sequence can refer to bits with a bit error rate below the bit error rate threshold or bits with a large amplitude (absolute value) of the soft bits output from the demodulated modulation symbol.

[0075] In some other embodiments, a bit from the information bits of the m-th coded bit sequence in the X coded bit sequences is mapped to the 0th bit of the mapped bit sequence of a modulation symbol in the modulation symbol sequence, and a bit from the information bits of the n-th coded bit sequence in the X coded bit sequences is mapped to the 1st bit of the mapped bit sequence of a modulation symbol. Here, m and n are non-negative integers, and m is not equal to n. In this way, all the information bits in the X coded bit sequences can be mapped to the first two bits of the mapped bit sequence of the modulation symbol. This results in better reliability of the first two bits, a larger amplitude corresponding to the first two bits, a better bit error rate, and ensures the accuracy of information transmission.

[0076] In some other embodiments, X is determined based on the modulation order. For example, X can be an integer multiple of the modulation order, such as X being equal to a times the modulation order, where a is equal to 1, 2, 3, 4, 5, 6, 8, 10, 12, or 16.

[0077] In one possible implementation, the maximum value of X is determined by at least one of the following: coding rate, transport block size, data rate, target delay, target bit error rate, target reliability, terminal type, basic graph matrix index, or modulation order.

[0078] Here, delay generally refers to the time required for a data packet of a certain size to successfully (correctly) reach the receiver (sender) from the source (sender), which is the transmission delay. Air interface delay refers to the time required for a data packet of a certain size to successfully (correctly) reach the terminal from the base station, or the time required for a data packet of a certain size to successfully (correctly) reach the base station from the terminal. The target delay can be some target threshold for the transmission delay or air interface delay as described above. In one example, the target delay can be equal to at least one of the following: 0.05ms, 0.1ms, 0.2ms, 0.5ms, 0.8ms, 1ms, 2ms, 5ms, or 10ms.

[0079] Reliability refers to the probability of successfully and correctly receiving a data packet of a certain size sent from the source (sender) to the destination (receiver). Bit error rate (BER) refers to the probability of incorrectly receiving a data packet of a certain size sent from the source (sender) to the destination (receiver). Reliability is equal to the difference between 1 and the BER. For example, if the BER is 0.01, then the reliability or probability of correct reception is 1 - 0.01 = 0.99. This target reliability can be some target threshold for reliability or probability of correct reception as described above. In one example, the target reliability can be equal to at least one of the following: 1-10 -1 1-10 -2 1-10 -3 1-10 -4 1-10 -5 1-10 -6 1-10 -7 1-10 -8 The target bit error rate can be some target threshold for the probability of incorrect reception as described above. In one example, the target bit error rate can be equal to at least one of the following: 10 -1 10 -2 10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 In one example, the target bit error rate is 10. -1 In one example, the target bit error rate is 10. -6 In one example, the target bit error rate is 10. -4 .

[0080] II. Modulation Symbols

[0081] In some embodiments, the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence is composed of bits from different coded bit sequences. This avoids errors in one coded bit sequence being mapped into one modulation symbol, thereby dispersing errors within a coded bit sequence and improving the robustness of the modulation symbol.

[0082] For example, in a modulation symbol sequence, there exist at least Y modulation symbols whose mapped bits come from different coded bit sequences, where Y is a positive integer. For example, Y could be equal to the number of symbols in the modulation symbol sequence, half that number, or 1 / 4 or 1 / 8 of the number of symbols. In one example, Y could be equal to 1. Another example is that the mapped bit sequence is the sequence of bits mapped onto the modulation symbols.

[0083] In some other embodiments, the 0th bit of the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence comes from the information bit of the 0th coded bit sequence of X coded bit sequences; and / or, the last bit of the mapped bit sequence of at least one modulation symbol comes from the parity bit of the last coded bit sequence of X coded bit sequences.

[0084] For example, in a modulation symbol sequence, there exists at least one modulation symbol mapping bit sequence in which the first bit of the mapping bit sequence is the information bit (or the first S bits) of the first coded bit sequence among multiple coded bit sequences, and the last bit of the mapping bit sequence is the parity bit (e.g., the last M bits, where M is a positive integer) of the last coded bit sequence among multiple coded bit sequences.

[0085] The above describes the coded bit sequence and the modulation symbol sequence. In determining the coded bit sequence, multiple coded bit sequences are obtained by encoding multiple information bit sequences based on the target coding scheme. Here, the number of bits in at least one of the multiple information bit sequences is equal to the maximum number of information bits in the target coding scheme. For example, the target coding scheme can be LDPC encoding.

[0086] In some embodiments, the maximum number of information bits is the product of the number of information columns (also known as the system column number) of the target encoding scheme and the maximum boost value. The number of information columns is equal to the difference between the number of columns and the number of rows of the parity check matrix of the target encoding scheme. For example, in at least one of the C information bit sequences, the number of bits in that sequence equals the maximum number of information bits in the target encoding scheme. In one example, the maximum number of information bits is 8448, the number of columns in the parity check matrix is ​​68 and the number of rows is 46, the number of information columns is 22, and the corresponding maximum boost value is 384. In another example, the maximum number of information bits is 3840, the number of columns in the parity check matrix is ​​52 and the number of rows is 42, the number of information columns is 10, and the corresponding maximum boost value is 384.

[0087] In one possible implementation, the C-part information bit sequence is obtained by dividing the same transport block into code blocks.

[0088] The following will describe an embodiment of this disclosure using LDPC encoding as an example of the target encoding method.

[0089] Example 1: Let C information bit sequences be c 0 ,c 1 ,c 2 ,...,c C-1Each information bit sequence contains K bits (multiple information bit sequences have the same number of bits), where K is a positive integer. Here, the r-th information bit sequence c... r for r equals 0, 1, 2, ..., C-1. LDPC encoding of the C information bit sequence yields the C encoded bit sequence e. 0 ,e 1 ,e 2 ,...,e C-1 Here, the r-th encoded bit sequence e r for r equals 0, 1, 2, ..., C-1. The number of bits in each coded bit sequence is N.

[0090] Next, X coded bit sequences from the C coded bit sequences can be interleaved to obtain an interleaved bit sequence. This interleaved bit sequence is: f0, f1, f2, ..., f E-1 E is the number of bits in the interleaved bit sequence, and E is a positive integer. Subsequently, the interleaved bit sequence can be modulated to obtain the modulation symbol sequence: g0, g1, g2, ..., g G-1 G is the number of modulation symbols in the modulation symbol sequence, and G is a positive integer.

[0091] Here, the lifting value Z of LDPC encoding c The number of bits K in the information bit sequence can be determined. For example, as shown in Table 1, select one that satisfies the inequality condition K. b ·Z c The minimum lift value ≥ K' is denoted as Z. c For example, let K b The index of the promoted subset determined by 22 and K' is 200 (i LS If ) is 0, then Z can be determined from the subset of lift values. c When the value is 16, the above inequality is satisfied.

[0092] Table 1

[0093] In this example, the size of the LDPC-encoded fundamental graph matrix can be 46 rows (row indices i = 0, 1, 2, ..., 45) and 68 columns (column indices j = 0, 1, 2, ..., 67). Its fundamental graph matrix and its corresponding parity check matrix are defined in Table 2. The row and column indices (corresponding to i and j) of the '1' elements in the fundamental graph matrix are defined in Table 2; the remaining undefined index positions are '0' elements. As shown in Table 2, H... BG V is the fundamental graph matrix. i,jThe parity check matrix contains the value of the element in the i-th row and j-th column, where row index i is the row index of the basic graph matrix, column index j is the column index of the basic graph matrix, and set index i is the set index. LS This is the index of a subset of the parity check matrix. Table 2 shows the index of the basic graph matrix corresponding to the LDPC code as 1 (i.e., BG1, the basic graph matrix with index 1), with 46 rows and 64 columns.

[0094] Table 2

[0095] Figure 3 shows the structure of the basic graph matrix of LDPC encoding. The basic graph matrix can be divided into five sub-matrix blocks (also called sub-matrices): A, B, C, D, and E. Sub-matrix blocks A and B constitute the core matrix in the upper left corner of the basic graph matrix. The systematic number of columns in the basic graph matrix is ​​Kb. Then, the parity check matrix can be determined based on this basic graph matrix and the maximum lift value.

[0096] Here, the construction of the parity-check matrix H of LDPC encoding is as follows: The matrix is ​​constructed by replacing the '1' elements in the basic graph matrix with the cyclically shifted identity matrix, and the matrix is ​​constructed by replacing the '0' elements with an all-zero square matrix. The calculation process is as follows:

[0097] Replace the '0' elements in the basic graph matrix with elements of size Z. c ×Z c A square matrix of all zeros. Replace the '1' elements in the fundamental graph matrix with elements of size Z. c ×Z c The matrix I(P) after cyclic shift of the identity matrix i,j ), i and j are the row and column indices of the basic graph matrix, respectively, I(P i,j () is of size Z c ×Z c The identity matrix is ​​cyclically shifted P to the right. i,j The matrix obtained by P. i,j =mod(V i,j Z c V i,j It is based on the subset index i LS The index of the basic graph matrix is ​​determined from Table 2.

[0098] It should be noted that the difference between the number of rows and columns in the basic graph matrix is ​​equal to the number of information columns, Kb. For example, if the number of columns is 68 and the number of rows is 64, then the number of information columns, Kb, is 22, which is the difference between the number of rows and columns in the parity check matrix. With a maximum lift of 384, the maximum number of information bits in LDPC encoding is equal to 22 * ​​384 = 8448, which is the product of the number of information columns and the maximum lift.

[0099] The above describes the process of determining the parity check matrix for LDPC encoding. After determining the parity check matrix, the information bit sequence can be encoded according to the parity check matrix H of LDPC encoding to generate the parity bit sequence w = [w0, w1, w2, ..., w M-1 ] T Its satisfaction Where c = [c0, c1, c2, ..., c K-1 ] T 0 is a column vector of all zeros. The calculation in the encoding process is performed using GF(2). Since the parity check matrix H can be determined by the parity check matrix and the boost value, the LDPC encoding process can also be based on the parity check matrix and the boost value to encode the information bit sequence and generate the parity bit sequence. For example, LDPC encoding of C information bit sequences yields C parity bit sequences. Combining each information bit sequence with its corresponding parity bit sequence can obtain the mother code bit sequence corresponding to each information bit sequence. For example, the r-th mother code bit sequence d r for Here, N cb is a positive integer.

[0100] In one example, the r-th bit sequence of the mother code d r for It includes the r-th information bit sequence c r The index is greater than or equal to 2×Z c All r bits, including all bits of the r-th parity bit sequence. That is, the r-th parent code bit sequence d r include and

[0101] In another example, the r-th bit sequence of the mother code d r for It includes the r-th information bit sequence c r All bits in the sequence, including all bits in the r-th parity bit sequence.

[0102] In another example, the r-th bit sequence of the mother code d r Number of bits N cbThe r-th bit sequence of the mother code is determined by factors such as the maximum number of antenna layers, the maximum code rate, and the maximum modulation order. r For sequence The starting index is 2×Z. c Continuous N cb It consists of 10 bits. Here, N cb It can be equal to K-2×Z c +M, or equal to K+M.

[0103] In one example, from the r-th bit sequence of the mother code d r The r-th encoded bit sequence e is obtained by bit selection. r for In one example, the r-th coded bit sequence e is determined based on the redundancy version, and the redundancy version number of the currently transmitted data is denoted as rv. id ,rv id It can be equal to 0, 1, 2, or 3. The output bit sequence obtained after rate matching of the r-th code block is represented as e. k k = 0, 1, 2, ..., E r -1, r=0,...,C-1, its generation process is as follows pseudocode:

[0104] Here, the starting position k0 is based on the redundant version number rv id The base matrix index is determined by Table 3. For example, as shown in Table 3, different redundant version numbers correspond to different starting positions k0.

[0105] Table 3

[0106] In another example, from the r-th bit sequence of the mother code d r From all bits, we can obtain the r-th encoded bit sequence e. r for If the r-th bit sequence of the master code is d r If padding bits exist, then padding bits are not included.

[0107] In this example, the number of information bit sequences is C = 16, that is, C = 16 information bit sequences are c 0 ,c 1 ,c 2 ,...,c 15 The number of bits in each information bit sequence is K = 8448, and the r-th information bit sequence is c r for r equals 0, 1, 2, ..., 15. Using the LDPC encoding method described above, the lift value Z of the LDPC encoding can be determined. cEquals 384. LDPC encoding of this C information bit sequence yields C encoded bit sequences, each consisting of e... 0 ,e 1 ,e 2 ,...,e C-1 Here, the number of bits in each encoded bit sequence is equal to 9126, that is, the number of bits in the r-th encoded bit sequence e. r for r equals 0, 1, 2, ..., 15.

[0108] The above is an example description of encoding information bit sequences. The following will describe the encoding, interleaving, and modulation processes using different interleaving methods.

[0109] Method 1: Determine the bits in the X encoded bit sequences as a first bit sequence and perform interleaving.

[0110] Referring to Figure 2, as shown in Figure 4, the interleaving process between the X coded bit sequences in S202 specifically includes S401 and S402.

[0111] In S401, a first bit sequence is determined based on X coded bit sequences.

[0112] Here, the first part of the first bit sequence includes information bits from X encoded bit sequences, and the second part of the first bit sequence includes check bits from X encoded bit sequences. The first part precedes the second part. In one example, all bits from the first and second parts constitute the first bit sequence.

[0113] A first bit sequence can be obtained by rearranging all bits in multiple bit sequences. During this rearrangement, all information bits from the X coded bit sequences are placed at the beginning of the first bit sequence (the first part mentioned above), while all parity bits are placed at the end (the second part mentioned above). For example, the order of information bits in the first part is the same as the order of information bits in the X coded bit sequences, and the order of parity bits in the second part is the same as the order of parity bits in the X coded bit sequences. In this way, the information bits or parity bits in each coded bit sequence still follow the order of the bits in the coded bit sequence and the arrangement order of the X coded bit sequences, thus preserving the information carried by the X coded bit sequences and ensuring the accuracy of the information.

[0114] In S402, the first bit sequence is interleaved.

[0115] Here, the number of bits in the interleaved bit sequence is equal to the number of bits in the first bit sequence.

[0116] Since the first bit sequence includes all the bits of the X coded bit sequences, it can be interleaved to obtain an interleaved bit sequence. This alters the order of the X coded bit sequences, thus mitigating burst errors in the coded bit sequences and improving data transmission quality.

[0117] In some embodiments, the i+j·Q-th bit in the interleaved bit sequence m The i-th bit is equal to the i-th E / Q-th bit in the first bit sequence. m +j bits; here, j is less than or equal to E / Q. m -1 is a non-negative integer, and i is less than or equal to Q. m -1 is a non-negative integer, Q m Here, E is the modulation order, and E is the number of bits in the first bit sequence. Thus, when decoding, the receiver can reconstruct the first bit sequence before interleaving according to this correspondence, thereby recovering the original information and ensuring data accuracy.

[0118] For example, all the information bits of the X=16 encoded bit sequences can be placed at the beginning of the first bit sequence; all the parity bits of the X=16 encoded bit sequences can be placed at the end of the first bit sequence, and the first bit sequence can be interleaved to obtain an interleaved bit sequence.

[0119] As shown in Figure 5, the information bit sequence 510 (including information bits a0-a) 99 After encoding, the resulting encoded bit sequence is 520 (including information bits a0-a0). 99 And parity bits P0-P 99 The information bits a0-a in the encoded bit sequence 520 99 The parity bits P0-P are placed at the beginning of the first bit sequence 530. 99 It is placed at the end of the first bit sequence 530. The first bit sequence 530 is interleaved to obtain the interleaved bit sequence 540. After processing the interleaved bit sequence 540, the modulation symbol sequence 550 is obtained.

[0120] Here, the first bit sequence 530 has 146016 bits. The first bit sequence 530 is interleaved using the following formula to obtain the interleaved bit sequence 540: The i·E / Qth bit in the first bit sequence 530 m +j bits are assigned to the i+j·Q-th bit in the interleaved bit sequence. m 1 bit. j equals 0 to E / Q m -1 is any integer, i equals 0 to Q. many integer Q = -1 m It is the modulation order, E is the number of bits in the first bit sequence (equal to 146016), Q m Both E and f are positive integers, f is the interleaved bit sequence 540, and e is the first bit sequence 530. Then, the interleaved bit sequence 540 is modulated and mapped to obtain the modulated and mapped symbol sequence 550.

[0121] In one possible implementation, the modulation mapping scheme can be one of the following: BPSK, QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, or 4096QAM. Here, the number of bits in the BPSK modulation mapping bit sequence (i.e., the modulation symbol sequence mentioned above) is equal to 1 (i.e., the corresponding modulation order Q). m The number of bits in the mapped bit sequence of QPSK modulation is equal to 2 (i.e., the corresponding modulation order Q). m The number of bits in the mapped bit sequence of 16QAM modulation is equal to 4 (i.e., the corresponding modulation order Q). m The number of bits in the mapped bit sequence of 64QAM modulation is equal to 6 (i.e., the corresponding modulation order Q). m The number of bits in the mapped bit sequence of 256QAM modulation is equal to 8 (i.e., the corresponding modulation order Q). m The number of bits in the mapped bit sequence of 1024QAM modulation is equal to 10 (i.e., the corresponding modulation order Q). m The number of bits in the mapped bit sequence of 4096QAM modulation is equal to 12 (i.e., the corresponding modulation order Q). m (Equals 12).

[0122] The mapped bit sequence corresponding to a certain modulation scheme is set as follows: The index of each bit in the mapped bit sequence is from 0 to Q. m -1. Corresponds to BPSK modulation, Q m When the value equals 1, meaning the mapped bit sequence contains only 1 bit, and the mapped bit sequence is {0}, the modulation symbol is... When the mapped bit sequence is {1}, the modulation symbol is Corresponding to QPSK modulation, Q m When the value equals 2, meaning there are 2 bits in the mapped bit sequence, and the mapped bit sequence is {0, 0}, the modulation symbol is... When the mapped bit sequence is {0, 1}, the modulation symbol is: When the mapped bit sequence is {1, 0}, the modulation symbol is: When the mapped bit sequence is {1, 1}, the modulation symbol is: Here, j is the imaginary unit.

[0123] Here, in higher-order modulation, such as modulation order Q... m In modulation schemes with a modulation order greater than 2, when the mapped bit sequence is demodulated at the receiver, the average reliability (amplitude value) of the soft bits located earlier in the soft bit sequence (soft bit idx) is greater than or equal to the average reliability (amplitude value) of the soft bits located later in the soft bit sequence. That is, the modulation order Q... m In modulation schemes with a value greater than 2, the average reliability of the bits corresponding to the smaller index in the mapped bit sequence is greater than or equal to the average reliability of the bits corresponding to the larger index. As shown in Figure 6(1), the mapped bit sequence of 16QAM modulation includes 4 bits (i.e., Q... m Equal to 4), as shown in Figure 6(1), the average reliability (amplitude value or mean log likelihood ratio, LLR) relationship of the corresponding demodulated output soft bit sequence is shown. The average amplitude value of the 0th soft bit and the 1st soft bit is the largest, followed by the 2nd soft bit and the 3rd soft bit. The mapped bit sequence of 64QAM modulation includes 6 bits (i.e., Q). m Equal to 6), as shown in Figure 6(2), the average reliability (amplitude value) relationship of the corresponding demodulated output soft bit sequence is shown. The average amplitude value of the 0th and 1st soft bits is the largest, followed by the 2nd and 3rd soft bits, and the average amplitude value of the 4th and 5th soft bits is the smallest. The mapped bit sequence of 256QAM modulation includes 8 bits (i.e., Q). m Equal to 8), as shown in Figure 6 (3), the average reliability (amplitude value) relationship of the corresponding demodulated output soft bit sequence is shown. The average amplitude value of the 0th and 1st soft bits is the largest, followed by the 2nd and 3rd soft bits, then the 4th and 5th soft bits, and the average amplitude value of the 6th and 7th soft bits is the smallest. The mapped bit sequence of 1024QAM modulation includes 10 bits (i.e., Q). m As shown in Figure 6(4), the average reliability (amplitude value) relationship of the corresponding demodulated soft bit sequence is as follows: the average amplitude value of the 0th and 1st soft bits is the largest, followed by the 2nd and 3rd soft bits, then the 4th and 5th soft bits, then the 6th and 7th soft bits, and the average amplitude value of the 8th and 9th soft bits is the smallest. It can be seen that in the demodulated soft bit sequence, the average amplitude value of the soft bits with the first index (close to 0) is relatively large, that is, the reliability is relatively high.

[0124] In some other embodiments, during interleaving, the information bits of each coded bit sequence can be grouped to the beginning of the first bit sequence, and the parity bits of each coded bit sequence can be grouped to the end of the first bit sequence before symbol-level interleaving is performed. Furthermore, the average reliability (amplitude value) of the earlier soft bits in the demodulated soft bit sequence of the modulation symbol is higher. In this way, the interleaving method allows the information bits of each coded bit sequence to be preferentially mapped to the high-reliability bits in the first bit sequence, resulting in higher decoding performance.

[0125] Another example, as shown in Figure 7, illustrates the amplitude values ​​(or log-likelihood ratios (LLRs) of different soft bits (idx) in the information sequence obtained after the receiver performs demodulation and desymbol-level interleaving on the received data signal. Taking X=4 as an example, the X=4 coded bit sequences are interleaved using 16QAM modulation. {a0, a1, a2, a3} represent the soft bit sequences of the information bit sequences in the X=4 coded bit sequences, and {p0, p1, p2, p3} represent the soft bit sequences of the parity bit sequences in the X=4 coded bit sequences. It can be seen that the amplitude values ​​of the soft bits in the information bit sequences are larger, while the amplitude values ​​of the soft bits in the parity bit sequences are smaller. Furthermore, since all bits of multiple coded bit sequences have undergone interleaving, burst errors can be dispersed, thereby resisting the effects of various burst interferences.

[0126] Method 2: Perform interleaving processing on each encoded bit sequence separately, and then perform interleaving processing based on the matrix.

[0127] Referring to Figure 2, as shown in Figure 8, the interleaving process between the X coded bit sequences in the above S202 specifically includes S801 and S802.

[0128] In S801, multiple second bit sequences are determined based on X coded bit sequences.

[0129] Here, a second bit sequence is obtained by interleaving a single encoded bit sequence. That is, multiple second bit sequences are obtained by interleaving X encoded bit sequences separately. The number of multiple second bit sequences is equal to the number of X encoded bit sequences.

[0130] In some embodiments, the i+j·Q-th bit in the v-th second bit sequence m The i-th bit is equal to the i-th E / Q-th bit in the v-th coded bit sequence. m +j bits; here, Q m Let Q be the modulation order, E be the number of bits in the multiple second bit sequences, and i be less than or equal to Q.m A non-negative integer, j is less than or equal to E / Q. m A non-negative integer, v equals 0 to X-1.

[0131] For example, multiple second bit sequences can satisfy the following formula: The r-th encoded bit sequence e r The i·E r / Q m +j bits are assigned to the r-th bit sequence f. r The i+j·Q m Bits, here, j equals 0 to E r / Q m -1 is any integer, i equals 0 to Q. m any integer Q = -1 m It is the modulation order, E r Q is the number of bits in the r-th encoded bit sequence. m and E r All are positive integers, f r It is the r-th second bit sequence, e r It is the r-th encoded bit sequence, where r equals 0, 1, ..., X-1.

[0132] In S802, multiple second bit sequences are interleaved.

[0133] Interleaving can be performed between multiple second bit sequences. In this way, not only are burst errors in each encoded bit sequence distributed across that encoded bit sequence, but burst errors in each encoded bit sequence can also be distributed across multiple second bit sequences, thereby further improving robustness.

[0134] Method 3: First, interleave each encoded bit sequence separately to obtain multiple second bit sequences, and then determine the multiple second bit sequences as a first bit sequence for interleaving.

[0135] Referring to Figure 4 and as shown in Figure 9, in the above S401, determining a first bit sequence based on X encoded bit sequences specifically includes S901 and S902.

[0136] In S901, X encoded bit sequences are defined as multiple second bit sequences.

[0137] It should be understood that the method of determining X encoded bit sequences into multiple second bit sequences is the same as the method in S701 above, and will not be repeated here.

[0138] In S902, multiple second bit sequences are defined as a single first bit sequence.

[0139] The method of determining multiple second bit sequences into a first bit sequence is the same as the method of determining X encoded bit sequences into a first bit sequence in S401 above, and will not be repeated here.

[0140] After determining multiple second bit sequences as a first bit sequence, the first bit sequence can be interleaved according to the above S402 method, thereby further increasing robustness.

[0141] Method 4: Divide the X encoded bit sequences into groups and then perform interleaving.

[0142] In some embodiments, multiple coded bit sequences are divided into Y groups of coded bit sequences, and each group of coded bit sequences is interleaved; here, at least one group of coded bit sequences contains X coded bit sequences. Thus, X coded bit sequences from multiple coded bit sequences are divided into Y groups of coded bit sequences, and the multiple coded bit sequences in each group are interleaved to obtain an interleaved bit sequence.

[0143] In one possible implementation, the number of coded bit sequences contained in the Y groups of coded bit sequences is equal, that is, the number of coded bit sequences in each group of coded bit sequences is X.

[0144] In another possible implementation, the data in the coded bit sequence of group Y is X or X+1.

[0145] The following describes the methods for interleaving a first bit sequence or multiple second bit sequences in methods one through three.

[0146] In some embodiments, referring to FIG4 and as shown in FIG10, the interleaving process of the first bit sequence in S402 specifically includes S1001, S1002 and S1003.

[0147] In S1001, a first bit sequence is written into the first matrix column by column.

[0148] Here, the first matrix is ​​E / Q. m Q m A matrix of columns.

[0149] In one possible implementation, the first matrix can be an E / Q matrix. m Q m A column-wise blank matrix can be created by writing all the bits from the first bit sequence into all the blank positions of the first matrix column by column. Thus, the first matrix after writing the first bit sequence includes all the bits from the first bit sequence.

[0150] It should be noted that when the bits in the first bit sequence are written into the first matrix column by column, E / Q m Q can represent the number of modulation symbols obtained by modulating the first bit sequence. m It can represent the number of bits in a modulation symbol. Therefore, an E / Q... m Q m All bits in a row of the first matrix can be viewed as bits mapped to a single modulation symbol.

[0151] In S1002, at least one column of the first matrix is ​​interleaved to obtain the second matrix.

[0152] Interleaving can be performed on at least one column of the first matrix, thereby shuffling the bit order in the first bit sequence and distributing burst errors to more modulation symbols, thus increasing robustness.

[0153] In one possible implementation, at least one column in the first matrix does not require interleaving.

[0154] In another possible implementation, the interleaving process for at least two columns in the first matrix is ​​handled differently.

[0155] In S1003, all bits in the second matrix are read out row by row.

[0156] After interleaving, all bits can be read sequentially according to the rows of the second matrix to obtain the interleaved bit sequence. In this way, the order of the bits in the read interleaved bit sequence is rearranged compared to the first bit sequence, and its burst errors are distributed across multiple modulation symbols, thereby improving the robustness of the signal.

[0157] In one possible implementation, in steps S1001, S1002, and S1003 above, the first bit sequence can be written row-by-row into the first matrix, and then at least one row in the first matrix can be interleaved to obtain the second matrix. Afterward, all bits in the second matrix are read column-by-column to obtain the interleaved bit sequence.

[0158] In this embodiment of the disclosure, in step 1001 above, the method of writing multiple second bit sequences into the first matrix, followed by interleaving and reading out the bits, is the same as in steps S1001, S1002, and S1003 above, and will not be repeated here. It should be understood that the order in which the bits in the multiple second bit sequences are written into the first matrix is ​​the order of the multiple second bit sequences (i.e., the order of the X encoded bit sequences obtained after encoding).

[0159] In some other embodiments, referring to FIG4 and as shown in FIG11, the interleaving process of the first bit sequence in S402 specifically includes S1101, S1102 and S1103.

[0160] In S1101, a first bit sequence is written row by row into the third matrix.

[0161] Here, the third matrix is ​​Q. m E / Q m A matrix of columns.

[0162] In one possible implementation, the third matrix can be a Q. m E / Q m The blank matrix in the column can be used to write all the bits in the first bit sequence into all the blank positions in the third matrix row by row. In this way, the third matrix after writing the first bit sequence includes all the bits in the first bit sequence.

[0163] It should be noted that when writing the bits of the first bit sequence into the first matrix in order, E / Q... m Q can represent the number of modulation symbols obtained by modulating the first bit sequence. m It can represent the number of bits in a modulation symbol. Therefore, a Q... m E / Q m All bits in a column of the third matrix can be viewed as bits mapped to a single modulation symbol.

[0164] In S1102, at least one row of the third matrix is ​​interleaved to obtain the fourth matrix.

[0165] In one possible implementation, at least one row in the first matrix does not require interleaving.

[0166] In another possible implementation, the interleaving process for at least two rows in the first matrix is ​​handled differently.

[0167] In S1103, all bits in the fourth matrix are read out column by column.

[0168] After interleaving, all bits can be read sequentially according to the columns of the fourth matrix to obtain the interleaved bit sequence. In this way, the order of the bits in the read interleaved bit sequence is rearranged compared to the first bit sequence, and its burst errors are distributed across multiple modulation symbols, thereby improving the robustness of the signal.

[0169] In one possible implementation, in steps S1101, S1102, and S1103 above, the first bit sequence can be written column-wise into the third matrix, and then at least one column of the third matrix can be interleaved to obtain a fourth matrix. Afterward, all bits in the fourth matrix are read row-wise to obtain the interleaved bit sequence.

[0170] In this embodiment of the disclosure, in S1101 above, the method of writing multiple second bit sequences into a third matrix, followed by interleaving and reading out the bits, is the same as in S1101, S1102, and S1103 above, and will not be repeated here. It should be understood that the order in which the bits in the multiple second bit sequences are written into the third matrix is ​​the order of the multiple second bit sequences (i.e., the order of the X encoded bit sequences obtained after encoding).

[0171] For the above interleaving process, the interleaving method includes cyclic shift interleaving; the number of shifts in cyclic shift interleaving is determined by one of the following: the number of bits in the first bit sequence or the second bit sequence, the modulation order, the number of X coded bit sequences, the number of information bits in the coded bit sequence, and the number of parity bits in the coded bit sequence.

[0172] Here, the number of shifts is function(R / 2) i R represents the number of rows or columns of the first or third matrix, i is an integer less than or equal to the modulation order, and function() is the floor function; or, the shift amount is function((R / Q)). m )×i), R equals EQ m , i is an integer less than or equal to the modulation order, Q m Here, represents the modulation order, and `function()` is the floor function. If the EQ... m Not equal to an integer, R can be equal to the number of rows or columns of the first or third matrix.

[0173] When writing the first bit sequence or multiple second bit sequences according to the rows of the first matrix, R is the number of rows in the first matrix. When writing the first bit sequence or multiple second bit sequences according to the columns of the third matrix, R equals EQ. m `function(x)` is the integer function, which can represent taking the smallest integer greater than or equal to the real number `x`, the largest integer less than or equal to the real number `x`, or the integer obtained by rounding the real number `x`. For example, in the case of performing cyclic shifting and interleaving on the `i`th row or `i`th column of the first matrix, the shift amount is equal to `function((R / Q)`. m )×i), where i equals 0, 1, ..., Q m -1.

[0174] In some other embodiments, interleaving is performed on the first bit sequence based on interleaving parameters, which include at least one of the following: the modulation order of the modulation scheme corresponding to the modulation symbol sequence, the number of bits in the first bit sequence, and the number of X coded bit sequences.

[0175] The following will describe the process of the above interleaving with examples.

[0176] Example 2 describes the process of determining the first bit sequence and interleaving the first bit sequence.

[0177] Let X = 8. All information bits from the X = 8 encoded bit sequences are placed at the beginning of the first bit sequence; all parity bits from the X = 8 encoded bit sequences are placed at the end of the first bit sequence. The first bit sequence is then interleaved to obtain an interleaved bit sequence. As shown in Figure 5, the number of bits E in the first bit sequence 530 is equal to 73008. Assuming the mapping modulation method is 64QAM, the modulation order Q... m It equals 6.

[0178] Then, the first bit sequence is written into an EQ in column-major order. m Q m The first matrix of columns, as shown in Figure 12, is matrix 1210, with R = EQ rows. m =73008 / 6=12168, the number of columns is Q m =6. The order of writing to the first matrix is ​​column-major. For example, after writing 12168 bits of column 0 (corresponding to bits 0 to 12167 in the first bit sequence), then write 12168 bits of column 1 (corresponding to bits 12168 to 24335 in the first bit sequence), and so on, writing all bits of the first bit sequence into the first matrix. In the first matrix 1210 shown in Figure 12, the leftmost column is column 0, and the rightmost column is column Q. m -1 = 5 columns.

[0179] Interleaving at least one column of the first matrix yields the second matrix, which is then read row-majorly to obtain the interleaved bit sequence. In one example, as shown in Figure 13, a cyclic shift interleaving operation is performed on the first column of the second matrix. The number of shifts is equal to function(R / 2) (i.e., when i = 1, counting from 0). Here, function(x) represents the smallest integer greater than or equal to the real number x, and R is the number of rows in the first matrix. R equals 12168, meaning the number of cyclic shifts is 6084.

[0180] In another example, a cyclic shift interleaving operation is performed on the first column of the first matrix, with the number of shifts equal to function(R / 2). 2 =3042 (i.e., i=2, counting from 0), and the second matrix can be obtained after cyclic shifting and interleaving operations.

[0181] In another example, a cyclic shift interleaving operation is performed on the i-th column of the first matrix, and the number of shifts in the cyclic shift is equal to function(R / 2). i Let i be 0, 1, ..., 5. That is, the number of shifts in the cyclic shift of column 0 is 12168, the number of shifts in the cyclic shift of column 1 is 6084, the number of shifts in the cyclic shift of column 2 is 3042, the number of shifts in the cyclic shift of column 3 is 1521, the number of shifts in the cyclic shift of column 4 is 760, and the number of shifts in the cyclic shift of column 5 is 380. After the cyclic shift interleaving operation, the second matrix can be obtained.

[0182] As shown in Figure 13, after performing cyclic shifting to obtain the second matrix, all bits of the second matrix can be read out row-wise to obtain the interleaved bit sequence. The bits in column 0 of the second matrix are mapped to the 0th bit of the corresponding mapping bit sequence for each modulation symbol; the bits in column 1 are mapped to the 1st bit; the bits in column 2 are mapped to the 2nd bit; and so on, with the bits in column 5 mapped to the 5th bit. Since the writing order of the first matrix 1210 shown in Figure 12 is column-wise, and the reading order of the second matrix shown in Figure 13 is row-wise, it can be guaranteed that in the soft bits of the demodulated output at the receiving end, the soft bit reliability of the information bits (or the first K bits) of the X=8 encoded bit sequence is higher than that of its parity bits (or the last M bits). Furthermore, different column interleavings between different columns in the second matrix can create an interleaving effect between different encoded bit sequences, dispersing continuous burst interference into different encoded bit sequences to improve reception performance.

[0183] In one example, the remaining X = 8 encoded bit sequences (i.e., the 8th to 15th encoded bit sequences) in the encoded bit sequence are interleaved according to the modulation order to obtain the interleaved bit sequence, which is then modulated and transmitted. The processing operations are similar to those described above and will not be repeated here.

[0184] Example 3 describes the process of determining multiple second bit sequences and interleaving these multiple second bit sequences.

[0185] In this example, the basic graph matrix of the LDPC code has a size of 42 rows (row indices i = 0, 1, 2, ..., 41) and 52 columns (column indices j = 0, 1, 2, ..., 51). Its basic graph matrix and corresponding parity check matrix are defined in Table 5. The row and column indices of the '1' elements in the basic graph matrix are defined in Table 5, and the remaining undefined index positions are '0' elements. For example, in this example, the number of columns is 52 and the number of rows is 42, so the number of information columns Kb = 10; among the lift values ​​shown in Table 1, the maximum lift value is 384, so the maximum number of information bits for this LDPC code is 10 × 384 = 3840. Table 5 gives the basic graph matrix index 2 (i.e., BG2) corresponding to the LDPC code, with 42 rows and 52 columns.

[0186] Table 5

[0187] In addition, the starting position k0 is based on the redundant version number rv id The base matrix index is determined by Table 6. The r-th encoded bit sequence e is determined based on the starting position k0. r for

[0188] Table 6

[0189] In another example, from the r-th bit sequence of the mother code d r From all bits, we can obtain the r-th encoded bit sequence e. r for If the r-th bit sequence of the master code is d r If padding bits exist, then padding bits are not included.

[0190] In this example, the number of information bit sequences is C = 100, that is, C = 100 information bit sequences are c 0 ,c 1 ,c 2 ,...,c 99 The number of bits in each information bit sequence is K = 3840, and the r-th information bit sequence is c r for r equals 0, 1, 2, ..., 99. Using the LDPC encoding method described above, the lift value Z of the LDPC encoding can be determined. c Equals 384. LDPC encoding of this C=100 information bit sequence yields C=100 encoded bit sequences, each consisting of e... 0 ,e 1 ,e 2 ,...,e 99Here, the number of bits in each encoded bit sequence is equal to 19200, that is, the number of bits in the r-th encoded bit sequence e. r for r equals 0, 1, 2, ..., 99.

[0191] In this example, the X = 20 coded bit sequences in the coded bit sequence are interleaved according to the modulation order to obtain the interleaved bit sequence. For example, using 64QAM modulation, Q... m =6, the X=20 encoded bit sequence is the 0th to 19th encoded bit sequence in the encoded bit sequence. The interleaving process in this example includes:

[0192] First, each of the 20 encoded bit sequences is interleaved individually according to the following formula to obtain 20 second bit sequences: The r-th encoded bit sequence e r The i·E r / Q m +j bits are assigned to the r-th bit sequence f. r The i+j·Q m Bit, j equals 0 to E r / Q m -1 is any integer, i equals 0 to Q. m Any integer of -1, E r f is the number of bits in the r-th encoded bit sequence (equal to 19200 bits). r It is the r-th second bit sequence, e r It is the r-th encoded bit sequence, where r equals 0, 1, ..., 19.

[0193] Then, each of the 20 second bit sequences is written into an E / Q array in row-major order. m Q m The first matrix, E, is equal to the total number of bits in 20 encoded bit sequences (X = 20), i.e., E equals 20 * 19200 = 384000. Interleaving at least one column of the first matrix yields the second matrix. Then, the second matrix is ​​read row-majorly to obtain the interleaved bit sequence. It should be understood that interleaving any one or more columns can be performed using the interleaving methods described above, which will not be elaborated upon here.

[0194] Here, interleaving each of the 20 encoded bit sequences individually to obtain 20 second bit sequences results in interleaving where the soft bit reliability of the information bits is higher than that of their parity bits. This means that information bits are mapped to positions with higher reliability in the mapped bit sequence of the modulation symbols, and parity bits are mapped to positions with lower reliability, improving the accuracy of information bit decoding at the receiver. Furthermore, column-wise interleaving of the first matrix not only ensures the above characteristics—that information bits are preferentially mapped to positions with higher reliability in the mapped bit sequence—but also disperses continuous errors from burst interference across the encoded bit sequences, thereby reducing the impact of burst errors.

[0195] In another example, after performing the above data processing on the 0th to 19th encoded bit sequences, the above data processing is then performed on the 20th to 39th encoded bit sequences, and so on up to the 80th to 99th encoded bit sequences.

[0196] Example 4, Step 1: Determine a transport block with a number of bits A.

[0197] Step 2: Add a cyclic redundancy check (CRC) sequence to the transport block to obtain a CRC-added bit sequence with a bit count of B. Here, the CRC check sequence has 24 bits.

[0198] Step 3: Divide the bit sequence after adding CRC into code blocks to obtain C parts of the bit sequence, and add code block-level CRC check bits to each part of the bit sequence to obtain C parts of information bit sequence.

[0199] Here, when C equals 1, no code block-level CRC check bits are added, meaning the information bit sequence is the same as the segmented bit sequence; when C is greater than 1, code block-level CRC check bits are added to each segmented bit sequence to obtain C information bit sequences.

[0200] Step four: Perform LDPC encoding on the C information bit sequences to obtain C encoded bit sequences.

[0201] Let C be the information bit sequences c 0 ,c 1 ,c 2 ,...,c C-1 Each information bit sequence contains K bits, where K is a positive integer. Here, the r-th information bit sequence c r for r equals 0, 1, 2, ..., C-1.

[0202] Step 5: Perform LDPC encoding on the C information bit sequences to obtain C encoded bit sequences.

[0203] Here, the C encoded bit sequences are e 0 ,e 1 ,e 2 ,...,e C-1 Among them, the r-th encoded bit sequence e r for r equals 0, 1, 2, ..., C-1.

[0204] Step 6: Interleave the X coded bit sequences in the C coded bit sequences according to the modulation order to obtain the interleaved bit sequences.

[0205] Here, X is a positive integer less than or equal to C. The X portions of the encoded bit sequence are interleaved to obtain an interleaved bit sequence, which is: f0, f1, f2, ..., f E-1 E is the number of bits in the interleaved bit sequence, and E is a positive integer.

[0206] Step 7: Modulate the interleaved bit sequence to obtain the modulation symbol sequence.

[0207] Here, the interleaved bit sequence is modulated and mapped to obtain the modulation symbol sequence: g0, g1, g2, ..., g G-1 G is the number of symbols in the modulation symbol sequence, and G is a positive integer.

[0208] Step 8: Send the modulation symbol sequence.

[0209] In this example, for simplicity, we assume that after code block segmentation, we obtain C = 64 information bit sequences, each containing 8 bits, and after LDPC encoding, we obtain X = 64 encoded bit sequences, each containing 12 bits. It should be noted that this is only for illustrating the interleaving effect; in real-world communication examples, such a short information bit sequence length may not be used.

[0210] In one example, interleaving X = 8 encoded bit sequences can be performed as follows: All information bits of the X = 8 encoded bit sequences are placed at the beginning of the first bit sequence; all parity bits of the X = 8 encoded bit sequences are placed at the end of the first bit sequence. This first bit sequence is then interleaved to obtain an interleaved bit sequence with 96 bits. The first bit sequence is interleaved according to the following formula: The i-th E / Q-th bit in the first bit sequence m+j bits are assigned to the i+j·Q-th bit in the interleaved bit sequence. m Bit, j equals 0 to E / Q m -1 is any integer, i equals 0 to Q. m Any integer -1, E equals 96, f is the interleaved bit sequence, e is the first bit sequence, and the modulation scheme is 16QAM modulation. m =4. Modulation mapping is performed on the interleaved bit sequence to obtain the modulation symbol sequence. Modulation mapping is performed on the interleaved bit sequence to obtain the modulation symbol sequence: d0, d1, d2, ..., d G-1 G is the number of symbols in the modulation symbol sequence, and G equals 24.

[0211] As shown in Figure 14, the position indices of the mapped bit sequence for each modulation symbol sequence in the X = 8 encoded bit sequences are given. For example, the bit positions in the mapped bit sequence of the 0th symbol d0 are {0, 36, 72, 32}, the bit positions in the mapped bit sequence of the 1st symbol d1 are {1, 37, 73, 33}, and so on. 22 The bit in the mapped bit sequence has the position index {30, 66, 22, 94} in the 8-part encoded bit sequence, and the last 23rd symbol d 23 The bit positions in the mapped bit sequence are {31, 67, 23, 95} within the 8 encoded bit sequences. In Figure 14, the integers in the table represent the position indices within the X = 8 encoded bit sequences. For example, position indices {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11} correspond to the bit index of the 0th encoded bit sequence within the X = 8 encoded bit sequences, and position indices {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23} correspond to the bit index of the 1st encoded bit sequence within the X = 8 encoded bit sequences. For instance, as shown in Figure 14, the information bits are located in rows 0 to 2, and the check bits are located in rows 2 to 3. In the soft bits obtained by demodulation at the receiving end, corresponding to the soft bits in rows 0 and 1 in Figure 14, the average reliability of the soft bits is higher than that of the soft bits in rows 2 and 3. That is, the information bits in the encoded bit sequence are preferentially mapped to the earlier rows as shown in Figure 14.

[0212] In another example, the first bit sequence is written into a Q in row-major order. m =4 lines of E / Q m The first matrix has 24 columns. At least one row of the first matrix is ​​interleaved to obtain the second matrix. That is, the i-th row of the first matrix is ​​subjected to a cyclic shift and interleaving process, with the number of shifts equal to: function((R / Q)m )×i), where i equals 0, 1, ..., Q m -1, R equals E / Q m =24. That is, the number of cyclic shifts in row 0 is 0, the number of cyclic shifts in row 1 is 6, the number of cyclic shifts in row 2 is 12, and the number of cyclic shifts in row 8 is 18. As shown in Figure 15, compared with Figure 14, Figure 15 shows the mapping of each bit index in the X=8 coded bit sequence after interleaving each row to each modulation symbol. For example, the bit in the mapped bit sequence of symbol 0 d0 has the position index {0, 62, 88, 46} in the 8 coded bit sequence, the bit in the mapped bit sequence of symbol 1 d1 has the position index {1, 63, 89, 47} in the 8 coded bit sequence, and so on. Then, the interleaved bit sequence is obtained by reading the second matrix column-first, and then modulation mapping is performed to obtain the modulation symbol sequence: d0, d1, d2, ..., d G-1 G equals 24.

[0213] In another example, X = 6 coded bit sequences are interleaved, and 64QAM modulation is used. m =6, the following operation can be performed: interleave each of the X=6 encoded bit sequences individually according to the following formula to obtain X=6 second bit sequences: The r-th encoded bit sequence e r The i·E r / Q m +j bits are assigned to the r-th bit sequence f. r The i+j·Q m Bit, j equals 0 to E r / Q m -1 is any integer, i equals 0 to Q. m any integer Q = -1 m It is the modulation order, E r E is the number of bits in the r-th encoded bit sequence. r equals 12, f r It is the r-th second bit sequence, e r This is the r-th encoded bit sequence, where r equals 0, 1, ..., 5. Here, these X = 6 second bit sequences are written into a Q in row-major order. m =6 lines of E / Q m The first matrix has 12 columns. Interleaving is performed on at least one row of the first matrix, and a cyclic shift is performed on the i-th row of the first matrix. The number of shifts is equal to: function(R / 2) i ), where i equals 0, 1, ..., Q m-1, R equals EQ m =12. That is, the number of cyclic shifts in row 0 is equal to 0, the number of cyclic shifts in row 1 is equal to 6, the number of cyclic shifts in row 2 is equal to 12, and the number of cyclic shifts in row 8 is equal to 18. As shown in (1) of Figure 16, this is the first matrix before interleaving. Here, the number in the 0th dashed box from the leftmost position represents the 0th coded bit sequence e in X = 6 coded bit sequences. 0 The index positions of all bits; the number within the first dashed box represents the first coded bit sequence e in the X = 6 coded bit sequences. 1 The index positions of all bits are determined accordingly; the second matrix after interleaving is shown in Figure 16(2). The bit positions in the mapped bit sequence of the 0th symbol d0 are {36, 51, 65, 6, 8, 10} in the 8 encoded bit sequences, and the bit positions in the mapped bit sequence of the 1st symbol d1 are {37, 62, 4, 7, 9, 11} in the 8 encoded bit sequences, and so on. Then, the interleaved bit sequence is obtained by reading the second matrix column-wise, and then modulation mapping is performed to obtain the modulation symbol sequence: d0, d1, d2, ..., d G-1 G equals 12.

[0214] The data processing method provided in this embodiment can be applied to the second node 102 in the communication system shown in FIG1. ​​FIG17 shows a schematic flowchart of another data processing method. As shown in FIG17, the data processing method includes the following: S1701-S1704.

[0215] In S1701, the modulation symbol sequence is received.

[0216] In S1702, the modulation symbol sequence is demodulated to obtain a soft bit sequence.

[0217] In S1703, all soft bits of the X encoded bit sequences in the soft bit sequence are deinterleaved to obtain multiple encoded soft bit sequences.

[0218] Here, X is an integer greater than 1.

[0219] In S1704, multiple information bit sequences are obtained by decoding based on multiple encoded soft bit sequences.

[0220] After receiving the modulation symbol sequence, the second node can demodulate it to obtain a soft bit sequence, which is the bit sequence corresponding to the interleaved bit sequence after the first node's interleaving process. Therefore, the first node also needs to deinterleave the soft bit sequences corresponding to the X coded bit sequences in the soft bit sequence to obtain multiple coded soft bit sequences, which are the bit sequences corresponding to the coded bit sequences after the first node's encoding process. In this way, the second node can decode based on multiple coded soft bit sequences to obtain multiple information bit sequences.

[0221] Since all soft bit sequences corresponding to the X coded bit sequences in the soft bit sequence of the modulation symbol sequence are obtained by interleaving the X coded bit sequences, some burst errors in the X coded bit sequences are distributed across more coded bit sequences. This reduces the impact of burst errors on one or several coded bit sequences, thereby increasing the robustness of the modulation symbol sequence and improving the accuracy of information transmission.

[0222] It should be noted that for descriptions of encoded bit sequences, interleaved bit sequences, etc., please refer to the description of the first node, and will not be repeated here in the embodiments of this disclosure.

[0223] It is understood that, in order to achieve the above-mentioned functions, the data processing apparatus includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the algorithmic steps of the examples described in conjunction with the embodiments of this disclosure, this disclosure can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0224] This disclosure embodiment can divide the data processing device into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one functional module. The integrated module can be implemented in hardware or software. It should be noted that the module division in this disclosure embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the example of dividing each functional module according to each function.

[0225] Figure 18 is a schematic diagram of a communication device provided in an embodiment of this disclosure. The communication device can execute the data processing method provided in the above-described method embodiment. As shown in Figure 18, the communication device includes a processing unit 1801 and a transmitting unit 1802.

[0226] The processing unit 1801 is used to encode multiple information bit sequences to obtain multiple encoded bit sequences.

[0227] The processing unit 1801 is further configured to perform interleaving processing on X coded bit sequences among the plurality of coded bit sequences to obtain an interleaved bit sequence, wherein X is an integer greater than 1.

[0228] The processing unit 1801 is also used to modulate the interleaved bit sequence to obtain a modulated symbol sequence;

[0229] The transmitting unit 1802 is used to transmit the modulation symbol sequence.

[0230] In one possible implementation, the information bits in the X coded bit sequences are mapped to the target bits in the modulation symbols of the modulation symbol sequence.

[0231] In one possible implementation, the index of the information bits in the X coded soft bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence is less than or equal to the index of the parity bits in the X coded bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence.

[0232] In one possible implementation, the reliability of the information bits in the X coded bit sequences mapped to the corresponding modulation symbol mapping bit sequences in the modulation symbol sequence is higher than the reliability of the parity bits in the X coded bit sequences mapped to the corresponding modulation symbol mapping bit sequences in the modulation symbol sequence.

[0233] In one possible implementation, a bit in the information bit of the m-th coded bit sequence of the X coded bit sequences is mapped to the 0th bit in the mapped bit sequence of a modulation symbol in the modulation symbol sequence, and a bit in the information bit of the n-th coded bit sequence of the X coded bit sequences is mapped to the 1st bit in the mapped bit sequence of the modulation symbol, where m and n are non-negative integers, and m is not equal to n.

[0234] In one possible implementation, the plurality of encoded bit sequences are C encoded bit sequences obtained by low-density parity-check coding (LDPC) of the plurality of information bit sequences, where C is a positive integer greater than 1 and X is less than or equal to C.

[0235] In one possible implementation, the X coded bit sequences are X consecutive coded bit sequences among the plurality of coded bit sequences.

[0236] In one possible implementation, the maximum value of X is one of the following: 2, 4, 6, 8, 10, 12, 16, 20, 24 or 32.

[0237] In one possible implementation, the maximum value of X is determined by at least one of the following: coding rate, transport block size, data rate, target delay, target bit error rate, target reliability, terminal type, basic graph matrix index, or modulation order.

[0238] In one possible implementation, the modulation order is any one of the following: 4, 6, 8, 10, or 12.

[0239] In one possible implementation, the number X of the coded bit sequence is determined based on the modulation order.

[0240] In one possible implementation, the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence is composed of bits from different coded bit sequences. In one example, the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence is composed of bits from z different coded bit sequences, where z equals Q. m / 2 or Q m , where Q m The modulation order is denoted by . The mapped bit sequence of at least one modulation symbol in the modulation symbol sequence includes at least one information bit from the z coded bit sequences.

[0241] In one possible implementation, the 0th bit of the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence comes from the information bit of the 0th coded bit sequence in the X coded bit sequences; and / or,

[0242] The last bit of the mapped bit sequence of at least one modulation symbol comes from the parity bit of the last encoded bit sequence among the X encoded bit sequences.

[0243] In one possible implementation, the processing unit 1801 is specifically configured to: determine a first bit sequence based on the X coded bit sequences, and perform interleaving processing on the first bit sequence to obtain the interleaved bit sequence; wherein, the first bit sequence includes all bits in the X coded bit sequences;

[0244] Alternatively, multiple second bit sequences are determined based on the X encoded bit sequences, and the multiple second bit sequences are interleaved to obtain the interleaved bit sequence; wherein, one second bit sequence is obtained by interleaving one of the encoded bit sequences separately.

[0245] In one possible implementation, the processing unit 1801 is specifically used to: determine a plurality of second bit sequences based on the X coded bit sequences;

[0246] The plurality of second bit sequences are used to determine the first bit sequence.

[0247] In one possible implementation, a first portion of the first bit sequence includes information bits from the X coded bit sequences, and a second portion of the first bit sequence includes check bits from the X coded bit sequences, with the first portion preceding the second portion. In one example, all bits from the first and second portions constitute the first bit sequence.

[0248] In one possible implementation, the i+j·Q-th bit in the v-th bit sequence of the second bit... m The i-th bit is equal to the i-th E / Q-th bit in the v-th coded bit sequence. m +j bits, v equals 0 to X-1;

[0249] Among them, Q m Let E be the modulation order, E be the number of bits in the plurality of second bit sequences, and i be less than or equal to Q. m A non-negative integer, j is less than or equal to E / Q. m . a non-negative integer.

[0250] In one possible implementation, the i+j·Q-th bit in the interleaved bit sequence m The i-th bit is equal to the i-th E / Q-th bit in the first bit sequence. m +j bits;

[0251] Among them, Q m Let Q be the modulation order, E be the number of bits in the first bit sequence, and i be a number less than or equal to Q. m A non-negative integer, j is less than or equal to E / Q. m . a non-negative integer.

[0252] In one possible implementation, the processing unit 1801 is specifically configured to: perform interleaving processing on the first bit sequence or the plurality of second bit sequences based on interleaving parameters, wherein the interleaving parameters include at least one of the following: modulation order, number of bits in the first bit sequence, and X.

[0253] In one possible implementation, the processing unit 1801 is specifically configured to: write the first bit sequence column-wise into a first matrix, wherein the first matrix is ​​an E / Q matrix. m Q m A column matrix; Q mWhere E is the modulation order, and E is the number of bits in the first bit sequence;

[0254] Interleave at least one column of the first matrix to obtain the second matrix;

[0255] Read all bits in the second matrix row by row;

[0256] Processing unit 1801 is specifically used for:

[0257] The first bit sequence is written row-wise into a first matrix, the first matrix being E / Q. m Q m A column matrix; Q m Where E is the modulation order, and E is the number of bits in the first bit sequence;

[0258] Interleave at least one row of the first matrix to obtain the second matrix;

[0259] Read all the bits in the second matrix column by column.

[0260] In one possible implementation, the processing unit 1801 is specifically used for:

[0261] The plurality of second bit sequences are written row-wise into a third matrix, the third matrix being an E / Q matrix. m Q m A column matrix; Q m Where E is the modulation order, and E is the number of bits in the plurality of second bit sequences;

[0262] Interleave at least one column of the third matrix to obtain the fourth matrix;

[0263] Read all bits in the fourth matrix row by row; or...

[0264] The interleaving process for the plurality of second bit sequences includes:

[0265] The plurality of second bit sequences are written column-wise into a third matrix, the third matrix being Q. m E / Q m A column matrix; Q m Where E is the modulation order, and E is the number of bits in the plurality of second bit sequences;

[0266] Interleave at least one row of the third matrix to obtain the fourth matrix;

[0267] Read all the bits in the fourth matrix column by column.

[0268] In one possible implementation, the interleaving process includes cyclic shift interleaving;

[0269] The number of shifts in the cyclic shift interleaving is determined by at least one of the following: the number of bits in the first bit sequence, the modulation order, the number of the X coded bit sequences, the number of information bits in the coded bit sequences, and the number of parity bits in the coded bit sequences.

[0270] In one possible implementation, the number of shifts is function(R / 2) i R equals E / Q m , i is a positive integer less than or equal to the modulation order, function() is a rounding function, which can represent taking the smallest integer greater than or equal to the input parameter, or taking the largest integer less than or equal to the input parameter, or taking the integer obtained by rounding the input parameter;

[0271] Alternatively, the shift amount is function((R / Q) m R equals E / Q (1 / Q) × i). m i is a positive integer less than or equal to the modulation order, Q m Let be the modulation order, and function() be the floor function.

[0272] In one possible implementation, the plurality of coded bit sequences are obtained by encoding a plurality of information bit sequences based on a target encoding method;

[0273] The number of bits in at least one of the plurality of information bit sequences is equal to the maximum number of information bits in the target encoding scheme.

[0274] In one possible implementation, the maximum number of information bits is the product of the number of information columns in the target encoding scheme and the maximum boost value, wherein the number of information columns is equal to the difference between the number of columns and the number of rows in the parity check matrix of the target encoding scheme.

[0275] In one possible implementation, the processing unit 1801 is specifically used to: divide the plurality of coded bit sequences into Y groups of coded bit sequences, and perform the interleaving process on each group of coded bit sequences; wherein at least one group of coded bit sequences contains X coded bit sequences, and Y is a positive integer.

[0276] In one possible implementation, the Y groups of coded bit sequences contain an equal number of coded bit sequences.

[0277] In one possible implementation, the number of coded bit sequences contained in the Y group of coded bit sequences includes two options: X and X+1.

[0278] In one possible implementation, the transmitting unit 1802 may include a single antenna or multiple antennas.

[0279] In one possible implementation, as shown in FIG19, the processing unit 1801 may further include an encoding unit 1901, an interleaving unit 1902, and a modulation unit 1903.

[0280] The encoding unit 1901 is used to encode multiple information bit sequences to obtain multiple encoded bit sequences.

[0281] Interleaving unit 1902 is used to interleave X coded bit sequences among the plurality of coded bit sequences to obtain an interleaved bit sequence, wherein X is an integer greater than 1.

[0282] The modulation unit 1903 is also used to modulate the interleaved bit sequence to obtain a modulation symbol sequence.

[0283] Figure 20 is a schematic diagram of another communication device provided in an embodiment of this disclosure. The communication device can execute the data processing method provided in the above-described method embodiments. As shown in Figure 20, the communication device includes a receiving unit 2001 and a processing unit 2002.

[0284] Receiver unit 2001 is used to receive modulation symbol sequences;

[0285] Processing unit 2002 is used to demodulate the modulation symbol sequence to obtain a soft bit sequence;

[0286] The processing unit 2002 is further configured to perform deinterleaving processing on all soft bits of the X coded bit sequences in the soft bit sequence, and obtain multiple coded soft bit sequences, wherein X is an integer greater than 1;

[0287] The processing unit 2002 is also used to decode the plurality of encoded soft bit sequences to obtain a plurality of information bit sequences.

[0288] In one possible implementation, the index of the information bits in the X coded soft bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence is less than or equal to the index of the parity bits in the X coded bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence.

[0289] In one possible implementation, at least one bit of the information bits of the m-th coded soft bit sequence in the X coded soft bit sequences is mapped to the 0th bit of the mapped bit sequence of a modulation symbol in the modulation symbol sequence, and at least one bit of the information bits of the n-th coded soft bit sequence in the X coded soft bit sequences is mapped to the 1st bit of the mapped bit sequence of the modulation symbol, where m and n are non-negative integers, and m is not equal to n.

[0290] In one possible implementation, the plurality of encoded soft bit sequences are C encoded soft bit sequences obtained by LDPC encoding the plurality of information bit sequences.

[0291] Where C is a positive integer greater than 1, and X is less than or equal to C.

[0292] In one possible implementation, the X coded soft bit sequences are X consecutive coded soft bit sequences among the plurality of coded soft bit sequences.

[0293] In one possible implementation, the maximum value of X is determined by at least one of the following: coding rate, transport block size, data rate, target delay, target bit error rate, target reliability, terminal type, basic graph matrix index, or modulation order.

[0294] In one possible implementation, the number of the plurality of coded soft bit sequences is determined based on the modulation order.

[0295] In one possible implementation, the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence is composed of bits from different encoded soft bit sequences.

[0296] In one possible implementation, the 0th bit of the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence comes from the information bit of the 0th coded soft bit sequence in the plurality of coded soft bit sequences; and / or,

[0297] The last bit of the mapped bit sequence of at least one modulation symbol comes from the parity bit of the last encoded soft bit sequence among the plurality of encoded soft bit sequences.

[0298] In one possible implementation, the transmitting unit 2001 may include a single antenna or multiple antennas.

[0299] In one possible implementation, as shown in FIG21, the processing unit 2002 may further include a demodulation unit 2101, a deinterleaving unit 2102, and a decoding unit 2103.

[0300] The demodulation unit 2101 is used to demodulate the modulation symbol sequence to obtain a soft bit sequence.

[0301] The deinterleaving unit 2102 is used to deinterleave all soft bits of the X coded bit sequences in the soft bit sequence and obtain multiple coded soft bit sequences, where X is an integer greater than 1;

[0302] Decoding unit 2103 is used to decode the plurality of encoded soft bit sequences to obtain a plurality of information bit sequences.

[0303] In the case of implementing the functions of the integrated modules described above in hardware, this disclosure provides another possible structure for the communication device involved in the above embodiments. As shown in FIG22, the communication device 220 includes: a processor 2202 and a bus 2204. Optionally, the communication device may further include a memory 2201 (also referred to as a storage medium); optionally, the communication device may further include a communication interface 2203.

[0304] Processor 2202 may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 2202 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 2202 may also be a combination of functions implementing computation, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0305] Processor 2202 can perform the following steps:

[0306] Step 1: Perform LDPC encoding on the C information bit sequences to obtain C encoded bit sequences, where C is an integer greater than 1.

[0307] Step 2: Interleave X coded bit sequences from the C coded bit sequences according to the modulation order to obtain the interleaved bit sequence, where X is an integer less than or equal to C.

[0308] Step 3: Modulate the interleaved bit sequence to obtain the modulated symbol sequence.

[0309] Step 4: Send the modulation symbol sequence through communication interface 2203.

[0310] Processor 2202 can also perform the following steps:

[0311] Step 1: Receive the modulation symbol sequence through communication interface 2203.

[0312] Step 2: Demodulate the modulation symbol sequence to obtain the soft bit sequence.

[0313] Step 3: Deinterleave multiple soft bit sequences in the soft bit sequence to obtain multiple coded soft bit sequences.

[0314] Step 4: Perform LDPC decoding on multiple encoded soft bit sequences to obtain multiple information bit sequences.

[0315] The communication interface 2203 is used to connect to other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0316] The memory 2201 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0317] As one possible implementation, the memory 2201 can exist independently of the processor 2202. The memory 2201 can be connected to the processor 2202 via a bus 2204 and is used to store instructions or program code. When the processor 2202 calls and executes the instructions or program code stored in the memory 2201, it can implement the data processing method provided in the embodiments of this disclosure.

[0318] In another possible implementation, the memory 2201 can also be integrated with the processor 2202.

[0319] In another possible implementation, the memory 2201 may further include data storage 2205 and processing instructions 2206. The data storage 2205 can be used as a local cache for information bit sequences, encoded bit sequences, parity matrices, transport blocks, and boost values, etc. The processing instructions 2206 are used to store processing instructions on how to encode, interleave, decode, deinterleave, etc., the data stored in the data storage 2205.

[0320] Bus 2204 can be an extended industry standard architecture (EISA) bus, etc. Bus 2204 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in Figure 22, but this does not mean that there is only one bus or one type of bus.

[0321] Some embodiments of this disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) storing computer program instructions that, when executed on a computer, cause the computer to perform a data processing method as described in any of the above embodiments.

[0322] For example, the computer-readable storage media described above may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0323] This disclosure provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the data processing method described in any of the above embodiments. The above descriptions are merely specific implementations of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions within the technical scope disclosed in this disclosure should be covered within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

A data processing method, wherein, The method includes: Multiple information bit sequences are encoded to obtain multiple encoded bit sequences; Interleave X coded bit sequences among the plurality of coded bit sequences to obtain an interleaved bit sequence, where X is an integer greater than 1; The interleaved bit sequence is modulated to obtain a modulated symbol sequence; The modulation symbol sequence is transmitted. The method of claim 1, wherein, The index of the information bit in the X coded bit sequence mapped to the mapping bit sequence of the modulation symbol in the modulation symbol sequence is less than or equal to the index of the parity bit in the X coded bit sequence mapped to the mapping bit sequence of the modulation symbol in the modulation symbol sequence. The method of claim 1, wherein, One bit of the information bit of the m-th coded bit sequence in the X coded bit sequences is mapped to the 0th bit of the mapping bit sequence of a modulation symbol in the modulation symbol sequence, and one bit of the information bit of the n-th coded bit sequence in the X coded bit sequences is mapped to the 1st bit of the mapping bit sequence of the modulation symbol, where m and n are non-negative integers, and m is not equal to n. The method of claim 1, wherein, The plurality of encoded bit sequences are C encoded bit sequences obtained by low-density parity-check code (LDPC) encoding of the plurality of information bit sequences, where C is a positive integer greater than 1, and X is less than or equal to C. The method of claim 1, wherein, The X coded bit sequences are X consecutive coded bit sequences among the plurality of coded bit sequences. According to the method of claim 1, wherein, The maximum value of X is one of the following: 2, 4, 6, 8, 10, 12, 16, 20, 24 or 32. According to the method of claim 1, wherein, The maximum value of X is determined by at least one of the following: coding rate, transport block size, data rate, target delay, target bit error rate, target reliability, terminal type, basic graph matrix index, or modulation order. According to the method of claim 1, wherein, The modulation order is any one of the following: 4, 6, 8, 10 or 12. According to the method of claim 1, wherein, The number X of the encoded bit sequence is determined based on the modulation order. According to the method of claim 1, wherein, The mapped bit sequence of at least one modulation symbol in the modulation symbol sequence is composed of bits from different encoded bit sequences. According to the method of claim 1, wherein, The 0th bit of the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence comes from the information bit of the 0th coded bit sequence in the X coded bit sequences; and / or, The last bit of the mapped bit sequence of the at least one modulation symbol comes from the parity bit of the last encoded bit sequence among the X encoded bit sequences. The method of claim 1, wherein, The interleaving process between X coded bit sequences in the plurality of coded bit sequences includes: A first bit sequence is determined based on the X coded bit sequences, and the first bit sequence is interleaved to obtain the interleaved bit sequence; wherein, the first bit sequence includes all bits in the X coded bit sequences; Alternatively, multiple second bit sequences are determined based on the X encoded bit sequences, and the multiple second bit sequences are interleaved to obtain the interleaved bit sequence; wherein, one second bit sequence is obtained by interleaving one of the encoded bit sequences separately. The method of claim 12, wherein, Determining a first bit sequence based on the X coded bit sequences includes: Multiple second bit sequences are determined based on the X encoded bit sequences; The plurality of second bit sequences are used to determine the first bit sequence. The method according to claim 12, wherein, The first part of the first bit sequence includes information bits from the X encoded bit sequences, and the second part of the first bit sequence includes check bits from the X encoded bit sequences. The first part precedes the second part. The method according to claim 12 or 13, wherein, The i+j·Q-th bit in the v-th bit sequence of the second bit sequence m The i-th bit is equal to the i-th E / Q-th bit in the v-th coded bit sequence. m +j bits, v equals 0 to X-1; wherein Q m is a modulation order, E is a number of bits in the plurality of second bit sequences, i is a non-negative integer less than or equal to Q m , and j is a non-negative integer less than or equal to E / Q m . The method of claim 12, wherein, The i+j·Q-th bit sequence in the interleaved bit sequence m The i-th bit is equal to the i-th E / Q-th bit in the first bit sequence. m +j bits; wherein Q m is a modulation order, E is a number of bits in the first bit sequence, i is a non-negative integer less than or equal to Q m , and j is a non-negative integer less than or equal to E / Q m . The method of claim 12, wherein, The interleaving process of the first bit sequence or the interleaving process of the plurality of second bit sequences includes: The first bit sequence or the plurality of second bit sequences are interleaved based on interleaving parameters, wherein the interleaving parameters include at least one of the following: modulation order, number of bits in the first bit sequence, and X. The method of claim 12, wherein, The interleaving process for the first bit sequence includes: writing the one first bit sequence column-wise into a first matrix, the first matrix being E / Q m row Q m column-wise into a first matrix, the first matrix being E / Q m is a modulation order, E is a number of bits in the first bit sequence; Interleave at least one column of the first matrix to obtain the second matrix; Read all bits in the second matrix row by row; or... The interleaving process for the first bit sequence includes: The one first bit sequence is written into a first matrix by row, the first matrix being Q m Row E / Q m Column matrix; Q m is a modulation order, E is a number of bits in the first bit sequence; Interleave at least one row of the first matrix to obtain the second matrix; Read all the bits in the second matrix column by column. The method of claim 12, wherein, The interleaving process for the plurality of second bit sequences includes: writing the plurality of second bit sequences by row into a third matrix, the third matrix being E / Q m row Q m matrix of columns; Q m is a modulation order, E is a number of bits in the plurality of second bit sequences; Interleave at least one column of the third matrix to obtain the fourth matrix; Read all bits in the fourth matrix row by row; or... The interleaving process for the plurality of second bit sequences includes: writing the plurality of second bit sequences column-wise into a third matrix, the third matrix being Q m row E / Q m matrix of columns; Q m is a modulation order, E is a number of bits in the plurality of second bit sequences; Interleave at least one row of the third matrix to obtain the fourth matrix; Read all the bits in the fourth matrix column by column. The method of claim 18 or 19, wherein, The interleaving process includes cyclic shift interleaving; The number of shifts in the cyclic shift interleaving is determined by at least one of the following: the number of bits in the first bit sequence, the modulation order, the number of the X coded bit sequences, the number of information bits in the coded bit sequences, and the number of parity bits in the coded bit sequences. The method of claim 20, wherein, The shift quantity is function ( R / 2 i ), R is equal to E / Q m , i is a positive integer less than or equal to the modulation order, and function() is a rounding function. or the shift quantity is function((R / Q m ) x i), R equals E / Q m , i is a positive integer less than or equal to the modulation order, Q m is the modulation order, and function( ) is a rounding function. The method of claim 1, wherein, The multiple coded bit sequences are obtained by encoding multiple information bit sequences based on the target encoding method; The number of bits in at least one of the plurality of information bit sequences is equal to the maximum number of information bits in the target encoding scheme. The method of claim 22, wherein, The maximum number of information bits is the product of the number of information columns in the target encoding method and the maximum boost value, where the number of information columns is equal to the difference between the number of columns and the number of rows in the parity check matrix of the target encoding method. The method of claim 1, wherein, The step of interleaving X coded bit sequences among the plurality of coded bit sequences to obtain an interleaved bit sequence includes: The plurality of coded bit sequences are divided into Y groups of coded bit sequences, and the interleaving process is performed on each group of coded bit sequences; wherein, at least one group of coded bit sequences contains X coded bit sequences, and Y is a positive integer. The method of claim 24, wherein, The Y-group coded bit sequences contain an equal number of coded bit sequences. The method of claim 24, wherein The number of coded bit sequences contained in the Y group of coded bit sequences It includes the following two types: X and X+1. According to the method of claim 1, wherein, The reliability of the information bits in the X coded bit sequences mapped to the corresponding modulation symbols in the modulation symbol sequence is higher than the reliability of the parity bits in the X coded bit sequences mapped to the corresponding modulation symbols in the modulation symbol sequence. A data processing method, wherein, The method includes: Receive modulation symbol sequence; The modulation symbol sequence is demodulated to obtain a soft bit sequence; Deinterleaving is performed on all soft bits of the X encoded bit sequences in the soft bit sequence to obtain multiple encoded soft bit sequences, where X is an integer greater than 1; Multiple information bit sequences are obtained by decoding the multiple encoded soft bit sequences. The method of claim 28, wherein, The index of the information bits in the X coded soft bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence is less than or equal to the index of the parity bits in the X coded bit sequences mapped to the mapping bit sequence of the modulation symbols in the modulation symbol sequence. The method of claim 28, wherein, At least one bit of the information bits of the m-th coded soft bit sequence in the X coded soft bit sequences is mapped to the 0th bit of the mapping bit sequence of a modulation symbol in the modulation symbol sequence, and at least one bit of the information bits of the n-th coded soft bit sequence in the X coded soft bit sequences is mapped to the 1st bit of the mapping bit sequence of the modulation symbol, where m and n are non-negative integers, and m is not equal to n. The method of claim 28, wherein, The plurality of encoded soft bit sequences are C encoded soft bit sequences obtained by LDPC encoding the plurality of information bit sequences, where C is a positive integer greater than 1, and X is less than or equal to C. The method of claim 28, wherein, The X coded soft bit sequences are X consecutive coded soft bit sequences among the plurality of coded soft bit sequences. The method of claim 28, wherein, The maximum value of X is determined by at least one of the following: coding rate, transport block size, data rate, target delay, target bit error rate, target reliability, terminal type, basic graph matrix index, or modulation order. The method of claim 28, wherein, The number X of the encoded soft bit sequence is determined based on the modulation order. The method of claim 28, wherein, The mapped bit sequence of at least one modulation symbol in the modulation symbol sequence is composed of bits from different encoded soft bit sequences. The method of claim 28, wherein, The 0th bit of the mapped bit sequence of at least one modulation symbol in the modulation symbol sequence comes from the information bit of the 0th coded soft bit sequence in the plurality of coded soft bit sequences; and / or, The last bit of the mapped bit sequence of the at least one modulation symbol comes from the parity bit of the last encoded soft bit sequence among the plurality of encoded soft bit sequences. A communication device, wherein include: Memory and processor; Memory and processor are coupled; The memory is used to store instructions that can be executed by the processor; When the processor executes the instructions, it performs the method as described in any one of claims 1-36. A computer-readable storage medium, wherein, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-36. A computer program product, wherein, The computer program product comprises computing technology program instructions which, when executed by a processor, implement the method of any one of claims 1-36.

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