Semiconductor device, array substrate, and display panel

Abstract

The present application relates to a semiconductor device, an array substrate, and a display panel. The semiconductor device comprises an active layer, a gate, a source, and a drain; the gate is arranged on one side of the active layer; the source and the drain are respectively connected to two opposite sides of the active layer; and the active layer comprises at least one first sublayer, the material of the first sublayer comprises a metal oxide conductive material and an electrical property adjusting element doped in the metal oxide conductive material, and the electrical property adjusting element comprises at least one of group VIII metal elements.

Description

Semiconductor devices, array substrates and display panels

[0001] This application claims the following priority:

[0002] 1. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510120882.3 and entitled "Semiconductor Device, Array Substrate and Display Panel", are incorporated herein by reference.

[0003] 2. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202520173868.5 and entitled "Display Panel and Display Device", are incorporated herein by reference.

[0004] 3. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202520174122.6 and entitled "Display Panel and Display Device", are incorporated herein by reference.

[0005] 4. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202520172407.6 and entitled "Display Panel and Display Device", are incorporated herein by reference.

[0006] 5. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122918.1 and entitled "Display Panel and Method for Preparing the Same", are incorporated herein by reference.

[0007] 6. Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510121539.0 and entitled "Display panel, method of manufacturing display panel and display device", the entire contents of which are incorporated herein by reference.

[0008] 7. Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510121244.3 and entitled "Display panel, method of manufacturing display panel and display device", the entire contents of which are incorporated herein by reference.

[0009] 8. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122793.2 and entitled "A Semiconductor Device and Display Panel", are incorporated herein by reference.

[0010] 9. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510121566.8 and entitled "Semiconductor Device and Display Panel", are incorporated herein by reference.

[0011] 10. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510121440.0 and entitled "Semiconductor Device and Display Panel", are incorporated herein by reference.

[0012] 11. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122941.0 and entitled "Array substrate and method of manufacturing thereof, display panel", are incorporated herein by reference.

[0013] 12. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122786.2 and entitled "A Thin Film Transistor and Display Panel", are incorporated herein by reference.

[0014] 13. Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122898.8 and entitled "Display panel and method of preparation thereof and display device", the entire contents of which are incorporated herein by reference;

[0015] 14. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122892.0 and entitled "Thin Film Transistor, Display Panel and Display Device", are incorporated herein by reference.

[0016] 15. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122890.1 and entitled "Display Panel and Display Device", are incorporated herein by reference.

[0017] 16. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122905.4 and entitled "Display Panel and Display Device", are incorporated herein by reference.

[0018] 17. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202520173722.0 and entitled "Display Panel and Display Device", are incorporated herein by reference.

[0019] 18. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510122928.5 and entitled "Display Device", are incorporated herein by reference.

[0020] 19. The entire contents of Chinese patent application filed with the China National Intellectual Property Administration on January 24, 2025, with application number 202510121424.1 and entitled "Array substrate and display panel", are incorporated herein by reference.

[0021] 20. The entire contents of Chinese Patent Application No. 202520172783.5, filed with the China National Intellectual Property Administration on January 24, 2025, entitled “Display Panel and Display Device”, are incorporated herein by reference. Technical Field

[0022] This application relates to the field of display technology, and in particular to a semiconductor device, an array substrate, and a display panel. Background Technology

[0023] Oxide semiconductor thin-film transistors have attracted widespread attention due to their advantages such as high electron mobility, excellent uniformity, good transparency and low cost.

[0024] For example, indium gallium zinc oxide (IGZO) semiconductor materials are already in mass production; however, due to material and process limitations, oxide semiconductor materials currently cannot achieve thin-film transistor devices with higher mobility. Summary of the Invention

[0025] This application provides a semiconductor device, an array substrate, and a display panel, which can improve the mobility of the active layer and the charging efficiency of the semiconductor device.

[0026] This application provides a semiconductor device comprising:

[0027] Active layer;

[0028] A gate is disposed on one side of the active layer;

[0029] The source and drain are respectively connected to the opposite sides of the active layer;

[0030] The active layer includes at least one first sublayer, the material of which includes a metal oxide conductive material and an electrical modulating element doped in the metal oxide conductive material, wherein the electrical modulating element includes at least one of group VIII metal elements.

[0031] In accordance with the above objectives of this application, embodiments of this application also provide an array substrate, the array substrate including the semiconductor device.

[0032] In accordance with the above objectives of this application, embodiments of this application also provide a display panel, the display panel including the array substrate. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0035] Figure 1 is a schematic diagram of a semiconductor device provided in an embodiment of this application;

[0036] Figure 2 is a schematic diagram of an active layer structure provided in an embodiment of this application;

[0037] Figure 3 is a schematic diagram of another structure of the active layer provided in an embodiment of this application;

[0038] Figure 4 is a schematic diagram of another structure of the semiconductor device provided in the embodiment of this application;

[0039] Figure 5 is a schematic diagram of a planar distribution of an array substrate provided in an embodiment of this application;

[0040] Figure 6 is a schematic diagram of a display panel provided in an embodiment of this application. Embodiments of the present invention

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0042] Referring to Figures 1 and 2, this application provides a semiconductor device 10, which includes an active layer 11, a gate 12, a source 13, and a drain 14. The gate 12 is disposed on one side of the active layer 11. The source 13 and the drain 14 are respectively connected to opposite sides of the active layer 11.

[0043] The active layer 11 includes at least one first sublayer 114. The material of the first sublayer 114 includes a metal oxide conductive material and an electrical modulating element doped in the metal oxide conductive material. The electrical modulating element includes at least one of the group VIII metal elements.

[0044] In the implementation process, this embodiment of the application reduces defect states in the metal oxide conductive material of the active layer 11 by doping it with the electrical adjustment element, thereby transforming it into a semiconductor material. Simultaneously, due to the high electron concentration in the metal oxide conductive material, the active layer 11 exhibits high mobility, improving the charging efficiency of the semiconductor device 10. Furthermore, by doping with the electrical adjustment element, this embodiment of the application reduces defect states in the metal oxide conductive material, thereby improving the light-induced stability of the active layer 11 and mitigating the negative bias of the threshold voltage Vth caused by light exposure.

[0045] In one embodiment of this application, the metal oxide conductive material includes at least one of indium tin oxide, antimony tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, and indium-doped zinc oxide.

[0046] In one embodiment of this application, the metal oxide conductive material is doped with at least one of the elemental form of the electrical regulating element and a compound of the electrical regulating element.

[0047] In one embodiment of this application, the metal oxide conductive material is doped with at least one of the elemental form of the electrical regulating element and the oxide of the electrical regulating element.

[0048] In one embodiment of this application, the metal oxide conductive material is doped with at least one of iron and iron oxide.

[0049] In one embodiment of this application, the active layer includes a channel and a first contact portion and a second contact portion located on opposite sides of the channel. The gate is aligned with the channel, the source is connected to the first contact portion, the drain is connected to the second contact portion, and the electrical adjustment element is distributed in the channel, the first contact portion, and the second contact portion.

[0050] In one embodiment of this application, the channel, the first contact portion, and the second contact portion are all semiconductors;

[0051] The semiconductor device further includes:

[0052] A substrate, wherein the gate is disposed on the substrate;

[0053] A first gate insulating layer is disposed on the substrate and covers the gate. The active layer is disposed on the side of the first gate insulating layer away from the gate. At least the orthogonal projection of the channel on the substrate is located within the orthogonal projection of the gate on the substrate. The source and the drain are disposed on the side of the first gate insulating layer away from the substrate and are respectively connected to the first contact portion and the second contact portion.

[0054] In one embodiment of this application, the channel is a semiconductor, and the first contact portion and the second contact portion are conductors;

[0055] The material of the channel includes the metal oxide conductive material and the electrical modifier doped in the metal oxide conductive material. The materials of the first contact portion and the second contact portion both include the metal oxide conductive material and the electrical modifier and conductor doped in the metal oxide conductive material.

[0056] In one embodiment of this application, the semiconductor device further includes:

[0057] A substrate, wherein the active layer is disposed on the substrate;

[0058] A second gate insulating layer is disposed on the side of the active layer away from the substrate and covers the active layer. The gate is disposed on the side of the second gate insulating layer away from the channel. The source and the drain are disposed on the side of the second gate insulating layer away from the active layer and are respectively connected to the first contact portion and the second contact portion.

[0059] In one embodiment of this application, the percentage of the number of metal atoms of the electrical adjustment element in the first sublayer is greater than or equal to 0.1% and less than or equal to 10%.

[0060] In one embodiment of this application, the carrier concentration of the first sublayer is greater than or equal to 1E14 cm⁻¹. -3 And less than or equal to 5E19cm -3 ;

[0061] The resistance of the first sublayer is greater than or equal to 1E4Ω / □ and less than or equal to 1E10Ω / □;

[0062] The Hall mobility of the first sublayer is greater than or equal to 30 cm. 2 / Vs, and less than or equal to 70cm 2 / Vs.

[0063] In one embodiment of this application, the active layer further includes at least one second sub-layer, which is stacked with at least one first sub-layer, and the material of the second sub-layer includes a metal oxide semiconductor material.

[0064] In one embodiment of this application, the Hall mobility of the second sublayer is less than that of the first sublayer.

[0065] In one embodiment of this application, the active layer includes a plurality of second sub-layers, and the first sub-layer is located between two adjacent second sub-layers.

[0066] Specifically, referring to Figures 1 and 2, the semiconductor device 10 is a thin-film transistor. In the semiconductor device 10, the active layer 11 includes a channel 111 and a first contact portion 112 and a second contact portion 113 located on opposite sides of the channel 111. The gate 12 is aligned with the channel 111 of the active layer 11, the source 13 is connected to the first contact portion 112, and the drain 14 is connected to the second contact portion 113.

[0067] Wherein, at least the channel 111 is a semiconductor. By controlling the voltage applied to the gate 12, the current channel 111 can be controlled to generate a current channel. When the channel 111 generates a current channel, the first contact 112 and the second contact 113 can be connected, thereby connecting the source 13 and the drain 14 to realize signal transmission.

[0068] In some embodiments, the semiconductor device 10 may further include a substrate 21 that carries the active layer 11, the gate 12, the source 13 and the drain 14, and an insulating layer that separates the device.

[0069] In one specific embodiment, referring to FIG1, the semiconductor device 10 may include a substrate 21, a gate 12 disposed on the substrate 21, a first gate insulating layer 22 disposed on the substrate 21 and covering the gate 12, an active layer 11 disposed on the side of the first gate insulating layer 22 away from the gate 12, a source 13 and a drain 14 disposed on the side of the first gate insulating layer 22 away from the substrate 21, and a first insulating layer 23 disposed on the first gate insulating layer 22 and covering the active layer 11, the source 13 and the drain 14, wherein the source 13 and the drain 14 are respectively connected to the first contact portion 112 and the second contact portion 113.

[0070] In this embodiment, the active layer 11 includes at least one first sublayer 114. The material of the first sublayer 114 includes a metal oxide conductive material and an electrical modifier doped in the metal oxide conductive material. The electrical modifier includes at least one group VIII metal element, and group VIII metal elements have a strong bonding ability with oxygen atoms. Doping the metal oxide conductive material with the electrical modifier can reduce the defect states in the metal oxide conductive material, transforming it into a semiconductor material. At the same time, since the metal oxide conductive material has a high electron concentration, the active layer can have a high mobility, improving the charging efficiency of the semiconductor device 10. In addition, by doping the electrical modifier, this embodiment can reduce the defect states in the metal oxide conductive material, thereby improving the light-induced stability of the active layer 11, mitigating the negative bias of the threshold voltage Vth caused by light exposure, and improving the subthreshold swing of the semiconductor device 10.

[0071] The electrical modulating element is distributed in the channel 111, the first contact portion 112 and the second contact portion 113, that is, the electrical modulating element can be uniformly distributed in the first sub-layer 114, and the channel 111, the first contact portion 112 and the second contact portion 113 can all be semiconductors.

[0072] In some embodiments, the orthographic projection of the channel 111 on the substrate 21 is located within the orthographic projection of the gate 12 on the substrate 21. Further, the orthographic projections of the first contact portion 112 on the substrate 21 and the orthographic projections of the second contact portion 113 on the substrate 21 both partially overlap with the orthographic projection of the gate 12 on the substrate 21.

[0073] In some embodiments, the conductive metal oxide material includes at least one selected from indium tin oxide (ITO), antimony tin oxide (ATO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), and indium-doped zinc oxide (IZO); the electrical modulating element may include at least one selected from iron, cobalt, nickel, ruthenium, rhodium, palladium, osmium, iridium, and platinum.

[0074] In some embodiments, the metal oxide conductive material is doped with at least one of the elemental form of the electrical regulating element and a compound of the electrical regulating element.

[0075] In some embodiments, the metal oxide conductive material is doped with at least one of the elemental form of the electrical regulating element and the oxide of the electrical regulating element; for example, when the electrical regulating element is iron, at least one of elemental iron and iron oxide can be doped into the metal oxide conductive material.

[0076] In some embodiments, the percentage of the number of metal atoms of the electrical regulating element in the first sublayer 114 is greater than or equal to 0.1% and less than or equal to 10%; for example, the percentage of the number of metal atoms of the electrical regulating element in the first sublayer 114 can be 0.1%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%.

[0077] It is understood that the above-mentioned percentage of metal atoms refers to the percentage of the number of atoms of the electrical regulating element among all metal atoms in the first sublayer 114.

[0078] In some embodiments, the carrier concentration of the first sublayer 114 is greater than or equal to 1E14 cm⁻¹. -3 And less than or equal to 5E19cm -3 It is understandable that when the carrier concentration of the membrane layer is too high, for example, when the carrier concentration of the membrane layer is at 1E20cm⁻¹, the situation becomes more complex. -3 Up to 1E21cm -3 Within a certain range, the film exhibits conductive properties. In this application, by using the electrical modulating element in a metal oxide conductive material with a high carrier concentration, the carrier concentration can be reduced, thereby achieving semiconductorization of the conductive material.

[0079] It should be noted that 1E14 cm -3 It refers to 1×10 14 cm -3 5E19 cm -3 It refers to 5×10 19 cm -3 .

[0080] In some embodiments, the resistance of the first sublayer 114 is greater than or equal to 1E4Ω / □ and less than or equal to 1E10Ω / □; it should be noted that the resistance mentioned above refers to sheet resistance, that is, the resistance value per unit area; for example, 1E4Ω / □ means 1×10 4 Ω / m 2 1E10Ω / □ refers to 1×10 10 Ω / m 2 .

[0081] In some embodiments, the Hall mobility of the first sublayer 114 is greater than or equal to 30 cm⁻¹. 2 / Vs, and less than or equal to 70cm 2 / Vs; Understandably, when the Hall mobility of the film is too high, for example, when the Hall mobility of the film is greater than 100 cm⁻¹. 2 At a velocity of / (V•s), the film exhibits conductive properties. The Hall mobility of the first semiconductor layer 3 provided in this embodiment is 30 cm⁻¹. 2 / Vs to 70cm 2 Within / Vs, it is indicated that the first semiconductor layer 3 has semiconductor characteristics.

[0082] In other words, the embodiments of this application can form a semiconductor material with a large carrier concentration and high mobility by doping the metal oxide conductive material with the electrical adjustment element, so as to realize the active layer 11 with high mobility.

[0083] In some embodiments, referring to Figures 1 and 2, the active layer 11 may further include at least one second sublayer 115, and the at least one second sublayer 115 is stacked with at least one first sublayer 114, wherein the material of the second sublayer 115 includes a metal oxide semiconductor material.

[0084] The Hall mobility of the second sublayer 115 is less than that of the first sublayer 114, and the material of the second sublayer 115 may include indium gallium zinc oxide (IGZO).

[0085] Furthermore, when the active layer 11 includes a first sub-layer 114 and a second sub-layer 115 stacked together, the first sub-layer 114 may be located between the second sub-layer 115 and the first gate insulating layer 22; or, the second sub-layer 115 may be located between the first sub-layer 114 and the first gate insulating layer 22. It should be noted that at least one side of the active layer 11 is the second sub-layer 115. The second sub-layer 115 is made of metal oxide semiconductor material. The second sub-layer 115 in the active layer 11 is in contact with other film layers, which helps to reduce defects at the contact interface between the active layer 11 and adjacent film layers, thereby improving the stability of the semiconductor device 10 and preventing the threshold voltage Vth of the semiconductor device 10 from becoming negatively biased, thereby further improving the performance and reliability of the semiconductor device 10. On the other hand, by adding the second sub-layer 115 to the active layer 11, it is beneficial to reduce the thickness of the first sub-layer 114, thereby reducing the overall thickness of the active layer 11 with high mobility. This helps to avoid the threshold voltage Vth from becoming negatively biased due to the excessive thickness of the active layer 11, thereby improving the stability of the semiconductor device 10.

[0086] In some embodiments, referring to Figures 1 and 3, when the active layer 11 includes a plurality of second sub-layers 115, the first sub-layer 114 is located between two adjacent second sub-layers 115. Thus, the second sub-layers 115 in the active layer 11 that are in contact with adjacent film layers are all made of metal oxide semiconductor material. This helps to reduce defects at the contact interface between the active layer 11 and adjacent film layers, thereby improving the stability of the semiconductor device 10 and preventing the threshold voltage Vth of the semiconductor device 10 from becoming negatively biased, thereby further improving the performance and reliability of the semiconductor device 10.

[0087] It should be noted that the semiconductor device 10 in the embodiment shown in Figure 1 is a bottom-gate thin-film transistor device, while the semiconductor device 10 provided in the embodiments of this application can also be a top-gate thin-film transistor device, as detailed below.

[0088] Referring to Figures 2, 3, and 4, in another specific embodiment of this application, the semiconductor device 10 may include a substrate 21, a light-shielding layer 31 disposed on the substrate 21, a barrier layer 24 disposed on the substrate 21 and covering the light-shielding layer 31, an active layer 11 disposed on the barrier layer 24, a second gate insulating layer 25 disposed on the side of the active layer 11 away from the substrate 21 and covering the active layer 11, a gate 12 disposed on the side of the second gate insulating layer 25 away from the channel 111, an interlayer dielectric layer 26 covering the active layer 11 and the gate 12, a source electrode 13 and a drain electrode 14 disposed on the side of the interlayer dielectric layer 26 away from the active layer 11, and a second insulating layer 27 disposed on the interlayer dielectric layer 26 and covering the source electrode 13 and the drain electrode 14; wherein the source electrode 13 and the drain electrode 14 pass through the interlayer dielectric layer 26 and are respectively connected to the first contact portion 112 and the second contact portion 113.

[0089] Wherein, the second gate insulating layer 25 at least covers the channel 111, the gate 12 is located on the side of the second gate insulating layer 25 away from the channel 111, the source 13 passes through the interlayer dielectric layer 26 and is connected to the first contact portion 112, and the drain 14 passes through the interlayer dielectric layer 26 and is connected to the second contact portion 113.

[0090] In this embodiment, the active layer 11 includes at least one first sublayer 114. The material of the first sublayer 114 includes a metal oxide conductive material and an electrical modifier doped in the metal oxide conductive material. The electrical modifier includes a group VIII metal element. Doping the metal oxide conductive material with the electrical modifier can reduce the defect states in the metal oxide conductive material, making it a semiconductor material. At the same time, since the metal oxide conductive material has a high electron concentration, the active layer can have a high mobility, thereby improving the charging efficiency of the semiconductor device 10. In addition, by doping the electrical modifier, this embodiment can reduce the defect states in the metal oxide conductive material, thereby improving the light-induced stability of the active layer 11 and mitigating the phenomenon of negative threshold voltage Vth bias caused by light exposure.

[0091] In some embodiments, the material of the channel 111 includes the metal oxide conductive material and the electrical modifier doped in the metal oxide conductive material, thereby the channel 111 is a semiconductor; the materials of the first contact portion 112 and the second contact portion 113 both include the metal oxide conductive material and the electrical modifier and conductor doped in the metal oxide conductive material, wherein the conductor doping in the first contact portion 112 and the second contact portion 113 makes the semiconductor conductive, so as to realize the electrical connection between the first contact portion 112 and the source 13 and between the second contact portion 113 and the drain 14.

[0092] In some embodiments, the conductor element includes at least one of B, Ne, P, and Ar.

[0093] In the process of manufacturing the semiconductor device 10, the elemental or oxide form of the electrical modifier can be mixed with the metal oxide conductive material first, and then deposited to obtain the active layer 11, so that the electrical modifier can be uniformly distributed in the active layer 11. Next, the regions in the active layer 11 corresponding to the first contact portion 112 and the second contact portion 113 can be conductiveized, for example, by using an ion implantation process.

[0094] It should be noted that in the embodiment shown in FIG4, the active layer 11 can also be provided with the second sub-layer 115, and the structure and position of the first sub-layer 114 and the second sub-layer 115 in the active layer 11 in the embodiment shown in FIG4 can be the same as those in the embodiment shown in FIG1, and will not be repeated here; in addition, in the embodiment shown in FIG4, the first sub-layer 114 and the second sub-layer 115 can be doped with conductor elements at the positions corresponding to the first contact portion 112 and the second contact portion 113 to perform conductorization process.

[0095] In summary, by doping the conductive metal oxide material of the active layer 11 with the electrical adjustment element, the defect states in the conductive metal oxide material can be reduced, transforming it into a semiconductor material. Simultaneously, due to the high electron concentration in the conductive metal oxide material, the active layer exhibits high mobility, improving the charging efficiency of the semiconductor device 10. Furthermore, by doping with the electrical adjustment element, the defect states in the conductive metal oxide material can be reduced, thereby improving the light-induced stability of the active layer 11 and mitigating the negative bias of the threshold voltage Vth caused by light exposure.

[0096] Additionally, referring to Figures 1 and 5, this application embodiment also provides an array substrate 400, which includes the semiconductor device 10 described in the above embodiments.

[0097] In some embodiments, the array substrate 400 includes a pixel arrangement area 101 and a non-pixel arrangement area 102 adjacent to the pixel arrangement area 101, and the non-pixel arrangement area 102 includes a driving circuit sub-region 1021; the pixel arrangement area 101 of the array substrate is used to set up a plurality of pixel circuits, and the non-pixel arrangement area 102 of the array substrate can be used to set up functional circuits and signal traces and other devices. For example, the driving circuit sub-region 1021 in the non-pixel arrangement area 102 can be used to set up functional circuits such as gate driving circuits and multiplexing circuits.

[0098] The semiconductor device 10 can be used in at least the gate driving circuit and the multiplexing circuit to form a thin-film transistor with high mobility in the gate driving circuit and the multiplexing circuit, thereby improving the performance and electrical signal transmission capability of the gate driving circuit and the multiplexing circuit.

[0099] In some embodiments, the array substrate further includes a scan signal line, one end of which is connected to the gate driving circuit, and the other end of which extends into the pixel arrangement area 101 and is connected to the pixel circuit. The gate driving circuit includes an output transistor connected to the scan signal line, and at least the output transistor in the gate driving circuit is the semiconductor device 10 to meet the signal output efficiency requirements of the output transistor. Further, all thin-film transistors in the gate driving circuit can be the semiconductor device 10; for example, the gate driving circuit may include a pull-up control module, a pull-up module, a pull-down module, and a pull-down sustaining module, in which case the thin-film transistors in the pull-up control module, the pull-up module, the pull-down module, and the pull-down sustaining module can all be the semiconductor device 10.

[0100] In some embodiments, the thin-film transistor in the pixel circuit may also be the semiconductor device 10.

[0101] Additionally, referring to Figures 1 and 6, this application embodiment also provides a display panel 40, which includes the array substrate 400 described in the above embodiments.

[0102] In some embodiments, the display panel 40 may be an organic light-emitting diode display panel, and the display panel may further include an anode layer, an organic light-emitting layer, a cathode layer and an encapsulation layer disposed on the array substrate 400.

[0103] In some embodiments, the display panel 40 may be a liquid crystal display panel, and the display panel may further include a pixel electrode disposed on the array substrate 400, a liquid crystal layer disposed on the side of the pixel electrode away from the array substrate 400, a color filter substrate disposed on the side of the liquid crystal layer away from the array substrate 400, and a common electrode disposed on the array substrate 400 and / or the color filter substrate.

[0104] It is understood that the display panel 40 contains the same array substrate 400 and semiconductor device 10 as in the above embodiments. Therefore, the display panel 40 can have the same beneficial effects as in the above embodiments, which will not be repeated here.

[0105] Mobility is one of the key metrics for evaluating the semiconductor device 10. It determines the speed at which charges move within the semiconductor device 10. Therefore, high mobility implies faster response times and higher operating efficiency, which is crucial for improving the overall performance of electronic devices. Simultaneously, higher mobility results in lower resistivity, leading to lower power consumption for the same current flow. This means that in a semiconductor device 10 with high mobility, the device can complete the same task with lower power consumption, thereby reducing energy waste and heat generation. Furthermore, mobility directly affects the switching speed and cutoff frequency of the semiconductor device 10. Therefore, a semiconductor device 10 with high mobility can shorten the time for minority carriers to transit the base region, thereby improving the switching speed and frequency response characteristics of the semiconductor device 10.

[0106] In this embodiment, the semiconductor device 10 provided in the foregoing embodiment has high mobility and light stability, which is beneficial to improving the response speed, working efficiency and stability of the display panel 40, and can reduce the power consumption of the display panel 40.

[0107] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0108] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0109] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0110] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device comprising: Active layer; A gate is disposed on one side of the active layer; The source and drain are respectively connected to opposite sides of the active layer; The active layer includes at least one first sublayer, the material of which includes a metal oxide conductive material and an electrical modulating element doped in the metal oxide conductive material, wherein the electrical modulating element includes at least one of group VIII metal elements.

2. The semiconductor device according to claim 1, wherein, The conductive metal oxide material includes at least one of indium tin oxide, antimony tin oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, and indium-doped zinc oxide.

3. The semiconductor device according to claim 1, wherein, The metal oxide conductive material is doped with at least one of the elemental form of the electrical regulating element and a compound of the electrical regulating element.

4. The semiconductor device according to claim 3, wherein, The metal oxide conductive material is doped with at least one of the elemental form of the electrical regulating element and the oxide of the electrical regulating element.

5. The semiconductor device according to claim 3, wherein, The metal oxide conductive material is doped with at least one of iron and iron oxide.

6. The semiconductor device according to claim 1, wherein, The active layer includes a channel and a first contact portion and a second contact portion located on opposite sides of the channel. The gate is aligned with the channel, the source is connected to the first contact portion, and the drain is connected to the second contact portion. The electrical adjustment element is distributed in the channel, the first contact portion, and the second contact portion.

7. The semiconductor device according to claim 6, wherein, The channel, the first contact portion, and the second contact portion are all semiconductors; The semiconductor device further includes: A substrate, wherein the gate is disposed on the substrate; A first gate insulating layer is disposed on the substrate and covers the gate. The active layer is disposed on the side of the first gate insulating layer away from the gate. At least the orthogonal projection of the channel on the substrate is located within the orthogonal projection of the gate on the substrate. The source and the drain are disposed on the side of the first gate insulating layer away from the substrate and are respectively connected to the first contact portion and the second contact portion.

8. The semiconductor device according to claim 6, wherein, The channel is a semiconductor, and the first contact portion and the second contact portion are conductors; The material of the channel includes the metal oxide conductive material and the electrical modifier doped in the metal oxide conductive material. The materials of the first contact portion and the second contact portion both include the metal oxide conductive material and the electrical modifier and conductor doped in the metal oxide conductive material.

9. The semiconductor device according to claim 8, wherein, The conductor element includes at least one of B, Ne, P, and Ar.

10. The semiconductor device according to claim 8, wherein, The semiconductor device further includes: A substrate, wherein the active layer is disposed on the substrate; A second gate insulating layer is disposed on the side of the active layer away from the substrate and covers the active layer. The gate is disposed on the side of the second gate insulating layer away from the channel. The source and the drain are disposed on the side of the second gate insulating layer away from the active layer and are respectively connected to the first contact portion and the second contact portion.

11. The semiconductor device according to claim 1, wherein, The percentage of the number of metal atoms of the electrical regulating element in the first sublayer is greater than or equal to 0.1% and less than or equal to 10%.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The carrier concentration of the first sublayer is greater than or equal to 1E14 cm⁻¹ -3 And less than or equal to 5E19cm -3 .

13. The semiconductor device according to any one of claims 1 to 11, wherein, The resistance of the first sublayer is greater than or equal to 1E4Ω / □ and less than or equal to 1E10Ω / □.

14. The semiconductor device according to any one of claims 1 to 11, wherein, The Hall mobility of the first sublayer is greater than or equal to 30 cm. 2 / Vs, and less than or equal to 70cm 2 / Vs.

15. The semiconductor device according to any one of claims 1 to 11, wherein, The active layer further includes at least one second sublayer, which is stacked with at least one first sublayer, and the material of the second sublayer includes a metal oxide semiconductor material.

16. The semiconductor device according to claim 15, wherein, The Hall mobility of the second sublayer is less than that of the first sublayer.

17. The semiconductor device according to claim 15, wherein, The active layer includes a plurality of second sub-layers, and the first sub-layer is located between two adjacent second sub-layers.

18. The semiconductor device according to any one of claims 1 to 11, wherein, The electrical modulating element may include at least one of iron, cobalt, nickel, ruthenium, rhodium, palladium, osmium, iridium, and platinum.

19. An array substrate comprising a semiconductor device as claimed in any one of claims 1 to 18.

20. A display panel comprising the array substrate as claimed in claim 19.

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