Memory and preparation method therefor, semiconductor package structure, and electronic device

Abstract

The present application relates to the technical field of semiconductor memory devices. Provided are a memory and a preparation method therefor, a semiconductor package structure, and an electronic device. The memory has a storage area and a logic area. The memory comprises a substrate, and a first dielectric layer, a second dielectric layer and a third dielectric layer, which are stacked on the substrate. The logic area of the memory has a logic device disposed on the substrate, a first metal layer disposed in the first dielectric layer, and a second metal layer disposed in the second dielectric layer, wherein the logic device is connected to the first metal layer, and the first metal layer is connected to the second metal layer. The storage area of the memory has a transistor and a capacitor, wherein the transistor is disposed on the substrate; the capacitor extends through the first dielectric layer, the second dielectric layer and the third dielectric layer, and the capacitor is connected to the transistor; and the sidewall of the capacitor is stepped. The memory provided in the present application can improve the compatibility between the capacitor and a logic circuit.

Description

Memory and its fabrication method, semiconductor packaging structure, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510125244.0, filed on January 26, 2025, entitled "Memory and its preparation method, semiconductor packaging structure, electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor memory device technology, and in particular to a memory and its fabrication method, a semiconductor packaging structure, and an electronic device. Background Technology

[0003] Embedded memory (eMemory), as a system-on-a-chip device, typically requires integrating traditional standalone memory (SAM) onto a system-on-a-chip (SOC) or microcontroller unit (MCU) chip. Compared to standalone memory, embedded memory, by integrating memory within the same chip, can significantly shorten the data communication time between the memory and logic circuits, thereby achieving greater bandwidth and faster speeds than standalone memory, meeting the requirements of in-memory computing.

[0004] While embedded memory offers numerous advantages, it presents challenges compared to standalone memory, requiring careful design considerations to ensure compatibility in terms of process flow and performance between the memory and logic areas. Current approaches propose placing the memory nodes above the select transistors and embedding them within the back-end logic circuitry. However, this approach still suffers from compatibility issues between the memory nodes and the back-end logic circuitry. Summary of the Invention

[0005] This application provides a memory and its fabrication method, a semiconductor packaging structure, and an electronic device. The aim is to improve the compatibility between capacitors and logic circuits.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] On one hand, this application provides a memory having a storage area and a logic area. The memory includes a substrate and a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked on the substrate. The logic area of ​​the memory includes logic devices disposed on the substrate, a first metal layer disposed within the first dielectric layer, and a second metal layer disposed within the second dielectric layer; the logic devices are connected to the first metal layer, and the first metal layer is connected to the second metal layer. The storage area of ​​the memory includes transistors and capacitors. The transistors are disposed on the substrate, and the capacitors penetrate the first, second, and third dielectric layers and are connected to the transistors. The sidewalls of the capacitors are stepped.

[0008] In the memory disclosed in this application, the capacitor is disposed within a multilayer dielectric layer of the storage area, and the sidewalls of the capacitor are stepped. It can be seen that when the capacitor is formed within the multilayer dielectric layer, the vias used to accommodate the capacitor are not formed using a single-stage opening process, but rather using at least two opening processes (because the vias are prepared using two or more opening processes, the sidewalls of the capacitor will only be stepped after the capacitor is formed within the via).

[0009] Since the vias for accommodating capacitors within the multilayer dielectric layers of the memory provided in this application can be formed using at least two aperture-opening processes, material can be filled into the vias after each aperture-opening to form a filler layer. Then, at least a portion of the metal layer for the logic circuit can be fabricated and polished. Thus, when polishing at least a portion of the metal layer of the logic region, the memory region can be supported by the filler layer. During polishing, the force applied by the polishing pad to the memory region and the logic region is relatively balanced, improving the polishing effect of the metal layer. This reduces the impact on the logic circuit when the capacitor is embedded in the subsequent logic circuit fabrication process, thereby improving the compatibility between the capacitor and the existing logic circuit fabrication process.

[0010] In addition, the vias used to accommodate capacitors are obtained by at least two opening processes. On the one hand, this can increase the depth of the vias used to accommodate capacitors, thereby improving the capacitance value of the capacitors. On the other hand, compared with the single opening process of the prior art, the at least two openings in this application can reduce the difficulty of opening vias and reduce the difficulty of fabricating memory.

[0011] In one feasible manner, the capacitor includes a first portion and a second portion connected to the first portion in a direction perpendicular to the surface of the substrate. The first portion extends through a first dielectric layer and a second dielectric layer, and the second portion extends through a third dielectric layer. The sidewalls of the first portion and the sidewalls of the second portion are connected in a stepped manner.

[0012] This application creates a stepped capacitor sidewall, with the first and second part sidewalls connected in a stepped manner. This allows for the formation of a via for accommodating the capacitor through a two-stage drilling process. One drilling creates a via within the first and second dielectric layers, while the second drilling creates a via within the third dielectric layer (thus, the sidewalls of the first and second part within the first and second dielectric layers are connected in a stepped manner to the sidewalls of the second part within the third dielectric layer). Using this two-stage drilling method, a via penetrating the first and second dielectric layers can be created in the storage region before the second metal layer is fabricated, and a filling material is filled within the via to form a filling layer. Then, the second metal layer is fabricated within the second dielectric layer of the logic region and polished. That is, since the sidewalls of the first part and the second part of the capacitor are connected in a stepped shape, the memory can be fabricated using the above process. When the second metal layer is polished, the storage area can provide a support structure to distribute the polishing pressure, which can improve the polishing effect of the second metal layer, thereby reducing the impact on the logic circuit when the capacitor is embedded in the logic circuit of the subsequent process and improving the compatibility between the capacitor and the logic circuit.

[0013] In one possible implementation, the memory further includes a fourth dielectric layer located between the second and third dielectric layers; a logic region having a third metal layer located within the fourth dielectric layer and connected to the second metal layer; a capacitor including a first portion, a second portion, and a third portion in a direction perpendicular to the surface of the substrate, the third portion being connected between the first and second portions; the first portion penetrating the first and second dielectric layers, the second portion penetrating the third dielectric layer, and the third portion penetrating the fourth dielectric layer; the sidewalls of the first portion and the third portion are connected in a stepped manner, and the sidewalls of the third portion and the second portion are connected in a stepped manner.

[0014] This application, through the aforementioned structural configuration, allows for the formation of through-holes for accommodating capacitors via a three-stage drilling process. One drilling creates a through-hole within the first and second dielectric layers, another creates a through-hole within the fourth dielectric layer, and a third creates a through-hole within the third dielectric layer. (These three drillings allow for a stepped connection between the sidewalls of the first and third portions of the capacitor, and vice versa.) This three-stage drilling approach allows for the creation of through-holes penetrating the first and second dielectric layers in the storage region before the second metal layer is fabricated, with the through-hole filled with material to form a filling layer. The second metal layer is then fabricated and polished. Similarly, before the third metal layer is fabricated, a through-hole penetrating the fourth dielectric layer is created in the storage region, with the through-hole filled with material to form a filling layer. The third metal layer is then fabricated and polished. Since the sidewalls of the first part and the third part are connected in a stepped shape, and the sidewalls of the third part and the second part are connected in a stepped shape, the memory can be fabricated using the above-mentioned process. In this way, when the second metal layer and the third metal layer are polished respectively, the memory area can be provided with a support structure to distribute the polishing pressure, thereby improving the polishing effect of the second metal layer and the third metal layer, and thus improving the process compatibility between the capacitor and the logic circuit.

[0015] In one feasible manner, along the direction from the first dielectric layer toward the substrate, the dimensions of a first portion gradually decrease along a first direction, the dimensions of a second portion gradually decrease along a first direction, and the dimensions of a third portion gradually decrease along a first direction; the first direction is parallel to the surface of the substrate.

[0016] This application achieves a gradual reduction in size along the first direction for the first portion of the capacitor, a gradual reduction in size along the first direction for the second portion, and a gradual reduction in size along the first direction for the third portion. This allows the vias within the multilayer dielectric layer used to house the capacitor to be formed using conventional etching processes, thereby reducing the difficulty of capacitor fabrication.

[0017] In one possible implementation, the fourth dielectric layer comprises multiple layers, which are stacked sequentially between the second and third dielectric layers; each fourth dielectric layer has a third metal layer, and each fourth dielectric layer has a third portion, with the sidewalls of two adjacent third portions connected in a stepped shape.

[0018] This application provides space for accommodating capacitors by incorporating multiple fourth dielectric layers, thereby improving the capacitance value. By connecting the sidewalls of adjacent third portions of the capacitor in a stepped manner, each fourth dielectric layer can have vias formed to accommodate the capacitors. In other words, multiple vias can be formed through a multi-stage drilling process (this process allows for the step-like connection of the sidewalls of adjacent third portions). This reduces the difficulty of creating vias for capacitor accommodating, thus simplifying memory fabrication. Furthermore, the multi-stage drilling process allows for filling the vias with material after each drilling in the fourth dielectric layer to form a filling layer; then, a third metal layer is fabricated within the fourth dielectric layer and polished. This improves the polishing effect of each third metal layer, achieving process compatibility between logic circuit and capacitor fabrication.

[0019] In one possible implementation, the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer; the dielectric layer is located between the first electrode layer and the second electrode layer, and the first electrode layer is connected to a transistor.

[0020] The capacitor of this application is embedded in a multilayer dielectric layer, which can form a deep trench capacitor within the multilayer dielectric layer, thereby increasing the surface area of ​​the first electrode layer and the second electrode layer of the capacitor and thus increasing the capacitance value of the capacitor.

[0021] In one possible implementation, the memory includes a first insulating layer and a second insulating layer, the first insulating layer being located between the second insulating layer and a substrate, and the second insulating layer being located between the first insulating layer and a first dielectric layer; the first insulating layer has a first contact hole connected to a first electrode of a transistor; the second insulating layer has a first conductive via connected to the first contact hole, and a capacitor is connected to the first conductive via.

[0022] This application enables the interconnection of transistors and capacitors located at different levels by setting a first contact hole and a first conductive via, thereby allowing the transistors and capacitors in the storage area to establish an electrical connection and ensuring the smooth operation of data reading and writing. In addition, the setting of the first contact hole and the first conductive via can also make more efficient use of space and realize the vertical interconnection of transistors and capacitors, which helps to integrate more storage cells within a limited chip area, thereby improving the capacity and integration of the memory.

[0023] On the other hand, this application also provides a semiconductor packaging structure, which includes a packaging substrate and a memory in any of the above-described possible implementations, the memory being connected to the packaging substrate.

[0024] The semiconductor package structure provided in this application, since it includes the aforementioned memory, has at least the same effect as the aforementioned memory. The semiconductor package structure can improve the compatibility between capacitors and logic circuits.

[0025] In another aspect, this application also provides an electronic device, which includes a circuit board and the aforementioned semiconductor packaging structure, wherein the semiconductor packaging structure is connected to the circuit board.

[0026] The electronic device provided in this application allows the memory area to be supported by a filling layer when polishing at least a portion of the metal layer of the logic circuit of the memory. Therefore, the force applied by the polishing pad to the memory area and the logic area is relatively balanced, which can improve the polishing effect of the metal layer. This reduces the impact on the logic circuit when the capacitor is embedded in the logic circuit of the subsequent process, and improves the compatibility between the capacitor and the logic circuit.

[0027] Furthermore, this application provides a method for fabricating a memory, the method comprising: forming a logic device on a substrate in a logic region, and forming a transistor on the substrate in a storage region; forming a first dielectric layer on the substrate, the logic device, and the transistor; forming a first metal layer within the first dielectric layer in the logic region, the first metal layer being connected to the logic device; forming a second dielectric layer covering the first dielectric layer and the first metal layer; and forming a first via in the storage region penetrating the second dielectric layer and the first dielectric layer, and filling the first via with a material to form a first filler. A second metal layer is formed within the second dielectric layer in the logic region, and the second metal layer is connected to the first metal layer; the second metal layer is polished; a third dielectric layer is formed, which is located on the second dielectric layer, the second metal layer, and the first filler layer; a second via is formed in the storage region, penetrating the third dielectric layer, and the second via corresponds to the first filler layer; the first filler layer is removed to obtain a connected first via and a second via, and the sidewall of the second via and the sidewall of the first via are connected in a stepped shape; a capacitor is formed in the first via and the second via, and the capacitor is connected to the transistor, and the sidewall of the capacitor is stepped.

[0028] In the memory fabrication method provided in this application, when forming the capacitor, the first metal layer, and the second metal layer, the method involves first forming the first metal layer; then forming the second dielectric layer, forming a first via through the storage region, and filling the first via with material to form a first filling layer; then forming the second metal layer interconnected with the first metal layer, and polishing the second metal layer; then forming the third dielectric layer, and opening the second via in the third dielectric layer; then removing the first filling layer, so that the second via and the exposed first via are connected; and finally forming the capacitor in the first and second vias.

[0029] This application, through the aforementioned fabrication method, allows capacitors to be embedded in downstream logic circuits. Because a first via is formed before polishing the second metal layer, and a first filling layer is formed within the first via, the storage area is supported during polishing of the second metal layer. This first filling layer can withstand the pressure during polishing, resulting in a more balanced force applied by the polishing pad to the storage and logic areas. This improves the polishing uniformity of the second metal layer, thereby reducing the impact on the logic circuit when the capacitor is embedded in the downstream logic circuit and improving the compatibility between the capacitor and the existing logic circuit process. Since the vias for accommodating the capacitor and the metal layers of the logic area are interleaved, and the vias for accommodating the capacitor employ a multi-stage opening process, the sidewalls of the capacitor obtained through this fabrication method are stepped.

[0030] In one possible implementation, the material of the first filling layer includes at least one of polycrystalline silicon or silicon nitride.

[0031] Polysilicon and silicon nitride are both materials with high hardness and good chemical stability. Using them as the first filler layer can provide effective structural support for the memory region, enhancing its structural strength. When the memory region needs to withstand the pressure of the polishing process of the corresponding metal layer, the presence of the first filler layer can make the stress on the memory region and logic region more balanced, thereby improving the polishing effect of the corresponding metal layer. In addition, polysilicon and silicon nitride have good etching selectivity and etching rate control in etching processes. Therefore, when it is necessary to remove the first filler layer, it can be effectively removed.

[0032] In one feasible embodiment, after polishing the second metal layer and before forming the third dielectric layer, the preparation method of this application further includes: forming a fourth dielectric layer, the fourth dielectric layer covering the second dielectric layer, the second metal layer, and the first filling layer; opening a third via through the fourth dielectric layer in the storage region, and filling the third via with material to form a second filling layer, the second filling layer and the first filling layer being connected, the sidewalls of the second filling layer and the sidewalls of the first filling layer being connected in a stepped manner; forming a third metal layer in the fourth dielectric layer of the logic region, the third metal layer being connected to the second metal layer; and polishing the third metal layer.

[0033] That is, after polishing the second metal layer and before forming the third dielectric layer, the preparation method of this application can further form a fourth dielectric layer and form a third via within the fourth dielectric layer of the storage region; then, fill the third via with material to form a second filling layer; subsequently, prepare the third metal layer within the fourth dielectric layer of the logic region, and then polish the third metal layer. In this way, before polishing the third metal layer, since the storage region has the first and second filling layers as structural supports, the stress on the storage region and the logic region is more balanced during polishing, resulting in a better polishing effect for the third metal layer. This process can improve the polishing effect of the second and third metal layers, enabling the capacitor to be embedded in the logic circuit with process compatibility. Furthermore, the first and third vias obtained after removing the first and second filling layers can increase the capacitance value of the capacitor and improve the storage capacity of the storage region.

[0034] In one possible implementation, the materials of the first filler layer and the second filler layer are the same.

[0035] This application uses the same material for the first and second filler layers, which reduces the difficulty of removing the first and second filler layers and allows for the effective removal of both layers in one step, simplifying the process.

[0036] In one possible implementation, the shapes of the openings of the third via facing away from the substrate, the second via facing away from the substrate, and the first via facing away from the substrate are all the same; the areas of the openings of the third via facing away from the substrate, the second via facing away from the substrate, and the first via facing away from the substrate are all the same.

[0037] With the above settings, the openings of the third through-hole, the second through-hole, and the first through-hole away from the substrate can be completely identical. In this way, the same photomask can be used when forming the first through-hole, the third through-hole, and the second through-hole, which can reduce the number of photomasks and lower manufacturing costs.

[0038] In one feasible manner, removing the first filler layer includes: removing the first filler layer using a wet etching process.

[0039] Wet etching involves a chemical reaction between a liquid chemical solution and the material to be etched, dissolving away unwanted portions. Because the solution can flow and penetrate into the interior of irregular pores, wet etching is more effective at removing the filling layer within stepped through-holes, thus achieving effective removal of the first filling layer.

[0040] In one feasible manner, forming a capacitor within a first via and a second via includes: forming the capacitor within the first via and the second via using an atomic layer deposition process.

[0041] Atomic layer deposition (ALD) is a technique that deposits atoms layer by layer onto a substrate by growing single-atom films. ALD offers high uniformity and consistency, enabling the formation of uniform and dense films on surfaces with complex shapes and structures. Therefore, when the first and second vias are connected to form a stepped via, the layer-by-layer deposition characteristic of ALD allows for relatively uniform coverage and deposition during capacitor formation. Attached Figure Description

[0042] Figure 1A is a schematic diagram of the structure of the electronic device provided in an embodiment of this application;

[0043] Figure 1B is a schematic diagram of the semiconductor packaging structure provided in an embodiment of this application;

[0044] Figure 2 is a circuit diagram of the storage array provided in an embodiment of this application;

[0045] Figure 3 is one of the schematic diagrams of the memory structure provided in the embodiment of this application;

[0046] Figure 4 is a second schematic diagram of the structure of the memory provided in an embodiment of this application;

[0047] Figure 5 is a third schematic diagram of the structure of the memory provided in the embodiment of this application;

[0048] Figure 6 is a schematic flowchart of one of the methods for fabricating a memory according to an embodiment of this application;

[0049] Figures 7 to 15 are schematic diagrams of the structure obtained after the corresponding steps are completed when preparing one of the memory provided in the embodiments of this application;

[0050] Figure 16 is a second schematic flowchart of the method for preparing the memory provided in the embodiment of this application;

[0051] Figures 17 to 21 are schematic diagrams of the structure obtained after the corresponding steps are completed when preparing another memory provided in the embodiments of this application;

[0052] Figures 22 to 26 are schematic diagrams of the structure obtained after the corresponding steps are completed when preparing another type of memory provided in the embodiments of this application.

[0053] Reference numerals: 01-Electronic device; 02-Semiconductor packaging structure; 100-Chip; 200-Circuit board; 300-Packaging substrate; 10-Substrate; 20-Second transistor; 30-First transistor; 411-First dielectric layer; 412-Second dielectric layer; 413-Third dielectric layer; 414-Fourth dielectric layer; 421-First via; 422-First fill layer; 431-Third via; 432-Second fill layer; 441-Second via; 51-First metal layer; 52-Second metal layer; 53-Third metal layer; 60-Capacitor; 62-Step; 621-First step; 622-Second step; 623-Third step; 631-First electrode layer; 632-Dielectric layer; 633-Second electrode layer; 70-First insulating layer; 71-First contact hole; 72-Second contact hole; 73-Third contact hole; 80-Second insulating layer; 81-First conductive via; 82-Electrode line; 83-Second conductive via; 90-Wiring layer; 110-Memory array; 111-Memory cell. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0056] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0057] In addition, in the description of the embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0058] This application provides an electronic device 01. The electronic device 01 can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers and robot vacuum cleaners), drones, radar equipment, in-vehicle equipment, and vehicles, among other different types of user equipment or terminal devices; the electronic device 01 can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device 01.

[0059] Figure 1A is a schematic diagram of the structure of an electronic device 01 provided in an embodiment of this application. The electronic device 01 may include a circuit board 200 and a semiconductor package structure 02 connected to the circuit board 200. The circuit board 200 may be a printed circuit board (PCB).

[0060] The semiconductor package structure 02 can be electrically connected to the circuit board 200 through an electrical connection structure, thereby enabling the semiconductor package structure 02 to achieve signal interconnection with other chips or other electronic modules on the circuit board 200.

[0061] In some implementations, the electrical connection structure may include multiple solder balls, such as a ball grid array (BGA); or, the electrical connection structure may include multiple conductive pillars, such as metal pillars.

[0062] Figure 1B is a schematic diagram of the semiconductor packaging structure provided in an embodiment of this application. Referring to Figure 1B, the semiconductor packaging structure 02 may include a packaging substrate 300 and a memory, and the memory may be connected to the packaging substrate 300. As shown in Figure 1A, the packaging substrate 300 may be connected to the circuit board 200 through an electrical connection structure.

[0063] The memory can be a chip 100 containing a System on a Chip (SOC). The System on a Chip can integrate storage circuitry and logic circuitry into the same chip 100; therefore, the memory can also be called embedded memory or on-chip memory.

[0064] The storage circuitry is used to store software programs and data. It can include a data storage area and a program storage area. The data storage area stores data from the electronic device 01 (such as audio data and image data); the program storage area stores the operating system and running applications of the electronic device 01. The memory can be Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), or Flash Memory, etc.

[0065] In some embodiments, the memory may include a storage array 110 and a controller, the controller being electrically connected to the storage array 110 and used to control the reading and writing of the storage array 110. For example, the controller is used to access the storage array 110 to write data into the storage array 110 or to read data from the storage array 110.

[0066] Figure 2 is a circuit diagram of a storage array 110 provided in an embodiment of this application. In some embodiments, the storage array 110 may include multiple storage cells 111 arranged in an array as shown in Figure 2, wherein each storage cell 111 can be used to store 1 bit or more bits of data. The storage array 110 may also include electrode lines such as word lines (WL) and bit lines (BL). Each storage cell 111 is electrically connected to a corresponding word line WL and bit line BL. Different storage cells 111 can be electrically connected through word lines and bit lines. One or more of the above-mentioned word lines and bit lines are used to select the storage cell 111 to be read or written in the storage array 110 by receiving the control level output by the control circuit, thereby realizing the data read and write operation. For convenience, the above-mentioned word lines and bit lines are collectively referred to as electrode lines in this embodiment of the application.

[0067] Referring again to Figure 2, in some examples, a memory cell 111 may include a transistor (Tr) and a capacitor (C). The transistor may have a gate, a source, and a drain. The gate is connected to a word line (WL), one of the drain and the source is connected to a bit line (BL), and the other of the drain and the source is connected to the capacitor. For example, the drain is connected to the capacitor, and the source is connected to the bit line.

[0068] In actual operation, the voltage signal on the word line controls the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line, or writing the data signal into the capacitor for storage through the bit line, so as to realize the read and write operation.

[0069] In the embodiments described in this application, the transistor may be a metal-oxide-semiconductor field-effect transistor. For example, an N-channel metal-oxide-semiconductor (NMOS) or a P-channel metal-oxide-semiconductor (PMOS); or, the transistor may also be a fin-field transistor (FinFET), such as a tri-gate transistor (TG). In other words, this application does not limit the specific type of transistor.

[0070] In some examples, the logic processing chip and memory exist as separate chips 100, communicating via an external bus. However, with increasing system complexity and higher demands for data processing speed, this discrete design has gradually revealed problems such as high latency and limited bandwidth. To address these bottlenecks, embedded memory, which integrates memory directly into the logic processing chip, has become widely used. Embedded memory enables high-speed, low-latency communication between the logic processing chip and memory, significantly improving the overall system performance.

[0071] While embedded memory technology offers numerous advantages, its design presents significant challenges. The logic area, responsible for complex computations and control tasks, requires attention to processing speed, power consumption, and logical correctness; while the storage area demands optimal data storage and read / write capabilities. These significant differences in functional requirements, circuit design, and manufacturing processes make achieving compatibility on a single chip extremely challenging. For example, if memory nodes (such as capacitors) need to be embedded into back-end logic circuitry, the compatibility between these nodes and the back-end logic circuitry becomes a critical and unavoidable issue.

[0072] This application proposes a novel memory and its fabrication method. The capacitors in this memory can be embedded in the subsequent logic circuitry without affecting the normal fabrication of the logic circuitry, thus improving the compatibility between the subsequent logic circuitry and the memory node. The memory and its fabrication method are described in detail below with reference to the accompanying drawings.

[0073] Figure 3 is a schematic diagram of the structure of the memory provided in an embodiment of this application; Figure 4 is a schematic diagram of the structure of the memory provided in an embodiment of this application; and Figure 5 is a schematic diagram of the structure of the memory provided in an embodiment of this application. Referring to Figures 3 to 5, the memory has isolated storage areas and logic areas.

[0074] In some examples, the substrate 10 can be made of silicon, germanium, silicon germanide, or silicon carbide; it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other group III-V compounds. Those skilled in the art can select a suitable material as the substrate 10 according to actual needs, and this application does not impose any limitations on this selection.

[0075] Substrate 10 has a storage area and a logic area. The storage area is used for data storage and access, while the logic area is used for data processing and control logic implementation. The storage area and the logic area work together to achieve data storage, processing, and control.

[0076] Storage areas and logic areas can be isolated using isolation zones. Isolation zones are used to separate storage areas from logic areas, preventing current leakage between them.

[0077] The memory may include a substrate 10 and a first dielectric layer 411, a second dielectric layer 412, and a third dielectric layer 413 stacked sequentially on the substrate 10. That is, the arrangement direction of the substrate 10, the first dielectric layer 411, the second dielectric layer 412, and the third dielectric layer 413 is parallel to the thickness direction of the substrate 10.

[0078] The inclusion of a first dielectric layer 411, a second dielectric layer 412, and a third dielectric layer 413 in this memory is merely an example. In some embodiments, the memory may include more dielectric layers. This application does not limit the number of dielectric layers, which can be determined according to actual needs. For example, it can be determined according to the number of specific metal layers required for the logic circuit of the memory.

[0079] In some examples, the material of the dielectric layer may include one or a combination of silicon oxide, silicon nitride, and silicon oxynitride. The materials of different dielectric layers may be the same or different.

[0080] In some examples, the logic area of ​​the memory can contain logic devices and logic circuits.

[0081] Logic devices can be circuit components used to implement various logic functions. Logic devices can be used to perform basic logic operations, such as AND, OR, NOT, NAND, and NOR.

[0082] For example, logic devices may include elements such as transistors, resistors, and capacitors.

[0083] Logic circuits can be connected to logic devices to work with them to achieve logic functions.

[0084] The logic circuit may include a first metal layer 51 disposed within a first dielectric layer 411, and a second metal layer 52 disposed within a second dielectric layer 412. The first metal layer 51 and the second metal layer 52 are different circuit layers of the logic circuit. The first metal layer 51 and the second metal layer 52 are connected, for example, through conductive vias.

[0085] In some examples, the memory's storage area may have transistors and capacitors 60. The transistors (also called gates or switches) in the storage area can be used to selectively allow or block data access to specific memory cells 111.

[0086] To facilitate the distinction between transistors in the memory region and transistors in the logic region, please refer to Figures 3 to 5. The transistor in the memory region can be referred to as the first transistor 30, and the transistor in the logic region can be referred to as the second transistor 20.

[0087] In Figures 3 to 5, the memory region shows only one memory cell (which includes a first transistor 30 and a capacitor 60), and the logic region shows only one logic device (i.e., a second transistor 20). It should be understood that the structures shown in Figures 3 to 5 are merely examples and are not intended to limit the memory cells and logic devices. For example, the memory region may include multiple memory cells, and the logic region may include multiple logic devices.

[0088] The capacitor 60 can penetrate the first dielectric layer 411, the second dielectric layer 412, and the third dielectric layer 413, respectively. That is, at least a portion of the capacitor 60 can penetrate the first dielectric layer 411, the second dielectric layer 412, and the third dielectric layer 413.

[0089] In other words, the multilayer dielectric layer contains logic circuits located in the logic area and memory nodes (capacitors 60 in this application) located in the memory area. That is, the capacitors 60 in the memory area can be embedded in the subsequent logic circuits.

[0090] By embedding the capacitor 60 of the memory area into the logic circuit of the back-end process, the logic circuit area of ​​the back-end process can be effectively utilized, the capacitance value of the capacitor 60 can be increased, and the memory performance of the memory area can be improved.

[0091] For example, referring to Figures 3, 4 or 5, the sidewalls of capacitor 60 may be stepped.

[0092] The sidewall of capacitor 60 is stepped, so that the sidewall of capacitor 60 can form a stepped surface 62, or in other words, the sidewall of capacitor 60 can form a corner.

[0093] This application places the capacitor 60 within a multilayer dielectric layer of the storage region, and makes the sidewalls of the capacitor 60 stepped. It can be seen that when the capacitor 60 is formed within the multilayer dielectric layer of the storage region, the vias for housing the capacitor 60 are not formed using a single-stage drilling process, but rather using at least two drilling processes. Because when vias are prepared using two or more drilling processes, each drilling creates an inverted trapezoidal via, resulting in multiple interconnected inverted trapezoidal vias. Thus, after the capacitor 60 is formed within these interconnected inverted trapezoidal vias, the sidewalls of the capacitor 60 will be stepped.

[0094] Because the sidewalls of capacitor 60 are stepped, the vias within the multilayer dielectric layer for housing capacitor 60 can be formed using at least two drilling processes. By employing a staged drilling process, material can be filled into the via after each drilling to form a filler layer, followed by fabrication of the corresponding metal layer for the logic region and polishing of that metal layer. Thus, when at least a portion of the metal layer of the logic region is polished, the storage region can be supported by the filler layer. During polishing, the force applied by the polishing pad to the storage region and logic region is relatively balanced, improving the polishing effect of the metal layer. This reduces the impact on the logic circuit when capacitor 60 is embedded in the subsequent logic circuit fabrication process, thereby improving the compatibility of capacitor 60 with the existing logic circuit fabrication process.

[0095] The filling layer in this application can also be referred to as a capacitor support (node ​​holder).

[0096] In some examples, as shown in FIG3, the capacitor 60 may include a first portion and a second portion along a direction perpendicular to the surface of the substrate 10, with the first portion connected to the second portion. The first portion may penetrate through a first dielectric layer 411 and a second dielectric layer 412, and the second portion may penetrate through a third dielectric layer 413. The sidewalls of the first portion and the sidewalls of the second portion are connected in a stepped manner.

[0097] The sidewalls of the first part and the second part are connected in a stepped shape, so that the sidewalls of the capacitor 60 can form a stepped surface 62. For example, the stepped surface 62 on the sidewall of the capacitor 60 can be located at the junction of the second dielectric layer 412 and the third dielectric layer 413, or the stepped surface 62 on the sidewall of the capacitor 60 can be located at the connection between the first part and the second part.

[0098] The capacitor 60 of this application includes a first portion disposed in the first dielectric layer 411 and the second dielectric layer 412, and a second portion disposed in the third dielectric layer 413. The sidewalls of the first portion and the second portion are connected in a stepped shape. Thus, a through-hole for accommodating the capacitor 60 can be formed by two opening processes. The through-hole formed by one opening is located in the first dielectric layer 411 and the second dielectric layer 412, and the through-hole formed by the other opening is located in the third dielectric layer 413 (in this way, the sidewalls of the first portion and the second portion can be connected in a stepped shape). With the above-mentioned two-opening method, a through-hole penetrating the first dielectric layer 411 and the second dielectric layer 412 can be opened before the second metal layer 52 of the logic circuit is prepared, and a filling layer is formed by filling the through-hole with material; then the second metal layer 52 is prepared in the second dielectric layer 412 and polished.

[0099] In other words, in the memory of this application, since the sidewalls of the first part and the second part of the capacitor 60 are connected in a stepped shape, the memory can be fabricated using the above-mentioned process. In this way, the storage area can provide a support structure to evenly distribute the polishing pressure when the second metal layer 52 is polished. During the polishing process, the force applied by the polishing pad to the storage area and the logic area is relatively balanced, which can improve the polishing effect of the second metal layer 52. This can reduce the impact of the capacitor 60 on the logic circuit when it is embedded in the logic circuit of the subsequent process, and improve the compatibility of the capacitor 60 with the original process of the logic circuit.

[0100] Referring to Figure 4, in another possible implementation, the memory further includes a fourth medium layer 414 located between the second medium layer 412 and the third medium layer 413.

[0101] The logic region may have a third metal layer 53 located within the fourth dielectric layer 414, and the third metal layer 53 is connected to the second metal layer 52.

[0102] Different metal layers can be interconnected through conductive vias. For example, the first metal layer 51 and the second metal layer 52 can be connected through conductive vias, and the second metal layer 52 and the third metal layer 53 can be connected through conductive vias.

[0103] As shown in Figure 4, along a direction perpendicular to the surface of the substrate 10, the capacitor 60 may include a first part, a second part, and a third part, with the third part connected between the first and second parts. The first part may penetrate the first dielectric layer 411 and the second dielectric layer 412, the second part may penetrate the third dielectric layer 413, and the third part may penetrate the fourth dielectric layer 414. The sidewalls of the first and third parts are connected in a stepped shape, as are the sidewalls of the third and second parts.

[0104] The sidewalls of the first part and the third part are connected in a stepped shape, and the sidewalls of the third part and the second part are connected in a stepped shape. In this way, the sidewalls of the capacitor 60 can form a stepped surface 62, which includes a first stepped surface 621 and a second stepped surface 622.

[0105] For example, the first step surface 621 may be located at the junction of the fourth dielectric layer 414 and the third dielectric layer 413, or in other words, the first step surface 621 may be located at the junction of the third part and the second part. The second step surface 622 may be located at the junction of the fourth dielectric layer 414 and the second dielectric layer 412, or in other words, the second step surface 622 may be located at the junction of the third part and the first part.

[0106] The capacitor 60 of this application may include a first portion disposed in the first dielectric layer 411 and the second dielectric layer 412, a second portion disposed in the third dielectric layer 413, and a third portion disposed in the fourth dielectric layer 414. Furthermore, the sidewalls of the first portion and the third portion are connected in a stepped shape, and the sidewalls of the third portion and the second portion are connected in a stepped shape. Thus, a through-hole for accommodating the capacitor 60 can be formed through a three-stage drilling process, wherein the through-hole formed by one drilling is located in the first dielectric layer 411 and the second dielectric layer 412, the through-hole formed by another drilling is located in the fourth dielectric layer 414, and the through-hole formed by yet another drilling is located in the third dielectric layer 413 (this three-stage drilling allows the sidewalls of the first portion and the third portion to be connected in a stepped shape, and the sidewalls of the third portion and the second portion to be connected in a stepped shape).

[0107] By using the above-mentioned three-stage opening method, a through-hole penetrating the first dielectric layer 411 and the second dielectric layer 412 can be opened before the second metal layer 52 of the logic circuit is prepared, and a filling layer is formed by filling the through-hole with material; then the second metal layer 52 is prepared in the second dielectric layer 412 and polished; similarly, before the third metal layer 53 of the logic circuit is prepared, a through-hole penetrating the fourth dielectric layer 414 can be opened, and a filling layer is formed by filling the through-hole with material; then the third metal layer 53 is prepared in the fourth dielectric layer 414 and polished.

[0108] In other words, in the memory of this application, since the sidewalls of the first part and the third part of the capacitor 60 are connected in a stepped shape, and the sidewalls of the third part and the second part are connected in a stepped shape, the memory can be fabricated using the above-mentioned process. In this way, when the second metal layer 52 and the third metal layer 53 are polished respectively, the storage area can be provided with a support structure to distribute the polishing pressure. During the polishing process, the force applied by the polishing pad to the storage area and the logic area is relatively balanced, which can improve the polishing effect of the second metal layer 52 and the third metal layer 53. This can reduce the impact of the capacitor 60 on the logic circuit when it is embedded in the logic circuit of the subsequent process, and improve the compatibility of the capacitor 60 with the original process of the logic circuit.

[0109] Referring to Figure 4, in one possible implementation, along the direction from the first dielectric layer to the substrate 10, the dimensions of the first portion gradually decrease along the first direction, the dimensions of the second portion gradually decrease along the first direction, and the dimensions of the third portion gradually decrease along the first direction. The first direction is parallel to the surface of the substrate 10.

[0110] For ease of understanding, taking the orientation shown in Figure 4 as an example, along the direction from top to bottom (i.e., the direction from the first dielectric layer 411 toward the substrate 10), the dimensions of the first part, the second part, and the third part gradually decrease in the horizontal direction. That is to say, the first part, the second part, and the third part are each arranged in an inverted trapezoidal shape.

[0111] In this application, the capacitor 60 has a first portion whose dimensions gradually decrease along the first direction, a second portion whose dimensions gradually decrease along the first direction, and a third portion whose dimensions gradually decrease along the first direction. This allows the vias within the multilayer dielectric layer used to house the capacitor 60 to be formed using a conventional etching process, reducing the fabrication difficulty of the capacitor 60.

[0112] Referring to Figure 5, in one possible implementation, the fourth dielectric layer 414 may include multiple layers, with the multiple fourth dielectric layers 414 stacked sequentially between the second dielectric layer 412 and the third dielectric layer 413.

[0113] The term "multilayer fourth dielectric layer 414" refers to two or more fourth dielectric layers 414. That is, the number of fourth dielectric layers 414 can be two, three, or more. This application does not impose any restrictions on this. Figure 5 illustrates an example where the fourth dielectric layer 414 includes two layers.

[0114] When the fourth dielectric layer 414 comprises multiple layers, each fourth dielectric layer 414 may contain a third metal layer 53. That is, the number of fourth dielectric layers 414 and the number of third metal layers 53 may be the same, and multiple fourth dielectric layers 414 and multiple third metal layers 53 may correspond one-to-one.

[0115] Furthermore, when the third metal layer 53 comprises multiple layers, adjacent third metal layers 53 can be interconnected.

[0116] When the fourth dielectric layer 414 comprises multiple layers, each fourth dielectric layer 414 may have a third part. That is, the number of fourth dielectric layers 414 and the number of third parts may be the same, and multiple fourth dielectric layers 414 and multiple third parts may correspond one-to-one.

[0117] As shown in Figure 5, when the fourth dielectric layer 414 comprises multiple layers, the sidewalls of two adjacent third parts are connected in a stepped shape. In this way, the sidewalls of the capacitor 60 can form a stepped surface 62, which includes a first stepped surface 621, a second stepped surface 622, and a third stepped surface 623.

[0118] That is, when the fourth dielectric layer 414 includes multiple layers, the step surface 62 may include a third step surface 623 in addition to the first step surface 621 and the second step surface 622. The third step surface 623 is located at the junction of two adjacent fourth dielectric layers 414, or in other words, the third step surface 623 is located at the connection of the sidewalls of two adjacent third parts.

[0119] As the number of layers in the fourth dielectric layer 414 increases, the number of third step surfaces 623 also increases accordingly. For example, when the fourth dielectric layer 414 includes three layers, the third step surface 623 may include two; when the fourth dielectric layer 414 includes four layers, the third step surface 623 may include three.

[0120] This application does not limit the number of third step surfaces 623. Those skilled in the art can select them as needed. For example, the height of the capacitor 60 can be selected based on the capacitance value of the capacitor 60, and the number of times the through holes for accommodating the capacitor 60 are opened can be selected based on the height of the capacitor 60. The number of times the through holes are opened determines the number of step surfaces 62.

[0121] This application provides space for accommodating the capacitor 60 by setting multiple fourth dielectric layers 414, thereby improving the capacitance value of the capacitor 60. By including multiple fourth dielectric layers 414 in the capacitor 60, with each fourth dielectric layer 414 having a third portion and the sidewalls of adjacent third portions connected in a stepped shape, each fourth dielectric layer 414 can have vias formed to create space for accommodating the capacitor 60. That is, multiple vias can be formed through multiple via-drilling processes (this process allows the sidewalls of adjacent third portions to be connected in a stepped shape), which reduces the difficulty of creating vias for accommodating the capacitor 60, thus reducing the fabrication difficulty of the memory. Furthermore, the multiple via-drilling process allows for filling the vias with material to form a filling layer after each via-drilling of the fourth dielectric layer 414; then, after fabricating the third metal layer 53 located within the fourth dielectric layer 414, the third metal layer 53 is polished. This improves the polishing effect of each third metal layer 53, thereby achieving process compatibility between the logic circuit and the capacitor 60 fabrication.

[0122] Referring to Figures 3 to 5, in one possible implementation, the capacitor 60 may include a first electrode layer 631, a dielectric layer 632, and a second electrode layer 633; ​​the dielectric layer 632 is located between the first electrode layer 631 and the second electrode layer 633, and the first electrode layer 631 is connected to a transistor.

[0123] Of course, the capacitor 60 shown in Figures 3 to 5, which includes two electrode layers, is only an example. In other embodiments, the capacitor 60 may also include three or more electrode layers, with a dielectric layer 632 between adjacent electrode layers.

[0124] This application embeds the capacitor 60 into the logic circuit of the back-end process, which can obtain a deep trench capacitor in the multilayer dielectric layer of the back-end logic circuit, thereby increasing the surface area of ​​the electrode layer of the capacitor 60 and thus increasing the capacitance value of the capacitor 60.

[0125] Please continue to refer to Figures 3 to 5. In one possible implementation, the memory may further include a first insulating layer 70 and a second insulating layer 80, wherein the first insulating layer 70 is located between the second insulating layer 80 and the substrate 10, and the second insulating layer 80 is located between the first insulating layer 70 and the first dielectric layer 411.

[0126] The material of the first insulating layer 70 can be the same as the material of the second insulating layer 80. The materials of the first insulating layer 70, the second insulating layer 80, and the multilayer dielectric layer can also be the same.

[0127] The first insulating layer 70 may have a first contact hole 71 connected to the first electrode of the transistor in the storage region. That is, the first insulating layer 70 may have a first contact hole 71 connected to the first electrode of the first transistor 30. The first electrode may be the source or the drain.

[0128] The second insulating layer 80 may have a first conductive through-hole 81 connected to the first contact hole 71, and the capacitor 60 is connected to the first conductive through-hole 81. In this way, the first electrode of the first transistor 30 can be connected to the capacitor 60 through the first contact hole 71 and the first conductive through-hole 81.

[0129] In some examples, a second contact hole 72 may also be provided within the first insulating layer 70 of the storage area, and an electrode line 82 may also be provided within the second insulating layer 80 of the storage area. The second contact hole 72 connects between the second electrode of the first transistor 30 and the electrode line 82. In this way, the first electrode of the first transistor 30 is connected to the capacitor 60 through the first contact hole 71 and the first conductive via 81, and the second electrode of the first transistor 30 is connected to the electrode line 82 through the second contact hole 72.

[0130] One of the first electrode and the second electrode is the source, and the other is the drain. The electrode line 82 can be a bit line, and the gate of the first transistor 30 can be connected to the word line, so that the gate of the first transistor 30 can be controlled through the word line.

[0131] The source and drain of the first transistor 30 can be located on both sides of the gate of the first transistor 30. The source and drain of the first transistor 30 can be obtained by ion implantation of the substrate 10. For example, sidewalls can be formed on both sides of the gate of the first transistor 30, and ion implantation of the substrate 10 can be performed through a mask formed by the sidewalls.

[0132] This application enables the interconnection of the first transistor 30 and the capacitor 60 located at different levels by setting the first contact hole 71 and the first conductive through hole 81, and enables the interconnection of the first transistor 30 and the electrode line 82 by setting the second contact hole 72. This allows the first transistor 30 in the storage area to establish electrical connections with the capacitor 60 and the electrode line 82 respectively, thereby ensuring the smooth operation of data reading and writing. In addition, the setting of the first contact hole 71, the first conductive through hole 81 and the second contact hole 72 also makes the connection of the first transistor 30 with the capacitor 60 and the electrode line 82 more flexible.

[0133] Furthermore, the arrangement of the first contact hole 71, the first conductive through hole 81, and the second contact hole 72 can make more efficient use of space, enabling vertical interconnection between the transistor and the capacitor 60 and the electrode line 82, respectively. This helps to integrate more memory cells 111 within the limited area of ​​the chip 100, thereby improving the capacity and integration of the memory.

[0134] In some embodiments, the memory may further include an etch stop layer that covers the substrate 10, the transistors in the memory region (e.g., the first transistor 30), and the logic devices in the logic region (e.g., the second transistor 20). Providing an etch stop layer can facilitate improved etching accuracy and mitigate over-etching issues.

[0135] Figure 6 is a flowchart of one of the methods for preparing a memory according to an embodiment of this application. Figures 7 to 15 are structural diagrams obtained after the corresponding steps are completed when preparing one of the memory methods provided in the embodiment of this application. Referring to Figures 6 to 15, this application also provides a method for preparing a memory, which includes steps S1-S11.

[0136] Please refer to Figure 7. Step S1 includes: forming a logic device on the substrate 10 in the logic region and forming a transistor on the substrate 10 in the memory region.

[0137] The substrate 10 here is a semiconductor material. For example, the material of the substrate 10 can be silicon, germanium, silicon germanide, or silicon carbide; it can also be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other group III-V compounds. Those skilled in the art can select a suitable material as the substrate 10 according to actual needs. This application does not limit the specific material of the substrate 10.

[0138] The storage area is responsible for storing and accessing data, while the logic area is responsible for data processing and implementing control logic. The storage area and the logic area can be isolated from each other using an isolation zone. The isolation zone is used to prevent current leakage between the storage area and the logic area.

[0139] For example, the isolation region can be obtained by ion implantation of the substrate 10; or it can be obtained by forming a trench on the substrate 10 and filling the trench with an insulating material (e.g., silicon oxide). This application does not limit the specific form of the isolation region, and a suitable isolation method can be selected according to the requirements.

[0140] The memory area contains transistors, and the logic area contains logic devices.

[0141] For example, a logic device may include components such as transistors, resistors, and capacitors. Figure 7 illustrates a logic device including transistors as an example. It should be understood that a logic device may include other electronic components in addition to transistors, and this application does not limit this.

[0142] To facilitate the distinction between transistors in the memory area and transistors in the logic area, the transistor in the memory area is referred to as the first transistor 30 in Figure 7, and the transistor in the logic area is referred to as the second transistor 20 in Figure 7. The same applies to other related figures.

[0143] This application does not limit the specific formation of the logic devices and the first transistor 30, nor the specific number of the logic devices and the first transistor 30, which can be determined according to the integrated circuit layout design of the memory.

[0144] Referring to Figure 9, step S2 includes: forming a first dielectric layer 411, which is located on the substrate 10, logic devices and transistors (i.e., the first transistor 30).

[0145] That is, the first dielectric layer 411 is formed on the entire surface, such that the first dielectric layer 411 is located on the entire substrate 10, logic device and first transistor 30.

[0146] When the memory has an etch stop layer covering the substrate 10, logic devices and the first transistor 30, the first dielectric layer 411 covers the etch stop layer; when the memory has a second insulating layer 80, a first conductive via 81, an electrode line 82 and a second conductive via 83, the first dielectric layer 411 covers the second insulating layer 80, the first conductive via 81, the electrode line 82 and the second conductive via 83.

[0147] Referring to Figure 9, step S3 includes: forming a first metal layer 51 located within the first dielectric layer 411 in the logic region, and the first metal layer 51 being connected to the logic device.

[0148] That is, the connection between the logic device and the first metal layer 51 can be realized through step S3, and the signal interconnection between the logic device and the logic circuit can be realized.

[0149] In one possible implementation, referring to Figures 7 and 8, after step S1: forming logic devices on substrate 10 in the logic region and forming transistors on substrate 10 in the memory region; and before step S2: forming the first dielectric layer 411, the method for fabricating the memory may further include steps 1)-4).

[0150] Step 1): Form a first insulating layer 70, which covers the substrate 10, logic devices, and transistors.

[0151] When the memory has an etch stop layer covering the substrate 10, logic devices and the first transistor 30, the first insulating layer 70 covers the etch stop layer. Figure 8 is an example including the etch stop layer.

[0152] Step 2): A first contact hole 71 connected to the first electrode of the transistor is formed in the first insulating layer 70 of the storage area; a second contact hole 72 connected to the second electrode of the transistor is formed in the first insulating layer 70 of the storage area; and a third contact hole 73 connected to the logic device is formed in the first insulating layer 70 of the logic area. One of the first electrode and the second electrode is the source electrode, and the other is the drain electrode.

[0153] Step 3): Form a second insulating layer 80, which covers the first insulating layer 70, the first contact hole 71, the second contact hole 72 and the third contact hole 73.

[0154] Step 4): A first conductive via 81 connected to the first contact hole 71 is formed in the second insulating layer 80 of the storage area; an electrode line 82 connected to the second contact hole 72 is formed in the second insulating layer 80 of the storage area; and a second conductive via 83 connected to the third contact hole 73 is formed in the second insulating layer 80 of the logic area.

[0155] Among them, the electrode line 82 connected to the second contact hole 72 can be a bit line.

[0156] This application enables the interconnection of the first transistor 30 and the capacitor 60 located at different levels by setting the first contact hole 71 and the first conductive through hole 81, and enables the interconnection of the first transistor 30 and the electrode line 82 by setting the second contact hole 72. This facilitates the establishment of electrical connections between the first transistor 30 in the storage area and the electrode line 82 and the storage node to be formed later, thereby ensuring the smooth operation of data reading and writing.

[0157] Furthermore, the arrangement of the first contact hole 71, the first conductive via 81, the second contact hole 72, the third contact hole 73, and the second conductive via 83 can utilize space more effectively. The first contact hole 71, the first conductive via 81, and the second contact hole 72 facilitate vertical interconnection between the transistor and the electrode line 82 and the memory node in subsequent processes. The third contact hole 73 and the second conductive via 83 facilitate vertical interconnection between the logic devices and the first metal layer 51 of the logic circuit in subsequent processes. The arrangement of these contact holes and conductive vias helps to integrate more memory cells and logic devices within a limited chip area.

[0158] Referring to Figures 8 and 9, when the memory fabrication method includes steps 1) to 4) above, in step S3, the first metal layer 51 is connected to the logic device via the first conductive via 81 and the first contact hole 71. In subsequent processes, when the memory node is connected to the transistor, the memory node is connected to the transistor via the first conductive via 81 and the first contact hole 71.

[0159] Referring to Figure 10, step S4 includes: forming a second dielectric layer 412, which covers the first dielectric layer 411 and the first metal layer 51.

[0160] The material of the second dielectric layer 412 can be the same as that of the first dielectric layer 411.

[0161] Referring to Figures 10 and 11, step S5 includes: opening a first through-hole 421 in the storage area that penetrates the second dielectric layer 412 and the first dielectric layer 411, and filling the first through-hole 421 with material to form a first filling layer 422.

[0162] That is, the first through-hole 421 penetrates the second dielectric layer 412 and the first dielectric layer 411, and the first through-hole 421 is located in the storage area.

[0163] When the second insulating layer 80 and the first conductive through hole 81 are present, the first through hole 421 corresponds to the first conductive through hole 81. That is, the first through hole 421 is disposed above the first conductive through hole 81, and the first conductive through hole 81 can be exposed after the first through hole 421 is formed.

[0164] A first filling layer 422 can be formed by filling the first through hole 421 with material. When there is a first conductive through hole 81, the first filling layer 422 is connected to the first conductive through hole 81.

[0165] The first filler layer 422 can serve as a temporary filler layer, providing support for the polishing of the metal layer in subsequent processes. The size of the first through-hole 421 can be designed according to the size of the memory node to be formed later. In this way, the first through-hole 421 can serve as a space for accommodating the first filler layer 422, and can also serve as a space for accommodating the memory node after the first filler layer 422 is removed in subsequent processes.

[0166] In one possible implementation, the material of the first filling layer 422 may include at least one of polysilicon or silicon nitride. It should be understood that the inclusion of at least one of polysilicon or silicon nitride as the material of the first filling layer 422 is merely an example and not a limitation on the specific material of the first filling layer 422. Any feasible material may be selected by those skilled in the art, as long as it can easily fill the first via 421, has a certain mechanical support, and is easy to remove by wet or dry processes.

[0167] Polycrystalline silicon and silicon nitride are both materials with high hardness and good chemical stability. Using them as the materials for the first filler layer 422 can provide effective structural support for the memory area, enhancing its structural strength and stability. When the memory area needs to withstand the pressure from the polishing process of the subsequent logic circuit metal layers, the presence of the first filler layer 422 can make the stress on the memory area and the logic area more balanced, thereby improving the polishing effect of the logic circuit metal layers.

[0168] Furthermore, polysilicon and silicon nitride exhibit excellent etching selectivity and etching rate control in etching processes. This means that when it is necessary to remove the first filler layer 422, the etching depth and morphology can be precisely controlled by adjusting the etching parameters, thereby achieving effective removal of the first filler layer 422.

[0169] Referring to Figure 12, step S6 includes: forming a second metal layer 52 located within the second dielectric layer 412 in the logic region, and the second metal layer 52 being connected to the first metal layer 51.

[0170] In other words, this application performs step S6 after performing step S5, that is, after opening a first through hole 421 in the storage area that penetrates the second dielectric layer 412 and the first dielectric layer 411, and filling the first through hole 421 with material to form a first filling layer 422, a second metal layer 52 located in the second dielectric layer 412 is formed.

[0171] In short, this application forms a first filling layer 422 in the storage area before the second metal layer 52 is formed.

[0172] The second metal layer 52 serves as one of the metal layers in the logic circuit of the logic region and is connected to the first metal layer 51. For example, the first metal layer 51 can be fabricated using a single damascene process, and the second metal layer 52 can be fabricated using a double damascene process. The first metal layer 51 and the second metal layer 52 can be vertically interconnected via conductive vias.

[0173] Step S7 includes polishing the second metal layer 52.

[0174] That is, after the second metal layer 52 is formed, the second metal layer 52 can be polished. For example, the second metal layer 52 can be treated with chemical mechanical polishing (CMP) to remove excess material and achieve planarization of the surface of the second metal layer 52.

[0175] Before polishing the second metal layer 52, this application first forms a first through-hole 421 and fills the first through-hole 421 with material to form a first filling layer 422. Thus, during polishing of the second metal layer 52, the storage area, supported by the first filling layer 422, can withstand the pressure during the polishing process. Therefore, the force applied by the polishing pad to the storage area and logic area is more balanced, improving the polishing uniformity of the second metal layer 52. This reduces the impact on the logic circuit when the storage node is embedded in the subsequent process, thereby improving the compatibility between the storage node and the existing logic circuit processes.

[0176] Referring to Figure 13, step S8 includes: forming a third dielectric layer 413, which is located on the second dielectric layer 412, the second metal layer 52 and the first filler layer 422.

[0177] The material of the third dielectric layer 413 can be the same as the material of the second dielectric layer 412.

[0178] The third dielectric layer 413 can also serve as a mask to protect the metal layers of the logic circuit, preventing any impact on the logic circuit during the subsequent removal of the first fill layer 422 and the second fill layer 432, as well as during the formation of memory nodes.

[0179] Step S9 includes: opening a second through hole 441 through the third dielectric layer 413 in the storage area, the second through hole 441 corresponding to the first filling layer 422.

[0180] The correspondence between the second through hole 441 and the first filling layer 422 means that the second through hole 441 and the first filling layer 422 are in corresponding positions. For example, the second through hole 441 is located directly above the first filling layer 422.

[0181] When there is no other filling layer between the second through hole 441 and the first filling layer 422, the second through hole 441 can expose the first filling layer 422, as shown in Figure 13.

[0182] Referring to Figures 13 and 14, step S10 includes: removing the first filling layer 422 to obtain a connected first through hole 421 and a second through hole 441, wherein the sidewall of the second through hole 441 and the sidewall of the first through hole 421 are connected in a stepped shape.

[0183] The step-like connection between the sidewall of the second through hole 441 and the sidewall of the first through hole 421 is due to the fact that the first through hole 421 and the second through hole 441 are obtained through two drilling processes, and a step will be formed at the connection between the first through hole 421 and the second through hole 441 obtained by the two drilling processes.

[0184] Referring to Figures 14 and 15, step S11 includes: forming a capacitor 60 within the first through-hole 421 and the second through-hole 441; the capacitor 60 is connected to the transistor; and the sidewalls of the capacitor 60 are stepped. It should be understood that the transistor here is a transistor in the storage region, i.e., the first transistor 30.

[0185] That is, after polishing the second metal layer 52, the first filling layer 422 is removed. At this time, the first through hole 421 is exposed, and a capacitor 60 can be formed in the first through hole 421 and the second through hole 441 to obtain a deep trench capacitor. The capacitor 60 is connected to the first transistor 30.

[0186] Capacitor 60 is the storage node of the storage area.

[0187] Through the above-described fabrication process, before the formation and polishing of the second metal layer 52, a first filling layer 422 is prepared in the storage area. Therefore, the first filling layer 422 can serve as a support structure for the storage area to share the polishing pressure of the second metal layer 52. This makes the forces on the storage area and the logic area more balanced during the polishing of the second metal layer 52, thereby improving the polishing effect of the second metal layer 52, reducing the impact of the capacitor 60 on the original process of the logic circuit when it is embedded in the logic circuit, and improving process compatibility.

[0188] Furthermore, after the metal layer of the logic circuit is polished, the first through-hole 421 can be exposed after removing the first filler layer 422. This first through-hole 421 can also be reused as a accommodating space for the capacitor 60, eliminating the need for secondary slotting to form a space for accommodating the capacitor 60. Therefore, this application achieves compatibility between the storage area and the logic area while also simplifying the process and reducing the process difficulty to a certain extent.

[0189] As shown in Figures 3 to 5, after forming the capacitor 60, the memory fabrication method provided in this application can further fabricate a wiring layer 90 located above the third dielectric layer 413 and the capacitor 60. The wiring layer 90 can be connected to the capacitor 60 and can also be connected to the corresponding metal layer of the logic circuit. In this way, the capacitor 60 can be interconnected with the logic circuit.

[0190] In some examples, after polishing the second metal layer 52, the step of forming the third dielectric layer 413 can be performed immediately thereafter. That is, after performing step S7, step S8 can be performed immediately thereafter.

[0191] Alternatively, other filling layers can be prepared in the storage region; then, other metal layers can be prepared in the logic region, and the corresponding metal layers can be polished; after that, the third dielectric layer 413 is formed. That is to say, other steps can be added between steps S7 and S8, or no other steps can be added.

[0192] For example, when other steps are added between steps S7 and S8, such as continuing to prepare other filling layers in the storage area or other metal layers in the logic area between steps S7 and S8, Figure 16 is a second schematic flowchart of the memory fabrication method provided in the embodiment of this application, and Figures 17 to 21 are schematic diagrams of the structure obtained after the corresponding steps are completed when fabricating another memory provided in the embodiment of this application. Referring to Figures 16 to 21, the memory fabrication method of this application may also include steps S12-S15.

[0193] That is, in another possible implementation, after polishing the second metal layer 52 and before forming the third dielectric layer 413, the method for fabricating the memory provided in this application may further include steps S12-S15.

[0194] Referring to Figure 17, step S12 includes: forming a fourth dielectric layer 414, which covers the second dielectric layer 412, the second metal layer 52, and the first filler layer 422.

[0195] Please refer to Figures 17 and 18. Step S13 includes: opening a third through hole 431 through the fourth dielectric layer 414 in the storage area, and filling the third through hole 431 with material to form a second filling layer 432. The second filling layer 432 is connected to the first filling layer 422, and the sidewall of the second filling layer 432 is connected to the sidewall of the first filling layer 422 in a stepped shape.

[0196] The third through-hole 431 corresponds to the first filler layer 422; for example, the third through-hole 431 and the first filler layer 422 are coaxially arranged. This facilitates the formation of the storage node after the first filler layer 422 and the second filler layer 432 are removed in subsequent processes.

[0197] The first through-hole 421 and the third through-hole 431 are formed through a two-stage drilling process. Therefore, a step will be created at the junction of the sidewall of the third through-hole 431 and the sidewall of the first through-hole 421. Similarly, a step will also be created at the junction of the sidewalls of the first filler layer 422 and the second filler layer 432. Referring to Figures 17 and 21, after the subsequent formation of the storage node (i.e., capacitor 60), capacitor 60 will also have a step at this location.

[0198] The second filling layer 432 provides support for the polishing of the subsequent metal layer (i.e., the third metal layer 53 in Figure 19), which is set in the same layer as it. This facilitates the balance of force on the polishing pad in the storage area and logic area when the metal layer set in the same layer as it is polished, thereby improving the polishing effect of the metal layer.

[0199] Referring to Figure 19, step S14 includes: forming a third metal layer 53 in the fourth dielectric layer 414 of the logic region, and the third metal layer 53 is connected to the second metal layer 52.

[0200] The third metal layer 53 can be obtained by a double damask process, and the third metal layer 53 can be connected to the second metal layer 52 through a conductive via.

[0201] Step S15 includes polishing the third metal layer 53.

[0202] That is, after the third metal layer 53 is formed, the third metal layer 53 can be polished. For example, the third metal layer 53 can be treated by chemical mechanical polishing to remove excess material of the third metal layer 53 and achieve planarization of the surface of the third metal layer 53.

[0203] Before polishing the third metal layer 53, this application first forms a third through-hole 431 and fills the third through-hole 431 with material to form a second filling layer 432. Thus, during polishing of the third metal layer 53, the storage area, supported by the first filling layer 422 and the second filling layer 432, can withstand the pressure during the polishing process. Therefore, the force applied by the polishing pad to the storage area and the logic area is more balanced, improving the polishing uniformity of the third metal layer 53 and thereby enhancing the compatibility of the capacitor 60 with the existing logic circuit process.

[0204] When the second metal layer 52 is polished and before the third dielectric layer 413 is formed, the memory fabrication method provided in this application further includes steps S12-S15, and steps S8-S11 undergo adaptive changes. For example:

[0205] Step S8: Form a third dielectric layer 413, which is located on the second dielectric layer 412, the second metal layer 52, and the first filler layer 422. Then, the corresponding step is updated to S8-1: Form a third dielectric layer 413, which is located on the fourth dielectric layer 414, the third metal layer 53, and the second filler layer 432, as shown in Figure 20.

[0206] That is, when the method for fabricating the memory provided in this application further includes steps S12-S15, the third dielectric layer 413 is located not only on the second dielectric layer 412, the second metal layer 52 and the first filling layer 422, but also on the fourth dielectric layer 414, the third metal layer 53 and the second filling layer 432.

[0207] Step S9: A second through-hole 441 is formed in the storage area, penetrating the third dielectric layer 413. The second through-hole 441 corresponds to the first fill layer 422. This is then updated to step S9-1: A second through-hole 441 is formed in the storage area, penetrating the third dielectric layer 413. The second through-hole 441 corresponds to the second fill layer 432, as shown in Figure 20.

[0208] That is, when the method for fabricating the memory provided in this application further includes steps S12-S15, the second through-hole 441 not only corresponds to the first filling layer 422, but also corresponds to the second filling layer 432.

[0209] Step S10: Remove the first filling layer 422 to obtain a connected first through hole 421 and a second through hole 441. The sidewall of the second through hole 441 and the sidewall of the first through hole 421 are connected in a stepped shape. Then, the process is updated to step S10-1: Remove the first filling layer 422 and the second filling layer 432 to obtain a connected first through hole 421, a third through hole 431, and a second through hole 441. The sidewall of the second through hole 441 and the sidewall of the third through hole 431 are connected in a stepped shape, and the sidewall of the third through hole 431 and the sidewall of the first through hole 421 are connected in a stepped shape.

[0210] That is, when the method for fabricating the memory provided in this application further includes steps S12-S15, it is necessary not only to remove the first filling layer 422, but also to remove the second filling layer 432. After removing the first filling layer 422 and the second filling layer 432, a connected first through-hole 421, a third through-hole 431, and a second through-hole 441 will be formed.

[0211] In addition, due to the presence of the third through hole 431, the connection between the sidewall of the second through hole 441 and the sidewall of the first through hole 421 can form two steps, namely, the sidewall of the second through hole 441 and the sidewall of the third through hole 431 are connected in a stepped shape, and the sidewall of the third through hole 431 and the sidewall of the first through hole 421 are connected in a stepped shape.

[0212] Step S11: A capacitor 60 is formed in the first through hole 421 and the second through hole 441. The capacitor 60 is connected to the transistor, and the sidewall of the capacitor 60 is stepped. The corresponding update is to step S11-1: A capacitor 60 is formed in the first through hole 421, the third through hole 431, and the second through hole 441. The capacitor 60 is connected to the transistor, and the sidewall of the capacitor 60 is stepped.

[0213] After forming capacitor 60, the device shown in FIG21 can be obtained. Similarly, as shown in FIG4, after forming capacitor 60, the memory fabrication method provided in this application can also fabricate wiring layer 90 located above the third dielectric layer 413 and capacitor 60. Wiring layer 90 can be connected to capacitor 60 and can be connected to the corresponding metal layer of logic circuit. In this way, capacitor 60 can be interconnected with logic circuit.

[0214] The fabrication method of this application involves polishing the second metal layer 52 and forming a fourth dielectric layer 414 before forming the third dielectric layer 413, and forming a third via 431 within the fourth dielectric layer 414 of the storage region. Then, material is filled into the third via 431 to form a second filling layer 432. Subsequently, a third metal layer 53 is fabricated within the fourth dielectric layer 414 of the logic region, and then polished. In this way, before polishing the third metal layer 53, because the storage region has the first filling layer 422 and the second filling layer 432 as structural supports, the stress on the storage region and the logic region is more balanced during polishing, resulting in a better polishing effect for the third metal layer 53. This process improves the polishing effect of the second metal layer 52 and the third metal layer 53, enabling the capacitor 60 to be embedded in the logic circuit and achieve process compatibility with the logic circuit.

[0215] In addition, the first through-hole 421 and the third through-hole 431 obtained after removing the first filling layer 422 and the second filling layer 432, in which capacitor 60 is fabricated, can increase the capacitance value of capacitor 60 and improve the storage capacity of the storage area.

[0216] In one possible implementation, step S10: removing the first fill layer 422 can be achieved in the following way:

[0217] The first filler layer 422 was removed using a wet etching process.

[0218] Wet etching uses a liquid chemical solution to react with the material being etched, dissolving away unwanted portions. Because the solution can flow and penetrate into irregularly shaped holes, wet etching is more effective at removing the filling layer within stepped vias.

[0219] In addition, wet etching requires simple equipment and has a high etching rate. Using wet etching to remove the first filling layer 422 is low-cost and highly efficient.

[0220] Furthermore, when there is a second filling layer 432 or other filling layers, a wet etching process can be used to remove them together.

[0221] In one feasible approach, the materials of the first filler layer 422 and the second filler layer 432 can be the same. Using the same materials for the first filler layer 422 and the second filler layer 432 can reduce the difficulty of removing them. For example, when removing the first filler layer 422 and the second filler layer 432 using wet etching, the same solution can be used to remove the filler layers.

[0222] In one possible implementation, the shapes of the openings of the third via 431, the second via 441, and the first via 421 away from the substrate 10 are all the same. The areas of the openings of the third via 431, the second via 441, and the first via 421 away from the substrate 10 are also the same.

[0223] That is, the openings of the third through-hole 431, the second through-hole 441, and the first through-hole 421 away from the substrate 10 are exactly the same. In this way, the same photomask can be used when forming the first through-hole 421, the third through-hole 431, and the second through-hole 441, which can reduce the number of photomasks and reduce manufacturing costs.

[0224] In one possible implementation, step S11: forming a capacitor 60 within the first via 421 and the second via 441 can be achieved by forming the capacitor 60 within the first via 421 and the second via 441 using an atomic layer deposition process.

[0225] Atomic layer deposition (ALD) is a technique that deposits atoms layer by layer onto a substrate by growing single-atom films. ALD offers high uniformity and consistency, enabling the formation of uniform and dense thin films on surfaces with complex shapes and structures. Therefore, when forming capacitors 60 within stepped vias, traditional thin-film deposition methods (such as PECVD or PVD) may encounter problems such as different deposition rates on the sidewalls and bottom, resulting in voids. This application utilizes ALD, which, due to its layer-by-layer deposition characteristics, achieves relatively uniform coverage and deposition on the bottom and sidewalls (including the steps) within the vias.

[0226] Step S11: A capacitor 60 is formed in the first through hole 421 and the second through hole 441. This can be achieved by forming a first electrode layer 631 on the sidewall and bottom wall of the first through hole 421 and the sidewall of the second through hole 441, and the first electrode layer 631 is connected to the transistor; a dielectric layer 632 is formed on the first electrode layer 631; and a second electrode layer 633 is formed on the dielectric layer 632.

[0227] Of course, the above-described method of forming the capacitor 60 is merely an example. In other embodiments, a dielectric layer 632 and a third electrode layer may be formed after the second electrode layer 633 is formed. The number of electrode layers and the number of dielectric layers 632 in the capacitor 60 can be determined according to design requirements. For example, the number of electrode layers can be appropriately increased when a high capacitance value is required. The above-described form of the capacitor 60 is merely an example and should not be considered as a limitation of this application.

[0228] Furthermore, in this embodiment, by setting a first filling layer 422 and a second filling layer 432, on the one hand, when the second metal layer 52 is polished and the third metal layer 53 is polished, the first filling layer 422 and the second filling layer 432 can provide structural support in the storage area, enabling the storage area and logic area to be relatively balanced in terms of force, thereby improving the polishing effect and achieving process compatibility; on the other hand, the first through hole 421 at the first filling layer 422 and the third through hole 431 at the second filling layer 432 can also disassemble the accommodating space of the capacitor 60. That is, the space used to accommodate the capacitor 60 is divided into the first through hole 421 and the third through hole 431, which can reduce the etching difficulty compared to performing deep trench etching in one go. Moreover, after drilling holes in stages, the aspect ratio of each hole is relatively low, so there is no need to specially add an etching stop layer, which can save the setting of the etching stop layer, simplify the process flow and reduce manufacturing costs.

[0229] Furthermore, the number of infill layers in this application can be adjusted arbitrarily from one to multiple layers according to the capacitance requirement. For example, the number of infill layers can be increased when a high capacitance is required, and the number of infill layers can be decreased when a low capacitance is required.

[0230] For example, when it is necessary to increase the capacitance of capacitor 60 on the basis of the second filling layer 432, Figures 22 to 26 are schematic diagrams of the structure obtained after the corresponding steps are completed when preparing another memory provided by the embodiment of this application. Referring to Figures 22 to 26, a filling layer can be further stacked on the second filling layer 432. The steps can be as follows:

[0231] As shown in Figure 22, after polishing the third metal layer 53, a new fourth dielectric layer 414 can be formed on the fourth dielectric layer 414, and a new third via 431 is opened on the new fourth dielectric layer 414 in the storage area. Then, referring to Figures 22 and 23, a new second filling layer 432 is formed by filling the new third via 431 with material. After that, a new third metal layer 53 is formed in the new fourth dielectric layer 414 in the logic area, as shown in Figure 24. Then, a third dielectric layer 413 is formed on the new third metal layer 53, and a through second via 441 is opened in the third dielectric layer 413 in the storage area, as shown in Figure 25. Finally, the first filling layer 422 and the two second filling layers 432 are removed, and a capacitor 60 is formed in the exposed first via, third via, and second via, thus obtaining the device shown in Figure 26.

[0232] In short, when it is necessary to increase the capacitance of capacitor 60, after performing step S15, the following steps can be repeated: forming a fourth dielectric layer 414; opening a third via 431 in the fourth dielectric layer 414 of the storage area; filling the third via 431 with material to form a second filling layer 432; forming a third metal layer 53 in the fourth dielectric layer 414 of the logic area and polishing it; finally, forming a third dielectric layer 413 and opening a second via 441 in the third dielectric layer 413, and then forming capacitor 60. The specific number of repetitions can be determined according to the capacitance requirement of capacitor 60.

[0233] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory has a storage area and a logic area, and the memory includes a substrate and a first dielectric layer, a second dielectric layer and a third dielectric layer stacked sequentially on the substrate; The logic region has logic devices disposed on the substrate, a first metal layer disposed within the first dielectric layer, and a second metal layer disposed within the second dielectric layer; the logic devices are connected to the first metal layer, and the first metal layer is connected to the second metal layer. The storage region has a transistor and a capacitor. The transistor is disposed on the substrate, and the capacitor penetrates the first dielectric layer, the second dielectric layer and the third dielectric layer. The capacitor is connected to the transistor. The sidewall of the capacitor is stepped.

2. The memory according to claim 1, characterized in that, Along a direction perpendicular to the surface of the substrate, the capacitor includes a first portion and a second portion connected to the first portion, the first portion penetrating the first dielectric layer and the second dielectric layer, and the second portion penetrating the third dielectric layer; the sidewalls of the first portion and the sidewalls of the second portion are connected in a stepped shape.

3. The memory according to claim 1, characterized in that, The memory further includes a fourth medium layer, which is located between the second medium layer and the third medium layer; The logic region has a third metal layer located within the fourth dielectric layer, and the third metal layer is connected to the second metal layer; Along a direction perpendicular to the surface of the substrate, the capacitor includes a first portion, a second portion, and a third portion, the third portion being connected between the first portion and the second portion; the first portion penetrates a first dielectric layer and a second dielectric layer, the second portion penetrates the third dielectric layer, and the third portion penetrates the fourth dielectric layer; The sidewall of the first part and the sidewall of the third part are connected in a stepped shape, and the sidewall of the third part and the sidewall of the second part are connected in a stepped shape.

4. The memory according to claim 3, characterized in that, Along the direction from the first dielectric layer to the substrate, the size of the first portion gradually decreases along the first direction, the size of the second portion gradually decreases along the first direction, and the size of the third portion gradually decreases along the first direction; The first direction is parallel to the surface of the substrate.

5. The memory according to claim 3 or 4, characterized in that, The fourth dielectric layer comprises multiple layers, which are stacked sequentially between the second dielectric layer and the third dielectric layer. Each of the fourth dielectric layers contains the third metal layer; each of the fourth dielectric layers contains the third portion; The sidewalls of two adjacent third parts are connected in a stepped shape.

6. The memory according to any one of claims 1-5, characterized in that, The capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer; The dielectric layer is located between the first electrode layer and the second electrode layer, and the first electrode layer is connected to the transistor.

7. The memory according to any one of claims 1-6, characterized in that, The memory includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the second insulating layer and the substrate, and the second insulating layer is located between the first insulating layer and the first dielectric layer; The first insulating layer has a first contact hole that connects to the first electrode of the transistor; The second insulating layer has a first conductive through hole that is connected to the first contact hole, and the capacitor is connected to the first conductive through hole.

8. A semiconductor packaging structure, characterized in that, include: Packaging substrate; The memory according to any one of claims 1-7, wherein the memory is connected to the packaging substrate.

9. An electronic device, characterized in that, include: Circuit board; The semiconductor packaging structure as described in claim 8 is connected to the circuit board.

10. A method for fabricating a memory, characterized in that, include: Logic devices are formed on the substrate in the logic region, and transistors are formed on the substrate in the memory region; A first dielectric layer is formed on the substrate, the logic device, and the transistor; A first metal layer is formed within the first dielectric layer in the logic region, and the first metal layer is connected to the logic device. A second dielectric layer is formed, which covers the first dielectric layer and the first metal layer; A first through-hole is formed in the storage area, penetrating the second dielectric layer and the first dielectric layer, and the first through-hole is filled with material to form a first filling layer; A second metal layer is formed within the second dielectric layer in the logic region, and the second metal layer is connected to the first metal layer. The second metal layer is polished. A third dielectric layer is formed on the second dielectric layer, the second metal layer, and the first filler layer; A second through-hole is formed in the storage area, penetrating the third dielectric layer, and the second through-hole corresponds to the first filling layer; Remove the first filling layer to obtain the first through hole and the second through hole that are connected. The sidewall of the second through hole and the sidewall of the first through hole are connected in a stepped shape. A capacitor is formed within the first and second through holes, the capacitor being connected to the transistor, and the sidewall of the capacitor being stepped.

11. The method for fabricating a memory according to claim 10, characterized in that, The material of the first filling layer includes at least one of polycrystalline silicon or silicon nitride.

12. The method for fabricating a memory according to claim 10 or 11, characterized in that, After polishing the second metal layer and before forming the third dielectric layer, the method further includes: A fourth dielectric layer is formed, which covers the second dielectric layer, the second metal layer, and the first filler layer; A third through hole is made in the storage area to penetrate the fourth medium layer, and the third through hole is filled with material to form a second filling layer. The second filling layer is connected to the first filling layer, and the sidewall of the second filling layer is connected to the sidewall of the first filling layer in a stepped shape. A third metal layer is formed within the fourth dielectric layer of the logic region, and the third metal layer is connected to the second metal layer. The third metal layer is polished.

13. The method for fabricating a memory according to claim 12, characterized in that, The material of the first filler layer is the same as the material of the second filler layer.

14. The method for fabricating a memory according to claim 12 or 13, characterized in that, The shapes of the openings of the third through-hole away from the substrate, the second through-hole away from the substrate, and the first through-hole away from the substrate are all the same. The areas of the openings of the third through-hole away from the substrate, the second through-hole away from the substrate, and the first through-hole away from the substrate are all the same.

15. The method for fabricating a memory according to any one of claims 10-14, characterized in that, Removing the first filler layer includes: The first filling layer was removed using a wet etching process.

16. The method for fabricating a memory according to any one of claims 10-15, characterized in that, Forming capacitors within the first and second through holes includes: Capacitors are formed in the first and second vias using atomic layer deposition.

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