Row drive buffer, display panel, drive and control method and display apparatus

Abstract

Provided in the present disclosure are a row drive buffer, a display panel, a drive and control method and a display apparatus. The row drive buffer comprises a control switch logic circuit and a buffer circuit; an output terminal of the buffer circuit is electrically connected to a drive output terminal; the control switch logic circuit is electrically connected to an enable control terminal, an input signal terminal and a control terminal of the buffer circuit and is used to, when the enable control terminal provides a valid enable control signal, provide, by means of the buffer circuit, to the drive output terminal an input signal provided by the input signal terminal and, when the enable control terminal provides an invalid enable control signal, control the buffer circuit to stop providing the input signal to the drive output terminal. The present disclosure can be compatible with an isolation function for a normal operation mode and an AOI (automated optical inspection) test mode.

Description

Line drive buffer, display panel, driving and control method and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510118340.2, filed in China on January 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a line drive buffer, a display panel, a driving and control method, and a display device. Background Technology

[0004] The associated row drive buffer is incompatible with the isolation function of normal operation mode and AOI (Automated Optical Inspection) test mode. Summary of the Invention

[0005] The main objective of this disclosure is to provide a line drive buffer, a display panel, a driving and control method, and a display device to solve the problem in the related art of incompatible isolation functions between normal working mode and AOI (automatic optical inspection) test mode.

[0006] In one aspect, embodiments of this disclosure provide a row drive buffer, including a control switch logic circuit and a buffer circuit; the output terminal of the buffer circuit is electrically connected to a drive output terminal.

[0007] The control switch logic circuit is electrically connected to the enable control terminal, the input signal terminal, and the control terminal of the buffer circuit, respectively. When the enable control terminal provides a valid enable control signal, it provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit. When the enable control terminal provides an invalid enable control signal, it controls the buffer circuit to stop providing the input signal to the drive output terminal.

[0008] Optionally, the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate, and a control inverter; the buffer circuit includes a first control terminal and a second control terminal.

[0009] The first input terminal of the first NAND gate is electrically connected to the enable control terminal, the second input terminal of the first NAND gate is electrically connected to the input signal terminal, and the output terminal of the first NAND gate is electrically connected to the input terminal of the control transmission gate.

[0010] The first input terminal of the second NAND gate is electrically connected to the enable control terminal, the second input terminal of the second NAND gate is electrically connected to the inverting input signal terminal, and the output terminal of the second NAND gate is electrically connected to the input terminal of the control inverter.

[0011] The output terminal of the control transmission gate is electrically connected to the first control terminal, and the output terminal of the control inverter is electrically connected to the second control terminal;

[0012] The control transmission gate is used to provide the signal connected to its input terminal to the first control terminal;

[0013] The control inverter is used to invert the signal input to its input terminal to obtain an inverted signal, and then provide the inverted signal to the second control terminal.

[0014] Optionally, the buffer includes an inverter, which includes at least one first transistor and at least one second transistor;

[0015] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the drive output terminal.

[0016] The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the drive output terminal, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0017] Optionally, the first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0018] In a second aspect, embodiments of this disclosure provide a display panel including a driving module, the driving module including N of the above-described row driving buffers; N is an integer greater than 1.

[0019] The display panel described in at least one embodiment of this disclosure includes multiple rows of scan lines; the nth row drive buffer includes an nth drive output terminal; n is a positive integer less than or equal to N; the nth drive output terminal is electrically connected to the nth row of scan lines.

[0020] Optionally, the drive module further includes a test control switch circuit;

[0021] The test control switch circuit includes N switch sub-circuits;

[0022] The control terminal of the nth switch sub-circuit is electrically connected to the test control line, the first terminal of the nth switch sub-circuit is electrically connected to the test signal line, and the second terminal of the nth switch sub-circuit is electrically connected to the nth drive output terminal. The nth switch sub-circuit is used to control the connection between the test signal line and the nth drive output terminal when the test control line provides a valid test control signal, and to control the disconnection between the test signal line and the nth drive output terminal when the test control line provides an invalid test control signal.

[0023] Optionally, the nth switch sub-circuit includes the nth transmission gate; the test control line includes a positive phase test control line and an inverted phase test control line;

[0024] The input terminal of the nth transmission gate is electrically connected to the test signal line, and the output terminal of the nth transmission gate is electrically connected to the nth drive output terminal.

[0025] The positive phase control terminal of the nth transmission gate is electrically connected to the positive phase test control line, and the negative phase control terminal of the nth transmission gate is electrically connected to the negative phase test control line.

[0026] Optionally, the test signal line is directly electrically connected to the first end of each of the N switch sub-circuits.

[0027] The display panel described in at least one embodiment of this disclosure further includes a shift register and a level converter;

[0028] The shift register includes a multi-stage shift register unit, and the level converter includes a multi-stage level conversion unit;

[0029] The nth-stage shift register unit is electrically connected to the nth-stage level conversion unit and is used to provide the nth-stage level conversion unit with the nth-stage drive signal;

[0030] The nth level level conversion unit is electrically connected to the nth row drive buffer and is used to perform level conversion on the nth drive signal and provide the level-converted nth drive signal to the nth row drive buffer.

[0031] The display panel described in at least one embodiment of this disclosure includes a multi-row, multi-column pixel circuit, and the driving module includes a first driving module, a second driving module, and a third driving module;

[0032] The first driving module is used to provide a first scan signal for writing control data voltage to the pixel circuit;

[0033] The second driving module is used to provide a second scanning signal for the pixel circuit to control light emission;

[0034] The third driving module is used to provide the pixel circuit with a third scan signal for initialization control;

[0035] The first drive module includes a first row drive buffer, the second drive module includes a second row drive buffer, and the third drive module includes a third row drive buffer; the first row drive buffer includes a first buffer, the second row drive buffer includes a second buffer, and the third row drive buffer includes a third buffer.

[0036] The first buffer includes A first transistors and A second transistors connected in parallel; the second buffer includes B first transistors and B second transistors connected in parallel; and the third buffer includes C first transistors and C second transistors connected in parallel.

[0037] A is greater than B, A is greater than C; A, B and C are all positive integers.

[0038] The display panel described in at least one embodiment of this disclosure includes a first test signal line, a second test signal line, and a third test signal line; the first driving module includes a first test control switch circuit, the second driving module includes a second test control switch circuit, and the third driving module includes a third test control switch circuit;

[0039] The first driving module includes a plurality of first row driving buffers arranged sequentially along a first direction, and the first test signal line extends along the first direction; the first test signal line is directly electrically connected to the first terminals of a plurality of switch sub-circuits included in the first test control switch circuit.

[0040] The second drive module includes multiple second row drive buffers arranged sequentially along a first direction, and the second test signal line extends along the first direction; the second test signal line is directly electrically connected to the first terminals of multiple switch sub-circuits included in the second test control switch circuit;

[0041] The third driving module includes multiple third row driving buffers arranged sequentially along a first direction, and the third test signal line extends along the first direction; the third test signal line is directly electrically connected to the first terminals of multiple switch sub-circuits included in the third test control switch circuit. Optionally, the driving module includes a multi-level driving circuit and at least one pseudo-driving circuit; the pseudo-driving circuit includes at least one pseudo row driving buffer; the display panel includes at least one row of pseudo pixel circuits;

[0042] The pseudo-row drive buffer in the last stage pseudo-drive circuit of the drive module is electrically connected to the corresponding test signal line and the last row pseudo-pixel circuit, respectively.

[0043] In a third aspect, embodiments of this disclosure provide a driving method applied to the aforementioned row driving buffer, the driving method comprising:

[0044] When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit;

[0045] When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the drive output terminal.

[0046] In a fourth aspect, an embodiment of the present disclosure provides a control method applied to the aforementioned display panel, characterized in that the control method includes:

[0047] When the display panel is in the optical inspection stage, the enable control terminal provides an invalid enable control signal, and the control switch logic circuit controls the buffer circuit to stop providing input signals to the drive output terminal. Under the control of the test control signal, the switch sub-circuit controls the connection between the test signal line and the corresponding drive output terminal.

[0048] When the display panel is in the display stage, the enable control terminal provides an effective enable control signal. The control switch logic circuit provides the input signal provided by the input signal terminal through the buffer circuit to the drive output terminal. Under the control of the test control signal, the switch sub-circuit controls the test signal line to disconnect from the corresponding drive output terminal.

[0049] In a fifth aspect, embodiments of this disclosure provide a display device including the display panel described above.

[0050] The row drive buffer, display panel, driving and control method, and display device described in this disclosure are compatible with the isolation function of normal working mode and AOI (automatic optical inspection) test mode. The state of the row drive buffer can be controlled to be on or off by the enable control signal, thereby realizing the isolation between normal working mode and AOI test mode. Attached Figure Description

[0051] Figure 1 is a structural diagram of the row-driven buffer according to an embodiment of this disclosure;

[0052] Figure 2 is a structural diagram of a row-driven buffer according to at least one embodiment of the present disclosure;

[0053] Figure 3 is a circuit diagram of a row drive buffer according to at least one embodiment of the present disclosure;

[0054] Figure 4 is a structural diagram of a row-driven buffer according to at least one embodiment of the present disclosure;

[0055] Figure 5A is a waveform diagram of a scanning signal with strong driving capability provided by the drive output terminal OT;

[0056] Figure 5B is a waveform diagram of a scan signal with weak driving capability provided by the drive output terminal OT;

[0057] Figure 6 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0058] Figure 7 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0059] Figure 8 is a circuit diagram of the driving module according to at least one embodiment of the present disclosure;

[0060] Figure 9A is a schematic diagram of the working state of at least one embodiment of the drive module shown in Figure 8;

[0061] Figure 9B is a schematic diagram of the working state of at least one embodiment of the drive module shown in Figure 8;

[0062] Figure 10 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0063] Figure 11 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0064] Figure 12A is a circuit diagram of a drive module according to at least one embodiment of the present disclosure;

[0065] Figure 12B is a circuit diagram of the shift register chip SRC in Figure 12A;

[0066] Figure 12C is the circuit diagram of the level converter chip LSC in Figure 12A;

[0067] Figure 12D is the circuit diagram of the row drive buffer chip LDC in Figure 12A;

[0068] Figure 13 is a circuit diagram of a plurality of row drive buffers according to at least one embodiment of the present disclosure;

[0069] Figure 14 is a partial layout diagram of at least one embodiment of the drive module;

[0070] Figure 15 is a layout diagram with signal lines added based on Figure 14. Detailed Implementation

[0071] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0072] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0073] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0074] As shown in Figure 1, the row drive buffer of this embodiment includes a control switch logic circuit 11 and a buffer circuit 12; the output terminal of the buffer circuit 12 is electrically connected to the drive output terminal OT.

[0075] The control switch logic circuit 11 is electrically connected to the enable control terminal LD_EN, the input signal terminal SI, and the control terminal of the buffer circuit 12, respectively. When the enable control terminal LD_EN provides a valid enable control signal, it provides the input signal provided by the input signal terminal SI through the buffer circuit 12 to the drive output terminal OT. When the enable control terminal LD_EN provides an invalid enable control signal, it controls the buffer circuit 12 to stop providing the input signal to the drive output terminal OT.

[0076] The row drive buffer described in this embodiment includes a control switch logic circuit and a buffer circuit. When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal to the drive output terminal through the buffer circuit. When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the drive output terminal, thereby controlling the drive output terminal to be in a high-impedance state. At this time, external test input signals for AOI testing can be provided to the drive output terminal through corresponding test signal lines for AOI testing. The row drive buffer described in this embodiment is compatible with the isolation function of normal working mode and AOI test mode. The state of the row drive buffer can be controlled to be on or off by the enable control signal, thereby achieving isolation between normal working mode and AOI test mode.

[0077] In addition to enhancing driving capability, the row drive buffer described in at least one embodiment of this disclosure also has the function of switching between normal working mode and AOI (automatic optical inspection) test mode. This not only ensures a single path for signal transmission in AOI test mode, but also protects the reliability of the drive module.

[0078] At least one embodiment of this disclosure provides a row driving buffer applied to a driving module, which is mainly implemented by digital circuits and provides control signals for row driving of a pixel circuit array.

[0079] A line driver (line drive buffer) is essentially a tri-state buffer. Its output is controlled by the enable input. When the enable input provides a valid enable control signal, the line driver outputs in its normal logic state; when the enable input provides an invalid enable control signal, the line driver's output is in a high-impedance state, equivalent to a circuit open circuit. The core function of the line drive buffer is to enhance the driving capability of the signal without changing the signal logic. Therefore, the line driver can serve as the last stage of the drive module, enhancing the driving capability of the line drive signals before they enter the pixel circuit array.

[0080] The drive signal output by the drive module controls the gate of the switching transistor in the pixel circuit (the first terminal of the switching transistor can be electrically connected to the data line, and the second terminal of the switching transistor can be electrically connected to the drive transistor). The switching timing of the switching transistor determines the working logic of the pixel circuit. If the response speed of the switching transistor is slow, the grayscale voltage may not be written to the pixel circuit in time, resulting in insufficient charging rate and poor display uniformity. Therefore, the Line Driver can improve the switching response time and optimize the instantaneous rise and fall time of the drive signal, thereby ensuring that the charging rate meets the design specifications.

[0081] In at least one embodiment of this disclosure, the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate, and a control inverter; the buffer circuit includes a first control terminal and a second control terminal.

[0082] The first input terminal of the first NAND gate is electrically connected to the enable control terminal, the second input terminal of the first NAND gate is electrically connected to the input signal terminal, and the output terminal of the first NAND gate is electrically connected to the input terminal of the control transmission gate.

[0083] The first input terminal of the second NAND gate is electrically connected to the enable control terminal, the second input terminal of the second NAND gate is electrically connected to the inverting input signal terminal, and the output terminal of the second NAND gate is electrically connected to the input terminal of the control inverter.

[0084] The output terminal of the control transmission gate is electrically connected to the first control terminal, and the output terminal of the control inverter is electrically connected to the second control terminal;

[0085] The control transmission gate is used to provide the signal connected to its input terminal to the first control terminal;

[0086] The control inverter is used to invert the signal input to its input terminal to obtain an inverted signal, and then provide the inverted signal to the second control terminal.

[0087] In a specific implementation, the control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate, and a control inverter; the buffer circuit includes a first control terminal and a second control terminal; the first NAND gate performs a NAND operation on the enable control signal and the input signal, and provides the resulting signal to the input terminal of the control transmission gate; the second NAND gate performs a NAND operation on the enable control signal and the inverted input signal provided by the inverted input signal terminal, and provides the resulting signal to the input terminal of the control inverter.

[0088] As shown in Figure 2, the control switch logic circuit includes a first NAND gate NAD1, a second NAND gate NAD2, a control transmission gate TGC, and a control inverter FC; the buffer circuit includes a first control terminal CT1 and a second control terminal CT2.

[0089] The first input terminal of the first NAND gate NAD1 is electrically connected to the enable control terminal LD_EN, the second input terminal of the first NAND gate NAD1 is electrically connected to the input signal terminal SI, and the output terminal of the first NAND gate NAD1 is electrically connected to the input terminal of the control transmission gate TGC.

[0090] The first input terminal of the second NAND gate NAD2 is electrically connected to the enable control terminal, the second input terminal of the second NAND gate NAD2 is electrically connected to the inverting input signal terminal FSI, and the output terminal of the second NAND gate NAD2 is electrically connected to the input terminal of the control inverter FC.

[0091] The output terminal of the control transmission gate TGC is electrically connected to the first control terminal CT1, and the output terminal of the control inverter TGC is electrically connected to the second control terminal CT2.

[0092] The control transmission gate TGC is used to provide the signal connected to its input terminal to the first control terminal CT1;

[0093] The control inverter FC is used to invert the signal input to its input terminal to obtain an inverted signal, and then provide the inverted signal to the second control terminal CT2.

[0094] The positive control terminal of TGC is electrically connected to the high voltage terminal VDD, and the negative control terminal of TGC is electrically connected to the second low voltage terminal VSS2.

[0095] In at least one embodiment of this disclosure, the buffer includes an inverter, the inverter including at least one first transistor and at least one second transistor;

[0096] The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the drive output terminal.

[0097] The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the drive output terminal, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0098] In a specific implementation, the buffer may include at least one inverter, which includes a first transistor and a second transistor; the gate of the first transistor is electrically connected to the first control terminal, the first terminal of the first transistor is electrically connected to the first voltage terminal, and the second terminal of the first transistor is electrically connected to the drive output terminal; the gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the drive output terminal, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0099] Optionally, the first transistor is a p-type transistor and the second transistor is an n-type transistor.

[0100] In at least one embodiment of this disclosure, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a first low voltage terminal.

[0101] As shown in Figure 3, based on at least one embodiment shown in Figure 2, the buffer includes an inverter, which includes a first transistor T1 and a second transistor T2;

[0102] The gate of T1 is electrically connected to the first control terminal CT1, the source of T1 is electrically connected to the high voltage terminal VDD, and the drain of T1 is electrically connected to the drive output terminal OT.

[0103] The gate of T2 is electrically connected to the second control terminal CT2, the source of T2 is electrically connected to the drive output terminal OT, and the drain of T2 is electrically connected to the first low voltage terminal VSS1.

[0104] T1 is a p-type transistor, and T2 is an n-type transistor.

[0105] At least one embodiment of the row-driven buffer shown in Figure 3 of this disclosure, when in operation,

[0106] When LD_EN provides a low voltage signal, SI provides a low voltage signal, and FSI provides a high voltage signal, NAD1 outputs a high voltage signal to the input of TGC, NAD2 outputs a high voltage signal to the input of FC, TGC outputs a high voltage signal to CT1, FC provides a low voltage signal to CT2, T1 and T2 are turned off, and OT is in a high impedance state.

[0107] When LD_EN provides a low voltage signal, SI provides a high voltage signal, and FSI provides a low voltage signal, NAD1 outputs a high voltage signal to the input of TGC, NAD2 outputs a high voltage signal to the input of FC, TGC outputs a high voltage signal to CT1, FC provides a low voltage signal to CT2, T1 and T2 are turned off, and OT is in a high impedance state.

[0108] When LD_EN provides a high voltage signal, SI provides a low voltage signal, and FSI provides a high voltage signal, NAD1 provides a high voltage signal to the input of TGC, NAD2 provides a low voltage signal to the input of FC, TGC outputs a high voltage signal to CT1, FC outputs a high voltage signal to CT2, T1 is turned off, T2 is turned on, OT and VSS1 are connected, and OT outputs a low voltage signal.

[0109] When LD_EN provides a high voltage signal, SI provides a high voltage signal, and FSI provides a low voltage signal, NAD1 provides a low voltage signal to the input of TGC, NAD2 provides a high voltage signal to the input of FC, TGC outputs a low voltage signal to CT1, FC outputs a low voltage signal to CT2, T1 is turned on, T2 is turned off, OT and VDD are connected, and OT outputs a high voltage signal.

[0110] In at least one embodiment of this disclosure, the row drive buffer may include an even number of inverters, thereby ensuring that when the enable control terminal provides a valid enable control signal, the signal input to the input terminal of the row drive buffer and the signal output from the output terminal of the row drive buffer are both high voltage signals, or both are low voltage signals.

[0111] In at least one embodiment shown in Figure 3, NAD1, NAD2, TGC, and FC are equivalent to the first inverter, and T1 and T2 are equivalent to the second inverter.

[0112] In at least one embodiment of this disclosure, the inverter may include a plurality of first transistors and a plurality of second transistors connected in parallel, so that more current can be output simultaneously, thereby achieving an enhanced driving effect;

[0113] The display panel may include a first driving module, a second driving module, and a third driving module;

[0114] The first driving module can be used to provide a first scanning signal, which is a row driving signal for controlling the writing of data voltage. It is closely related to the charging rate of the pixel circuit, so it needs strong driving capability. The inverter included in the row driving buffer of the first driving module can be 32 first transistors and 32 second transistors connected in parallel.

[0115] The second driving module can be used to provide a second scan signal, which is a row driving signal for light emission control. The inverter included in the row driving buffer of the second driving module can be composed of eight first transistors and eight second transistors connected in parallel.

[0116] The third driving module can be used to provide a third scanning signal, which is a row driving signal that resets the potential of the first electrode of the light-emitting element. The inverter included in the row driving buffer of the third driving module can be composed of eight first transistors connected in parallel and eight second transistors connected in parallel.

[0117] The number of transistors used in the inverter of the row drive buffer in the drive module can be adjusted according to the driving requirements of the pixel circuit. The number of transistors used can be selected based on the design requirements.

[0118] As shown in Figure 4, in at least one embodiment of this disclosure, the row drive buffer LD is essentially a tri-state buffer. Compared to related buffers, an enable control terminal LD_EN is added. The enable control terminal LD_EN is used to provide an enable control signal, the function of which is to control whether the input signal can be transmitted to the drive output terminal. When LD_EN outputs a high voltage signal, LD is in normal working state, that is, the input signal can pass through the LD to output a signal; when LD_EN outputs a low voltage signal, LD is in cutoff state, that is, the input signal cannot pass through the LD output, the drive output terminal is in high impedance state, and if a signal passes through the drive output terminal, it will not backflow to the input signal terminal.

[0119] In at least one embodiment of this disclosure, the main function of the row drive buffer is to maintain the waveform amplitude of the scan signal unchanged and enhance the driving capability of the scan signal. Driving capability refers to the ability of the output signal of the preceding drive circuit to be effectively responded to by the subsequent drive circuit within a specified time, that is, the voltage changes to the expected voltage value within a specified time. Insufficient driving capability will result in insufficient output current, meaning the upper and lower edges of the scan signal will not be steep enough, and the time spent maintaining the expected voltage value within the specified time will be short. Especially in the display field, to meet the pixel charging rate requirements, the voltage of the scan signal needs to be changed to the expected voltage within a limited rise time Tr and a limited fall time Tf, and it needs to be maintained for a sufficient effective time Ta.

[0120] Figure 5A is a waveform diagram of a scanning signal with strong driving capability provided by the drive output terminal OT, and Figure 5B is a waveform diagram of a scanning signal with weak driving capability provided by the drive output terminal OT.

[0121] The display panel described in this embodiment includes a driving module, which includes N row driving buffers as described above; N is an integer greater than 1.

[0122] The display panel described in at least one embodiment of this disclosure includes multiple rows of scan lines; the nth row drive buffer includes an nth drive output terminal; n is a positive integer less than or equal to N; the nth drive output terminal is electrically connected to the nth row of scan lines.

[0123] In at least one embodiment of this disclosure, the drive module further includes a test control switch circuit;

[0124] The test control switch circuit includes N switch sub-circuits;

[0125] The control terminal of the nth switch sub-circuit is electrically connected to the test control line, the first terminal of the nth switch sub-circuit is electrically connected to the test signal line, and the second terminal of the nth switch sub-circuit is electrically connected to the nth drive output terminal. The nth switch sub-circuit is used to control the connection between the test signal line and the nth drive output terminal when the test control line provides a valid test control signal, and to control the disconnection between the test signal line and the nth drive output terminal when the test control line provides an invalid test control signal.

[0126] In a specific implementation, the drive module may include a test control switch circuit, which includes N switch sub-circuits;

[0127] During the display phase, the test control line provides an invalid test control signal, and the nth switch sub-circuit controls the test signal line to disconnect from the nth drive output terminal;

[0128] During the optical inspection phase, the test control line provides an effective test control signal. The nth switch sub-circuit controls the connection between the test signal line and the nth drive output terminal to provide the test signal provided by the test signal line to the nth drive output terminal.

[0129] In at least one embodiment of this disclosure, the nth switch sub-circuit includes an nth transmission gate; the test control line includes a positive phase test control line and an inverted phase test control line;

[0130] The input terminal of the nth transmission gate is electrically connected to the test signal line, and the output terminal of the nth transmission gate is electrically connected to the nth drive output terminal.

[0131] The positive phase control terminal of the nth transmission gate is electrically connected to the positive phase test control line, and the negative phase control terminal of the nth transmission gate is electrically connected to the negative phase test control line.

[0132] In a specific implementation, the nth switch sub-circuit may include an nth transmission gate, which controls the connection or disconnection between the test signal line and the nth drive output terminal under the control of the positive test control signal provided by the positive test control line and the negative test control signal provided by the negative test control line.

[0133] In at least one embodiment of this disclosure, the test signal line is directly electrically connected to the first terminal of each of the N switch sub-circuits.

[0134] In practical implementation, the test signal line can be directly electrically connected to the first end of all N switch sub-circuits. The extension direction of the test signal line is approximately the same as the extension direction of the data line. The test signal line runs through all rows from top to bottom. Each switch sub-circuit directly obtains the test signal from the test signal line. If a switch sub-circuit in a certain row fails, it will not affect the AOI inspection of other rows, nor will it hinder the cascading transmission of the AOI test signal. The above setting avoids the problem of being unable to perform AOI testing due to device failure.

[0135] As shown in Figure 6, the driving module described in at least one embodiment of this disclosure includes a first row driving buffer LD1, a second row driving buffer LD2, and a third row driving buffer LD3.

[0136] The display panel described in at least one embodiment of this disclosure includes a first row of scan lines S1, a second row of scan lines S2, and a third row of scan lines S3;

[0137] The first row drive buffer LD1 includes a first drive output terminal OT1; the first drive output terminal OT1 is electrically connected to the first row scan line S1.

[0138] The second row drive buffer LD2 includes a second drive output terminal OT2; the second drive output terminal OT2 is electrically connected to the second row scan line S2.

[0139] The third row drive buffer LD3 includes a third drive output terminal OT3; the third drive output terminal OT3 is electrically connected to the third row scan line S3.

[0140] At least one embodiment of the drive module further includes a test control switch circuit;

[0141] The test control switch circuit includes a first switch sub-circuit K1, a second switch sub-circuit K2, and a third switch sub-circuit K3;

[0142] The control terminal of the first switch sub-circuit K1 is electrically connected to the test control line EN. The first terminal of the first switch sub-circuit K1 is electrically connected to the test signal line G_A. The second terminal of the first switch sub-circuit K1 is electrically connected to the first drive output terminal OT1. The first switch sub-circuit K1 is used to control the test signal line G_A to be connected to the first drive output terminal OT1 when the test control line EN provides a valid test control signal, and to control the test signal line G_A to be disconnected from the first drive output terminal OT1 when the test control line EN provides an invalid test control signal.

[0143] The control terminal of the second switch sub-circuit K2 is electrically connected to the test control line EN. The first terminal of the second switch sub-circuit K2 is electrically connected to the test signal line G_A. The second terminal of the second switch sub-circuit K2 is electrically connected to the second drive output terminal OT2. The second switch sub-circuit K2 is used to control the connection between the test signal line G_A and the second drive output terminal OT2 when the test control line EN provides a valid test control signal, and to control the disconnection between the test signal line G_A and the second drive output terminal OT2 when the test control line EN provides an invalid test control signal.

[0144] The control terminal of the third switch sub-circuit K3 is electrically connected to the test control line EN. The first terminal of the third switch sub-circuit K3 is electrically connected to the test signal line G_A. The second terminal of the third switch sub-circuit K3 is electrically connected to the third drive output terminal OT3. The third switch sub-circuit K3 is used to control the connection between the test signal line G_A and the third drive output terminal OT3 when the test control line EN provides a valid test control signal, and to control the disconnection between the test signal line G_A and the third drive output terminal OT3 when the test control line EN provides an invalid test control signal.

[0145] As shown in Figure 7, based on at least one embodiment shown in Figure 6,

[0146] The first switch sub-circuit includes a first transmission gate TG1; the test control line includes a positive phase test control line EN_A and a negative phase test control line EN_A';

[0147] The input terminal of the first transmission gate TG1 is electrically connected to the test signal line G_A, and the output terminal of the first transmission gate TG1 is electrically connected to the first drive output terminal OT1.

[0148] The positive phase control terminal of the first transmission gate TG1 is electrically connected to the positive phase test control line EN_A, and the negative phase control terminal of the first transmission gate TG1 is electrically connected to the negative phase test control line EN_A'.

[0149] The second switching sub-circuit includes a second transmission gate TG2;

[0150] The input terminal of the second transmission gate TG2 is electrically connected to the test signal line G_A, and the output terminal of the second transmission gate TG2 is electrically connected to the second drive output terminal OT2.

[0151] The positive phase control terminal of the second transmission gate TG2 is electrically connected to the positive phase test control line EN_A, and the negative phase control terminal of the second transmission gate TG2 is electrically connected to the negative phase test control line EN_A'.

[0152] The third switching sub-circuit includes a third transmission gate TG3;

[0153] The input terminal of the third transmission gate TG3 is electrically connected to the test signal line G_A, and the output terminal of the third transmission gate TG3 is electrically connected to the third drive output terminal OT3.

[0154] The positive phase control terminal of the third transmission gate TG3 is electrically connected to the positive phase test control line EN_A, and the negative phase control terminal of the third transmission gate TG3 is electrically connected to the negative phase test control line EN_A'.

[0155] As shown in Figure 8, based on at least one embodiment shown in Figure 7,

[0156] The first transmission gate includes a first first NAND gate NAD11, a first second NAND gate NAD12, a first control transmission gate TGC1, a first control inverter FC1, a first first transistor T11, and a first second transistor T12;

[0157] The first input terminal of the first NAND gate NAD11 is electrically connected to the enable control terminal LD_EN, the second input terminal of the first NAND gate NAD11 is electrically connected to the first input signal terminal SI1, and the output terminal of the first NAND gate NAD11 is electrically connected to the input terminal of the first control transmission gate TGC1.

[0158] The first input terminal of the first second NAND gate NAD12 is electrically connected to the enable control terminal LD_EN, the second input terminal of the first second NAND gate NAD12 is electrically connected to the first inverting input signal terminal FSI1, and the output terminal of the first second NAND gate NAD12 is electrically connected to the input terminal of the first control inverter FC1.

[0159] The output terminal of the first control transmission gate TGC1 is electrically connected to the first first control terminal CT11, and the output terminal of the first control inverter TGC1 is electrically connected to the first second control terminal CT12.

[0160] The first control transmission gate TGC1 is used to provide the signal connected to its input terminal to the first control terminal CT11;

[0161] The first control inverter FC1 is used to invert the signal input to its input terminal to obtain an inverted signal, and to provide the inverted signal to the first second control terminal CT12.

[0162] The positive control terminal of TGC1 is electrically connected to the high voltage terminal VDD, and the negative control terminal of TGC1 is electrically connected to the second low voltage terminal VSS2.

[0163] The gate of T11 is electrically connected to CT11, the source of T11 is electrically connected to the high voltage terminal VDD, and the drain of T11 is electrically connected to OT1.

[0164] The gate of T12 is electrically connected to CT12, the source of T12 is electrically connected to OT1, and the drain of T12 is electrically connected to the first low voltage terminal VSS1.

[0165] The second transmission gate includes a second first NAND gate NAD21, a second second NAND gate NAD22, a second control transmission gate TGC2, a second control inverter FC2, a second first transistor T21, and a second second transistor T22;

[0166] The first input terminal of the second first NAND gate NAD21 is electrically connected to the enable control terminal LD_EN, the second input terminal of the second first NAND gate NAD21 is electrically connected to the second input signal terminal SI2, and the output terminal of the second first NAND gate NAD21 is electrically connected to the input terminal of the second control transmission gate TGC2.

[0167] The first input terminal of the second NAND gate NAD22 is electrically connected to the enable control terminal LD_EN, the second input terminal of the second NAND gate NAD22 is electrically connected to the second inverting input signal terminal FSI2, and the output terminal of the second NAND gate NAD22 is electrically connected to the input terminal of the second control inverter FC2.

[0168] The output terminal of the second control transmission gate TGC2 is electrically connected to the second first control terminal CT21, and the output terminal of the second control inverter TGC2 is electrically connected to the second second control terminal CT22.

[0169] The second control transmission gate TGC2 is used to provide the signal connected to its input terminal to the second first control terminal CT21;

[0170] The second control inverter FC2 is used to invert the signal input to its input terminal to obtain an inverted signal, and then provide the inverted signal to the second control terminal CT22.

[0171] The positive control terminal of TGC2 is electrically connected to the high voltage terminal VDD, and the negative control terminal of TGC2 is electrically connected to the second low voltage terminal VSS2.

[0172] The gate of T21 is electrically connected to CT21, the source of T21 is electrically connected to the high voltage terminal VDD, and the drain of T21 is electrically connected to OT2.

[0173] The gate of T22 is electrically connected to CT22, the source of T22 is electrically connected to OT2, and the drain of T22 is electrically connected to the first low voltage terminal VSS1.

[0174] The third transmission gate includes the third first NAND gate NAD31, the third second NAND gate NAD32, the third control transmission gate TGC3, the third control inverter FC3, the third first transistor T31, and the third second transistor T32;

[0175] The first input terminal of the third first NAND gate NAD31 is electrically connected to the enable control terminal LD_EN, the second input terminal of the third first NAND gate NAD31 is electrically connected to the third input signal terminal SI3, and the output terminal of the third first NAND gate NAD31 is electrically connected to the input terminal of the third control transmission gate TGC3.

[0176] The first input terminal of the third second NAND gate NAD32 is electrically connected to the enable control terminal LD_EN, the second input terminal of the third second NAND gate NAD32 is electrically connected to the third inverting input signal terminal FSI3, and the output terminal of the third second NAND gate NAD32 is electrically connected to the input terminal of the third control inverter FC3.

[0177] The output terminal of the third control transmission gate TGC3 is electrically connected to the third first control terminal CT31, and the output terminal of the third control inverter TGC3 is electrically connected to the third second control terminal CT32.

[0178] The third control transmission gate TGC3 is used to provide the signal connected to its input terminal to the third first control terminal CT31;

[0179] The third control inverter FC3 is used to invert the signal input to its input terminal to obtain the inverted signal, and then provide the inverted signal to the third second control terminal CT32.

[0180] The positive control terminal of TGC3 is electrically connected to the high voltage terminal VDD, and the negative control terminal of TGC3 is electrically connected to the second low voltage terminal VSS2.

[0181] The gate of T31 is electrically connected to CT31, the source of T31 is electrically connected to the high voltage terminal VDD, and the drain of T31 is electrically connected to OT3.

[0182] The gate of T32 is electrically connected to CT32, the source of T32 is electrically connected to OT3, and the drain of T32 is electrically connected to the first low voltage terminal VSS1.

[0183] In at least one embodiment shown in Figure 8, T11, T21 and T31 are all p-type transistors, and T12, T22 and T32 are all n-type transistors.

[0184] In at least one embodiment shown in Figure 8, during operation, in the display phase, LD_EN provides a high voltage signal, EN_A provides a low voltage signal, and EN_A' provides a high voltage signal; as shown in Figure 9A, TG1, TG2, and TG3 are all turned off, G_A is disconnected from OT1, G_A is disconnected from OT2, and G_A is disconnected from OT3.

[0185] When SI1 provides a high voltage signal and FSI1 provides a low voltage signal, NAD11 outputs a low voltage signal TGC1, TGC1 provides a low voltage signal to CT11, and T11 is turned on; NAD12 outputs a high voltage signal to FC1, FC1 outputs a low voltage signal to CT12, and T12 is turned off.

[0186] When SI1 provides a low voltage signal and FSI1 provides a high voltage signal, NAD11 outputs a high voltage signal to TGC1, TGC1 provides a high voltage signal to CT11, and T11 is turned off; NAD12 outputs a low voltage signal to FC1, FC1 outputs a high voltage signal to CT12, and T12 is turned on.

[0187] When SI2 provides a high voltage signal and FSI2 provides a low voltage signal, NAD21 outputs a low voltage signal TGC2, TGC2 provides a low voltage signal to CT21, and T21 is turned on; NAD22 outputs a high voltage signal to FC2, FC2 outputs a low voltage signal to CT22, and T22 is turned off.

[0188] When SI2 provides a low voltage signal and FSI2 provides a high voltage signal, NAD21 outputs a high voltage signal to TGC2, TGC2 provides a high voltage signal to CT21, and T21 is turned off; NAD22 outputs a low voltage signal to FC2, FC2 outputs a high voltage signal to CT22, and T22 is turned on.

[0189] When SI3 provides a high voltage signal and FSI3 provides a low voltage signal, NAD31 outputs a low voltage signal TGC3, TGC3 provides a low voltage signal to CT31, and T31 is turned on; NAD32 outputs a high voltage signal to FC3, FC3 outputs a low voltage signal to CT32, and T32 is turned off.

[0190] When SI3 provides a low voltage signal and FSI3 provides a high voltage signal, NAD31 outputs a high voltage signal to TGC3, TGC3 provides a high voltage signal to CT31, and T31 is turned off; NAD32 outputs a low voltage signal to FC3, FC3 outputs a high voltage signal to CT32, and T32 is turned on.

[0191] In at least one embodiment shown in Figure 8, during the optical detection stage, LD_EN provides a low voltage signal, EN_A provides a high voltage signal, and EN_A' provides a low voltage signal; as shown in Figure 9B, TG1, TG2, and TG3 are all turned on, controlling the connection between G_A and OT1, controlling the connection between G_A and OT2, and controlling the connection between G_A and OT3.

[0192] NAD11 outputs a high voltage signal to TGC1, TGC1 provides a high voltage signal to CT11, and T11 is turned off; NAD12 outputs a high voltage signal to FC1, FC1 provides a low voltage signal to CT12, and T12 is turned off;

[0193] NAD21 outputs a high voltage signal to TGC2, TGC2 provides a high voltage signal to CT21, and T21 is turned off; NAD22 outputs a high voltage signal to FC2, FC2 provides a low voltage signal to CT22, and T22 is turned off.

[0194] NAD31 outputs a high voltage signal to TGC3, TGC3 provides a high voltage signal to CT31, and T31 is turned off; NAD32 outputs a high voltage signal to FC3, FC3 provides a low voltage signal to CT32, and T32 is turned off.

[0195] In at least one embodiment shown in Figure 8, during the optical detection phase, TG1, TG2, and TG3 are all in the on state. The test signal for AOI testing is provided from the test signal line G_A to OT1, OT2, and OT3, and finally acts on the gate of the transistor in the pixel circuit. Since each row drive buffer is in a high impedance state, the signal will not flow back to the row drive buffer, thus protecting the drive module during the optical detection phase. That is, the row drive buffer achieves isolation between the normal operation mode and the AOI test mode.

[0196] The display panel described in at least one embodiment of this disclosure further includes a shift register and a level converter;

[0197] The shift register includes a multi-stage shift register unit, and the level converter includes a multi-stage level conversion unit;

[0198] The nth-stage shift register unit is electrically connected to the nth-stage level conversion unit and is used to provide the nth-stage drive signal to the nth-stage level conversion unit;

[0199] The nth level level conversion unit is electrically connected to the nth row drive buffer and is used to perform level conversion on the nth drive signal and provide the level-converted nth drive signal to the nth row drive buffer.

[0200] In a specific implementation, the display panel may further include a shift register and a level converter. The shift register includes a multi-level shift register unit, and the level converter includes a multi-level level conversion unit. The nth-level shift register unit provides the nth-level drive signal to the nth-level level conversion unit. The nth-level level conversion unit performs level conversion on the nth-level drive signal and provides the level-converted nth-level drive signal to the nth-row drive buffer.

[0201] As shown in Figure 10, the nth-stage shift register unit 91 is electrically connected to the nth-stage level conversion unit 92, and is used to provide the nth-stage drive signal to the nth-stage level conversion unit 92.

[0202] The nth level level conversion unit 92 is electrically connected to the nth row drive buffer 93, and is used to perform level conversion on the nth drive signal and provide the level-converted nth drive signal to the nth row drive buffer 93.

[0203] In at least one embodiment of this disclosure, each shift register unit is mainly composed of a double-edge flip-flop and a logic unit. The main function of the double-edge flip-flop is to serially transmit control signals line by line, with a line cycle interval between each line; the main function of the logic unit is to generate the pixel circuit control timing by logically combining the control signals generated by the DDIC (Display Driver Integrated Circuit).

[0204] Because the display device uses a Two-Chip configuration, the voltage output by the DDIC needs to support all modules within the BP (backplane driver). However, different modules require different voltage ranges. Therefore, signals similar to control signals can only meet the voltage requirements of most modules. For example, the high voltage of the control signal is 4.8V, and the low voltage is 0V. However, the back gate voltage and source voltage of the reset transistor in the pixel circuit are negative. To ensure effective switching closure, the gate potential also needs to be set to a negative voltage (e.g., -3.2V). Therefore, a level shifting unit is needed to convert the low voltage of the output waveform to a negative voltage.

[0205] As shown in Figure 11, the shift register includes a first-level shift register unit SR1, a second-level shift register unit SR2, a third-level shift register unit SR3, and a fourth-level shift register unit SR4.

[0206] The level converter includes a first-stage level conversion unit LS1, a second-stage level conversion unit LS2, a third-stage level conversion unit LS3, and a fourth-stage level conversion unit LS4;

[0207] The drive module includes a first row drive buffer LD1, a second row drive buffer LD2, a third row drive buffer LD3, and a fourth row drive buffer LD4;

[0208] SR1 is electrically connected to the start voltage terminal STV, the control clock signal terminal CKV, the pulse control signal terminal PL, and the first scan control pin GSD, respectively.

[0209] SR1 can be electrically connected to LS1 through the first drive signal terminal G1_R1, the second drive signal terminal G2_R1, and the third drive signal terminal G3_R1 of the first row, respectively;

[0210] SR2 can be electrically connected to LS2 via the first drive signal terminal G1_R2 of the second row, the second drive signal terminal G2_R2 of the second row, and the third drive signal terminal G3_R2 of the second row, respectively;

[0211] SR3 can be electrically connected to LS3 through the first drive signal terminal G1_R3 of the third row, the second drive signal terminal G2_R3 of the third row, and the third drive signal terminal G3_R3 of the third row, respectively;

[0212] SR4 can be electrically connected to LS4 through the first drive signal terminal G1_R4, the second drive signal terminal G2_R4, and the third drive signal terminal G3_R4 of the fourth row, respectively;

[0213] G1_R1 is electrically connected to the first input terminal of SR2, G2_R1 is electrically connected to the second input terminal of SR2, and G3_R1 is electrically connected to the third input terminal of SR2.

[0214] G1_R2 is electrically connected to the first input terminal of SR3, G2_R2 is electrically connected to the second input terminal of SR3, and G3_R2 is electrically connected to the third input terminal of SR3.

[0215] G1_R3 is electrically connected to the first input terminal of SR4, G2_R3 is electrically connected to the second input terminal of SR4, and G3_R3 is electrically connected to the third input terminal of SR4.

[0216] LD1 is electrically connected to the first scan signal terminal G1_RW1, the second scan signal terminal G2_RW1, and the third scan signal terminal G3_RW1 of the first row, respectively, and is used to provide the first scan signal of the first row through G1_RW1, the second scan signal of the first row through G2_RW1, and the third scan signal of the first row through G3_RW1.

[0217] LD2 is electrically connected to the first scan signal terminal G1_RW2 of the second row, the second scan signal terminal G2_RW2 of the second row, and the third scan signal terminal G3_RW2 of the second row, respectively, and is used to provide the first scan signal of the second row through G1_RW2, the second scan signal of the second row through G2_RW2, and the third scan signal of the second row through G3_RW2;

[0218] LD3 is electrically connected to the first scan signal terminal G1_RW3 of the third row, the second scan signal terminal G2_RW3 of the third row, and the third scan signal terminal G3_RW3 of the third row, respectively, and is used to provide the first scan signal of the third row through G1_RW3, the second scan signal of the third row through G2_RW3, and the third scan signal of the third row through G3_RW3;

[0219] LD4 is electrically connected to the first scan signal terminal G1_RW4, the second scan signal terminal G2_RW4, and the third scan signal terminal G3_RW4 of the fourth row, respectively, and is used to provide the first scan signal of the fourth row through G1_RW4, the second scan signal of the fourth row through G2_RW4, and the third scan signal of the fourth row through G3_RW4.

[0220] In Figure 11, B1 is a schematic diagram of the waveform of the signal output by the shift register unit, B2 is a schematic diagram of the waveform of the signal output by the level conversion unit, and B3 is a schematic diagram of the waveform of the signal output by the row drive buffer.

[0221] The display panel described in at least one embodiment of this disclosure includes a multi-row, multi-column pixel circuit, as shown in FIG11. The driving module includes a first driving module GA1, a second driving module GA2, and a third driving module GA3.

[0222] The first driving module GA1 is used to provide a first scan signal for writing control data voltage to the pixel circuit;

[0223] The second driving module GA2 is used to provide a second scanning signal for the pixel circuit to control light emission;

[0224] The third driving module GA3 is used to provide the pixel circuit with a third scan signal for initialization control;

[0225] The first drive module includes a first row drive buffer, the second drive module includes a second row drive buffer, and the third drive module includes a third row drive buffer; the first row drive buffer includes a first buffer, the second row drive buffer includes a second buffer, and the third row drive buffer includes a third buffer.

[0226] The first buffer includes A first transistors and A second transistors connected in parallel; the second buffer includes B first transistors and B second transistors connected in parallel; and the third buffer includes C first transistors and C second transistors connected in parallel.

[0227] A is greater than B, A is greater than C; A, B and C are all positive integers.

[0228] In specific implementation, the first driving module GA1 provides a first scan signal, the second driving module GA2 provides a second scan signal, and the third driving module GA3 provides a third scan signal. The first scan signal is a row driving signal that controls the writing of data voltage and is closely related to the charging rate of the pixel circuit. Therefore, it requires strong driving capability. Thus, the number of transistors in the inverter included in the row driving buffer of the first driving module can be set to be greater than the number of transistors in the inverter included in the row driving buffer of the second driving module, and the number of transistors in the inverter included in the row driving buffer of the first driving module can be set to be greater than the number of transistors in the inverter included in the row driving buffer of the third driving module.

[0229] In at least one embodiment of this disclosure, the second scan signal is a row drive signal for performing light emission control; the third scan signal is a row drive signal for performing initialization control.

[0230] As shown in Figure 12A, at least one embodiment of the driving module may include a shift register chip SRC, a level converter chip LSC, and a row drive buffer chip LDC.

[0231] The shift register chip SRC includes a first drive signal output pin WSn, a second drive signal output pin DSn, and a third drive signal output pin AZn;

[0232] The level converter chip LSC includes a first drive signal input pin WSI, a second drive signal input pin DSI, a third drive signal input pin AZI, a first first drive signal providing pin WS_LS_OUT, a second first drive signal providing pin WS_LS_OUT', a first second drive signal providing pin DS_LS_OUT', a second second drive signal providing pin DS_LS_OUT', a first third drive signal providing pin AZ_LS_OUT', and a second third drive signal providing pin AZ_LS_OUT'.

[0233] The row drive buffer chip LDC includes a first first drive signal input pin WS, a second first drive signal input pin WS', a first second drive signal input pin DS, a second second drive signal input pin DS', a first third drive signal input pin AZ, a second third drive signal input pin, a first scan signal output pin WS_OUT, a second scan signal output pin DS_OUT, and a third scan signal output pin AZ_OUT;

[0234] AZn is electrically connected to AZI, DSn is electrically connected to DSI, and WSn is electrically connected to WS.

[0235] AZ_LS_OUT1 is electrically connected to AZ, AZ_LS_OUT2 is electrically connected to AZ', DS_LS_OUT1 is electrically connected to DS, DS_LS_OUT2 is electrically connected to DS', WS_LS_OUT1 is electrically connected to WS, and WS_LS_OUT2 is electrically connected to WS'.

[0236] In at least one embodiment shown in Figure 12A, VSS1 is a first low voltage terminal, VSS2 is a second low voltage terminal, VDD is a high voltage terminal, and GND is a ground terminal.

[0237] The line drive buffer chip LDC also includes a first enable control pin LD_EN_WS, a second enable control pin LD_EN_DS, and a third enable control pin LD_EN_AZ;

[0238] The shift register chip SRC also includes a first control clock pin CKV_WS1, a second control clock pin CKV_WS1, a second control clock pin CKV_DS, a third control clock pin CKV_AZ, a first control pulse pin CKV_LF_PULSE_DS, a second control pulse pin CKV_LF_PULSE_AZ, a first scan control pin GSD, a second scan control pin GSD', an input pin Rn, a first pin Dn_WS1, a second pin Dn_WS2, a third pin Dn_DS, a fourth pin Dn_AZ, a fifth pin Dn_LF_PULSE_DS, a sixth pin Dn_LF_PULSE_AZ, a seventh pin Q_INTER_WS1, an eighth pin Q_INTER_WS2, a ninth pin Q_INTER_DS, and a tenth pin. Pins Q_INTER_AZ, 11th pin Q_INTER_LF_PULSE_DS, 12th pin Q_INTER_LF_PULSE_AZ, 13th pin Dn+1_WS1, 14th pin Dn+1_WS2, 15th pin Dn+1_DS, 16th pin Dn+1_AZ, 17th pin Dn+1_LF_PULSE_DS, 18th pin Dn+1_LF_PULSE_AZ, 19th pin Q_INTER+1_WS1, 20th pin Q_INTER+1_WS2, 21st pin Q_INTER+1_DS, 22nd pin Q_INTER+1_AZ, 23rd pin Q_INTER+1_LF_PULSE_DS, and 24th pin Q_INTER+1_LF_PULSE_AZ;

[0239] The port labeled GVDD is the high voltage port, and the port labeled GGND is the ground port.

[0240] The terminal labeled CKV1 is the first clock signal terminal, the terminal labeled CKV2 is the second clock signal terminal, the terminal labeled CKV3 is the third clock signal terminal, the terminal labeled CKV4 is the fourth clock signal terminal, the terminal labeled CKV5 is the fifth clock signal terminal, the terminal labeled CKV6 is the sixth clock signal terminal, the terminal labeled LD_EN1 is the first enable control terminal, the terminal labeled LD_EN2 is the second enable control terminal, and the terminal labeled LD_EN3 is the third enable control terminal.

[0241] Figure 12B is the circuit diagram of the shift register chip SRC in Figure 12A, Figure 12C is the circuit diagram of the level converter chip LSC in Figure 12A, and Figure 12D is the circuit diagram of the row drive buffer chip LDC in Figure 12A.

[0242] The display panel described in at least one embodiment of this disclosure includes a first test signal line, a second test signal line, and a third test signal line; the first driving module includes a first test control switch circuit, the second driving module includes a second test control switch circuit, and the third driving module includes a third test control switch circuit;

[0243] The first driving module includes a plurality of first row driving buffers arranged sequentially along a first direction, and the first test signal line extends along the first direction; the first test signal line is directly electrically connected to the first terminals of a plurality of switch sub-circuits included in the first test control switch circuit.

[0244] The second drive module includes multiple second row drive buffers arranged sequentially along a first direction, and the second test signal line extends along the first direction; the second test signal line is directly electrically connected to the first terminals of multiple switch sub-circuits included in the second test control switch circuit;

[0245] The third drive module includes multiple third row drive buffers arranged sequentially along a first direction, and the third test signal line extends along the first direction; the third test signal line is directly electrically connected to the first end of multiple switch sub-circuits included in the third test control switch circuit.

[0246] Optionally, the first direction can be the vertical direction.

[0247] As shown in Figure 13, G_A1 is the first test signal line, G_A2 is the second test signal line, and G_A3 is the third test signal line; G_A1, G_A2, and G_A3 extend in the vertical direction;

[0248] The first drive module includes a first test control switch circuit 121, which includes a first first switch sub-circuit K11, a second first switch sub-circuit K21, and a third first switch sub-circuit K31.

[0249] The second drive module includes a second test control switch circuit 122, which includes a first second switch sub-circuit K12, a second second switch sub-circuit K22, and a third second switch sub-circuit K32.

[0250] The third drive module includes a third test control switch circuit 123, which includes a first third switch sub-circuit K13, a second third switch sub-circuit K23 and a third third switch sub-circuit K33.

[0251] The first drive module includes a first first row drive buffer LD11, a second first row drive buffer LD21, and a third first row drive buffer LD31; LD11, LD21, and LD31 are arranged in a vertical direction.

[0252] The second drive module includes a first second-row drive buffer LD12, a second second-row drive buffer LD22, and a third second-row drive buffer LD32; LD12, LD22, and LD32 are arranged vertically.

[0253] The third drive module includes a first third-row drive buffer LD13, a second third-row drive buffer LD23, and a third third-row drive buffer LD33; LD13, LD23, and LD33 are arranged vertically.

[0254] K11, K21 and K31 are all directly electrically connected to G_A1;

[0255] K12, K22 and K32 are all directly electrically connected to G_A2;

[0256] K13, K23, and K33 are all directly electrically connected to G_A3.

[0257] In Figure 13, the line labeled EN_A is the positive phase test control line, and the line labeled EN_A' is the negative phase test control line.

[0258] In at least one embodiment shown in Figure 13, the first test signal line is directly electrically connected to the first terminals of the plurality of switch sub-circuits included in the first test control switch circuit; the second test signal line is directly electrically connected to the first terminals of the plurality of switch sub-circuits included in the second test control switch circuit; the third test signal line is directly electrically connected to the first terminals of the plurality of switch sub-circuits included in the third test control switch circuit; each switch sub-circuit directly obtains the test signal from the corresponding test signal line. If a row of switch sub-circuits fails, it will not affect the AOI inspection of other rows, nor will it hinder the cascading transmission of the AOI test signal. The above configuration avoids the problem of being unable to perform AOI testing due to device failure.

[0259] In at least one embodiment of this disclosure, the driving module includes a multi-level driving circuit and at least one pseudo-driving circuit; the pseudo-driving circuit includes at least one pseudo-row driving buffer; the display panel includes at least one row of pseudo-pixel circuit.

[0260] The pseudo-row drive buffer in the last stage pseudo-drive circuit of the drive module is electrically connected to the corresponding test signal line and the last row pseudo-pixel circuit, respectively.

[0261] In a specific implementation, the drive module may include N levels of drive circuits and at least one level of pseudo-drive circuit; N is an integer greater than 1.

[0262] The at least one pseudo-driving circuit can be cascaded with the Nm-th driving circuit included in the driving module. That is, the at least one pseudo-driving circuit can be set after the N-th driving circuit. The pseudo-row driving buffer in the last pseudo-driving circuit included in the driving module can be directly electrically connected to the corresponding test signal line and the last row pseudo-pixel circuit. So that during normal display, under the premise that the transmission gates included in the test control switch circuit are turned off, the corresponding electrical test signal can be directly provided to the last row pseudo-pixel circuit through the corresponding test signal line to perform electrical detection.

[0263] Figure 14 is a layout diagram of the drive module;

[0264] As shown in Figure 14, at least one embodiment of the driving module includes the 3073rd first row driving buffer LD30731, the 3073rd second row driving buffer LD30732, the 3073rd third row driving buffer LD30733, the 3074th first row driving buffer LD30741, the 3074th second row driving buffer LD30742, the 3074th third row driving buffer LD30743, the first pseudo first row driving buffer LDD11, the first pseudo second row driving buffer LDD12, the first pseudo third row driving buffer LDD13, the second pseudo first row driving buffer LDD21, the second pseudo second row driving buffer LDD22, and the second pseudo third row driving buffer LDD23;

[0265] LD30731 is used to provide a first scan signal for the 3073rd row pixel circuit included in the display panel, LD30732 is used to provide a second scan signal for the 3073rd row pixel circuit included in the display panel, and LD30733 is used to provide a third scan signal for the 3073rd row pixel circuit included in the display panel.

[0266] LD30741 is used to provide a first scan signal for the 3074th row pixel circuit included in the display panel, LD30742 is used to provide a second scan signal for the 3074th row pixel circuit included in the display panel, and LD30743 is used to provide a third scan signal for the 3074th row pixel circuit included in the display panel.

[0267] LDD11 is electrically connected to the first row of Dummy pixel circuits included in the display panel, LDD12 is electrically connected to the first row of Dummy pixel circuits included in the display panel, and LDD13 is electrically connected to the first row of Dummy pixel circuits included in the display panel.

[0268] LDD21 is electrically connected to the second row of dummy pixel circuits included in the display panel, LDD22 is electrically connected to the second row of dummy pixel circuits included in the display panel, and LDD23 is electrically connected to the second row of dummy pixel circuits included in the display panel.

[0269] As shown in Figure 14, at least one embodiment of the driving module further includes a 3703rd first transmission gate TG37031, a 3703rd second transmission gate TG37032, a 3703rd third transmission gate TG37033, a 3704th first transmission gate TG37041, a 3704th second transmission gate TG37042, a 3704th third transmission gate TG37043, a first pseudo-first transmission gate TGD11, a first pseudo-second transmission gate TGD12, and a first pseudo-third transmission gate TGD13;

[0270] TG37031 is directly connected to the first test signal line (not shown in Figure 14) via the first wire L1, TG30732 is directly connected to the second test signal line (not shown in Figure 14) via the second wire L2, and TG37033 is directly connected to the third test signal line (not shown in Figure 14) via the third wire L3.

[0271] In at least one embodiment shown in Figure 14, TG37031 is directly electrically connected to the first test signal line via a corresponding wire, TG30732 is directly connected to the second test signal line via a corresponding wire, TG37033 is directly connected to the third test signal line via a corresponding wire, TG37041 is directly connected to the first test signal line via a corresponding wire, TG30742 is directly connected to the second test signal line via a corresponding wire, TG37043 is directly connected to the third test signal line via a corresponding wire, TGD11 is directly connected to the first test signal line via a corresponding wire, TGD12 is directly connected to the second test signal line via a corresponding wire, and TGD13 is directly connected to the third test signal line via a corresponding wire. Each transmission gate directly obtains the corresponding test signal from the corresponding test signal line. If a transmission gate fails, it will not affect the AOI inspection of other rows, nor will it hinder the cascading transmission of the AOI test signal. The above configuration avoids the problem of being unable to perform AOI testing due to device failure.

[0272] In at least one embodiment shown in FIG14, the 3073rd first row drive buffer LD30731, the 3073rd second row drive buffer LD30732 and the 3073rd third row drive buffer LD30733 are arranged sequentially along a direction away from the display area;

[0273] The 3074th first row drive buffer LD30741, the 3074th second row drive buffer LD30742, and the 3074th third row drive buffer LD30743 are arranged sequentially in the direction away from the display area;

[0274] The first pseudo-first row drive buffer LDD11, the first pseudo-second row drive buffer LDD12, and the first pseudo-third row drive buffer LDD13 are arranged sequentially along the direction away from the display area;

[0275] The second pseudo-first row drive buffer LDD21, the second pseudo-second row drive buffer LDD22, and the second pseudo-third row drive buffer LDD23 are arranged sequentially in a direction away from the display area.

[0276] In practical implementation, since the sensitivity of the first scan signal is greater than that of the second scan signal, and the sensitivity of the second scan signal is greater than that of the third scan signal, the first row drive buffer, the second row drive buffer, and the third row drive buffer can be arranged sequentially along the direction away from the display area; that is, the distance between the first row drive buffer and the display area is set to be closer, so as to avoid the problem of signal distortion caused by the first scan signal due to the excessively long connection between it and the display area.

[0277] Figure 15 is a layout diagram based on Figure 14, with the addition of the first test signal line G_A1, the second test signal line G_A2, the third test signal line G_A3, the positive phase test control line EN_A, and the negative phase test control line EN_A'.

[0278] As shown in Figure 15, the first test signal line G_A1, the second test signal line G_A2, the third test signal line G_A3, the positive phase test control line EN_A, and the negative phase test control line EN_A' can be arranged sequentially along the direction closest to the display area.

[0279] In at least one embodiment shown in Figure 15, G_A1, G_A2, G_A3, EN_A and EN_A' can be located on the same layer, G_A1, G_A2, G_A3, EN_A and EN_A' can be located on the side of the drive module away from the substrate, and G_A1, G_A2, G_A3, EN_A, EN_A' and the drive module can all be disposed on the substrate.

[0280] In at least one embodiment shown in Figures 14 and 15, at the rear end of the row drive buffer corresponding to the last row pseudo-pixel circuit, the corresponding first transmission gate, the corresponding second transmission gate, and the corresponding third transmission gate may not be provided. The second pseudo first row drive buffer LDD21 can be electrically connected to the first test signal line and the first scan terminal of the last row pseudo-pixel circuit, respectively. The second pseudo second row drive buffer LDD221 can be electrically connected to the second test signal line and the second scan terminal of the last row pseudo-pixel circuit, respectively. The second pseudo third row drive buffer LDD23 can be electrically connected to the third test signal line and the third scan terminal of the last row pseudo-pixel circuit, respectively. So that during normal display, under the premise that the transmission gates included in the test control switch circuit are turned off, the corresponding electrical test signals can be directly provided to the last row pseudo-pixel circuit through the first test signal line, the second test signal line, and the third test signal line to enable electrical detection.

[0281] The driving method described in this embodiment is applied to the above-mentioned row driving buffer, and the driving method includes:

[0282] When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit;

[0283] When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the drive output terminal.

[0284] The control method described in this embodiment is applied to the above-mentioned display panel, and the control method includes:

[0285] When the display panel is in the optical inspection stage, the enable control terminal provides an invalid enable control signal, and the control switch logic circuit controls the buffer circuit to stop providing input signals to the drive output terminal. Under the control of the test control signal, the switch sub-circuit controls the connection between the test signal line and the corresponding drive output terminal.

[0286] When the display panel is in the display stage, the enable control terminal provides an effective enable control signal. The control switch logic circuit provides the input signal provided by the input signal terminal through the buffer circuit to the drive output terminal. Under the control of the test control signal, the switch sub-circuit controls the test signal line to disconnect from the corresponding drive output terminal.

[0287] The display device described in this disclosure includes the display panel described above.

[0288] Optionally, the display device may be a silicon-based OLED microdisplay.

[0289] Silicon-based OLED (Organic Light Emitting Diode) microdisplays are active-matrix organic light-emitting diode display devices fabricated using single-crystal silicon as the active driving backplane, combining CMOS (Complementary Metal Oxide Semiconductor) technology and OLED technology. Silicon-based OLED microdisplays offer advantages such as ultra-high resolution, high PPI (Pixels Per Inch), high contrast, high brightness, low power consumption, small size, and light weight, making them widely used in AR (Augmented Reality), VR (Virtual Reality), MR (Mixed Reality), EVF (Electronic Viewfinder), FPV (First Person View, a device based on a wireless camera mounted on a remote-controlled aircraft or vehicle model), drones, thermal imagers, night vision devices, infrared cameras, and medical equipment.

[0290] In at least one embodiment of this disclosure, the silicon-based OLED microdisplay can be composed of two ICs: a Si-BP (driver backplane) and a DDIC (display driver integrated circuit). The Si-BP mainly consists of a pixel circuit array, a driver module, and a source driver.

[0291] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A row drive buffer, comprising a control switch logic circuit and a buffer circuit; the output terminal of the buffer circuit is electrically connected to the drive output terminal; The control switch logic circuit is electrically connected to the enable control terminal, the input signal terminal, and the control terminal of the buffer circuit, respectively. When the enable control terminal provides a valid enable control signal, it provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit. When the enable control terminal provides an invalid enable control signal, it controls the buffer circuit to stop providing the input signal to the drive output terminal.

2. The row-driven buffer as described in claim 1, wherein, The control switch logic circuit includes a first NAND gate, a second NAND gate, a control transmission gate, and a control inverter; the buffer circuit includes a first control terminal and a second control terminal. The first input terminal of the first NAND gate is electrically connected to the enable control terminal, the second input terminal of the first NAND gate is electrically connected to the input signal terminal, and the output terminal of the first NAND gate is electrically connected to the input terminal of the control transmission gate. The first input terminal of the second NAND gate is electrically connected to the enable control terminal, the second input terminal of the second NAND gate is electrically connected to the inverting input signal terminal, and the output terminal of the second NAND gate is electrically connected to the input terminal of the control inverter. The output terminal of the control transmission gate is electrically connected to the first control terminal, and the output terminal of the control inverter is electrically connected to the second control terminal; The control transmission gate is used to provide the signal connected to its input terminal to the first control terminal; The control inverter is used to invert the signal input to its input terminal to obtain an inverted signal, and then provide the inverted signal to the second control terminal.

3. The row-driven buffer as described in claim 2, wherein, The buffer includes an inverter, which includes at least one first transistor and at least one second transistor; The gate of the first transistor is electrically connected to the first control terminal, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the drive output terminal. The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the drive output terminal, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

4. The row-driven buffer as described in claim 3, wherein, The first transistor is a p-type transistor, and the second transistor is an n-type transistor.

5. A display panel, comprising a driving module, the driving module comprising N row driving buffers as described in any one of claims 1 to 4; N being an integer greater than 1.

6. The display panel as claimed in claim 5, wherein, Includes multiple scan lines; the nth row drive buffer includes the nth drive output; n is a positive integer less than or equal to N; The nth drive output terminal is electrically connected to the nth scan line.

7. The display panel as claimed in claim 6, wherein, The drive module also includes a test control switch circuit; The test control switch circuit includes N switch sub-circuits; The control terminal of the nth switch sub-circuit is electrically connected to the test control line, the first terminal of the nth switch sub-circuit is electrically connected to the test signal line, and the second terminal of the nth switch sub-circuit is electrically connected to the nth drive output terminal. The nth switch sub-circuit is used to control the connection between the test signal line and the nth drive output terminal when the test control line provides a valid test control signal, and to control the disconnection between the test signal line and the nth drive output terminal when the test control line provides an invalid test control signal.

8. The display panel as claimed in claim 7, wherein, The nth switch sub-circuit includes the nth transmission gate; the test control line includes a positive phase test control line and an inverted phase test control line; The input terminal of the nth transmission gate is electrically connected to the test signal line, and the output terminal of the nth transmission gate is electrically connected to the nth drive output terminal. The positive phase control terminal of the nth transmission gate is electrically connected to the positive phase test control line, and the negative phase control terminal of the nth transmission gate is electrically connected to the negative phase test control line.

9. The display panel as claimed in claim 7 or 8, wherein, The test signal line is directly electrically connected to the first terminal of each of the N switch sub-circuits.

10. The display panel according to any one of claims 6 to 8, wherein, It also includes shift registers and level shifters; The shift register includes a multi-stage shift register unit, and the level converter includes a multi-stage level conversion unit; The nth-stage shift register unit is electrically connected to the nth-stage level conversion unit and is used to provide the nth-stage drive signal to the nth-stage level conversion unit; The nth level level conversion unit is electrically connected to the nth row drive buffer and is used to perform level conversion on the nth drive signal and provide the level-converted nth drive signal to the nth row drive buffer.

11. The display panel according to any one of claims 5 to 8, wherein, It includes a multi-row, multi-column pixel circuit, and the driving module includes a first driving module, a second driving module, and a third driving module; The first driving module is used to provide a first scan signal for writing control data voltage to the pixel circuit; The second driving module is used to provide a second scanning signal for the pixel circuit to control light emission; The third driving module is used to provide the pixel circuit with a third scan signal for initialization control; The first drive module includes a first row drive buffer, the second drive module includes a second row drive buffer, and the third drive module includes a third row drive buffer; the first row drive buffer includes a first buffer, the second row drive buffer includes a second buffer, and the third row drive buffer includes a third buffer. The first buffer includes A first transistors and A second transistors connected in parallel; the second buffer includes B first transistors and B second transistors connected in parallel; and the third buffer includes C first transistors and C second transistors connected in parallel. A is greater than B, A is greater than C; A, B and C are all positive integers.

12. The display panel as claimed in claim 11, wherein, It includes a first test signal line, a second test signal line, and a third test signal line; the first drive module includes a first test control switch circuit, the second drive module includes a second test control switch circuit, and the third drive module includes a third test control switch circuit; The first driving module includes a plurality of first row driving buffers arranged sequentially along a first direction, and the first test signal line extends along the first direction; the first test signal line is directly electrically connected to the first terminals of a plurality of switch sub-circuits included in the first test control switch circuit. The second drive module includes multiple second row drive buffers arranged sequentially along a first direction, and the second test signal line extends along the first direction; the second test signal line is directly electrically connected to the first terminals of multiple switch sub-circuits included in the second test control switch circuit; The third drive module includes multiple third row drive buffers arranged sequentially along a first direction, and the third test signal line extends along the first direction; the third test signal line is directly electrically connected to the first end of multiple switch sub-circuits included in the third test control switch circuit.

13. The display panel as claimed in claim 5, wherein, The driving module includes a multi-level driving circuit and at least one pseudo-driving circuit; the pseudo-driving circuit includes at least one pseudo-row driving buffer; the display panel includes at least one row of pseudo-pixel circuit. The pseudo-row drive buffer in the last stage pseudo-drive circuit of the drive module is electrically connected to the corresponding test signal line and the last row pseudo-pixel circuit, respectively.

14. A driving method applied to a row driving buffer as described in any one of claims 1 to 5, the driving method comprising: When the enable control terminal provides a valid enable control signal, the control switch logic circuit provides the input signal provided by the input signal terminal to the drive output terminal through the buffer circuit; When the enable control terminal provides an invalid enable control signal, the control switch logic circuit controls the buffer circuit to stop providing the input signal to the drive output terminal.

15. A control method applied to a display panel as described in any one of claims 7 to 9, the control method comprising: When the display panel is in the optical inspection stage, the enable control terminal provides an invalid enable control signal, and the control switch logic circuit controls the buffer circuit to stop providing input signals to the drive output terminal. Under the control of the test control signal, the switch sub-circuit controls the connection between the test signal line and the corresponding drive output terminal. When the display panel is in the display stage, the enable control terminal provides an effective enable control signal. The control switch logic circuit provides the input signal provided by the input signal terminal through the buffer circuit to the drive output terminal. Under the control of the test control signal, the switch sub-circuit controls the test signal line to disconnect from the corresponding drive output terminal.

16. A display device comprising a display panel as claimed in any one of claims 5 to 13.

Images