Driving module, driving method and display apparatus

Abstract

Provided in the present disclosure are a driving module, a driving method and a display apparatus. The driving module comprises N stages of driving circuits, wherein N is an integer greater than 1; m and n are positive integers; and m is greater than 1, and n is greater than m. The driving module further comprises a partial-display control circuit, a first scanning control switch circuit and a second scanning control switch circuit, wherein the partial-display control circuit controls, in a partial display mode, the connection between a starting voltage terminal and a partial input terminal under the control of a display mode control signal; during forward scanning, the first scanning control switch circuit controls, in the partial display mode, the connection between the partial input terminal and an mth input terminal under the control of a scanning control signal; and during backward scanning, the second scanning control switch circuit controls, in the partial display mode, the connection between the partial input terminal and an nth input terminal. By means of the present disclosure, partial display can be realized while reducing power consumption.

Description

Drive module, drive method and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510118329.6, filed in China on January 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a driving module, driving method and display device. Background Technology

[0004] The relevant local display scheme displays the non-local display area as black and the local display area as the target image. However, this scheme results in high power consumption for the driving module. Summary of the Invention

[0005] The main objective of this disclosure is to provide a driving module, driving method, and display device to solve the problem of high power consumption when implementing partial display in related technologies.

[0006] In one aspect, embodiments of this disclosure provide a driving module, including N-level driving circuits; N is an integer greater than 1; the m-th driving circuit in the N-level driving circuit is a start-up driving circuit, the n-th driving circuit in the N-level driving circuit is a stop-off driving circuit, and m and n are positive integers; m is greater than 1, and n is greater than m; the driving module further includes a partial display control circuit, a first scan control switch circuit, and a second scan control switch circuit;

[0007] The local display control circuit is electrically connected to the display mode control terminal, the starting voltage terminal, and the local input terminal, and is used to control the connection between the starting voltage terminal and the local input terminal under the control of the display mode control signal provided by the display mode control terminal in the local display mode.

[0008] The first scan control switch circuit is electrically connected to the scan control terminal, the local input terminal and the m-th input terminal respectively. It is used to control the connection between the local input terminal and the m-th input terminal under the control of the scan control signal provided by the scan control terminal in the local display mode during forward scanning. The m-th input terminal is the input terminal of the start-stage drive circuit.

[0009] The second scan control switch circuit is electrically connected to the scan control terminal, the local input terminal, and the nth input terminal, respectively, and is used to control the connection between the local input terminal and the nth input terminal under the control of the scan control signal in the local display mode during reverse scanning; the nth input terminal is the input terminal of the cutoff stage drive circuit.

[0010] Optionally, the local display control circuit includes a local display control transmission gate; the display mode control terminal includes a first display mode control terminal and a second display mode control terminal.

[0011] The positive phase control terminal of the local display control transmission gate is electrically connected to the first display mode control terminal, the negative phase control terminal of the local display control transmission gate is electrically connected to the second display mode control terminal, the first terminal of the local display control transmission gate is electrically connected to the starting voltage terminal, and the second terminal of the local display control transmission gate is electrically connected to the local input terminal.

[0012] The first scan control switch circuit includes a first scan control transmission gate, and the second scan control switch circuit includes a second scan control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0013] The positive phase control terminal of the first scan control transmission gate is electrically connected to the positive scan control terminal, the negative phase control terminal of the first scan control transmission gate is electrically connected to the negative scan control terminal, the first terminal of the first scan control transmission gate is electrically connected to the local input terminal, and the second terminal of the first scan control transmission gate is electrically connected to the m-th input terminal.

[0014] The positive control terminal of the second scan control transmission gate is electrically connected to the negative scan control terminal, the negative control terminal of the second scan control transmission gate is electrically connected to the positive scan control terminal, the first terminal of the second scan control transmission gate is electrically connected to the local input terminal, and the second terminal of the second scan control transmission gate is electrically connected to the nth input terminal.

[0015] Optionally, the starting stage driving circuit includes an m-th stage driving signal generation circuit, a first starting switch circuit, and a second starting switch circuit.

[0016] The m-th stage drive signal generation circuit is electrically connected to the m-th input terminal and the m-th cascaded output terminal respectively, and is used to generate and provide the m-th cascaded signal through the m-th cascaded output terminal based on the m-th input signal connected to the m-th input terminal.

[0017] The first start switch circuit is electrically connected to the display mode control terminal, the m-th input terminal, and the first start node, respectively, and is used to control the connection or disconnection between the m-th input terminal and the first start node under the control of the display mode control signal provided by the display mode control terminal;

[0018] The second start switch circuit is electrically connected to the display mode control terminal, the m-th cascade output terminal, and the second start node, respectively, and is used to control the connection or disconnection between the m-th cascade output terminal and the second start node under the control of the display mode control signal.

[0019] Optionally, the first start switch circuit includes a first start switch transmission gate, the second start switch circuit includes a second start switch transmission gate, and the display mode control terminal includes a first display mode control terminal and a second display mode control terminal.

[0020] The positive phase control terminal of the first start switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the first start switch transmission gate is electrically connected to the first display mode control terminal, the first end of the first start switch transmission gate is electrically connected to the m-th input terminal, and the second end of the first start switch transmission gate is electrically connected to the first start node.

[0021] The positive phase control terminal of the second start switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the second start switch transmission gate is electrically connected to the first display mode control terminal, the first end of the second start switch transmission gate is electrically connected to the m-th cascade output terminal, and the second end of the second start switch transmission gate is electrically connected to the second start node.

[0022] Optionally, the starting stage drive circuit further includes an m-th forward scan control circuit and an m-th reverse scan control circuit;

[0023] The m-th forward scan control circuit is electrically connected to the scan control terminal, the m-th cascaded output terminal, and the m-th forward scan output node, respectively, and is used to control the connection between the m-th cascaded output terminal and the m-th forward scan output node under the control of the scan control signal during forward scanning.

[0024] The m-th reverse scan control circuit is electrically connected to the scan control terminal, the m-th input terminal, and the m-th reverse scan input node, respectively, and is used to control the connection between the m-th input terminal and the m-th reverse scan input node under the control of the scan control signal during reverse scanning.

[0025] The m-th level drive signal generation circuit is also electrically connected to the m-th drive signal output terminal, and is used to generate and provide the m-th drive signal through the m-th drive signal output terminal based on the m-th input signal.

[0026] Optionally, the m-th forward scan control circuit includes an m-th forward scan control transmission gate, and the m-th reverse scan control circuit includes an m-th reverse scan control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0027] The positive phase control terminal of the m-th forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the m-th forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the m-th forward scan control transmission gate is electrically connected to the m-th cascaded output terminal, and the second terminal of the m-th forward scan control transmission gate is electrically connected to the m-th forward scan output node.

[0028] The positive phase control terminal of the m-th backscan control transmission gate is electrically connected to the backscan control terminal, the negative phase control terminal of the m-th backscan control transmission gate is electrically connected to the positive phase control terminal, the first terminal of the m-th backscan control transmission gate is electrically connected to the m-th input terminal, and the second terminal of the m-th backscan control transmission gate is electrically connected to the m-th backscan input node.

[0029] Optionally, the m-th stage drive signal generation circuit includes an m-th stage D flip-flop and an m-th stage AND gate;

[0030] The input terminal of the m-th stage D flip-flop is electrically connected to the m-th input terminal, the control terminal of the m-th stage D flip-flop is electrically connected to the first control clock signal terminal, the first output terminal of the m-th stage D flip-flop is electrically connected to the m-th cascaded output terminal, and the second output terminal of the m-th stage D flip-flop is electrically connected to the m-th output terminal.

[0031] The first input terminal of the m-th AND gate is electrically connected to the m-th output terminal, the second input terminal of the m-th AND gate is electrically connected to the m-th cascaded output terminal, and the output terminal of the m-th AND gate is electrically connected to the m-th drive signal output terminal.

[0032] Optionally, the cutoff stage driving circuit includes an nth stage driving signal generation circuit, an nth forward scan control circuit, an nth reverse scan control circuit, a first cutoff switch circuit, and a second cutoff switch circuit.

[0033] The nth stage drive signal generation circuit is electrically connected to the nth input terminal and the nth cascade output terminal respectively, and is used to generate and provide the nth cascade signal through the nth cascade output terminal based on the nth input signal connected to the nth input terminal.

[0034] The nth forward scan control circuit is electrically connected to the scan control terminal, the nth cascaded output terminal, and the nth forward scan output node, respectively, and is used to control the connection between the nth cascaded output terminal and the nth forward scan output node under the control of the scan control signal during forward scanning.

[0035] The nth reverse scan control circuit is electrically connected to the scan control terminal, the nth input terminal, and the nth reverse scan input node, respectively, and is used to control the connection between the nth input terminal and the nth reverse scan input node under the control of the scan control signal during reverse scan.

[0036] The first cutoff switch circuit is electrically connected to the display mode control terminal, the nth forward scan output node and the first cutoff node respectively, and is used to control the connection or disconnection between the nth forward scan output node and the first cutoff node under the control of the display mode control signal provided by the display mode control terminal;

[0037] The second cutoff switch circuit is electrically connected to the display mode control terminal, the nth backscan input node, and the second cutoff node, respectively, and is used to control the connection or disconnection between the nth backscan input node and the second cutoff node under the control of the display mode control signal.

[0038] Optionally, the nth forward scan control circuit includes an nth forward scan control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0039] The positive phase control terminal of the nth forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the nth forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the nth forward scan control transmission gate is electrically connected to the nth cascaded output terminal, and the second terminal of the nth forward scan control transmission gate is electrically connected to the nth forward scan output node.

[0040] The nth backscan control circuit includes an nth backscan control transmission gate;

[0041] The positive phase control terminal of the nth backscan control transmission gate is electrically connected to the backscan control terminal, the negative phase control terminal of the nth backscan control transmission gate is electrically connected to the positive phase control terminal, the first terminal of the nth backscan control transmission gate is electrically connected to the nth input terminal, and the second terminal of the nth backscan control transmission gate is electrically connected to the nth backscan input node.

[0042] The first cutoff switch circuit includes a first cutoff switch transmission gate; the display mode control terminal includes a first display mode control terminal and a second display mode control terminal.

[0043] The positive phase control terminal of the first cutoff switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the first cutoff switch transmission gate is electrically connected to the first display mode control terminal, the first end of the first cutoff switch transmission gate is electrically connected to the nth positive scan output node, and the second end of the first cutoff switch transmission gate is electrically connected to the first cutoff node.

[0044] The second cutoff switch circuit includes a second cutoff switch transmission gate;

[0045] The positive phase control terminal of the second cut-off switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the second cut-off switch transmission gate is electrically connected to the first display mode control terminal, the first end of the second cut-off switch transmission gate is electrically connected to the nth reverse scan input node, and the second end of the second cut-off switch transmission gate is electrically connected to the second cut-off node.

[0046] Optionally, the nth-stage drive signal generation circuit is also electrically connected to the nth-stage drive signal output terminal, and is used to generate and provide the nth-stage drive signal through the nth-stage drive signal output terminal based on the nth-stage input signal.

[0047] Optionally, the nth stage drive signal generation circuit includes an nth stage D flip-flop and an nth AND gate;

[0048] The input terminals of the nth stage D flip-flop are electrically connected to the nth input terminal, the control terminal of the nth stage D flip-flop is electrically connected to the second control clock signal terminal, the first output terminal of the nth stage D flip-flop is electrically connected to the nth cascaded output terminal, and the second output terminal of the nth stage D flip-flop is electrically connected to the nth output terminal.

[0049] The first input terminal of the nth AND gate is electrically connected to the mth output terminal, the second input terminal of the nth AND gate is electrically connected to the nth cascaded output terminal, and the output terminal of the nth AND gate is electrically connected to the nth drive signal output terminal.

[0050] The driving module described in at least one embodiment of this disclosure further includes a global display control circuit;

[0051] The global display control circuit is electrically connected to the display mode control terminal, the starting voltage terminal, and the global input terminal, respectively, and is used to control the connection between the starting voltage terminal and the global input terminal under the control of the display mode control signal in the global display mode.

[0052] Optionally, the global display control circuit includes a global display control transmission gate; the display mode control terminal includes a first display mode control terminal and a second display mode control terminal.

[0053] The positive control terminal of the global display control transmission gate is electrically connected to the second display mode control terminal, the negative control terminal of the global display control transmission gate is electrically connected to the first display mode control terminal, the first terminal of the global display control transmission gate is electrically connected to the starting voltage terminal, and the second terminal of the global display control transmission gate is electrically connected to the global input terminal.

[0054] The driving module described in at least one embodiment of this disclosure further includes A forward scan input control circuits; where A is a positive integer.

[0055] The forward scan input control circuit is electrically connected to the global input terminal, the forward scan start control terminal, the scan control terminal, and the a input terminal, respectively. In global display mode, it performs a forward scan and, when scanning begins from the a-th stage drive circuit in the N-stage drive circuit, controls the connection between the global input terminal and the a input terminal under the control of the forward scan start control signal provided by the forward scan start control terminal and the scan control signal provided by the scan control terminal; the a input terminal is the input terminal of the a-th stage drive circuit.

[0056] a is a positive integer less than or equal to A.

[0057] Optionally, the a-th forward scan input control circuit includes an a-th first forward scan input control transmission gate and an a-th second forward scan input control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0058] The positive phase control terminal of the a-th first forward scan input control transmission gate is electrically connected to the a-th forward scan start control terminal, the negative phase control terminal of the a-th first forward scan input control transmission gate is electrically connected to the a-th negative phase forward scan start control terminal, the first terminal of the a-th first forward scan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the a-th first forward scan input control transmission gate is electrically connected to the first terminal of the a-th second forward scan input control transmission gate.

[0059] The positive phase control terminal of the a-th second forward scan input control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the a-th second forward scan input control transmission gate is electrically connected to the reverse scan control terminal, and the second terminal of the a-th second forward scan input control transmission gate is electrically connected to the a-th input terminal.

[0060] Optional, A is greater than 1;

[0061] The b-th stage drive circuit includes the (b-1)-th control cutoff circuit; b is an integer less than or equal to A and greater than 1;

[0062] The b-1 control cutoff circuit is electrically connected to the b-th forward scan start control terminal, the b-th input terminal, and the b-1-th forward scan output node, respectively, and is used to control the connection or disconnection between the b-th input terminal and the b-1-th forward scan output node under the control of the b-th forward scan start control signal provided by the b-th forward scan start control terminal;

[0063] The b-th input terminal is the input terminal of the b-th stage drive circuit in the N-stage drive circuit.

[0064] Optionally, the (b-1)th control cutoff circuit includes a (b-1)th control cutoff transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0065] The positive phase control terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th inverted forward scan start control terminal, the inverted phase control terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th forward scan start control terminal, the first terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th input terminal, and the second terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b-1)th forward scan output node.

[0066] Optionally, the (b-1)th stage drive circuit in the N-stage drive circuit includes a (b-1)th forward scan control transmission gate;

[0067] The positive phase control terminal of the (b-1)th forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the (b-1)th forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the (b-1)th forward scan control transmission gate is electrically connected to the (b-1)th cascade output terminal, and the second terminal of the (b-1)th forward scan control transmission gate is electrically connected to the (b-1)th forward scan output node; the (b-1)th cascade output terminal is the cascade output terminal of the (b-1)th stage drive circuit.

[0068] The driving module described in at least one embodiment of this disclosure further includes a first reverse scan input control circuit;

[0069] The first reverse scan input control circuit is electrically connected to the global input terminal, the first reverse scan start control terminal, the scan control terminal, and the Nth input terminal, respectively. It is used to perform reverse scanning in global display mode and, when scanning starts from the Nth level drive circuit in the Nth level drive circuit, control the connection between the global input terminal and the Nth input terminal under the control of the first reverse scan start control signal provided by the first reverse scan start control terminal; the Nth input terminal is the input terminal of the Nth level drive circuit in the Nth level drive circuit.

[0070] Optionally, the first backscan input control circuit includes a first backscan input control transmission gate and a second backscan input control transmission gate;

[0071] The positive control terminal of the first backscan input control transmission gate is electrically connected to the first backscan start control terminal, the negative control terminal of the first backscan input control transmission gate is electrically connected to the first negative backscan start control terminal, the first terminal of the first backscan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the first backscan input control transmission gate is electrically connected to the first terminal of the second backscan input control transmission gate.

[0072] The positive control terminal of the second first reverse scan input control transmission gate is electrically connected to the reverse scan control terminal, the negative control terminal of the second first reverse scan input control transmission gate is electrically connected to the positive scan control terminal, and the second terminal of the second first reverse scan input control transmission gate is electrically connected to the Nth input terminal.

[0073] The driving module described in at least one embodiment of this disclosure further includes C reverse scan input control circuits; where C is a positive integer.

[0074] The (c+1)th backscan input control circuit is electrically connected to the global input terminal, the (c+1)th backscan start control terminal, and the Ncth backscan input node, respectively. It is used to perform reverse scanning in global display mode and control the connection between the global input terminal and the Ncth backscan input node when scanning starts from the Ncth level driving circuit in the Nth level driving circuit; c is a positive integer less than or equal to C.

[0075] Optionally, the (c+1)th backscan input control circuit includes the (c+1)th backscan input control transmission gate;

[0076] The positive control terminal of the (c+1)th backscan input control transmission gate is electrically connected to the (c+1)th backscan start control terminal, the negative control terminal of the (c+1)th backscan input control transmission gate is electrically connected to the (c+1)th negative backscan start control terminal, the first terminal of the (c+1)th backscan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the (c+1)th backscan input control transmission gate is electrically connected to the Ncth backscan input node.

[0077] The driving module described in at least one embodiment of this disclosure further includes C cutoff circuits;

[0078] The c-th cutoff circuit is electrically connected to the c+1-th backscan start control terminal, the N-c+1-th cascaded output terminal, and the Nc-th backscan input node, respectively, and is used to control the connection or disconnection between the Nc-th backscan input node and the N-c+1-th cascaded output terminal under the control of the c+1-th backscan start control signal provided by the c+1-th backscan start control terminal.

[0079] Optionally, the c-th cutoff circuit includes a c-th cutoff transmission gate;

[0080] The positive phase control terminal of the c-th cutoff transmission gate is electrically connected to the c+1-th reverse scan start control terminal, the negative phase control terminal of the c-th cutoff transmission gate is electrically connected to the c+1-th reverse scan start control terminal, the first terminal of the c-th cutoff transmission gate is electrically connected to the Nc-th reverse scan input node, and the second terminal of the c-th cutoff transmission gate is electrically connected to the N-c+1-th cascaded output terminal.

[0081] In a second aspect, embodiments of this disclosure provide a driving method applied to the aforementioned driving module, the driving method comprising: in a partial display mode,

[0082] Under the control of the display mode control signal, the local display control circuit controls the connection between the starting voltage terminal and the local input terminal;

[0083] During forward scanning, the first scan control switch circuit, under the control of the scan control signal, controls the connection between the local input terminal and the m-th input terminal, where the m-th input terminal is the input terminal of the start-stage drive circuit.

[0084] During reverse scanning, the second scan control switch circuit, under the control of the scan control signal, controls the connection between the local input terminal and the nth input terminal; the nth input terminal is the input terminal of the cutoff stage drive circuit.

[0085] In a third aspect, embodiments of this disclosure provide a display device including the driving module described above.

[0086] When the driving module, driving method and display device described in the embodiments of this disclosure are in operation, in the partial display mode, only the partial display area displays the target image on the entire screen, and the non-partial display area does not work. Compared with the related driving module, the driving module described in the embodiments of this disclosure has reduced power consumption and can be applied to small silicon-based OLED (organic light-emitting diode) display products with limited resources. Attached Figure Description

[0087] Figure 1 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0088] Figure 2 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0089] Figure 3 is a structural diagram of at least one embodiment of the start-stage drive circuit in the drive module;

[0090] Figure 4 is a structural diagram of at least one embodiment of the starting stage drive circuit;

[0091] Figure 5 is a structural diagram of at least one embodiment of the starting stage drive circuit;

[0092] Figure 6 is a structural diagram of at least one embodiment of the starting stage drive circuit;

[0093] Figure 7A is a structural diagram of at least one embodiment of the starting stage drive circuit;

[0094] Figure 7B is a circuit diagram based on Figure 7A with the addition of TGP and TG1;

[0095] Figure 7C is a schematic diagram of the operating state of at least one embodiment of the starting stage drive circuit;

[0096] Figure 8 is a structural diagram of at least one embodiment of the cutoff stage drive circuit in the drive module;

[0097] Figure 9 is a structural diagram of at least one embodiment of the cutoff stage drive circuit;

[0098] Figure 10 is a circuit diagram of at least one embodiment of the cutoff stage drive circuit;

[0099] Figure 11A is a circuit diagram of at least one embodiment of the cutoff stage drive circuit;

[0100] Figure 11B is a circuit diagram based on Figure 11A with the addition of TGP and TG2;

[0101] Figure 11C is a schematic diagram of the working state of at least one embodiment of the cutoff stage drive circuit;

[0102] Figure 12 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0103] Figure 13 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0104] Figure 14 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0105] Figure 15 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0106] Figure 16 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0107] Figure 17 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0108] Figure 18 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0109] Figure 19 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0110] Figure 20 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0111] Figure 21 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0112] Figure 22 is a structural diagram of the drive module according to at least one embodiment of the present disclosure;

[0113] Figure 23A is a circuit diagram of the first-stage driving circuit, the second-stage driving circuit, and the third-stage driving circuit in the driving module according to at least one embodiment of the present disclosure;

[0114] Figure 23B is a circuit diagram of the first-stage driving circuit, the second-stage driving circuit, the third-stage driving circuit, and the fourth-stage driving circuit in the driving module according to at least one embodiment of the present disclosure.

[0115] Figure 23C is a circuit diagram of the m-th to n-th stage drive circuits in the drive module according to at least one embodiment of the present disclosure;

[0116] Figure 23D is a circuit diagram of the N-3rd stage drive circuit to the Nth stage drive circuit in the drive module according to at least one embodiment of the present disclosure;

[0117] Figure 24A is the circuit diagram of the first part B1 in Figure 23B, and Figure 24B is the circuit diagram of the second part B2 in Figure 23B.

[0118] Figure 24C is the circuit diagram of the third part B3 in Figure 23C, and Figure 24D is the circuit diagram of the fourth part B4 in Figure 23C.

[0119] Figure 24E is the circuit diagram of the fifth part B5 in Figure 23D, and Figure 24F is the circuit diagram of the sixth part B6 in Figure 23D. Detailed Implementation

[0120] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0121] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0122] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0123] The driving module described in this embodiment includes N-level driving circuits; N is an integer greater than 1; the m-th driving circuit in the N-level driving circuit is a start-up driving circuit, and the n-th driving circuit in the N-level driving circuit is a stop-off driving circuit, where m and n are positive integers; m is greater than 1, and n is greater than m; as shown in Figure 1, the driving module also includes a local display control circuit 11, a first scan control switch circuit 12, and a second scan control switch circuit 13;

[0124] The local display control circuit 11 is electrically connected to the display mode control terminal ENP, the starting voltage terminal STV, and the local input terminal PI. It is used to control the connection between the starting voltage terminal STV and the local input terminal PI under the control of the display mode control signal provided by the display mode control terminal ENP in the local display mode.

[0125] The first scan control switch circuit 12 is electrically connected to the scan control terminal GSD, the local input terminal PI, and the m-th input terminal Sm, respectively. In the local display mode, during forward scanning, under the control of the scan control signal provided by the scan control terminal GSD, the local input terminal PI and the m-th input terminal Sm are connected. The m-th input terminal Sm is the input terminal of the start-stage drive circuit.

[0126] The second scan control switch circuit 13 is electrically connected to the scan control terminal GSD, the local input terminal PI, and the nth input terminal Sn, respectively, and is used to control the connection between the local input terminal PI and the nth input terminal Sn under the control of the scan control signal in the local display mode during reverse scanning; the nth input terminal Sn is the input terminal of the cutoff stage drive circuit.

[0127] In Figure 1, the circuit labeled GAm is the m-th stage drive circuit, and the circuit labeled GAn is the n-th stage drive circuit.

[0128] In the operation of the driving module described in this embodiment, in partial display mode, the partial display control circuit 11, under the control of the display mode control signal provided by the display mode control terminal ENP, controls the connection between the starting voltage terminal STV and the partial input terminal PI, so as to write the starting voltage provided by the starting voltage terminal STV into the partial input terminal PI; in partial display mode, during forward scanning, the first scan control switch circuit 12, under the control of the scan control signal provided by the scan control terminal GSD, controls the connection between the partial input terminal PI and the m-th input terminal Sm, so as to write the starting voltage into the input terminal of the starting stage driving circuit; in partial display mode, during reverse scanning, the second scan control switch circuit 13, under the control of the scan control signal, controls the connection between the partial input terminal PI and the n-th input terminal Sn, so as to write the starting voltage into the input terminal of the cutoff stage driving circuit.

[0129] When the driving module described in this embodiment is working, in the partial display mode, only the partial display area displays the target image on the entire screen, and the non-partial display area does not work. Compared with related driving modules, the driving module described in this embodiment has reduced power consumption and can be applied to small silicon-based OLED (organic light-emitting diode) display products with limited resources.

[0130] When the related driver module is working, it controls the non-local display area to display a black screen and the local display area to display the target image. The related driver module has high power consumption.

[0131] When the driving module described in this embodiment is working, in the global display mode, the local display control circuit 11, under the control of the display mode control signal provided by the display mode control terminal ENP, controls the disconnection between the starting voltage terminal STV and the local input terminal PI, so as to stop writing the starting voltage provided by the starting voltage terminal STV into the local input terminal PI.

[0132] In at least one embodiment of this disclosure, the driving module can be applied to a silicon-based OLED (organic light-emitting diode) microdisplay, but is not limited thereto.

[0133] This disclosure provides a driving module capable of partial screen display. The driving module includes a start-up stage driving circuit, a stop-down stage driving circuit, a partial display control circuit, a first scan control switch circuit, and a second scan switch circuit. In partial display mode, the partial display control circuit writes a start-up voltage to the partial input terminal under the control of a display mode control signal.

[0134] In partial display mode, during forward scanning, the first scan control switch circuit, under the control of the scan control signal, controls the connection between the partial input terminal and the input terminal of the start-stage drive circuit, and writes the start voltage into the input terminal of the start-stage drive circuit.

[0135] In partial display mode, during reverse scanning, the second scan control switch circuit, under the control of the scan control signal, controls the connection between the partial input terminal PI and the input terminal of the cutoff stage drive circuit, and writes the starting voltage into the input terminal of the cutoff stage drive circuit.

[0136] With the above settings, you can enable the partial display function.

[0137] In at least one embodiment of this disclosure, as shown in FIG2, based on at least one embodiment of the driving module shown in FIG1, the local display control circuit may include a local display control transmission gate TGP; the display mode control terminal includes a first display mode control terminal EN_PART and a second display mode control terminal EN_PART';

[0138] The positive control terminal of the local display control transmission gate TGP is electrically connected to the first display mode control terminal EN_PART, the negative control terminal of the local display control transmission gate TGP is electrically connected to the second display mode control terminal EN_PART', the first terminal of the local display control transmission gate TGP is electrically connected to the starting voltage terminal STV, and the second terminal of the local display control transmission gate TGP is electrically connected to the local input terminal PI.

[0139] The first scan control switch circuit includes a first scan control transmission gate TG1, and the second scan control switch circuit includes a second scan control transmission gate TG2; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW;

[0140] The positive phase control terminal of the first scan control transmission gate TG1 is electrically connected to the positive scan control terminal GSD_FW, the negative phase control terminal of the first scan control transmission gate TG1 is electrically connected to the negative scan control terminal GSD_BW, the first terminal of the first scan control transmission gate TG1 is electrically connected to the local input terminal PI, and the second terminal of the first scan control transmission gate TG1 is electrically connected to the m-th input terminal Sm.

[0141] The positive phase control terminal of the second scan control transmission gate TG2 is electrically connected to the negative scan control terminal GSD_BW, the negative phase control terminal of the second scan control transmission gate TG2 is electrically connected to the positive scan control terminal GSD_FW, the first terminal of the second scan control transmission gate TG2 is electrically connected to the local input terminal PI, and the second terminal of the second scan control transmission gate TG2 is electrically connected to the nth input terminal Sn.

[0142] At least one embodiment shown in FIG2 of this disclosure, when in operation, in partial display mode,

[0143] EN_PART provides a high voltage signal, EN_PART' provides a low voltage signal, TGP is turned on, STV and PI are connected, and STV provides the starting voltage to PI;

[0144] During forward scanning, GSD_FW provides a high voltage signal, GSD_BW provides a low voltage signal, TG1 is turned on, and PI and Sm are connected to write the starting voltage to Sm.

[0145] During reverse scanning, GSD_FW provides a low voltage signal, GSD_BW provides a high voltage signal, TG2 is turned on, and PI and Sn are connected to write the starting voltage to Sn.

[0146] In at least one embodiment shown in Figure 2 of this disclosure, during operation, in global display mode, EN_PART provides a low voltage signal, EN_PART' provides a high voltage signal, TGP is turned off, and STV and PI are disconnected.

[0147] In at least one embodiment of this disclosure, as shown in FIG3, the at least one embodiment of the start-stage driving circuit includes an m-th stage driving signal generation circuit 30, a first start-up switch circuit 31, and a second start-up switch circuit 32.

[0148] The m-th stage drive signal generation circuit 30 is electrically connected to the m-th input terminal Sm and the m-th cascade output terminal CTm respectively, and is used to generate and provide the m-th cascade signal through the m-th cascade output terminal CTm based on the m-th input signal connected to the m-th input terminal Sm.

[0149] The first start switch circuit 31 is electrically connected to the display mode control terminal ENP, the m-th input terminal Sm, and the first start node NS1, respectively, and is used to control the connection or disconnection between the m-th input terminal Sm and the first start node NS1 under the control of the display mode control signal provided by the display mode control terminal ENP.

[0150] The second start switch circuit 32 is electrically connected to the display mode control terminal ENP, the m-th cascade output terminal CTm, and the second start node NS2, respectively, and is used to control the connection or disconnection between the m-th cascade output terminal CTm and the second start node NS2 under the control of the display mode control signal.

[0151] At least one embodiment shown in FIG3 of this disclosure, in operation, in partial display mode,

[0152] Under the control of the display mode control signal, the first start switch circuit 31 controls the m-th input terminal Sm to disconnect from the first start node NS1, and the second start switch circuit 32 controls the m-th cascaded output terminal CTm to disconnect from the second start node NS2, thereby blocking the signal transmission path between the start stage drive circuit and the (m-1)-th stage drive circuit, thus ensuring partial display.

[0153] At least one embodiment shown in Figure 3 of this disclosure, when in operation, in global display mode,

[0154] Under the control of the display mode control signal, the first start switch circuit 31 controls the connection between the m-th input terminal Sm and the first start node NS1, and the second start switch circuit 32 controls the connection between the m-th cascaded output terminal CTm and the second start node NS2, so as to conduct the signal transmission path between the start stage drive circuit and the (m-1)-th stage drive circuit, thereby enabling global display.

[0155] In at least one embodiment of this disclosure, as shown in FIG4, based on at least one embodiment shown in FIG3, the first start switch circuit includes a first start switch transmission gate TGS1, the second start switch circuit includes a second start switch transmission gate TGS2, and the display mode control terminal includes a first display mode control terminal EN_PART and a second display mode control terminal EN_PART'.

[0156] The positive phase control terminal of the first start switch transmission gate TGS1 is electrically connected to the second display mode control terminal EN_PART', the negative phase control terminal of the first start switch transmission gate TGS1 is electrically connected to the first display mode control terminal EN_PART, the first terminal of the first start switch transmission gate TGS1 is electrically connected to the m-th input terminal Sm, and the second terminal of the first start switch transmission gate TGS1 is electrically connected to the first start node NS1.

[0157] The positive phase control terminal of the second start switch transmission gate TGS2 is electrically connected to the second display mode control terminal EN_PART', the negative phase control terminal of the second start switch transmission gate TGS2 is electrically connected to the first display mode control terminal EN_PART, the first terminal of the second start switch transmission gate TGS2 is electrically connected to the m-th cascade output terminal CTm, and the second terminal of the second start switch transmission gate TGS2 is electrically connected to the second start node NS2.

[0158] In operation, at least one embodiment shown in FIG4 of this disclosure provides a low voltage signal and a high voltage signal in partial display mode, EN_PART' provides a low voltage signal, TGS1 and TGS2 are turned off, Sm is disconnected from NS1, and CTm is disconnected from NS2.

[0159] In global display mode, EN_PART' provides a high voltage signal, EN_PART provides a low voltage signal, TGS1 and TGS2 are turned on, Sm is connected to NS1, and CTm is connected to NS2.

[0160] In at least one embodiment of this disclosure, as shown in FIG5, based on at least one embodiment shown in FIG4, the start-stage drive circuit further includes an m-th forward scan control circuit 51 and an m-th reverse scan control circuit 52;

[0161] The m-th forward scan control circuit 51 is electrically connected to the scan control terminal GSD, the m-th cascaded output terminal CTm, and the m-th forward scan output node NTm, respectively, and is used to control the connection between the m-th cascaded output terminal CTm and the m-th forward scan output node NTm under the control of the scan control signal during forward scanning.

[0162] The m-th reverse scan control circuit 52 is electrically connected to the scan control terminal GSD, the m-th input terminal Sm, and the m-th reverse scan input node NIm, respectively, and is used to control the connection between the m-th input terminal Sm and the m-th reverse scan input node NIm under the control of the scan control signal when performing reverse scan.

[0163] The m-th drive signal generation circuit 30 is also electrically connected to the m-th drive signal output terminal Gm, and is used to generate and provide the m-th drive signal through the m-th drive signal output terminal Gm according to the m-th input signal.

[0164] At least one embodiment shown in FIG5 of this disclosure is in operation.

[0165] During forward scanning, the m-th forward scan control circuit 51, under the control of the scan control signal, controls the connection between the m-th cascaded output terminal CTm and the m-th forward scan output node NTm; the m-th reverse scan control circuit 52, under the control of the scan control signal, controls the disconnection between the m-th input terminal Sm and the m-th reverse scan input node NIm.

[0166] During reverse scanning, the m-th reverse scanning control circuit 52, under the control of the scan control signal, controls the connection between the m-th input terminal Sm and the m-th reverse scanning input node NIm; the m-th forward scanning control circuit 51, under the control of the scan control signal, controls the disconnection between the m-th cascaded output terminal CTm and the m-th forward scanning output node NTm.

[0167] In at least one embodiment of this disclosure, as shown in FIG6, based on at least one embodiment shown in FIG5, the m-th forward scan control circuit includes the m-th forward scan control transmission gate TGFm, and the m-th reverse scan control circuit includes the m-th reverse scan control transmission gate TGBm; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW;

[0168] The positive phase control terminal of the m-th forward scan control transmission gate TGFm is electrically connected to the forward scan control terminal GSD_FW, the negative phase control terminal of the m-th forward scan control transmission gate TGFm is electrically connected to the reverse scan control terminal GSD_BW, the first terminal of the m-th forward scan control transmission gate TGFm is electrically connected to the m-th cascaded output terminal CTm, and the second terminal of the m-th forward scan control transmission gate TGFm is electrically connected to the m-th forward scan output node NTm.

[0169] The positive phase control terminal of the m-th backscan control transmission gate TGBm is electrically connected to the backscan control terminal GSD_BW, the inverting phase control terminal of the m-th backscan control transmission gate TGBm is electrically connected to the positive phase control terminal GSD_FW, the first terminal of the m-th backscan control transmission gate TGBm is electrically connected to the m-th input terminal Sm, and the second terminal of the m-th backscan control transmission gate TGBm is electrically connected to the m-th backscan input node NIm.

[0170] At least one embodiment shown in FIG6 of this disclosure is in operation.

[0171] During forward scanning, GSD_FW provides a high voltage signal, GSD_BW provides a low voltage signal, TGFm is turned on, and CTm and NTm are connected; TGBm is turned off, and Sm and NIm are disconnected.

[0172] During reverse scan, GSD_FW provides a low voltage signal, GSW_BW provides a high voltage signal, TGBm is turned on, and Sm and NIm are connected; TGFm is turned off, and CTm and NTm are disconnected.

[0173] In at least one embodiment of this disclosure, as shown in FIG7A, based on at least one embodiment shown in FIG6, the m-th stage drive signal generation circuit includes an m-th stage D flip-flop DFFm and an m-th AND gate ADm;

[0174] The input terminal of the m-th stage D flip-flop DFFm is electrically connected to the m-th input terminal Sm, the control terminal of the m-th stage D flip-flop DFFm is electrically connected to the first control clock signal terminal CK1, the first output terminal of the m-th stage D flip-flop DFFm is electrically connected to the m-th cascaded output terminal CTm, and the second output terminal of the m-th stage D flip-flop DFFm is electrically connected to the m-th output terminal OTm.

[0175] The first input terminal of the m-th AND gate ADm is electrically connected to the m-th output terminal OTm, the second input terminal of the m-th AND gate ADm is electrically connected to the m-th cascaded output terminal CTm, and the output terminal of the m-th AND gate ADm is electrically connected to the m-th drive signal output terminal Gm.

[0176] In Figure 7A, the terminal labeled D is the input terminal of the D flip-flop, the terminal labeled Q_INTER is the first output terminal of the D flip-flop, the terminal labeled Q is the second output terminal of the D flip-flop, the terminal labeled CK is the control terminal of the flip-flop, the terminal labeled R is the reset terminal of the D flip-flop, the terminal labeled GND is the ground terminal, the terminal labeled Q' is the inverting output terminal of the D flip-flop, and the terminal labeled Vdd is the power supply terminal.

[0177] In Figure 7A, the label Fm is the m-th output inverter, and the label GFm is the m-th inverting drive signal output terminal.

[0178] Figure 7B is a circuit diagram based on Figure 7A with the addition of TGP and TG1.

[0179] In at least one embodiment shown in Figure 7B, during operation, the starting voltage can be written into the starting stage driving circuit in the local display mode, and the control signal transmission direction is forward scanning. This enables the display area above the starting stage to be inactive, so that the pixel circuit corresponding to the m-th stage driving circuit can function as the starting row of the local display area.

[0180] As shown in Figure 7B, in partial display mode, during forward scanning,

[0181] EN_PART provides a high voltage signal, EN_PART' provides a low voltage signal, TGP is turned on, STV and PI are connected, GSD_FW provides a high voltage signal, GSD_BW provides a low voltage signal, TG1 is turned on, STV writes the starting voltage to the m-th input terminal Sm;

[0182] In Figure 7B, the node between TG1 and TGS1 is the signal level transmission endpoint between the (m-1)th stage drive circuit and the mth stage drive circuit, the node between TGS2 and TGFm is the signal level transmission start point between the mth stage drive circuit and the m+1th stage drive circuit, and NTm is the signal level transmission endpoint between the mth stage drive circuit and the m+1th stage drive circuit.

[0183] At least one embodiment shown in Figure 7B during operation

[0184] When the starting voltage is input to Sm from TGP and TG1, it will pass through the signal level transmission endpoint. That is, the starting voltage may be transmitted upward or downward. If the starting voltage is transmitted upward, the logic of the starting row module will conflict with the local display requirements. Therefore, in order to ensure that the starting voltage is transmitted stably to the next level, TGS1 is added to the path of transmission to the next level for switching control. Similarly, after the signal passes through DFFm, there is also a signal level transmission starting point between the m-th driving circuit and the (m+1)-th driving circuit. Therefore, TGS2 also needs to be added to the path of transmission to the next level for switching control.

[0185] As shown in Figure 7C, when EN_PART provides a high voltage signal and EN_PART' provides a low voltage signal, the local display mode is entered, TGS1 and TGS2 are both disconnected, thereby controlling the signal transmission direction to be downward.

[0186] When EN_PART provides a low voltage signal and EN_PART' provides a high voltage signal, the global display mode is entered, and both TGS1 and TGS2 are turned on (which can be regarded as two wires). The transmission direction can be selected according to the forward and reverse scanning settings.

[0187] In at least one embodiment of this disclosure, as shown in FIG8, at least one embodiment of the cutoff stage driving circuit may include an nth stage driving signal generation circuit 80, an nth forward scan control circuit 81, an nth reverse scan control circuit 82, a first cutoff switch circuit 83, and a second cutoff switch circuit 84.

[0188] The nth stage drive signal generation circuit 80 is electrically connected to the nth input terminal Sn and the nth cascade output terminal CTn respectively, and is used to generate and provide the nth cascade signal through the nth cascade output terminal CTn based on the nth input signal connected to the nth input terminal Sn;

[0189] The nth forward scan control circuit 81 is electrically connected to the scan control terminal GSD, the nth cascaded output terminal CTn, and the nth forward scan output node NTn, respectively, and is used to control the connection between the nth cascaded output terminal CTm and the nth forward scan output node NTn under the control of the scan control signal during forward scanning.

[0190] The nth reverse scan control circuit 82 is electrically connected to the scan control terminal GSD, the nth input terminal Sn, and the nth reverse scan input node NIn, respectively, and is used to control the connection between the nth input terminal Sn and the nth reverse scan input node NIn under the control of the scan control signal when performing reverse scan.

[0191] The first cutoff switch circuit 83 is electrically connected to the display mode control terminal ENP, the nth forward scan output node NTn and the first cutoff node NJ1 respectively, and is used to control the connection or disconnection between the nth forward scan output node NTn and the first cutoff node NJ1 under the control of the display mode control signal provided by the display mode control terminal ENP.

[0192] The second cutoff switch circuit 84 is electrically connected to the display mode control terminal ENP, the nth backscan input node NIn, and the second cutoff node NJ2, respectively, and is used to control the connection or disconnection between the nth backscan input node NIn and the second cutoff node NJ2 under the control of the display mode control signal.

[0193] At least one embodiment shown in FIG8 of this disclosure, in partial display mode during operation,

[0194] Under the control of the display mode control signal, the first cutoff switch circuit 83 controls the nth forward scan output node NTn to disconnect from the first cutoff node NJ1, and the second cutoff switch circuit 84 controls the nth reverse scan input node NIn to disconnect from the second cutoff node NJ2, thereby disconnecting the signal transmission path between the nth stage drive circuit and the (n+1)th stage drive circuit.

[0195] During forward scanning, the nth forward scan control circuit 81, under the control of the scan control signal, controls the connection between the nth cascaded output terminal CTm and the nth forward scan output node NTn; the nth reverse scan control circuit 82, under the control of the scan control signal, controls the disconnection between the nth input terminal Sn and the nth reverse scan input node NIn.

[0196] During reverse scanning, the nth reverse scan control circuit 82, under the control of the scan control signal, controls the connection between the nth input terminal Sn and the nth reverse scan input node NIn; the nth forward scan control circuit 81, under the control of the scan control signal, controls the disconnection between the nth cascaded output terminal CTm and the nth forward scan output node NTn.

[0197] In at least one embodiment of this disclosure, as shown in FIG9, based on at least one embodiment shown in FIG8, the nth forward scan control circuit includes an nth forward scan control transmission gate TGFn; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW;

[0198] The positive phase control terminal of the nth forward scan control transmission gate TGFn is electrically connected to the forward scan control terminal GSD_FW, the negative phase control terminal of the nth forward scan control transmission gate TGFn is electrically connected to the reverse scan control terminal GSD_BW, the first terminal of the nth forward scan control transmission gate TGn is electrically connected to the nth cascaded output terminal CTn, and the second terminal of the nth forward scan control transmission gate TGn is electrically connected to the nth forward scan output node NTn.

[0199] The nth backscan control circuit includes the nth backscan control transmission gate TGBn;

[0200] The positive phase control terminal of the nth backscan control transmission gate TGBn is electrically connected to the backscan control terminal GSD_BW, the negative phase control terminal of the nth backscan control transmission gate TGBn is electrically connected to the positive phase control terminal GSD_FW, the first terminal of the nth backscan control transmission gate TGBn is electrically connected to the nth input terminal Sn, and the second terminal of the nth backscan control transmission gate TGBn is electrically connected to the nth backscan input node NIn.

[0201] The first cutoff switch circuit includes a first cutoff switch transmission gate TGJ1; the display mode control terminal includes a first display mode control terminal EN_PART and a second display mode control terminal EN_PART'.

[0202] The positive phase control terminal of the first cutoff switch transmission gate TGJ1 is electrically connected to the second display mode control terminal EN_PART', the negative phase control terminal of the first cutoff switch transmission gate TGJ1 is electrically connected to the first display mode control terminal EN_PART, the first terminal of the first cutoff switch transmission gate TGJ1 is electrically connected to the nth positive scan output node NTn, and the second terminal of the first cutoff switch transmission gate TGJ1 is electrically connected to the first cutoff node NJ1.

[0203] The second cutoff switch circuit includes a second cutoff switch transmission gate TGJ2;

[0204] The positive phase control terminal of the second cutoff switch transmission gate TGJ2 is electrically connected to the second display mode control terminal EN_PART', the negative phase control terminal of the second cutoff switch transmission gate TGJ2 is electrically connected to the first display mode control terminal EN_PART, the first terminal of the second cutoff switch transmission gate TGJ2 is electrically connected to the nth reverse scan input node NIn, and the second terminal of the second cutoff switch transmission gate TGJ2 is electrically connected to the second cutoff node NJ2.

[0205] In at least one embodiment shown in FIG9 of this disclosure, during operation, in partial display mode, EN_PART provides a high voltage signal, EN_PART' provides a low voltage signal, TGJ1 and TGJ2 are turned off, NTn is disconnected from NJ1, NIn is disconnected from NJ2, and the signal transmission path between the nth stage drive circuit and the n+1th stage drive circuit is disconnected, so that partial display can be performed.

[0206] In global display mode, EN_PART provides a low voltage signal, EN_PART' provides a high voltage signal, TGJ1 and TGJ2 are turned on, NTn is connected to NJ1, and NIn is connected to NJ2, thus turning on the signal transmission path between the nth stage drive circuit and the (n+1)th stage drive circuit to enable global display.

[0207] At least one embodiment shown in FIG9 of this disclosure is in operation.

[0208] During forward scanning, GSD_FW provides a high voltage signal, GSD_BW provides a low voltage signal, TGFn is turned on, TGBn is turned off, CTn and NTn are connected, and Sn and Nin are disconnected.

[0209] During reverse scan, GSD_FW provides a low voltage signal, GSD_BW provides a high voltage signal, TGBn is turned on, TGFn is turned off, Sn and Nin are connected, and CTn and NTn are disconnected.

[0210] As shown in Figure 10, based on at least one embodiment shown in Figure 9, the nth stage drive signal generation circuit is also electrically connected to the nth drive signal output terminal Gn, and is used to generate and provide the nth drive signal through the nth drive signal output terminal Gn according to the nth input signal.

[0211] In at least one embodiment of this disclosure, as shown in FIG11A, based on at least one embodiment shown in FIG10, the nth stage drive signal generation circuit includes an nth stage D flip-flop DFFn and an nth AND gate ADn;

[0212] The input terminal of the nth stage D flip-flop DFFn is electrically connected to the nth input terminal Sn, the control terminal of the nth stage D flip-flop DFFn is electrically connected to the second control clock signal terminal CK2, the first output terminal of the nth stage D flip-flop DFFn is electrically connected to the nth cascaded output terminal CTn, and the second output terminal of the nth stage D flip-flop DFFn is electrically connected to the nth output terminal OTn.

[0213] The first input terminal of the nth AND gate ADn is electrically connected to the mth output terminal OTn, the second input terminal of the nth AND gate ADn is electrically connected to the nth cascaded output terminal CTn, and the output terminal of the nth AND gate ADn is electrically connected to the nth drive signal output terminal Gn.

[0214] In at least one embodiment of this disclosure, when the D flip-flop is in operation, the signal connected to the input terminal of the D flip-flop is written to the first output terminal of the D flip-flop at the rising edge of the clock signal connected to the control terminal of the D flip-flop, and the signal connected to the first output terminal of the D flip-flop is written to the second output terminal of the D flip-flop at the falling edge of the control signal connected to the control terminal of the D flip-flop.

[0215] In Figure 11A, the nth output inverter is labeled Fn, and the nth inverting drive signal output terminal is labeled GFn.

[0216] Figure 11A is a circuit diagram of at least one embodiment of the cutoff stage drive circuit.

[0217] In at least one embodiment shown in FIG11A, TGJ1 and TGJ2 are circuit modules for controlling the direction of signal transmission.

[0218] In operation, at least one embodiment shown in FIG11A of this disclosure provides a high voltage signal and EN_PART' provides a low voltage signal in partial display mode. TGJ1 and TGJ2 are turned off, NIn and NJ2 are disconnected, and NTn and NJ1 are disconnected to disconnect the signal transmission path between the nth stage drive circuit and the n+1th stage drive circuit.

[0219] In global display mode, EN_PART provides a low voltage signal, EN_PART' provides a high voltage signal, TGJ1 and TGJ2 are turned on, NIn and NJ2 are connected, and NTn and NJ1 are connected to establish the signal transmission path between the nth stage drive circuit and the (n+1)th stage drive circuit.

[0220] Figure 11B is a circuit diagram based on Figure 11A with the addition of TGP and TG2.

[0221] In Figure 11B, the connection node between TG2 and TGBn is the signal level transmission endpoint between the nth stage drive circuit and the (n+1)th stage drive circuit.

[0222] The connection node between DFFn and TGFn is the signal level transmission point between the nth stage driver circuit and the (n-1)th stage driver circuit.

[0223] In at least one embodiment shown in FIG11B of this disclosure, when the initial voltage is written to Sn during operation, the signal faces three shunt paths: transmission to the next level, entry into DFFn in the nth stage driving circuit, and transmission to the next level.

[0224] When the signal is transmitted to the next higher level driver circuit, logically speaking, the end point of this path is connected to Q_INTER of the (n-1)th level driver circuit. That is, the signal is directly output without passing through the D flip-flop in the (n-1)th level driver circuit. This means that there is no line cycle interval between the nth driving signal output by the nth level driver circuit and the (n-1)th driving signal output by the (n-1)th level driver circuit, resulting in a timing error. From a physical structure perspective, this path is a forward scan transmission path. That is, when the scan mode is reverse scan mode, the forward scan control transmission gate in the (n-1)th level driver circuit is turned off, and the path for the signal to be transmitted from Sn to the next higher level driver circuit is broken.

[0225] When the signal enters the DFFn in the nth stage driver circuit, this path is the expected input path. This is because, as a cutoff stage, it needs to output the current stage driver signal and also transmit the signal level to the input of the D flip-flop in the (n-1)th stage driver circuit in reverse scan mode.

[0226] When the signal is transmitted to the next stage driver circuit, logically, the end point of this path connects to Q_INTER in the (n+1)th stage driver circuit, meaning the signal does not pass through the D flip-flop output in the (n+1)th stage driver circuit, resulting in a timing error. From a physical structure perspective, this path is a reverse scan transmission path. In reverse scan mode, the reverse scan control transmission gate in the (n+1)th stage driver circuit is turned on. Therefore, TGJ2, controlled by EN_PART and EN_PART', needs to be set separately to cut off the signal transmission path. Furthermore, as the last stage driver circuit for partial display, the driver circuits below the cutoff stage driver circuit should not work in partial display mode. Therefore, this path should be disconnected.

[0227] When the signal enters the DFFn in the nth stage driver circuit, it faces two branching paths: transmission to the next stage driver circuit and transmission to the next stage driver circuit.

[0228] Since the cutoff stage driver circuit needs to implement a reverse scan mode, the signal needs to be transmitted to the next higher-level driver circuit. Simultaneously, a new TGJ1 controlled by EN_PART and EN_PART' needs to be added to the path for transmission to the next higher-level driver circuit to control the truncation of the downward transmission path. In summary, when EN_PART provides a high voltage signal and EN_PART' provides a low voltage signal, the system enters a partial display mode, and the signal is transmitted along the solid line path shown in Figure 11C. When EN_PART provides a low voltage signal and EN_PART' provides a high voltage signal, the system enters a global display mode, and the transmission direction is selected according to the forward / reverse scan settings.

[0229] The driving module described in at least one embodiment of this disclosure further includes a global display control circuit;

[0230] The global display control circuit is electrically connected to the display mode control terminal, the starting voltage terminal, and the global input terminal, respectively, and is used to control the connection between the starting voltage terminal and the global input terminal under the control of the display mode control signal in the global display mode.

[0231] In a specific implementation, the driving module may further include a global display control circuit; in the global display mode, the global display control circuit, under the control of the display mode control signal, controls the connection between the starting voltage terminal and the global input terminal, so as to control the writing of the starting voltage to the global input terminal.

[0232] As shown in Figure 12, based on at least one embodiment shown in Figure 1, the driving module of at least one embodiment of this disclosure further includes a global display control circuit 111;

[0233] The global display control circuit 111 is electrically connected to the display mode control terminal ENP, the start voltage terminal STV, and the global input terminal GI, respectively, and is used to control the connection between the start voltage terminal STV and the global input terminal GI under the control of the display mode control signal in the global display mode.

[0234] As shown in Figure 13, based on at least one embodiment shown in Figure 12, the global display control circuit may include a global display control transmission gate TGQ; the display mode control terminal includes a first display mode control terminal EN_PART and a second display mode control terminal EN_PART'.

[0235] The positive control terminal of the global display control transmission gate TGQ is electrically connected to the second display mode control terminal EN_PART', the negative control terminal of the global display control transmission gate TGQ is electrically connected to the first display mode control terminal EN_PART, the first terminal of the global display control transmission gate TGQ is electrically connected to the starting voltage terminal STV, and the second terminal of the global display control transmission gate TGQ is electrically connected to the global input terminal GI.

[0236] The driving module described in at least one embodiment of this disclosure further includes A forward scan input control circuits; where A is a positive integer.

[0237] The forward scan input control circuit is electrically connected to the global input terminal, the forward scan start control terminal, the scan control terminal, and the a input terminal, respectively. In global display mode, it performs a forward scan and, when scanning begins from the a-th stage drive circuit in the N-stage drive circuit, controls the connection between the global input terminal and the a input terminal under the control of the forward scan start control signal provided by the forward scan start control terminal and the scan control signal provided by the scan control terminal; the a input terminal is the input terminal of the a-th stage drive circuit.

[0238] a is a positive integer less than or equal to A.

[0239] In at least one embodiment of this disclosure, A equals 3 as an example.

[0240] As shown in Figure 14, based on at least one embodiment shown in Figure 13, the driving module described in at least one embodiment of this disclosure may further include a first forward scan input control circuit 131, a second forward scan input control circuit 132, and a third forward scan input control circuit 133.

[0241] The first forward scan input control circuit 131 is electrically connected to the global input terminal GI, the first forward scan start control terminal FS1, the scan control terminal GSD, and the first input terminal S1, respectively. In global display mode, it performs forward scanning and, when scanning begins from the first-stage drive circuit GA1 in the N-stage drive circuit, controls the connection between the global input terminal GI and the first input terminal S1 under the control of the first forward scan start control signal provided by the first forward scan start control terminal FS1 and the scan control signal provided by the scan control terminal GSD; the first input terminal S1 is the input terminal of the first-stage drive circuit GA1.

[0242] The second forward scan input control circuit 132 is electrically connected to the global input terminal GI, the second forward scan start control terminal FS2, the scan control terminal GSD, and the second input terminal S2, respectively. In global display mode, it performs forward scanning and, when scanning begins from the second-stage drive circuit GA2 in the N-stage drive circuit, controls the connection between the global input terminal GI and the second input terminal S2 under the control of the second forward scan start control signal provided by the second forward scan start control terminal FS2 and the scan control signal provided by the scan control terminal GSD; the second input terminal S2 is the input terminal of the second-stage drive circuit GA2.

[0243] The third forward scan input control circuit 133 is electrically connected to the global input terminal GI, the third forward scan start control terminal FS3, the scan control terminal GSD, and the third input terminal S3, respectively. It is used to perform forward scanning in global display mode and, when scanning starts from the third-level drive circuit GA3 in the N-level drive circuit, control the connection between the global input terminal GI and the third input terminal S3 under the control of the third forward scan start control signal provided by the third forward scan start control terminal SF3 and the scan control signal provided by the scan control terminal GSD; the third input terminal S3 is the input terminal of the third-level drive circuit GA3.

[0244] Optionally, the a-th forward scan input control circuit includes an a-th first forward scan input control transmission gate and an a-th second forward scan input control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0245] The positive phase control terminal of the a-th first forward scan input control transmission gate is electrically connected to the a-th forward scan start control terminal, the negative phase control terminal of the a-th first forward scan input control transmission gate is electrically connected to the a-th negative phase forward scan start control terminal, the first terminal of the a-th first forward scan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the a-th first forward scan input control transmission gate is electrically connected to the first terminal of the a-th second forward scan input control transmission gate.

[0246] The positive phase control terminal of the a-th second forward scan input control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the a-th second forward scan input control transmission gate is electrically connected to the reverse scan control terminal, and the second terminal of the a-th second forward scan input control transmission gate is electrically connected to the a-th input terminal.

[0247] In a specific implementation, the a-th forward scan input control circuit may include an a-th first forward scan input control transmission gate and an a-th second forward scan input control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal; the a-th first forward scan input control transmission gate controls the connection or disconnection between the global input terminal and the first terminal of the a-th second forward scan input control transmission gate; the a-th second forward scan input control transmission gate controls the connection or disconnection between the a-th input terminal of the reverse scan control terminal.

[0248] As shown in Figure 15, based on at least one embodiment shown in Figure 14, the first forward scan input control circuit includes a first first forward scan input control transmission gate TGZ11 and a first second forward scan input control transmission gate TGZ12; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW.

[0249] The positive phase control terminal of the first forward scan input control transmission gate TGZ11 is electrically connected to the first forward scan start control terminal FS1, the negative phase control terminal of the first forward scan input control transmission gate TGZ11 is electrically connected to the first negative phase forward scan start control terminal NFS1, the first terminal of the first forward scan input control transmission gate TGZ11 is electrically connected to the global input terminal GI, and the second terminal of the first forward scan input control transmission gate TGZ11 is electrically connected to the first terminal of the first second forward scan input control transmission gate TGZ12.

[0250] The positive phase control terminal of the first second forward scan input control transmission gate TGZ12 is electrically connected to the forward scan control terminal GSD_FW, the negative phase control terminal of the first second forward scan input control transmission gate TGZ12 is electrically connected to the reverse scan control terminal GSD_BW, and the second terminal of the first second forward scan input control transmission gate TGZ12 is electrically connected to the first input terminal S1.

[0251] The second forward scan input control circuit includes a second first forward scan input control transmission gate TGZ21 and a second second forward scan input control transmission gate TGZ22; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW;

[0252] The positive phase control terminal of the second first forward scan input control transmission gate TGZ21 is electrically connected to the second forward scan start control terminal FS2, the negative phase control terminal of the second first forward scan input control transmission gate TGZ21 is electrically connected to the second negative phase forward scan start control terminal NFS2, the first terminal of the second first forward scan input control transmission gate TGZ21 is electrically connected to the global input terminal GI, and the second terminal of the second first forward scan input control transmission gate TGZ21 is electrically connected to the first terminal of the second second forward scan input control transmission gate TGZ22.

[0253] The positive phase control terminal of the second positive scan input control transmission gate TGZ22 is electrically connected to the positive scan control terminal GSD_FW, the negative phase control terminal of the second positive scan input control transmission gate TGZ22 is electrically connected to the negative scan control terminal GSD_BW, and the second terminal of the second positive scan input control transmission gate TGZ22 is electrically connected to the second input terminal S2.

[0254] The second forward scan input control circuit includes a second first forward scan input control transmission gate TGZ21 and a second second forward scan input control transmission gate TGZ22; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW;

[0255] The positive phase control terminal of the third first forward scan input control transmission gate TGZ31 is electrically connected to the third forward scan start control terminal FS3, the negative phase control terminal of the third first forward scan input control transmission gate TGZ31 is electrically connected to the third negative phase forward scan start control terminal NFS3, the first terminal of the third first forward scan input control transmission gate TGZ31 is electrically connected to the global input terminal GI, and the second terminal of the third first forward scan input control transmission gate TGZ31 is electrically connected to the first terminal of the third second forward scan input control transmission gate TGZ32.

[0256] The positive phase control terminal of the third second forward scan input control transmission gate TGZ32 is electrically connected to the forward scan control terminal GSD_FW, the negative phase control terminal of the third second forward scan input control transmission gate TGZ32 is electrically connected to the reverse scan control terminal GSD_BW, and the second terminal of the third second forward scan input control transmission gate TGZ32 is electrically connected to the third input terminal S3.

[0257] In at least one embodiment of this disclosure, A is greater than 1;

[0258] The b-th stage drive circuit includes the (b-1)-th control cutoff circuit; b is an integer less than or equal to A and greater than 1;

[0259] The b-1 control cutoff circuit is electrically connected to the b-th forward scan start control terminal, the b-th input terminal, and the b-1-th forward scan output node, respectively, and is used to control the connection or disconnection between the b-th input terminal and the b-1-th forward scan output node under the control of the b-th forward scan start control signal provided by the b-th forward scan start control terminal;

[0260] The b-th input terminal is the input terminal of the b-th stage drive circuit in the N-stage drive circuit.

[0261] When the driving module described in at least one embodiment of this disclosure is in operation, in global display mode, during forward scanning,

[0262] When scanning starts from the b-th stage drive circuit, the b-1 control cutoff circuit, under the control of the b-th forward scan start control signal provided by the b-th forward scan start control terminal, controls the b-th input terminal to disconnect from the b-1 forward scan output node, thereby disconnecting the signal transmission path between the b-th stage drive circuit and the b-1 stage drive circuit.

[0263] As shown in Figure 16, based on at least one embodiment shown in Figure 15, the second-stage drive circuit GA2 includes a first control cutoff circuit 151.

[0264] The first control cutoff circuit 151 is electrically connected to the second forward scan start control terminal FS2, the second input terminal S2 and the first forward scan output node NT1 respectively, and is used to control the connection or disconnection between the second input terminal S2 and the first forward scan output node NT1 under the control of the second forward scan start control signal provided by the second forward scan start control terminal FS2.

[0265] The second input terminal S2 is the input terminal of the second-stage driving circuit GA2 in the N-stage driving circuit;

[0266] The third-stage drive circuit GA3 includes a second control cutoff circuit 152;

[0267] The second control cutoff circuit 152 is electrically connected to the third forward scan start control terminal FS3, the third input terminal S3, and the second forward scan output node NT2, respectively, and is used to control the connection or disconnection between the third input terminal S3 and the second forward scan output node NT2 under the control of the third forward scan start control signal provided by the third forward scan start control terminal FS3.

[0268] The third input terminal S3 is the input terminal of the third-stage drive circuit GA3 in the N-stage drive circuit.

[0269] At least one embodiment of the driving module shown in Figure 16 of this disclosure, during operation, in global display mode, during forward scanning,

[0270] When scanning begins from the second-stage drive circuit, TGZ21 and TGZ22 are turned on, controlling the connection between GI and S2. The first control cut-off circuit 151 controls the disconnection between S2 and NT1 to disconnect the signal transmission path between the second-stage drive circuit and the first-stage drive circuit.

[0271] When scanning begins from the third-stage drive circuit, TGZ31 and TGZ32 are turned on, connecting GI and S3. The second control cut-off circuit 152 controls S3 to disconnect from NT2, thus breaking the signal transmission path between the third-stage drive circuit and the second-stage drive circuit.

[0272] Optionally, the (b-1)th control cutoff circuit includes a (b-1)th control cutoff transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal;

[0273] The positive phase control terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th inverted forward scan start control terminal, the inverted phase control terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th forward scan start control terminal, the first terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th input terminal, and the second terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b-1)th forward scan output node.

[0274] As shown in Figure 17, based on at least one embodiment shown in Figure 16, the first control cutoff circuit includes a first control cutoff transmission gate TGA1; the scan control terminal includes a forward scan control terminal GSD_FW and a reverse scan control terminal GSD_BW;

[0275] The positive control terminal of the first control cutoff transmission gate TGA1 is electrically connected to the second inverted forward scan start control terminal NFS2, the inverted control terminal of the first control cutoff transmission gate TGA1 is electrically connected to the second forward scan start control terminal FS2, the first terminal of the first control cutoff transmission gate TGA1 is electrically connected to the second input terminal S2, and the second terminal of the first control cutoff transmission gate TGA1 is electrically connected to the first forward scan output node NT1.

[0276] The second control cutoff circuit includes the second control cutoff transmission gate TGA2;

[0277] The positive control terminal of the second control cutoff transmission gate TGA2 is electrically connected to the third inverted forward scan start control terminal NFS3, the inverted control terminal of the second control cutoff transmission gate TGA2 is electrically connected to the third forward scan start control terminal FS3, the first terminal of the second control cutoff transmission gate TGA2 is electrically connected to the third input terminal S3, and the second terminal of the second control cutoff transmission gate TGA2 is electrically connected to the second forward scan output node NT2.

[0278] Optionally, the (b-1)th stage drive circuit in the N-stage drive circuit may include the (b-1)th forward scan control transmission gate;

[0279] The positive phase control terminal of the (b-1)th forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the (b-1)th forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the (b-1)th forward scan control transmission gate is electrically connected to the (b-1)th cascaded output terminal, and the second terminal of the (b-1)th forward scan control transmission gate is electrically connected to the (b-1)th forward scan output node.

[0280] The (b-1)th cascaded output terminal is the cascaded output terminal of the (b-1)th stage drive circuit.

[0281] The drive module described in at least one embodiment of this disclosure may further include a first reverse scan input control circuit;

[0282] The first reverse scan input control circuit is electrically connected to the global input terminal, the first reverse scan start control terminal, the scan control terminal, and the Nth input terminal, respectively. It is used to perform reverse scanning in global display mode and, when scanning starts from the Nth level drive circuit in the Nth level drive circuit, control the connection between the global input terminal and the Nth input terminal under the control of the first reverse scan start control signal provided by the first reverse scan start control terminal; the Nth input terminal is the input terminal of the Nth level drive circuit in the Nth level drive circuit.

[0283] In a specific implementation, the driving module may further include a first reverse scan input control circuit. In the global display mode, when performing a reverse scan and starting the scan from the Nth level driving circuit in the Nth level driving circuit, the first reverse scan input control circuit controls the connection between the global input terminal and the Nth input terminal under the control of the first reverse scan start control signal.

[0284] As shown in Figure 18, based on at least one embodiment shown in Figure 17, the drive module described in at least one embodiment of this disclosure further includes a first reverse scan input control circuit 171;

[0285] The first reverse scan input control circuit 171 is electrically connected to the global input terminal GI, the first reverse scan start control terminal BS1, the scan control terminal GSD, and the Nth input terminal SN, respectively. It is used to perform reverse scanning in global display mode and, when scanning starts from the Nth level drive circuit GAN in the N-level drive circuit, control the connection between the global input terminal GI and the Nth input terminal SN under the control of the first reverse scan start control signal provided by the first reverse scan start control terminal BS1. The Nth input terminal SN is the input terminal of the Nth level drive circuit GAN in the N-level drive circuit.

[0286] Optionally, the first backscan input control circuit includes a first backscan input control transmission gate and a second backscan input control transmission gate;

[0287] The positive control terminal of the first backscan input control transmission gate is electrically connected to the first backscan start control terminal, the negative control terminal of the first backscan input control transmission gate is electrically connected to the first negative backscan start control terminal, the first terminal of the first backscan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the first backscan input control transmission gate is electrically connected to the first terminal of the second backscan input control transmission gate.

[0288] The positive control terminal of the second first reverse scan input control transmission gate is electrically connected to the reverse scan control terminal, the negative control terminal of the second first reverse scan input control transmission gate is electrically connected to the positive scan control terminal, and the second terminal of the second first reverse scan input control transmission gate is electrically connected to the Nth input terminal.

[0289] As shown in Figure 19, based on at least one embodiment shown in Figure 18,

[0290] The first backscan input control circuit includes a first backscan input control transmission gate TGI11 and a second backscan input control transmission gate TGI21;

[0291] The positive control terminal of the first backscan input control transmission gate TGI11 is electrically connected to the first backscan start control terminal BS1, the inverting control terminal of the first backscan input control transmission gate TGI11 is electrically connected to the first inverting backscan start control terminal NBS1, the first terminal of the first backscan input control transmission gate TGI11 is electrically connected to the global input terminal GI, and the second terminal of the first backscan input control transmission gate TGI11 is electrically connected to the first terminal of the second backscan input control transmission gate TGI21.

[0292] The positive control terminal of the second first reverse scan input control transmission gate TGI21 is electrically connected to the reverse scan control terminal GSD_BW, the inverting control terminal of the second first reverse scan input control transmission gate TGI21 is electrically connected to the positive scan control terminal GSD_FW, and the second terminal of the second first reverse scan input control transmission gate TGI21 is electrically connected to the Nth input terminal SN.

[0293] The driving module described in at least one embodiment of this disclosure further includes C reverse scan input control circuits; where C is a positive integer.

[0294] The (c+1)th backscan input control circuit is electrically connected to the global input terminal, the (c+1)th backscan start control terminal, and the Ncth backscan input node, respectively. It is used to perform reverse scanning in global display mode and control the connection between the global input terminal and the Ncth backscan input node when scanning starts from the Ncth level driving circuit in the Nth level driving circuit; c is a positive integer less than or equal to C.

[0295] In at least one embodiment of this disclosure, C equals 2 as an example.

[0296] As shown in FIG20, based on at least one embodiment shown in FIG19, the driving module of at least one embodiment of the present disclosure further includes a second backscan input control circuit 172 and a third backscan input control circuit 173;

[0297] The second reverse scan input control circuit 172 is electrically connected to the global input terminal GI, the second reverse scan start control terminal BS2, and the (N-1)th reverse scan input node NIN-1, respectively. It is used to perform reverse scanning in global display mode and control the connection between the global input terminal GI and the (N-1)th reverse scan input node NIN-1 when scanning starts from the (N-1)th drive circuit GAN-1 in the N-level drive circuit.

[0298] The third reverse scan input control circuit 173 is electrically connected to the global input terminal GI, the third reverse scan start control terminal BS3, and the (N-2)th reverse scan input node NIN-2, respectively. It is used to perform reverse scanning in global display mode and control the connection between the global input terminal GI and the (N-2)th reverse scan input node NIN-2 when scanning starts from the (N-2)th drive circuit GAN-2 in the N-level drive circuit.

[0299] Optionally, the (c+1)th backscan input control circuit includes the (c+1)th backscan input control transmission gate;

[0300] The positive control terminal of the (c+1)th backscan input control transmission gate is electrically connected to the (c+1)th backscan start control terminal, the negative control terminal of the (c+1)th backscan input control transmission gate is electrically connected to the (c+1)th negative backscan start control terminal, the first terminal of the (c+1)th backscan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the (c+1)th backscan input control transmission gate is electrically connected to the Ncth backscan input node.

[0301] The driving module described in at least one embodiment of this disclosure further includes C cutoff circuits;

[0302] The c-th cutoff circuit is electrically connected to the c+1-th backscan start control terminal, the N-c+1-th cascaded output terminal, and the Nc-th backscan input node, respectively, and is used to control the connection or disconnection between the Nc-th backscan input node and the N-c+1-th cascaded output terminal under the control of the c+1-th backscan start control signal provided by the c+1-th backscan start control terminal.

[0303] In a specific implementation, the drive module may include C cutoff circuits. The c-th cutoff circuit, under the control of the c+1-th backscan start control signal, controls the connection or disconnection between the Nc-th backscan input node and the N-c+1-th cascaded output terminal.

[0304] When the driving module described in at least one embodiment of this disclosure is in operation, in global mode, during reverse scanning,

[0305] When scanning begins from the Nc-th stage driver circuit, the c-th cutoff circuit, under the control of the c+1-th reverse scan start control signal, controls the Nc-th reverse scan input node to disconnect from the N-c+1-th cascaded output terminal, thereby disconnecting the signal transmission path between the N-c+1-th stage driver circuit and the Nc-th stage driver circuit.

[0306] As shown in Figure 21, based on at least one embodiment shown in Figure 20, the driving module described in at least one embodiment of this disclosure may further include a first cutoff circuit 201 and a second cutoff circuit 202.

[0307] The first cutoff circuit 201 is electrically connected to the second backscan start control terminal BS2, the Nth cascade output terminal CTN, and the (N-1)th backscan input node NIN-1, respectively, and is used to control the connection or disconnection between the (N-1)th backscan input node NIN-1 and the Nth cascade output terminal CTN under the control of the second backscan start control signal provided by the second backscan start control terminal BS2.

[0308] The second cutoff circuit 202 is electrically connected to the third backscan start control terminal BS3, the N-1th cascade output terminal CTN-1, and the N-2th backscan input node NIN-2, respectively. It is used to control the connection or disconnection between the N-2th backscan input node NIN-2 and the N-1th cascade output terminal CTN-1 under the control of the third backscan start control signal provided by the third backscan start control terminal BS3.

[0309] At least one embodiment of the driving module shown in Figure 21 of this disclosure, during operation, in global display mode, during reverse scanning,

[0310] When scanning starts from the (N-1)th stage drive circuit, the first cutoff circuit 201, under the control of the second reverse scan start control signal, controls the connection between the (N-1)th reverse scan input node NIN-1 and the Nth cascade output terminal CTN to disconnect the signal transmission path between the (N-1)th stage drive circuit and the Nth stage drive circuit.

[0311] When scanning starts from the N-2 stage drive circuit, the second cutoff circuit 202, under the control of the third reverse scan start control signal, controls the connection between the N-2 stage reverse scan input node NIN-2 and the N-1 stage cascade output terminal CTN-1 to disconnect the signal transmission path between the N-2 stage drive circuit and the N-1 stage drive circuit.

[0312] Optionally, the c-th cutoff circuit includes a c-th cutoff transmission gate;

[0313] The positive phase control terminal of the c-th cutoff transmission gate is electrically connected to the (c+1)-th reverse sweep start control terminal, the inverting phase control terminal of the c-th cutoff transmission gate is electrically connected to the (c+1)-th reverse sweep start control terminal, the first terminal of the c-th cutoff transmission gate is electrically connected to the Nc-th reverse sweep input node, and the second terminal of the c-th cutoff transmission gate is electrically connected to the N-c+1-th cascaded output terminal.

[0314] As shown in Figure 22, based on at least one embodiment shown in Figure 21, the first cutoff circuit includes a first cutoff transmission gate TGC1;

[0315] The positive phase control terminal of the first cutoff transmission gate TGC1 is electrically connected to the second reverse scan start control terminal NBS2, the inverting phase control terminal of the first cutoff transmission gate TGC1 is electrically connected to the second reverse scan start control terminal BS2, the first terminal of the first cutoff transmission gate TGC1 is electrically connected to the (N-1)th reverse scan input node NIN-1, and the second terminal of the first cutoff transmission gate TGC1 is electrically connected to the Nth cascaded output terminal CTN.

[0316] The positive phase control terminal of the second cutoff transmission gate TGC2 is electrically connected to the third reverse scan start control terminal NBS3. The inverting phase control terminal of the second cutoff transmission gate TGC2 is electrically connected to the third reverse scan start control terminal BS3. The first terminal of the second cutoff transmission gate TGC2 is electrically connected to the (N-2)th reverse scan input node NIN-2. The second terminal of the second cutoff transmission gate TGC2 is electrically connected to the (N-1)th cascaded output terminal CTN-1.

[0317] Figure 23A is a circuit diagram of the first three stages of drive circuits included in the drive module according to at least one embodiment of the present disclosure.

[0318] In Figure 23A, the first-stage driving circuit includes a first-stage D flip-flop DFF1, a first AND gate AD1, a first inverter F1, a first forward scan control transmission gate TGF1, and a first reverse scan control transmission gate TGB1.

[0319] The input terminal of DFF1 is electrically connected to the first input terminal S1, the first output terminal of DFF1 is electrically connected to the first cascaded output terminal CT1, and the second output terminal of DFF1 is electrically connected to the first output terminal OT1.

[0320] The control terminal of DFF1 is electrically connected to the first clock signal terminal CLK1;

[0321] The first input terminal of AD1 is electrically connected to OT1, the second input terminal of AD1 is electrically connected to CT1, and the output terminal of AD1 is electrically connected to the first drive signal output terminal G1.

[0322] The input terminal of F1 is electrically connected to G1, and the output terminal of F1 is electrically connected to the first inverting drive signal output terminal GF1.

[0323] The positive phase control terminal of TGB1 is electrically connected to GSD_BW, the negative phase control terminal of TGB1 is electrically connected to GSD_FW, the first terminal of TGB1 is electrically connected to S1, and the second terminal of TGB1 is electrically connected to the second cascade output terminal CT2.

[0324] The positive phase control terminal of TGF1 is electrically connected to GSD_FW, the negative phase control terminal of TGF1 is electrically connected to GSD_BW, the first terminal of TGF1 is electrically connected to CT1, and the second terminal of TGF1 is electrically connected to the first positive scan output node NT1.

[0325] The positive phase control terminal of TGA1 is electrically connected to NFS2, the negative phase control terminal of TGA1 is electrically connected to FS2, the first terminal of TGA1 is electrically connected to the second input terminal S2, and the second terminal of TGA1 is electrically connected to the first forward scan output node NT1.

[0326] The second-stage driving circuit includes a second-stage D flip-flop DFF2, a second AND gate AD2, a second inverter F2, a second forward scan control transmission gate TGF2, and a second reverse scan control transmission gate TGB2;

[0327] The input terminal of DFF2 is electrically connected to the second input terminal S2, the first output terminal of DFF2 is electrically connected to the second cascaded output terminal CT2, and the second output terminal of DFF2 is electrically connected to the second output terminal OT2.

[0328] The control terminal of DFF2 is electrically connected to the second clock signal terminal CLK2;

[0329] The first input terminal of AD2 is electrically connected to OT2, the second input terminal of AD2 is electrically connected to CT2, and the output terminal of AD2 is electrically connected to the second drive signal output terminal G2.

[0330] The input terminal of F2 is electrically connected to G2, and the output terminal of F2 is electrically connected to the second inverting drive signal output terminal GF2.

[0331] The positive phase control terminal of TGB2 is electrically connected to GSD_BW, the negative phase control terminal of TGB2 is electrically connected to GSD_FW, the first terminal of TGB2 is electrically connected to S2, and the second terminal of TGB2 is electrically connected to the third cascade output terminal CT3.

[0332] The positive phase control terminal of TGF2 is electrically connected to GSD_FW, the negative phase control terminal of TGF2 is electrically connected to GSD_BW, the first terminal of TGF2 is electrically connected to CT2, and the second terminal of TGF2 is electrically connected to the second positive scan output node NT2.

[0333] The positive phase control terminal of TGA2 is electrically connected to NFS3, the negative phase control terminal of TGA2 is electrically connected to FS3, the first terminal of TGA2 is electrically connected to the third input terminal S3, and the second terminal of TGA2 is electrically connected to the second forward scan output node NT2.

[0334] The third-stage drive circuit includes a third-stage D flip-flop DFF3, a third AND gate AD3, a third inverter F3, a third forward scan control transmission gate TGF3, and a third reverse scan control transmission gate TGB3;

[0335] The input terminal of DFF3 is electrically connected to the third input terminal S3, the first output terminal of DFF3 is electrically connected to the third cascaded output terminal CT3, and the second output terminal of DFF3 is electrically connected to the third output terminal OT3.

[0336] The control terminal of DFF3 is electrically connected to the third clock signal terminal CLK3;

[0337] The first input terminal of AD3 is electrically connected to OT3, the second input terminal of AD3 is electrically connected to CT3, and the output terminal of AD3 is electrically connected to the third drive signal output terminal G3.

[0338] The input terminal of F3 is electrically connected to G3, and the output terminal of F3 is electrically connected to the third inverting drive signal output terminal GF3.

[0339] The positive phase control terminal of TGB3 is electrically connected to GSD_BW, the negative phase control terminal of TGB3 is electrically connected to GSD_FW, the first terminal of TGB3 is electrically connected to S3, and the second terminal of TGB3 is electrically connected to the fourth cascade output terminal CT4.

[0340] The positive control terminal of TGF3 is electrically connected to GSD_FW, the inverting control terminal of TGF3 is electrically connected to GSD_BW, the first terminal of TGF3 is electrically connected to CT3, and the second terminal of TGF3 is electrically connected to the fourth input terminal S4.

[0341] As shown in Figure 23B, based on at least one embodiment shown in Figure 23A, the driving module of at least one embodiment of this disclosure further includes a fourth-level driving circuit;

[0342] The fourth-stage drive circuit includes a fourth-stage D flip-flop DFF4, a fourth AND gate AD4, a fourth inverter F4, a fourth forward scan control transmission gate TGF4, and a fourth reverse scan control transmission gate TGB4;

[0343] The input terminal of DFF4 is electrically connected to the fourth input terminal S4, the first output terminal of DFF4 is electrically connected to the fourth cascaded output terminal CT4, and the second output terminal of DFF4 is electrically connected to the fourth output terminal OT4.

[0344] The control terminal of DFF4 is electrically connected to the fourth clock signal terminal CLK4.

[0345] The first input terminal of AD4 is electrically connected to OT4, the second input terminal of AD4 is electrically connected to CT4, and the output terminal of AD4 is electrically connected to the fourth drive signal output terminal G4.

[0346] The input terminal of F4 is electrically connected to G4, and the output terminal of F4 is electrically connected to the fourth inverting drive signal output terminal GF4.

[0347] The positive phase control terminal of TGB4 is electrically connected to GSD_BW, the negative phase control terminal of TGB4 is electrically connected to GSD_FW, the first terminal of TGB4 is electrically connected to S4, and the second terminal of TGB4 is electrically connected to the second start node NS2.

[0348] The positive phase control terminal of TGF4 is electrically connected to GSD_FW, the negative phase control terminal of TGF4 is electrically connected to GSD_BW, the first terminal of TGF4 is electrically connected to CT4, and the second terminal of TGF4 is electrically connected to the first start node NS1.

[0349] As shown in Figure 23C, m can be equal to 5 and n can be equal to 8. That is, the fifth-level driving circuit is the starting-level driving circuit, the eighth-level driving circuit is the cutting-off-level driving circuit, and the local display area corresponds to the fifth-level driving circuit to the eighth-level driving circuit.

[0350] As shown in Figure 23C, the m-th stage drive circuit may include TGS1, TGS2, DFFm, TGBm and TGFm;

[0351] NTm is electrically connected to the (m+1)th input terminal Sm+1, and NIm is electrically connected to the (m+1)th cascaded output terminal CTm+1.

[0352] The (m+1)th stage drive circuit may include the (m+1)th stage D flip-flop DFFm+1, the (m+1)th stage AND gate ADm+1, the (m+1)th stage inverter Fm+1, the (m+1)th stage forward scan control transmission gate TGFm+1, and the (m+1)th stage reverse scan control transmission gate TGBm+1;

[0353] The input terminal of DFFm+1 is electrically connected to the (m+1)th input terminal Sm+1, the control terminal of DFFm+1 is electrically connected to the (m+1)th clock signal terminal CLKm+1, the first output terminal of DFFm+1 is electrically connected to the (m+1)th cascaded output terminal CTm+1, and the second output terminal of DFFm+1 is electrically connected to the (m+1)th output terminal OTm+1.

[0354] The first input terminal of ADm+1 is electrically connected to OTm+1, the second input terminal of ADm+1 is electrically connected to CTm+1, and the output terminal of ADm+1 is electrically connected to the (m+1)th drive signal output terminal Gm+1.

[0355] The input terminal of Fm+1 is electrically connected to Gm+1, and the output terminal of Fm+1 is electrically connected to the (m+1)th inverted drive signal output terminal GFm+1.

[0356] The positive phase control terminal of TGFm+1 is electrically connected to GSD_FW, the negative phase control terminal of TGFm+1 is electrically connected to GSD_BW, the first terminal of TGFm+1 is electrically connected to CTm+1, and the second terminal of TGFm+1 is electrically connected to the (m+2)th input terminal Sm+2.

[0357] The positive phase control terminal of TGBm+1 is electrically connected to GSD_BW, the negative phase control terminal of TGBm+1 is electrically connected to GSD_FW, the first terminal of TGBm+1 is electrically connected to Sm+1, and the second terminal of TGBm+1 is electrically connected to the (m+2)th cascaded output terminal CTm+2.

[0358] The (m+2)th stage drive circuit may include the (m+2)th stage D flip-flop DFFm+2, the (m+2)th stage AND gate ADm+2, the (m+2)th stage inverter Fm+2, the (m+2)th stage forward scan control transmission gate TGFm+2, and the (m+2)th stage reverse scan control transmission gate TGBm+2;

[0359] The input terminal of DFFm+2 is electrically connected to the (m+2)th input terminal Sm+2, the control terminal of DFFm+2 is electrically connected to the (m+2)th clock signal terminal CLKm+2, the first output terminal of DFFm+2 is electrically connected to the (m+2)th cascaded output terminal CTm+2, and the second output terminal of DFFm+2 is electrically connected to the (m+2)th output terminal OTm+2.

[0360] The first input terminal of ADm+2 is electrically connected to OTm+2, the second input terminal of ADm+2 is electrically connected to CTm+2, and the output terminal of ADm+2 is electrically connected to the (m+2)th drive signal output terminal Gm+2.

[0361] The input terminal of Fm+2 is electrically connected to Gm+2, and the output terminal of Fm+2 is electrically connected to the (m+2)th inverted drive signal output terminal GFm+2.

[0362] The positive phase control terminal of TGFm+2 is electrically connected to GSD_FW, the negative phase control terminal of TGFm+2 is electrically connected to GSD_BW, the first terminal of TGFm+2 is electrically connected to CTm+2, and the second terminal of TGFm+2 is electrically connected to the nth input terminal Sn.

[0363] The positive phase control terminal of TGBm+2 is electrically connected to GSD_BW, the negative phase control terminal of TGBm+2 is electrically connected to GSD_FW, the first terminal of TGBm+2 is electrically connected to Sm+2, and the second terminal of TGBm+2 is electrically connected to the nth cascade output terminal CTn.

[0364] The nth stage drive circuit includes DFFn, And, Fn, TGBn, TGFn, TGJ1, and TGJ2.

[0365] In at least one embodiment shown in Figures 23C and 23D, NJ1 is electrically connected to the (N-3)th cascaded output terminal CTN-3, and NJ2 is electrically connected to the (N-3)th input terminal SN-3.

[0366] N-3 equals n+1, meaning N can be equal to 12.

[0367] As shown in Figure 23D, the drive module described in at least one embodiment of this disclosure may include a second backscan input control circuit and a third backscan input control circuit;

[0368] The second backscan input control circuit includes a second backscan input control transmission gate TGI2, and the third backscan input control circuit includes a third backscan input control transmission gate TGI3.

[0369] The positive phase control terminal of TGI2 is electrically connected to the second reverse scan start control terminal BS2, the negative phase control terminal of TGI2 is electrically connected to the second reverse scan start control terminal NBS2, the first terminal of TGI2 is electrically connected to the global input terminal GI, and the second terminal of TGI2 is electrically connected to the (N-1)th reverse scan input node NIN-1.

[0370] The positive phase control terminal of TGI3 is electrically connected to the third reverse scan start control terminal BS3, the negative phase control terminal of TGI3 is electrically connected to the third reverse scan start control terminal NBS3, the first terminal of TGI3 is electrically connected to the global input terminal GI, and the second terminal of TGI3 is electrically connected to the (N-2)th reverse scan input node NIN-2.

[0371] The (N-3)th stage drive circuit may include the (N-3)th stage D flip-flop DFFN-3, the (N-3)th stage AND gate ADN-3, the (N-3)th stage inverter FN-3, the (N-3)th stage forward scan control transmission gate TGFN-3, and the (N-3)th stage reverse scan control transmission gate TGBN-3;

[0372] The input terminal of DFFN-3 is electrically connected to the (N-3)th input terminal SN-3, the first output terminal of DFFN-3 is electrically connected to the (N-3)th cascaded output terminal CTN-3, and the second output terminal of DFFN-3 is electrically connected to the (N-3)th output terminal OTN-3.

[0373] The control terminal of DFFN-3 is electrically connected to the (N-3)th clock signal terminal CLKN-3;

[0374] The first input terminal of ADN-3 is electrically connected to OTN-3, the second input terminal of ADN-3 is electrically connected to CTN-3, and the output terminal of ADN-3 is electrically connected to the (N-3)th drive signal output terminal GN-3.

[0375] The input terminal of FN-3 is electrically connected to GN-3, and the output terminal of FN-3 is electrically connected to the (N-3)th inverting drive signal output terminal GFN-3.

[0376] The positive phase control terminal of TGBN-3 is electrically connected to GSD_BW, the negative phase control terminal of TGBN-3 is electrically connected to GSD_FW, the first terminal of TGBN-3 is electrically connected to SN-3, and the second terminal of TGBN-3 is electrically connected to the (N-2)th cascaded output terminal CTN-2.

[0377] The positive phase control terminal of TGFN-3 is electrically connected to GSD_FW, the negative phase control terminal of TGFN-3 is electrically connected to GSD_BW, the first terminal of TGFN-3 is electrically connected to CTN-3, and the second terminal of TGFN-3 is electrically connected to the (N-2)th input terminal SN-2.

[0378] The (N-2)th stage drive circuit may include the (N-2)th stage D flip-flop DFFN-2, the (N-2)th stage AND gate ADN-2, the (N-2)th stage inverter FN-2, the (N-2)th stage forward scan control transmission gate TGFN-2, and the (N-2)th stage reverse scan control transmission gate TGBN-2;

[0379] The input terminal of DFFN-2 is electrically connected to the (N-2)th input terminal SN-2, the first output terminal of DFFN-2 is electrically connected to the (N-2)th cascaded output terminal CTN-2, and the second output terminal of DFFN-2 is electrically connected to the (N-2)th output terminal OTN-2.

[0380] The control terminal of DFFN-2 is electrically connected to the (N-2)th clock signal terminal CLKN-2;

[0381] The first input terminal of ADN-2 is electrically connected to OTN-2, the second input terminal of ADN-2 is electrically connected to CTN-2, and the output terminal of ADN-2 is electrically connected to the (N-2)th drive signal output terminal GN-2.

[0382] The input terminal of FN-2 is electrically connected to GN-2, and the output terminal of FN-2 is electrically connected to the (N-2)th inverting drive signal output terminal GFN-2.

[0383] The positive phase control terminal of TGBN-2 is electrically connected to GSD_BW, the negative phase control terminal of TGBN-2 is electrically connected to GSD_FW, the first terminal of TGBN-2 is electrically connected to SN-2, and the second terminal of TGBN-2 is electrically connected to NIN-2.

[0384] The positive phase control terminal of TGFN-2 is electrically connected to GSD_FW, the negative phase control terminal of TGFN-2 is electrically connected to GSD_BW, the first terminal of TGFN-2 is electrically connected to CTN-2, and the second terminal of TGFN-2 is electrically connected to the (N-1)th input terminal SN-1.

[0385] The driving module described in at least one embodiment of this disclosure may include a first cutoff transmission gate TGC1 and a second cutoff transmission gate TGC2;

[0386] The positive phase control terminal of TGC2 is electrically connected to GSD_BW, the negative phase control terminal of TGC2 is electrically connected to GSD_FW, the first terminal of TGC2 is electrically connected to the (N-2)th reverse scan input node NIN-2, and the second terminal of TGC2 is electrically connected to the (N-1)th cascaded output terminal CTN-1.

[0387] The (N-1)th stage drive circuit may include the (N-1)th stage D flip-flop DFFN-1, the (N-1)th stage AND gate ADN-1, the (N-1)th stage inverter FN-1, the (N-1)th stage forward scan control transmission gate TGFN-1, and the (N-1)th stage reverse scan control transmission gate TGBN-1;

[0388] The input terminal of DFFN-1 is electrically connected to the (N-1)th input terminal SN-1, the first output terminal of DFFN-1 is electrically connected to the (N-1)th cascaded output terminal CTN-1, and the second output terminal of DFFN-1 is electrically connected to the (N-1)th output terminal OTN-1.

[0389] The control terminal of DFFN-1 is electrically connected to the (N-1)th clock signal terminal CLKN-1;

[0390] The first input terminal of ADN-1 is electrically connected to OTN-1, the second input terminal of ADN-1 is electrically connected to CTN-1, and the output terminal of ADN-1 is electrically connected to the (N-1)th drive signal output terminal GN-1.

[0391] The input terminal of FN-1 is electrically connected to GN-1, and the output terminal of FN-1 is electrically connected to the (N-1)th inverting drive signal output terminal GFN-1.

[0392] The positive phase control terminal of TGBN-1 is electrically connected to GSD_BW, the negative phase control terminal of TGBN-1 is electrically connected to GSD_FW, the first terminal of TGBN-1 is electrically connected to SN-1, and the second terminal of TGBN-1 is electrically connected to NIN-1.

[0393] The non-inverting control terminal of TGFN-1 is electrically connected to GSD_FW, the inverting control terminal of TGFN-1 is electrically connected to GSD_BW, the first terminal of TGFN-1 is electrically connected to CTN-1, and the second terminal of TGFN-1 is electrically connected to the Nth input terminal SN.

[0394] The positive phase control terminal of TGC1 is electrically connected to GSD_BW, the negative phase control terminal of TGC1 is electrically connected to GSD_FW, the first terminal of TGC1 is electrically connected to the (N-1)th reverse scan input node NIN-1, and the second terminal of TGC1 is electrically connected to the Nth cascaded output terminal CTN.

[0395] The drive module described in at least one embodiment of this disclosure further includes a first first backscan input control transmission gate TGI11 and a second first backscan input control transmission gate TGI21;

[0396] The Nth stage drive circuit includes the Nth stage D flip-flop DFFN, the Nth AND gate ADN, and the Nth inverter FN;

[0397] The input terminal of the DFFN is electrically connected to the Nth input terminal SN, the first output terminal of the DFFN is electrically connected to the Nth cascaded output terminal CTN, and the second output terminal of the DFFN is electrically connected to the Nth output terminal OTN.

[0398] The control terminal of DFFN is electrically connected to the Nth clock signal terminal CLKN;

[0399] The first input terminal of ADN is electrically connected to OTN, the second input terminal of ADN is electrically connected to CTN, and the output terminal of ADN is electrically connected to the Nth drive signal output terminal GN.

[0400] The input terminal of FN is electrically connected to GN, and the output terminal of FN is electrically connected to the output terminal of the Nth inverting drive signal GFN.

[0401] Figure 24A is the circuit diagram of the first part B1 in Figure 23B, and Figure 24B is the circuit diagram of the second part B2 in Figure 23B.

[0402] Figure 24C is the circuit diagram of the third part B3 in Figure 23C, and Figure 24D is the circuit diagram of the fourth part B4 in Figure 23C.

[0403] Figure 24E is the circuit diagram of the fifth part B5 in Figure 23D, and Figure 24F is the circuit diagram of the sixth part B6 in Figure 23D.

[0404] In at least one embodiment of this disclosure, the driving module is also compatible with forward scanning and reverse scanning functions. The implementation of forward and reverse scanning functions requires the use of GSD_FW and GSD_BW.

[0405] When GSD_FW provides a high voltage signal and GSD_BW provides a low voltage signal, a forward scan is performed;

[0406] When GSD_BW provides a high voltage signal and GSD_FW provides a low voltage signal, a reverse scan is performed.

[0407] At least one embodiment of the driving module shown in Figures 23A-23D of this disclosure, when in operation, in partial display mode

[0408] EN_PART provides a high voltage signal, EN_PART' provides a low voltage signal, TGP is turned on, STV and PI are connected, STV provides the starting voltage to PI, TCQ is turned off, and STV and GI are disconnected.

[0409] During forward scanning, GSD_FW provides a high voltage signal, GSD_BW provides a low voltage signal, TG1 is turned on, connecting PI and Sm, and writing the starting voltage to Sm; TG2 is turned off, disconnecting PI and Sn; TGS1 and TGS2 are turned off, disconnecting Sm and NS1, and disconnecting CTm and NS2; thus disconnecting the signal transmission path between the nth stage drive circuit and the (n-1)th stage drive circuit; TGFm is turned on, controlling the connection between CTm and Sm+1; TGBm is turned off, S... Disconnect between m and NIm; TGBm+1 is off, disconnect between Sm+1 and CTm+2; TGFm+1 is on, connect CTm+1 and Sm+2; TGBm+2 is off, disconnect between Sm+2 and CTn; TGFm+2 is on, connect CTm+2 and Sn; TGJ1 and TGJ2 are off, disconnect CTn and NJ1, disconnect Sn and TGJ2, thus disconnecting the signal transmission path between the nth stage drive circuit and the (n+1)th stage drive circuit;

[0410] During reverse scanning, GSD_BW provides a high voltage signal, GSD_FW provides a low voltage signal, TG2 is turned on, and PI and Sn are connected; TGJ1 is turned off, controlling CTn and NJ1 to disconnect, TGJ2 is turned off, controlling Sn and NJ2 to disconnect, thus disconnecting the signal transmission path between the nth stage drive circuit and the (n+1)th stage drive circuit; TGBm+2 is turned on, TGFm+2 is turned off, CTn and Sm+2 are connected, and Sn and CTm+2 are disconnected; TGBm+1 is turned on, TGFm+1 is turned off, CTm+2 and Sm+1 are connected, and Sm+2 and CTm+1 are disconnected; TGBm is turned on, TGFm is turned off, CTm+1 and Sm are connected, and Sm+1 and CTm are disconnected; TGS1 and TGS2 are turned off, Sm and NS1 are disconnected, and CTm and NS2 are disconnected, thus disconnecting the signal transmission path between the nth stage drive circuit and the (n-1)th stage drive circuit.

[0411] At least one embodiment of the driving module shown in Figures 23A-23D of this disclosure, when in operation, in global display mode

[0412] EN_PART provides a low voltage signal, EN_PART' provides a high voltage signal, TGQ is turned on, STV and GI are connected, and the starting voltage provided by STV is written to GI;

[0413] During forward scanning, scanning can be initiated by the first-stage drive circuit, the second-stage drive circuit, or the third-stage drive circuit through FS1, NFS1, FS2, NFS2, FS3, and NFS3.

[0414] When FS1 provides a high voltage signal, NFS1 provides a low voltage signal, FS2 and FS3 provide low voltage signals, and NFS2 and NFS3 provide high voltage signals, TGZ11 is turned on, TGZ21 is turned off, TGZ31 is turned off, and GI is connected to TGZ12; when GSD_FW provides a high voltage signal and GSW_BW provides a low voltage signal, TGZ12 is turned on, and GI is connected to S1, writing the starting voltage to S1; when TGB1 is turned off, S1 is disconnected from CT2; when TGF1 is turned on, CT1 is connected to NT1; when TGA1 is turned on, it controls the connection between NT1 and S2. Turn on to control the connection between CT1 and S2; turn off TGZ21 and TGZ22, disconnect GI from S2, turn off TGB2, disconnect S2 from CT3, turn on TGF2, connect CT2 and NT2, turn on TGA2, control the connection between NT2 and S3, and control the connection between CT2 and S3; turn off TGZ31 and TGZ32, disconnect GI from S3, turn off TGB3, disconnect S3 from CT4, turn on TGF3, connect CT3 and S4, turn off TGB4, turn on TGF4, control the connection between CT4 and NS1, and control the disconnect between S4 and NS2.

[0415] When FS2 provides a high voltage signal, NFS2 provides a low voltage signal, FS1 and FS3 provide low voltage signals, and NFS1 and NFS3 provide high voltage signals, TGZ21 is turned on, TGZ11 is turned off, TGZ31 is turned off, and GI is connected to TGZ22; GSD_FW provides a high voltage signal, GSW_BW provides a low voltage signal, TGZ22 is turned on, and GI is connected to S2, writing the starting voltage to S2; TGA2 is turned off, controlling the disconnection between S2 and CT1; TGB2 is turned off, disconnecting S2 and CT3; TGF2 is turned on, connecting CT2 and NT2; TGA2 is turned on, controlling the connection between NT2 and S3, thereby controlling the connection between CT2 and S3; TGB3 is turned off, disconnecting S3 and CT4; TGF3 is turned on, connecting CT3 and S4; TGB4 is turned off, disconnecting S4 and NS2, turning on TGF4, and connecting CT4 and NS1.

[0416] When FS3 provides a high voltage signal, NFS3 provides a low voltage signal, FS1 and FS2 provide low voltage signals, and NFS1 and NFS2 provide high voltage signals, TGZ31 is turned on, TGZ11 is turned off, TGZ21 is turned off, and GI is connected to TGZ32; when GSD_FW provides a high voltage signal and GSW_BW provides a low voltage signal, TGZ32 is turned on, and GI is connected to S3, writing the starting voltage to S3; TGA2 is turned off, controlling the disconnection between S3 and CT2; TGB3 is turned off, controlling the disconnection between S3 and CT4; TGF3 is turned on, and CT3 is connected to S4; TGB4 is turned off, S4 is disconnected from NS2, TGF4 is turned on, and CT4 is connected to NS1.

[0417] At least one embodiment of the driving module shown in Figures 23A-23D of this disclosure, when in operation, in global display mode

[0418] EN_PART provides a low voltage signal, EN_PART' provides a high voltage signal, TGQ is turned on, STV and GI are connected, and the starting voltage provided by STV is written to GI;

[0419] During reverse scanning, scanning can be initiated by the Nth stage drive circuit, the (N-1)th stage drive circuit, or the Nth stage drive circuit through BS1, NBS1, BS2, NBS2, BS3, and NB3.

[0420] When BS1 provides a high voltage signal, NBS1 provides a low voltage signal, BS2 and BS3 provide low voltage signals, and NBS2 and NBS3 provide high voltage signals, TGI11 is turned on, connecting GI and TGI21; TGI2 and TGI3 are turned off, disconnecting GI from NIN-1 and NIN-2; TGI21 is turned on, connecting GI to SN to write the starting voltage to SN; TGFN-1 is turned off, TGC1 is turned on, TGBN-1 is turned on, connecting CTN to SN-1 and disconnecting SN from CTN-1; TGC2 is turned on, TGBN-2 is turned on, TGFN-2 is turned off, connecting CTN-1 to SN-2 and disconnecting SN from CTN-2; TGBN-3 is turned on, TGFN-3 is turned off, connecting CTN-2 to SN-3 and disconnecting SN from CTN-3.

[0421] When BS2 provides a high voltage signal, NBS2 provides a low voltage signal, BS1 and BS3 provide low voltage signals, and NBS1 and NBS3 provide high voltage signals, TGI11 and TGI21 are turned off, TGI3 is turned off, disconnecting control GI from SN and from NIN-2, turning TGI2 on, connecting control GI to NIN-1 to write the starting voltage into NIN-1; TGC1 is turned off, disconnecting control NIN-1 from CTN, breaking the signal transmission path between the (N-1)th stage drive circuit and the Nth stage drive circuit; TGFN- 1. Disconnects, controlling the disconnection between SN and CTN-1, turns TGBN-1 on, and connects NIN-1 and SN-1 to control the connection between CTN and SN-1; 2. Turns on TGC2, controlling the connection between CTN-1 and NIN-2, turns TGBN-2 on, and connects NIN-2 and SN-2 to control the connection between CTN-1 and SN-2; 3. Turns off TGFN-2, disconnecting SN-1 and CTN-2; 4. Turns on TGBN-3, turns off TGFN-3, connecting CTN-2 and SN-3, and disconnecting SN-2 and CTN-3.

[0422] When BS3 provides a high voltage signal, NBS3 provides a low voltage signal, BS1 and BS2 provide low voltage signals, and NBS1 and NBS2 provide high voltage signals, TGI11 and TGI12 are turned off, controlling the disconnection between GI and SN, and controlling the disconnection between GI and NIN-1. TGI3 is turned on, connecting GI and NIN-2 to write the starting voltage into NIN-2. TGC2 is turned off, controlling the disconnection between NIN-2 and CTN-1 to control the disconnection of the signal transmission path between the (N-2)th stage drive circuit and the (N-1)th stage drive circuit. TGBN-2 is turned on, connecting NIN-2 and SN-2 to control the connection between CTN-1 and SN-2. TGFN-2 is turned off, disconnecting SN-1 and CTN-2. TGBN-3 is turned on, TGFN-3 is turned off, connecting CTN-2 and SN-3, and disconnecting SN-2 and CTN-3.

[0423] The driving method described in at least one embodiment of this disclosure is applied to the above-mentioned driving module, and the driving method includes: in a partial display mode,

[0424] Under the control of the display mode control signal, the local display control circuit controls the connection between the starting voltage terminal and the local input terminal;

[0425] During forward scanning, the first scan control switch circuit, under the control of the scan control signal, controls the connection between the local input terminal and the m-th input terminal, where the m-th input terminal is the input terminal of the start-stage drive circuit.

[0426] During reverse scanning, the second scan control switch circuit, under the control of the scan control signal, controls the connection between the local input terminal and the nth input terminal; the nth input terminal is the input terminal of the cutoff stage drive circuit.

[0427] The display device described in this disclosure includes the driving module described above.

[0428] In at least one embodiment of this disclosure, the display device may be a One-Chip silicon-based microdisplay, but is not limited thereto.

[0429] The display device described in at least one embodiment of this disclosure can adopt a One-Chip mode, where the DDIC (Display Driver Integrated Circuit) and BP (Backplane) are both on the same IC (Integrated Circuit). The Si-BP (Driver Backplane) portion mainly consists of a pixel circuit array, a drive module, and a Source Driver. At least one embodiment of this disclosure provides a novel drive module, which is mainly implemented by digital circuits and provides control signals for the row drive of the pixel circuit array. The drive module described in at least one embodiment of this disclosure enables the function of partial screen display, that is, the light-emitting row drive signals output by the drive module can be directly transmitted to a local display area of ​​a specified resolution.

[0430] From a product performance perspective, high-resolution devices need to be compatible with low-resolution images and support users' ability to freely adjust resolution to adapt to different application scenarios. For high-resolution devices to be compatible with low-resolution images, directly displaying the actual size of the low-resolution image is the preferred option for maintaining clarity; that is, directly using the corresponding number of pixels to restore the original resolution of the image (displaying the image pixel-for-pixel), resulting in the image appearing only in a portion of the screen's center. Regarding user-adjustable resolution, different users have different display preferences for the same image / video. Providing greater flexibility enhances product competitiveness; for example, video playback could support both full-screen display and in-center display (cinema mode). Therefore, from a product performance perspective, the partial display technology provided in at least one embodiment of this disclosure not only improves the compatibility and versatility of the display product itself but also enhances the user experience.

[0431] In terms of power consumption advantages, the partial display scheme provided in at least one embodiment of this disclosure differs from related partial display schemes in that: traditional partial display schemes display non-partial display areas as black and the partial display area displays the target image; while in at least one embodiment of this disclosure, only the partial display area displays the target image, and the non-partial display areas are inactive. Therefore, compared with related partial display schemes, the driving module described in at least one embodiment of this disclosure has reduced power consumption and can be applied to resource-constrained small silicon-based OLED products.

[0432] Silicon-based OLED (Organic Light Emitting Diode) microdisplays are active-matrix organic light-emitting diode display devices fabricated using single-crystal silicon as the active driving backplane, combining CMOS (Complementary Metal Oxide Semiconductor) technology and OLED technology. Silicon-based OLED microdisplays offer advantages such as ultra-high resolution, high PPI (Pixels Per Inch), high contrast, high brightness, low power consumption, small size, and light weight, making them widely used in AR (Augmented Reality), VR (Virtual Reality), MR (Mixed Reality), EVF (Electronic Viewfinder), FPV (First Person View, a device based on a wireless camera mounted on a remote-controlled aircraft or vehicle model), drones, thermal imagers, night vision devices, infrared cameras, and medical equipment.

[0433] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A driving module, comprising N-stage driving circuits; N is an integer greater than 1; the m-th driving circuit in the N-stage driving circuit is a start-up driving circuit, the n-th driving circuit in the N-stage driving circuit is a cutoff driving circuit, m and n are positive integers; m is greater than 1, n is greater than m; the driving module further comprises a local display control circuit, a first scan control switch circuit, and a second scan control switch circuit; The local display control circuit is electrically connected to the display mode control terminal, the starting voltage terminal, and the local input terminal, and is used to control the connection between the starting voltage terminal and the local input terminal under the control of the display mode control signal provided by the display mode control terminal in the local display mode. The first scan control switch circuit is electrically connected to the scan control terminal, the local input terminal and the m-th input terminal respectively. It is used to control the connection between the local input terminal and the m-th input terminal under the control of the scan control signal provided by the scan control terminal in the local display mode during forward scanning. The m-th input terminal is the input terminal of the start-stage drive circuit. The second scan control switch circuit is electrically connected to the scan control terminal, the local input terminal, and the nth input terminal, respectively, and is used to control the connection between the local input terminal and the nth input terminal under the control of the scan control signal in the local display mode during reverse scanning; the nth input terminal is the input terminal of the cutoff stage drive circuit.

2. The drive module as described in claim 1, wherein, The local display control circuit includes a local display control transmission gate; the display mode control terminal includes a first display mode control terminal and a second display mode control terminal. The positive phase control terminal of the local display control transmission gate is electrically connected to the first display mode control terminal, the negative phase control terminal of the local display control transmission gate is electrically connected to the second display mode control terminal, the first terminal of the local display control transmission gate is electrically connected to the starting voltage terminal, and the second terminal of the local display control transmission gate is electrically connected to the local input terminal. The first scan control switch circuit includes a first scan control transmission gate, and the second scan control switch circuit includes a second scan control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal; The positive phase control terminal of the first scan control transmission gate is electrically connected to the positive scan control terminal, the negative phase control terminal of the first scan control transmission gate is electrically connected to the negative scan control terminal, the first terminal of the first scan control transmission gate is electrically connected to the local input terminal, and the second terminal of the first scan control transmission gate is electrically connected to the m-th input terminal. The positive control terminal of the second scan control transmission gate is electrically connected to the negative scan control terminal, the negative control terminal of the second scan control transmission gate is electrically connected to the positive scan control terminal, the first terminal of the second scan control transmission gate is electrically connected to the local input terminal, and the second terminal of the second scan control transmission gate is electrically connected to the nth input terminal.

3. The drive module as described in claim 1, wherein, The starting stage drive circuit includes an m-th stage drive signal generation circuit, a first starting switch circuit, and a second starting switch circuit. The m-th stage drive signal generation circuit is electrically connected to the m-th input terminal and the m-th cascaded output terminal respectively, and is used to generate and provide the m-th cascaded signal through the m-th cascaded output terminal based on the m-th input signal connected to the m-th input terminal. The first start switch circuit is electrically connected to the display mode control terminal, the m-th input terminal, and the first start node, respectively, and is used to control the connection or disconnection between the m-th input terminal and the first start node under the control of the display mode control signal provided by the display mode control terminal; The second start switch circuit is electrically connected to the display mode control terminal, the m-th cascade output terminal, and the second start node, respectively, and is used to control the connection or disconnection between the m-th cascade output terminal and the second start node under the control of the display mode control signal.

4. The drive module as described in claim 3, wherein, The first start switch circuit includes a first start switch transmission gate, the second start switch circuit includes a second start switch transmission gate, and the display mode control terminal includes a first display mode control terminal and a second display mode control terminal. The positive phase control terminal of the first start switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the first start switch transmission gate is electrically connected to the first display mode control terminal, the first end of the first start switch transmission gate is electrically connected to the m-th input terminal, and the second end of the first start switch transmission gate is electrically connected to the first start node. The positive phase control terminal of the second start switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the second start switch transmission gate is electrically connected to the first display mode control terminal, the first end of the second start switch transmission gate is electrically connected to the m-th cascade output terminal, and the second end of the second start switch transmission gate is electrically connected to the second start node.

5. The drive module as described in claim 3, wherein, The starting stage drive circuit also includes an m-th forward scan control circuit and an m-th reverse scan control circuit; The m-th forward scan control circuit is electrically connected to the scan control terminal, the m-th cascaded output terminal, and the m-th forward scan output node, respectively, and is used to control the connection between the m-th cascaded output terminal and the m-th forward scan output node under the control of the scan control signal during forward scanning. The m-th reverse scan control circuit is electrically connected to the scan control terminal, the m-th input terminal, and the m-th reverse scan input node, respectively, and is used to control the connection between the m-th input terminal and the m-th reverse scan input node under the control of the scan control signal during reverse scanning. The m-th level drive signal generation circuit is also electrically connected to the m-th drive signal output terminal, and is used to generate and provide the m-th drive signal through the m-th drive signal output terminal based on the m-th input signal.

6. The drive module as described in claim 5, wherein, The m-th forward scan control circuit includes the m-th forward scan control transmission gate, and the m-th reverse scan control circuit includes the m-th reverse scan control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal. The positive phase control terminal of the m-th forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the m-th forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the m-th forward scan control transmission gate is electrically connected to the m-th cascaded output terminal, and the second terminal of the m-th forward scan control transmission gate is electrically connected to the m-th forward scan output node. The positive phase control terminal of the m-th backscan control transmission gate is electrically connected to the backscan control terminal, the negative phase control terminal of the m-th backscan control transmission gate is electrically connected to the positive phase control terminal, the first terminal of the m-th backscan control transmission gate is electrically connected to the m-th input terminal, and the second terminal of the m-th backscan control transmission gate is electrically connected to the m-th backscan input node.

7. The drive module as described in claim 5, wherein, The m-th stage drive signal generation circuit includes an m-th stage D flip-flop and an m-th AND gate; The input terminal of the m-th stage D flip-flop is electrically connected to the m-th input terminal, the control terminal of the m-th stage D flip-flop is electrically connected to the first control clock signal terminal, the first output terminal of the m-th stage D flip-flop is electrically connected to the m-th cascaded output terminal, and the second output terminal of the m-th stage D flip-flop is electrically connected to the m-th output terminal. The first input terminal of the m-th AND gate is electrically connected to the m-th output terminal, the second input terminal of the m-th AND gate is electrically connected to the m-th cascaded output terminal, and the output terminal of the m-th AND gate is electrically connected to the m-th drive signal output terminal.

8. The drive module as described in claim 1, wherein, The cutoff stage driving circuit includes an nth stage driving signal generation circuit, an nth forward scan control circuit, an nth reverse scan control circuit, a first cutoff switch circuit, and a second cutoff switch circuit. The nth stage drive signal generation circuit is electrically connected to the nth input terminal and the nth cascade output terminal respectively, and is used to generate and provide the nth cascade signal through the nth cascade output terminal based on the nth input signal connected to the nth input terminal. The nth forward scan control circuit is electrically connected to the scan control terminal, the nth cascaded output terminal, and the nth forward scan output node, respectively, and is used to control the connection between the nth cascaded output terminal and the nth forward scan output node under the control of the scan control signal during forward scanning. The nth reverse scan control circuit is electrically connected to the scan control terminal, the nth input terminal, and the nth reverse scan input node, respectively, and is used to control the connection between the nth input terminal and the nth reverse scan input node under the control of the scan control signal during reverse scan. The first cutoff switch circuit is electrically connected to the display mode control terminal, the nth forward scan output node and the first cutoff node respectively, and is used to control the connection or disconnection between the nth forward scan output node and the first cutoff node under the control of the display mode control signal provided by the display mode control terminal; The second cutoff switch circuit is electrically connected to the display mode control terminal, the nth backscan input node, and the second cutoff node, respectively, and is used to control the connection or disconnection between the nth backscan input node and the second cutoff node under the control of the display mode control signal.

9. The drive module as described in claim 8, wherein, The nth forward scan control circuit includes an nth forward scan control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal; The positive phase control terminal of the nth forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the nth forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the nth forward scan control transmission gate is electrically connected to the nth cascaded output terminal, and the second terminal of the nth forward scan control transmission gate is electrically connected to the nth forward scan output node. The nth backscan control circuit includes an nth backscan control transmission gate; The positive phase control terminal of the nth backscan control transmission gate is electrically connected to the backscan control terminal, the negative phase control terminal of the nth backscan control transmission gate is electrically connected to the positive phase control terminal, the first terminal of the nth backscan control transmission gate is electrically connected to the nth input terminal, and the second terminal of the nth backscan control transmission gate is electrically connected to the nth backscan input node. The first cutoff switch circuit includes a first cutoff switch transmission gate; the display mode control terminal includes a first display mode control terminal and a second display mode control terminal. The positive phase control terminal of the first cutoff switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the first cutoff switch transmission gate is electrically connected to the first display mode control terminal, the first end of the first cutoff switch transmission gate is electrically connected to the nth positive scan output node, and the second end of the first cutoff switch transmission gate is electrically connected to the first cutoff node. The second cutoff switch circuit includes a second cutoff switch transmission gate; The positive phase control terminal of the second cut-off switch transmission gate is electrically connected to the second display mode control terminal, the negative phase control terminal of the second cut-off switch transmission gate is electrically connected to the first display mode control terminal, the first end of the second cut-off switch transmission gate is electrically connected to the nth reverse scan input node, and the second end of the second cut-off switch transmission gate is electrically connected to the second cut-off node.

10. The drive module as described in claim 8, wherein, The nth-level drive signal generation circuit is also electrically connected to the nth-level drive signal output terminal, and is used to generate and provide the nth-level drive signal through the nth-level drive signal output terminal based on the nth-level input signal.

11. The drive module as described in claim 10, wherein, The nth stage drive signal generation circuit includes an nth stage D flip-flop and an nth AND gate; The input terminals of the nth stage D flip-flop are electrically connected to the nth input terminal, the control terminal of the nth stage D flip-flop is electrically connected to the second control clock signal terminal, the first output terminal of the nth stage D flip-flop is electrically connected to the nth cascaded output terminal, and the second output terminal of the nth stage D flip-flop is electrically connected to the nth output terminal. The first input terminal of the nth AND gate is electrically connected to the mth output terminal, the second input terminal of the nth AND gate is electrically connected to the nth cascaded output terminal, and the output terminal of the nth AND gate is electrically connected to the nth drive signal output terminal.

12. The drive module as described in claim 1, wherein, It also includes a global display control circuit; The global display control circuit is electrically connected to the display mode control terminal, the starting voltage terminal, and the global input terminal, respectively, and is used to control the connection between the starting voltage terminal and the global input terminal under the control of the display mode control signal in the global display mode.

13. The drive module as described in claim 12, wherein, The global display control circuit includes a global display control transmission gate; the display mode control terminal includes a first display mode control terminal and a second display mode control terminal. The positive control terminal of the global display control transmission gate is electrically connected to the second display mode control terminal, the negative control terminal of the global display control transmission gate is electrically connected to the first display mode control terminal, the first terminal of the global display control transmission gate is electrically connected to the starting voltage terminal, and the second terminal of the global display control transmission gate is electrically connected to the global input terminal.

14. The drive module as described in claim 13, wherein, It also includes A forward scan input control circuits; A is a positive integer; The forward scan input control circuit is electrically connected to the global input terminal, the forward scan start control terminal, the scan control terminal, and the a input terminal, respectively. In global display mode, it performs a forward scan and, when scanning begins from the a-th stage drive circuit in the N-stage drive circuit, controls the connection between the global input terminal and the a input terminal under the control of the forward scan start control signal provided by the forward scan start control terminal and the scan control signal provided by the scan control terminal; the a input terminal is the input terminal of the a-th stage drive circuit. a is a positive integer less than or equal to A.

15. The drive module as described in claim 14, wherein, The a-th forward scan input control circuit includes an a-th first forward scan input control transmission gate and an a-th second forward scan input control transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal; The positive phase control terminal of the a-th first forward scan input control transmission gate is electrically connected to the a-th forward scan start control terminal, the negative phase control terminal of the a-th first forward scan input control transmission gate is electrically connected to the a-th negative phase forward scan start control terminal, the first terminal of the a-th first forward scan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the a-th first forward scan input control transmission gate is electrically connected to the first terminal of the a-th second forward scan input control transmission gate. The positive phase control terminal of the a-th second forward scan input control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the a-th second forward scan input control transmission gate is electrically connected to the reverse scan control terminal, and the second terminal of the a-th second forward scan input control transmission gate is electrically connected to the a-th input terminal.

16. The drive module as described in claim 15, wherein, A is greater than 1; The b-th stage drive circuit includes the (b-1)-th control cutoff circuit; b is an integer less than or equal to A and greater than 1; The b-1 control cutoff circuit is electrically connected to the b-th forward scan start control terminal, the b-th input terminal, and the b-1-th forward scan output node, respectively, and is used to control the connection or disconnection between the b-th input terminal and the b-1-th forward scan output node under the control of the b-th forward scan start control signal provided by the b-th forward scan start control terminal; The b-th input terminal is the input terminal of the b-th stage drive circuit in the N-stage drive circuit.

17. The drive module as claimed in claim 16, wherein, The b-1 control cutoff circuit includes the b-1 control cutoff transmission gate; the scan control terminal includes a forward scan control terminal and a reverse scan control terminal; The positive phase control terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th inverted forward scan start control terminal, the inverted phase control terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th forward scan start control terminal, the first terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b)th input terminal, and the second terminal of the (b-1)th control cutoff transmission gate is electrically connected to the (b-1)th forward scan output node.

18. The drive module as claimed in claim 16 or 17, wherein, The (b-1)th stage drive circuit in the Nth stage drive circuit includes the (b-1)th forward scan control transmission gate; The positive phase control terminal of the (b-1)th forward scan control transmission gate is electrically connected to the forward scan control terminal, the negative phase control terminal of the (b-1)th forward scan control transmission gate is electrically connected to the reverse scan control terminal, the first terminal of the (b-1)th forward scan control transmission gate is electrically connected to the (b-1)th cascade output terminal, and the second terminal of the (b-1)th forward scan control transmission gate is electrically connected to the (b-1)th forward scan output node; the (b-1)th cascade output terminal is the cascade output terminal of the (b-1)th stage drive circuit.

19. The drive module as described in claim 13, wherein, It also includes a first reverse scan input control circuit; The first reverse scan input control circuit is electrically connected to the global input terminal, the first reverse scan start control terminal, the scan control terminal, and the Nth input terminal, respectively. It is used to perform reverse scanning in global display mode and, when scanning starts from the Nth level drive circuit in the Nth level drive circuit, control the connection between the global input terminal and the Nth input terminal under the control of the first reverse scan start control signal provided by the first reverse scan start control terminal; the Nth input terminal is the input terminal of the Nth level drive circuit in the Nth level drive circuit.

20. The drive module as described in claim 19, wherein, The first backscan input control circuit includes a first backscan input control transmission gate and a second backscan input control transmission gate; The positive control terminal of the first backscan input control transmission gate is electrically connected to the first backscan start control terminal, the negative control terminal of the first backscan input control transmission gate is electrically connected to the first negative backscan start control terminal, the first terminal of the first backscan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the first backscan input control transmission gate is electrically connected to the first terminal of the second backscan input control transmission gate. The positive control terminal of the second first reverse scan input control transmission gate is electrically connected to the reverse scan control terminal, the negative control terminal of the second first reverse scan input control transmission gate is electrically connected to the positive scan control terminal, and the second terminal of the second first reverse scan input control transmission gate is electrically connected to the Nth input terminal.

21. The drive module as described in claim 19, wherein, It also includes C reverse scan input control circuits; C is a positive integer; The (c+1)th backscan input control circuit is electrically connected to the global input terminal, the (c+1)th backscan start control terminal, and the Ncth backscan input node, respectively. It is used to perform reverse scanning in global display mode and control the connection between the global input terminal and the Ncth backscan input node when scanning starts from the Ncth level driving circuit in the Nth level driving circuit; c is a positive integer less than or equal to C.

22. The drive module as described in claim 21, wherein, The (c+1)th reverse scan input control circuit includes the (c+1)th reverse scan input control transmission gate; The positive control terminal of the (c+1)th backscan input control transmission gate is electrically connected to the (c+1)th backscan start control terminal, the negative control terminal of the (c+1)th backscan input control transmission gate is electrically connected to the (c+1)th negative backscan start control terminal, the first terminal of the (c+1)th backscan input control transmission gate is electrically connected to the global input terminal, and the second terminal of the (c+1)th backscan input control transmission gate is electrically connected to the Ncth backscan input node.

23. The drive module as described in claim 21, wherein, It also includes C cutoff circuits; The c-th cutoff circuit is electrically connected to the c+1-th backscan start control terminal, the N-c+1-th cascaded output terminal, and the Nc-th backscan input node, respectively, and is used to control the connection or disconnection between the Nc-th backscan input node and the N-c+1-th cascaded output terminal under the control of the c+1-th backscan start control signal provided by the c+1-th backscan start control terminal.

24. The drive module as described in claim 22, wherein, The c-th cutoff circuit includes the c-th cutoff transmission gate; The positive phase control terminal of the c-th cutoff transmission gate is electrically connected to the c+1-th reverse scan start control terminal, the negative phase control terminal of the c-th cutoff transmission gate is electrically connected to the c+1-th reverse scan start control terminal, the first terminal of the c-th cutoff transmission gate is electrically connected to the Nc-th reverse scan input node, and the second terminal of the c-th cutoff transmission gate is electrically connected to the N-c+1-th cascaded output terminal.

25. A driving method applied to a driving module as described in any one of claims 1 to 24, the driving method comprising: In partial display mode, Under the control of the display mode control signal, the local display control circuit controls the connection between the starting voltage terminal and the local input terminal; During forward scanning, the first scan control switch circuit, under the control of the scan control signal, controls the connection between the local input terminal and the m-th input terminal, where the m-th input terminal is the input terminal of the start-stage drive circuit. During reverse scanning, the second scan control switch circuit, under the control of the scan control signal, controls the connection between the local input terminal and the nth input terminal; the nth input terminal is the input terminal of the cutoff stage drive circuit.

26. A display device comprising the driving module as described in any one of claims 1 to 24.

Images