Driving backplane and display panel

Abstract

The present application belongs to the technical field of display. Disclosed are a driving backplane and a display panel. The driving backplane comprises: a substrate, and a plurality of pixel driving circuits, a plurality of first data lines and a plurality of second data lines, which are located on one side of the substrate. A plurality of first pixel driving circuits in one column of pixel driving circuits are electrically connected to one first data line, and a plurality of second pixel driving circuits in one column of pixel driving circuits are electrically connected to one second data line. In a first direction, a signal output point in a first pixel driving circuit and / or a signal output point in a second pixel driving circuit are / is distributed between a first data line and a second data line, and the minimum distance between each signal output point and the first data line and the minimum distance between each signal output point and the second data line are both greater than 0. In this way, two data lines can respectively provide data signals for different pixel driving circuits, thus ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect.

Description

Driver backplane and display panel

[0001] This application claims priority to Chinese Patent Application No. 202510125399.4, filed on January 26, 2025, entitled “Driver Backplane and Display Panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to a driving backplane and a display panel. Background Technology

[0003] Organic light-emitting diode (OLED) is a current-driven organic light-emitting device. OLED display panels are widely used in the display field due to their advantages such as thinness, self-illumination, high resolution, and fast response speed.

[0004] OLED display panels typically include a driving backplane and multiple light-emitting devices, which are electrically connected to the driving backplane. The driving backplane includes a substrate, multiple pixel driving circuits, and multiple data lines located on one side of the substrate. The multiple pixel driving circuits are arranged in multiple rows and columns, with each column of pixel driving circuits electrically connected to one of the data lines. Each data line provides a data signal to a corresponding column of pixel driving circuits. When a data signal is input to a pixel driving circuit, the corresponding row of that pixel driving circuit can be activated for charging.

[0005] Since a single data line provides data signals to each pixel driving circuit in a corresponding column of pixel driving circuits, in order to prevent accidental charging, the pixel driving circuits are turned on row by row for charging. This results in a shorter charging time for each pixel driving circuit, affecting the display effect of the display panel. Summary of the Invention

[0006] This application provides a driving backplane and a display panel, which can solve the problem of short charging time for pixel driving circuits. The technical solution is as follows:

[0007] On one hand, a driving backplane is provided, comprising: a substrate, and a plurality of pixel driving circuits, a plurality of first data lines and a plurality of second data lines located on one side of the substrate;

[0008] The plurality of pixel driving circuits are arranged in multiple columns along a first direction and in multiple rows along a second direction; the extension directions of the first data line and the second data line are both parallel to the second direction; a column of the pixel driving circuits includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, the plurality of first pixel driving circuits are electrically connected to a first data line, the plurality of second pixel driving circuits are electrically connected to a second data line, and the first data line and the second data line are located on both sides of a column of the pixel driving circuits;

[0009] Both the first pixel driving circuit and the second pixel driving circuit have a signal output point, which is used to be electrically connected to the light-emitting device.

[0010] The signal output points in the first pixel driving circuit and / or the second pixel driving circuit are distributed between the first data line and the second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the first data line, and the minimum distance between the signal output point and the second data line are both greater than 0.

[0011] Optionally, in the first direction, the minimum distance between the signal output point in the first pixel driving circuit and the first data line is greater than or equal to the minimum distance between the signal output point in the first pixel driving circuit and the second data line.

[0012] And / or, in the first direction, the minimum distance between the signal output point in the second pixel driving circuit and the second data line is greater than or equal to the minimum distance between the signal output point in the second pixel driving circuit and the first data line.

[0013] Optionally, the first pixel driving circuit and / or the second pixel driving circuit includes:

[0014] The first transistor has its gate electrically connected to the first reset signal line, its first terminal electrically connected to the first initial power line, and its second terminal electrically connected to the first node.

[0015] The second transistor has its gate electrically connected to the gate signal line, its first terminal electrically connected to the third node, and its second terminal electrically connected to the first node.

[0016] The third transistor has its gate electrically connected to the first node, its first electrode electrically connected to the third node, and its second electrode electrically connected to the second node.

[0017] The fourth transistor has its gate electrically connected to the gate signal line, its first terminal electrically connected to the first data line or the second data line, and its second terminal electrically connected to the second node.

[0018] The fifth transistor has its gate electrically connected to the light-emitting control signal line, its first terminal electrically connected to the first power supply line, and its second terminal electrically connected to the second node.

[0019] The sixth transistor has its gate electrically connected to the light-emitting control signal line, its first electrode electrically connected to the third node, and its second electrode electrically connected to the signal output point.

[0020] The seventh transistor has its gate electrically connected to the second reset signal line, its first terminal electrically connected to the second initial power supply line, and its second terminal electrically connected to the signal output point.

[0021] A storage capacitor, wherein the first capacitor electrode of the storage capacitor is connected to the first power line, and the second capacitor electrode of the storage capacitor is electrically connected to the first node.

[0022] Optionally, the third node includes a first strip portion and a second strip portion, the first strip portion extending along the first direction and the second strip portion extending along the second direction; one end of the first strip portion is electrically connected to the second strip portion, the other end of the first strip portion is electrically connected to the first electrode of the third transistor, one end of the second strip portion is electrically connected to the first electrode of the second transistor, and the other end of the second strip portion is electrically connected to the first electrode of the sixth transistor.

[0023] The orthographic projection of the second body portion in the first pixel driving circuit onto the substrate does not coincide with the orthographic projection of the second data line onto the substrate.

[0024] Optionally, the orthographic projection of the first body portion in the first pixel driving circuit onto the substrate has a first overlapping area with the orthographic projection of the second data line onto the substrate;

[0025] The first power line has a first shielding portion, which is located between the first strip portion and the second data line in a direction perpendicular to the substrate, and the first overlapping area is located within the orthographic projection of the first shielding portion on the substrate.

[0026] Optionally, in the first direction, the minimum distance between the signal output point in the first pixel driving circuit and the second data line is greater than or equal to the minimum distance between the second body portion in the first pixel driving circuit and the second data line.

[0027] Optionally, the driving backplane further includes: a light-shielding layer, which is electrically connected to the first power line; the orthographic projections of the channel regions of the first transistor, the second transistor, the third transistor, and the fourth transistor on the substrate are all located within the orthographic projection of the light-shielding layer on the substrate;

[0028] The light-shielding layer has a first light-shielding trace, the overall extension direction of the first light-shielding trace is parallel to the first direction, and the orthographic projection of the first light-shielding trace on the substrate does not coincide with the orthographic projection of the first strip portion on the substrate.

[0029] Optionally, the driving backplane further includes: a power auxiliary line, the overall extension direction of which is parallel to the second direction, and the power auxiliary line having: auxiliary line segments distributed in the first direction between the first data line and the signal output points in the first pixel driving circuit;

[0030] In the first direction, the minimum distance between the signal output point of the first pixel driving circuit and the auxiliary line segment is less than or equal to the minimum distance between the signal output point of the first pixel driving circuit and the second data line.

[0031] Optionally, the drive backplate further includes a light-shielding layer, which is electrically connected to the first power line;

[0032] The light-shielding layer has a second light-shielding trace, the overall extension direction of the second light-shielding trace is parallel to the second direction, and the orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the power auxiliary line on the substrate.

[0033] Optionally, the first node includes a first part, a second part, and a third part. The first end of the first part, the first end of the second part, and the first end of the third part are electrically connected to each other. The second end of the first part is electrically connected to the second electrode of the first transistor. The second end of the second part is electrically connected to the second electrode of the second transistor. The second end of the third part is electrically connected to the gate of the third transistor.

[0034] Wherein, the orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the first portion on the substrate.

[0035] Optionally, the orthographic projection of the first portion on the substrate and the orthographic projection of the power supply auxiliary line on the substrate have a second overlapping region;

[0036] The first power line also has a second shielding portion, which is located between the first portion and the power auxiliary line in a direction perpendicular to the substrate, and the second overlapping area is located within the orthographic projection of the second shielding portion on the substrate.

[0037] Optionally, the power auxiliary line may also have a transition region in its orthographic projection on the substrate that connects to the second overlapping region. The transition region is located outside the orthographic projection of the second light-shielding trace on the substrate and overlaps with the orthographic projection of the second shielding portion on the substrate.

[0038] Optionally, the second node includes a third body portion and a fourth body portion, the third body portion extending along the first direction and the fourth body portion extending along the second direction; one end of the third body portion is electrically connected to the fourth body portion, the other end of the third body portion is electrically connected to the second electrode of the third transistor, one end of the fourth body portion is electrically connected to the second electrode of the fourth transistor, and the other end of the fourth body portion is electrically connected to the second electrode of the fifth transistor;

[0039] Wherein, the orthographic projection of the third body portion in the first pixel driving circuit onto the substrate has a third overlapping area with the orthographic projection of the first data line onto the substrate;

[0040] The first power line also has a third shielding portion, which is located between the third strip portion and the first data line in a direction perpendicular to the substrate, and the third overlapping area is located within the orthographic projection of the third shielding portion on the substrate.

[0041] Optionally, in the first direction, the fourth transistor in the first pixel driving circuit is located on the side of the first data line away from the signal output point in the first pixel driving circuit, and the fourth transistor in the second pixel driving circuit is located on the side of the second data line away from the signal output point in the second pixel driving circuit.

[0042] Wherein, in the first direction, the minimum distance between the fourth transistor in the first pixel driving circuit and the first data line is equal to the minimum distance between the fourth transistor in the second pixel driving circuit and the second data line.

[0043] Optionally, the driving backplane has multiple periodic partitions, and eight pixel driving circuits are distributed in one periodic partition, with the eight pixel driving circuits arranged in two rows and four columns.

[0044] Within the same periodic partition, the two pixel driving circuits arranged in the second direction are respectively: a first pixel driving circuit and a second pixel driving circuit; the four pixel driving circuits arranged in the first direction are respectively: two first pixel driving circuits and two second pixel driving circuits arranged in succession.

[0045] Optionally, the driving backplane further includes: a first power line; the first power line has a plurality of second shielding portions, the plurality of second shielding portions corresponding to the plurality of pixel driving circuits, and the second shielding portions and the corresponding pixel driving circuits are distributed in the same sub-pixel area;

[0046] Specifically, for two second shielding portions arranged adjacent to each other in the second direction within the same periodic partition, the orthographic projection of one second shielding portion on the substrate overlaps with the orthographic projection of the first data line on the substrate, but does not coincide with the orthographic projection of the second data line on the substrate; the orthographic projection of the other second shielding portion on the substrate overlaps with the orthographic projection of the second data line on the substrate, but does not coincide with the orthographic projection of the first data line on the substrate.

[0047] Optionally, the driving backplate has a display area and a non-display area distributed around the display area; the plurality of pixel driving circuits, the plurality of first data lines and the plurality of second data lines are all located at least within the display area;

[0048] The drive backplane also includes a multiplexer and multiple bonding pads, wherein the multiplexer and the multiple bonding pads are both located in the non-display area, and the multiplexer is closer to the display area than the multiple bonding pads.

[0049] The multiplexer has multiple first ports on the side facing the display area and multiple second ports on the side away from the display area. The multiple first ports are electrically connected to the multiple first data lines and the multiple second data lines, and the multiple second ports are electrically connected to the multiple bonding pads.

[0050] On the other hand, a display panel is provided, including: any of the above-described driving backplane, and a plurality of light-emitting devices electrically connected to the driving backplane.

[0051] Optionally, the display panel further includes: a plurality of separately disposed first electrode blocks; the plurality of first electrode blocks correspond to the plurality of light-emitting devices, wherein the anode of the light-emitting device is at least a portion of the corresponding first electrode block;

[0052] The drive backplane further includes: a first power line; the first power line includes: a plurality of first sub-power lines extending along the second direction, and a plurality of second sub-power lines extending along the first direction; the first sub-power lines and the second sub-power lines are electrically connected at their intersections; in the first direction, the width of the first sub-power line is greater than the width of the first data line and greater than the width of the second data line.

[0053] Wherein, the orthographic projection of the first electrode block on the substrate overlaps with the orthographic projections of the adjacent first data lines and second data lines on the substrate, and also overlaps with the orthographic projections of the two adjacent first sub-power lines on the substrate; in the first direction, the adjacent first data lines and second data lines are distributed between the two adjacent first sub-power lines.

[0054] The beneficial effects of the technical solution provided in this application include at least the following:

[0055] Multiple first pixel driving circuits in a pixel driving circuit can be electrically connected to a corresponding first data line, and multiple second pixel driving circuits in a pixel driving circuit can be electrically connected to a corresponding second data line. In this way, the two data lines can provide data signals to different pixel driving circuits, ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. Simultaneously, the signal output points in the first and / or second pixel driving circuits can be distributed between the corresponding first and second data lines in a first direction. Furthermore, in the first direction, the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line, can both be greater than zero. This ensures that the distance between the first and second data lines is large, avoiding mutual interference; it also ensures that the signal output point has a certain distance from both the first and second data lines, thereby reducing the influence of the data signals loaded on the first and second data lines on the signal output point, making the potential of the signal output point more stable, further improving the display effect. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 is a top view of a drive backplate provided in an embodiment of this application;

[0058] Figure 2 is a structural layout of a drive backplane provided in an embodiment of this application;

[0059] Figure 3 is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0060] Figure 4 is a schematic diagram of the membrane structure of a driving backplate provided in an embodiment of this application;

[0061] Figure 5 is a structural layout of a light-shielding layer in a drive backplate provided in an embodiment of this application;

[0062] Figure 6 is a structural layout of an active layer in a driving backplane provided in an embodiment of this application;

[0063] Figure 7 is a structural layout of the first gate layer in a driving backplane provided in an embodiment of this application;

[0064] Figure 8 is a structural layout of the second gate layer in a driving backplane provided in an embodiment of this application;

[0065] Figure 9 is a structural layout of the first conductive layer in a driving backplane provided in an embodiment of this application;

[0066] Figure 10 is a structural layout of the second conductive layer in a driving backplane provided in an embodiment of this application;

[0067] Figure 11 is a structural layout of a driver backplane in which a light-shielding layer, an active layer, and a first gate layer are stacked, according to an embodiment of this application.

[0068] Figure 12 is a structural layout of an active layer, a first gate layer, a second gate layer, a first conductive layer, and a second conductive layer stacked in a driving backplane according to an embodiment of this application;

[0069] Figure 13 is a structural layout of a driver backplane in which a light-shielding layer, an active layer, a first gate layer, and a first conductive layer are stacked, according to an embodiment of this application.

[0070] Figure 14 is a structural layout of a drive backplane with a superimposed light-shielding layer and an active layer provided in an embodiment of this application;

[0071] Figure 15 is a structural layout of a drive backplane in which a light-shielding layer, an active layer, a first gate layer, and a second gate layer are stacked, according to an embodiment of this application.

[0072] Figure 16 is a structural layout of a driver backplane provided in an embodiment of this application, in which a light-shielding layer, an active layer, a first gate layer, a second gate layer, and a first conductive layer are stacked.

[0073] Figure 17 is a schematic diagram of a second overlapping region and the surrounding membrane structure provided in an embodiment of this application;

[0074] Figure 18 is a structural layout of a drive backplane provided in an embodiment of this application;

[0075] Figure 19 is a top view of a drive backplate provided in an embodiment of this application;

[0076] Figure 20 is a schematic diagram of the film layer structure of a display panel provided in an embodiment of this application;

[0077] Figure 21 is a structural layout of a display panel provided in an embodiment of this application;

[0078] Figure 22 is a structural layout of a drive backplane provided in an embodiment of this application. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0080] In all embodiments of this application, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this disclosure, the source is referred to as the first terminal and the drain as the second terminal; alternatively, the drain can be referred to as the first terminal and the source as the second terminal. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, and the two ends are the source and drain, respectively.

[0081] Please refer to Figures 1 and 2. Figure 1 is a top view of a driving backplane provided in an embodiment of this application, and Figure 2 is a structural layout diagram of a driving backplane provided in an embodiment of this application. The driving backplane 100 may include a substrate 01, and multiple pixel driving circuits 02, multiple first data lines DT1, and multiple second data lines DT2 located on one side of the substrate 01. The driving backplane 100 may include multiple sub-pixel regions, each corresponding to a pixel driving circuit 02, and the pixel driving circuit 02 may be located within the corresponding sub-pixel region.

[0082] Multiple pixel driving circuits 02 can be arranged in multiple columns along the first direction X and in multiple rows along the second direction Y.

[0083] The extension directions of both the first data line DT1 and the second data line DT2 can be parallel to the second direction Y. The multi-column pixel driving circuit 02 can correspond to multiple first data lines DT1 and multiple second data lines DT2. A portion of the pixel driving circuit 02 in one column can be electrically connected to a corresponding first data line DT1, and another portion of the pixel driving circuit 02 can be electrically connected to a corresponding second data line DT2.

[0084] The pixel driving circuit 02 may include multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022, and the multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022 may be alternately arranged. Each of the multiple first pixel driving circuits 021 in the pixel driving circuit 02 may be electrically connected to a corresponding first data line DT1, and each of the multiple second pixel driving circuits 022 in the pixel driving circuit 02 may be electrically connected to a corresponding second data line DT2. A first data line DT1 and a second data line DT2 may be located on opposite sides of the corresponding pixel driving circuit 02.

[0085] Thus, a row of pixel driving circuits 02 can correspond to a first data line DT1 and a second data line DT2, and these two data lines can provide data signals to multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022 respectively, thereby ensuring that each pixel driving circuit 02 has sufficient charging time, which can improve the display effect of the display panel.

[0086] Each pixel driving circuit 02 can have a signal output point 023; that is, both the first pixel driving circuit 021 and the second pixel driving circuit 022 can have a signal output point 023. The signal output point 023 can be used to electrically connect with a light-emitting device. In this way, the pixel driving circuit 02 can drive the light-emitting device to emit light, and multiple pixel driving circuits 02 can drive multiple light-emitting devices to emit light, thereby enabling the display panel to display the corresponding image.

[0087] The signal output points 023 in the first pixel driving circuit 021 and / or the second pixel driving circuit 022 can be distributed in the first direction X between the corresponding first data line DT1 and the corresponding second data line DT2. This ensures a large distance between the first data line DT1 and the second data line DT2, preventing mutual interference. Simultaneously, in the first direction X, the minimum distance between the signal output point 023 and the corresponding first data line DT1 can be greater than 0, and the minimum distance between the signal output point 023 and the corresponding second data line DT2 can also be greater than 0. This ensures that the signal output point 023 has a certain distance from both the first data line DT1 and the second data line DT2, thereby reducing the influence of the data signals loaded on the first data line DT1 and the second data line DT2 on the signal output point 023, making the potential of the signal output point 023 more stable, and further improving the display effect.

[0088] In summary, this application provides a driving backplane, which may include a substrate, and multiple pixel driving circuits, multiple first data lines, and multiple second data lines located on one side of the substrate. Multiple first pixel driving circuits in a column of pixel driving circuits can be electrically connected to a corresponding first data line, and multiple second pixel driving circuits in a column of pixel driving circuits can be electrically connected to a corresponding second data line. Thus, the two data lines can provide data signals to different pixel driving circuits respectively, ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. Simultaneously, the signal output points of the first and / or second pixel driving circuits can be distributed between the corresponding first and second data lines in a first direction, and the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line, can both be greater than 0 in the first direction. This ensures a large distance between the first and second data lines, preventing them from interfering with each other; it also ensures a certain distance between the signal output point and both the first and second data lines, thereby reducing the impact of the data signals loaded on the first and second data lines on the signal output point, making the potential of the signal output point more stable, and further improving the display effect.

[0089] In one possible implementation, referring to Figure 2, for any first pixel driving circuit 021, in the first direction X, the minimum distance between the signal output point 023 in the first pixel driving circuit 021 and the first data line DT1 can be greater than or equal to the minimum distance between the signal output point 023 in the first pixel driving circuit 021 and the second data line DT2.

[0090] And / or, for any second pixel driving circuit 022, in the first direction X, the minimum distance between the signal output point 023 in the second pixel driving circuit 022 and the second data line DT2 can be greater than or equal to the minimum distance between the signal output point 023 in the second pixel driving circuit 022 and the first data line DT1.

[0091] This ensures that the signal output point 023 in the first pixel driving circuit 021 and / or the second pixel driving circuit 022 is relatively far from the first data line DT1 and the second data line DT2 in the first direction X. This further reduces the impact of the data signals loaded on the first data line DT1 and the second data line DT2 on the signal output point 023, making the potential of the signal output point 023 more stable and further improving the display effect. Simultaneously, the relatively large distance between the signal output point 023 in the first pixel driving circuit 021 and the first data line DT1, and between the signal output point 023 in the second pixel driving circuit 022 and the second data line DT2 in the first direction X, allows for the arrangement of other traces between the signal output point 023 in the first pixel driving circuit 021 and the first data line DT1, and between the signal output point 023 in the second pixel driving circuit 022 and the second data line DT2.

[0092] Please refer to Figure 3. The first pixel driving circuit 021 and / or the second pixel driving circuit 022 may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C1.

[0093] The first transistor T1 can be a first reset transistor. The gate of the first transistor T1 is electrically connected to the first reset signal line RST1, the first terminal of the first transistor T1 is electrically connected to the first initial power supply line VINIT1, and the second terminal of the first transistor T1 is electrically connected to the first node N1. In response to the first reset signal provided by the first reset signal line RST1, the first transistor T1 can transmit the first initial power supply signal provided by the first initial power supply line VINIT1 to the first node N1, thereby resetting the first node N1. In this embodiment, the first transistor T1 can be a dual-gate transistor, that is, the first transistor T1 can include two transistors connected in series.

[0094] The second transistor T2 can be a compensation transistor. The gate of the second transistor T2 is electrically connected to the gate signal line GATE, the first terminal of the second transistor T2 is electrically connected to the third node N3, and the second terminal of the second transistor T2 is electrically connected to the first node N1. This second transistor T2 can adjust the potentials of the first node N1 and the third node N3 in response to the gate drive signal provided by the gate signal line GT. In this embodiment, the second transistor T2 can be a dual-gate transistor, that is, the second transistor T2 can include two transistors connected in series.

[0095] The third transistor T3 can be a driving transistor. The gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. This third transistor T3 can respond to the potentials of the first node N1 and the second node N2, transmitting a driving signal to the third node N3.

[0096] The fourth transistor T4 can be a data write transistor. The gate of the fourth transistor T4 is electrically connected to the gate signal line GATE, the first terminal of the fourth transistor T4 is electrically connected to the corresponding first data line DT1 or second data line DT2, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2. This fourth transistor T4 can respond to the gate drive signal provided by the gate signal line GT and transmit the data signal provided by the corresponding first data line DT1 or second data line DT2 to the second node N2.

[0097] The fifth transistor T5 can be the first light-emitting control transistor. The gate of the fifth transistor T5 is electrically connected to the light-emitting control signal line EM, the first terminal of the fifth transistor T5 is electrically connected to the drive power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. This fifth transistor T5 can respond to the light-emitting control signal provided by the light-emitting control signal line EM and transmit the first light-emitting control signal to the second node N2.

[0098] The sixth transistor T6 can be the second light-emitting control transistor. The gate of the sixth transistor T6 is electrically connected to the light-emitting control signal line EM, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the signal output point 023. This sixth transistor T6 can respond to the light-emitting control signal provided by the light-emitting control signal line EM, transmitting the drive signal from the third node N3 to the signal output point 023. The light-emitting device can be electrically connected to the signal output point 023, thereby emitting light under the drive signal.

[0099] The seventh transistor T7 can be the second reset transistor. The gate of the seventh transistor T7 is electrically connected to the second reset signal line RST2, the first terminal of the seventh transistor T7 is electrically connected to the second initial power supply line VINIT2, and the second terminal of the seventh transistor T7 is electrically connected to the signal output point 023. This seventh transistor T7 can respond to the second reset signal provided by the second reset signal line RST2 by transmitting the second initial power supply signal provided by the second initial power supply line VINIT2 to the signal output point 023, thereby resetting the potential of the signal output point 023.

[0100] The storage capacitor C1 may have two capacitor electrodes. The first capacitor electrode of the storage capacitor C1 is electrically connected to the first power line VDD, and the second capacitor electrode of the storage capacitor C1 is electrically connected to the first node N1. This storage capacitor C1 can stabilize the potential of the first node N1, thereby improving the stability of the first node N1.

[0101] Please refer to Figure 4, which is a schematic diagram of the film structure of a driving backplane provided in an embodiment of this application. The driving backplane 100 may include: a substrate 01, and the following layers stacked on the substrate 01 in a direction perpendicular to and away from the substrate 01: a light-shielding layer BSM, a buffer layer 03, an active layer POLY, a first gate insulating layer 04, a first gate layer GATE1, a second gate insulating layer 05, a second gate layer GATE2, an interlayer dielectric layer 06, a first conductive layer SD1, a first planarization layer 07, a second conductive layer SD2, and a second planarization layer 08.

[0102] The pixel driving circuit 02 may include at least a portion of the film layers of the driving backplane 100. Specifically, the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 in the pixel driving circuit 02 may each include an active layer POLY, a first gate layer GATE1, and a first conductive layer SD1. The storage capacitor C1 in the pixel driving circuit 02 may include the first gate layer GATE1 and the second gate layer GATE2. Furthermore, multiple first data lines DT1 and multiple second data lines DT2 may be located within the second conductive layer SD2.

[0103] It should be noted that Figure 4 is only used to illustrate the stacking relationship of the various film layers of the driving backplane 100, and is not used to represent a specific cross-sectional view of the driving backplane 100 or the connection relationship of the various transistors in the pixel driving circuit 02. The individual structural layouts of each film layer can be referred to in Figures 5 to 10, and the structural layouts of the superimposed film layers can be referred to in Figures 11 to 16. Specifically, Figure 5 is the structural layout of the light-shielding layer BSM; Figure 6 is the structural layout of the active layer POLY; Figure 7 is the structural layout of the first gate layer GATE1; Figure 8 is the structural layout of the second gate layer GATE2; Figure 9 is the structural layout of the first conductive layer SD1; Figure 10 is the structural layout of the second conductive layer SD2; Figure 11 is the structural layout of the light-shielding layer BSM, the active layer POLY, and the first gate layer GATE1 superimposed; Figure 12 is the structural layout of the active layer POLY, the first gate layer GATE1, the second gate layer GATE2, the first conductive layer SD1, and the second conductive layer SD2. Figure 13 shows the stacked structure of the light-shielding layer BSM, the active layer POLY, the first gate layer GATE1, and the first conductive layer SD1; Figure 14 shows the stacked structure of the light-shielding layer BSM and the active layer POLY; Figure 15 shows the stacked structure of the light-shielding layer BSM, the active layer POLY, the first gate layer GATE1, and the second gate layer GATE2; Figure 16 shows the stacked structure of the light-shielding layer BSM, the active layer POLY, the first gate layer GATE1, the second gate layer GATE2, and the first conductive layer SD1.

[0104] The following embodiments all take the first pixel driving circuit 021 as an example to illustrate the positional relationship between each node and the trace in the first pixel driving circuit 021.

[0105] Referring to Figures 6 and 11, at least a portion of the third node N3 in the first pixel driving circuit 021 can be located in the active layer POLY. The third node N3 can include a first body portion 10 and a second body portion 20. The first body portion 10 can extend along a first direction X, and the second body portion 20 can extend along a second direction Y. The first body portion 10 and the second body portion 20 can be electrically connected to each other. One end of the first body portion 10 can be electrically connected to the second body portion 20, and the other end of the first body portion 10 can be electrically connected to the first electrode of the third transistor T3. One end of the second body portion 20 can be electrically connected to the first electrode of the second transistor T2, and the other end of the second body portion 20 can be electrically connected to the first electrode of the sixth transistor T6.

[0106] For any first pixel driving circuit 021, if the orthographic projection of the second body portion 20 on the substrate 01 in the first pixel driving circuit 021 coincides with the orthographic projection of the second data line DT2 on the substrate 01, that is, the overlap area of ​​the orthographic projection of the second body portion 20 on the substrate 01 and the orthographic projection of the second data line DT2 on the substrate 01 is large, this will cause the data signal loaded on the second data line DT2 to have a greater impact on the third node N3, and a large coupling capacitance will be generated between the second body portion 20 and the second data line DT2, resulting in a large total capacitance of the third node N3, which affects the display effect.

[0107] Therefore, in this embodiment, referring to FIG12, for any first pixel driving circuit 021, the orthographic projection of the second body portion 20 in the first pixel driving circuit 021 onto the substrate 01 is ensured not to coincide with the orthographic projection of the second data line DT2 onto the substrate 01. This ensures that there is a certain distance between the second body portion 20 and the second data line DT2 in the first direction X, thereby avoiding a large overlap area between the orthographic projections of the second body portion 20 and the second data line DT2 onto the substrate 01. This reduces the impact of the data signal loaded on the second data line DT2 on the third node N3, ensuring the stability of the potential of the third node N3. Simultaneously, it reduces the total capacitance of the third node N3, thereby improving image retention and enhancing the display effect of the display panel.

[0108] In one possible scenario, for any given first pixel driving circuit 021, the impact of the data signal loaded on the second data line DT2 on the signal output point 023 is greater than the impact of the data signal loaded on the second data line DT2 on the second body portion 20. Therefore, as shown in Figure 12, in the first direction X, the minimum distance between the signal output point 023 in the first pixel driving circuit 021 and the second data line DT2 can be greater than or equal to the minimum distance between the second body portion 20 in the first pixel driving circuit 021 and the second data line DT2. This ensures that the distance between the signal output point 023 in the first pixel driving circuit 021 and the second data line DT2 is greater in the first direction X, thereby reducing the impact of the data signal loaded on the second data line DT2 on the signal output point 023, reducing the coupling capacitance between the second data line DT2 and the signal output point 023, and thus making the potential of the signal output point 023 more stable, improving the display effect of the display panel.

[0109] Referring to Figure 12, for any first pixel driving circuit 021, the orthographic projection of the first body portion 10 in the first pixel driving circuit 021 onto the substrate 01 and the orthographic projection of the second data line DT2 onto the substrate 01 may have a first overlapping region S1. In this way, the second data line DT2 will generate a coupling capacitance with the first body portion 10, thereby affecting the total capacitance of the third node N3 and causing the potential of the third node N3 to be unstable.

[0110] Referring to Figures 8 and 12, in this embodiment, the first power line VDD may have a first shielding portion P1. The first shielding portion P1 may be located between the first strip portion 10 and the second data line DT2 in a direction perpendicular to the substrate 01, and the first overlapping region S1 may be located within the orthogonal projection of the first shielding portion P1 onto the substrate 01. Thus, the first shielding portion P1 can shield the coupling capacitance generated between the first strip portion 10 and the second data line DT2, thereby reducing the influence of the data signal loaded on the second data line DT2 on the third node N3 and ensuring the stability of the potential of the third node N3. Simultaneously, the total capacitance of the third node N3 can be reduced, thereby improving image retention and enhancing the display effect.

[0111] It should be noted that, referring to Figures 8 to 10 and Figure 12, the first power line VDD in this embodiment can be located within the first conductive layer SD1, the second conductive layer SD2, and the second gate layer GATE2. Multiple first power lines VDD located within the first conductive layer SD1 and the second conductive layer SD2 can extend along the second direction Y, and their orthogonal projections on the substrate 01 can overlap, thereby increasing the cross-sectional area of ​​the first power lines VDD and reducing losses during power transmission. Multiple first power lines VDD located within the second gate layer GATE2 can extend along the first direction X, and their orthogonal projections on the substrate 01 can overlap with those of the first power lines VDD located within the first conductive layer SD1 and the second conductive layer SD2, thereby electrically connecting the first power lines VDD located in different layers. The first shielding portion P1 can be located within the second gate layer GATE2.

[0112] The light-shielding layer BSM in the driving backplane 100 can also be electrically connected to the first power line VDD. Thus, the light-shielding layer BSM can also serve as a trace for the first power signal, thereby increasing the area of ​​the first power signal trace and reducing voltage loss during transmission. The light-shielding layer BSM can also protect the channel region of the transistors, preventing direct light from illuminating the channel region and affecting the normal turn-on and turn-off of the transistors. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the pixel driving circuit 02 mainly control the writing of data signals and are crucial for the normal operation of the pixel driving circuit 02. Therefore, as shown in Figures 11 and 14, the orthogonal projection of the channel region of these four transistors onto the substrate 01 can all lie within the orthogonal projection of the light-shielding layer BSM onto the substrate 01, thus effectively protecting the channel region of these four transistors from direct light illumination and ensuring the normal operation of these four transistors.

[0113] Referring to Figures 5 and 11, the light-shielding layer BSM can have a first light-shielding trace B1 and a second light-shielding trace B2. The overall extension direction of the first light-shielding trace B1 is parallel to the first direction X, and the overall extension direction of the second light-shielding trace B2 is parallel to the second direction Y. The first light-shielding trace B1 can intersect with the second light-shielding trace B2. Since the first body portion 10 of the first pixel driving circuit 021 also extends along the first direction X, if the orthographic projection of the first light-shielding trace B1 on the substrate 01 coincides with the orthographic projection of the first body portion 10 on the substrate 01, that is, if the overlap area of ​​the orthographic projection of the first light-shielding trace B1 on the substrate 01 and the orthographic projection of the first body portion 10 on the substrate 01 is large, a large coupling capacitance will be generated between the first light-shielding trace B1 and the first body portion 10, which will result in a large total capacitance of the third node N3.

[0114] Therefore, in this embodiment, referring to FIG14, it is ensured that the orthographic projection of the first light-shielding trace B1 on the substrate 01 does not coincide with the orthographic projection of the first body portion 10 on the substrate 01. Thus, in the second direction Y, there is a certain distance between the first light-shielding trace B1 and the first body portion 10, thereby avoiding a large overlap area between their orthographic projections on the substrate 01 and the substrate 01. This reduces the coupling capacitance between the first light-shielding trace B1 and the first body portion 10, thereby reducing the total capacitance of the third node N3, improving image retention, and enhancing the display effect of the display panel.

[0115] In one possible implementation, referring to Figure 9, the driving backplane 100 may include power auxiliary lines SIP, which may be located on the first conductive layer SD1. There may be multiple power auxiliary lines SIP, and the overall extension direction of all multiple power auxiliary lines SIP can be parallel to the second direction Y. The power auxiliary lines SIP can be connected to the second power line VSS. Optionally, if the second power supply is a cathode power supply, then the power auxiliary lines SIP can be cathode power supply auxiliary lines. Because the resistance of the cathode layer in the display panel is high, the voltage drop is more significant the further away from the second power supply point, which can easily cause uneven light emission in the display panel. Connecting multiple power auxiliary lines SIP to the cathode layer increases the number and density of the second power supply points on the cathode layer, thereby reducing the voltage drop and improving the uneven light emission phenomenon of the display panel.

[0116] Referring to Figure 12, for any first pixel driving circuit 021, in the first direction X, the signal output point 023 of the first pixel driving circuit 021 is located between the corresponding first data line DT1 and the second data line DT2, and the distance between the signal output point 023 and the corresponding first data line DT1 is greater than or equal to the distance between the signal output point 023 and the corresponding second data line DT2. Therefore, in the first direction X, there is space between the signal output point 023 and the first data line DT1 for arranging other traces. The auxiliary power line SIP can have an auxiliary segment 001, so the auxiliary segment 001 can be distributed between the first data line DT1 and the signal output point 023 of the first pixel driving circuit 021 in the first direction X. That is, in the first direction X, the signal output point 023 of the first pixel driving circuit 021 can be located between the auxiliary segment 001 and the second data line DT2.

[0117] A certain distance needs to be maintained between the auxiliary line segment 001 and the signal output point 023 in the first pixel driving circuit 021 to prevent the second power signal loaded on the auxiliary line segment 001 from pulling down the potential of the signal output point 023. Since the data signal loaded on the second data line DT2 is a transition signal, it has a greater impact on the signal output point 023 than the auxiliary line segment 001. Therefore, in this embodiment, it is necessary to ensure that the minimum distance between the auxiliary line segment 001 and the signal output point 023 in the first pixel driving circuit 021 in the first direction X is less than or equal to the minimum distance between the second data line DT2 and the signal output point 023 in the first pixel driving circuit 021. This minimizes the impact of the second data line DT2 and the auxiliary line segment 001 on the signal output point 023, ensuring the stability of the potential of the signal output point 023.

[0118] Referring to Figures 5, 9, and 13, the overall extension direction of the power auxiliary line SIP can be parallel to the second direction Y, and the overall extension direction of the second light-shielding trace B2 of the light-shielding layer BSM can also be parallel to the second direction Y. That is, the power auxiliary line SIP can be roughly parallel to the second light-shielding trace B2. To increase transmittance, the orthographic projection of the power auxiliary line SIP on the substrate 01 can be made to overlap with the orthographic projection of the second light-shielding trace B2 on the substrate 01 as much as possible. In this way, the area of ​​the orthographic projection of the trace on the substrate 01 can be reduced, thereby increasing the transmittance of the display panel and improving the display effect. At the same time, due to the increased light transmittance, the sensitivity of the under-display optical fingerprint hole is also increased, thereby improving the user experience. In addition, since both the power auxiliary line SIP and the second light-shielding trace B2 can be used as power lines, and the distance between the power auxiliary line SIP and the second light-shielding trace B2 is relatively large in the direction perpendicular to the substrate 01, the power auxiliary line SIP and the second light-shielding trace B2 will not have much mutual influence when their orthogonal projections on the substrate 01 are overlapped.

[0119] Referring to Figures 11 and 12, at least a portion of the first node N1 in the first pixel driving circuit 021 can be located in the active layer POLY and the first conductive layer SD1. The first node N1 can include a first portion L1, a second portion L2, and a third portion L3. At least a portion of the first portion L1 and the second portion L2 can be located in the active layer POLY, and at least a portion of the third portion L3 can be located in the first conductive layer SD1. The first end of the first portion L1, the second end of the second portion L2, and the first end of the third portion L3 are electrically connected to each other. The second end of the first portion L1 is electrically connected to the second electrode of the first transistor T1, the second end of the second portion L2 is electrically connected to the second electrode of the second transistor T2, and the second end of the third portion L3 is electrically connected to the gate of the third transistor T3.

[0120] In this circuit, the orthographic projection of the first portion L1 of the first pixel driving circuit 021 onto the substrate 01 can overlap with the orthographic projection of the second light-shielding trace B2 of the light-shielding layer BSM onto the substrate 01. Since one electrode of the storage capacitor C1 is electrically connected to the first power line VDD, and the other electrode of the storage capacitor C1 is electrically connected to the N1 node, while the second light-shielding trace B2 is electrically connected to the first power line VDD, the second light-shielding trace B2 can also form a storage capacitor C1 with the first portion L1 of the first pixel driving circuit 021 within the overlapping area of ​​the orthographic projections, thereby increasing the capacitance value of the storage capacitor C1.

[0121] Since the orthographic projection of the power supply auxiliary line SIP on the substrate 01 can overlap with the orthographic projection of the second light-shielding trace B2 on the substrate 01, and the orthographic projection of the second light-shielding trace B2 on the substrate 01 can also overlap with the orthographic projection of the first portion L1 in the first pixel driving circuit 021 on the substrate 01, in one possible case, referring to FIG12, the orthographic projection of the first portion L1 in the first pixel driving circuit 021 on the substrate 01 can have a second overlapping region S2 with the orthographic projection of the power supply auxiliary line SIP on the substrate 01, and the second overlapping region S2 can be located in the region where the second light-shielding trace B2 and the orthographic projection of the first portion L1 on the substrate 01 overlap.

[0122] However, in the second overlapping region S2, the second power signal loaded on the power auxiliary line SIP will pull down the potential of the first node N1 in the first pixel driving circuit 021. Therefore, in this embodiment, as shown in FIG9, the first power line VDD may also have a second shield P2. The second shield P2 may be located within the second gate layer GATE2. The second shield P2 may be located between the first portion L1 in the first pixel driving circuit 021 and the power auxiliary line SIP in a direction perpendicular to the substrate 01. The second overlapping region S2 may be located within the orthogonal projection of the second shield P2 on the substrate 01. In this way, the second shield P2 can shield the influence of the second power signal loaded on the power auxiliary line SIP on the first node N1 in the first pixel driving circuit 021, thereby ensuring the stability of the potential of the first node N1 in the first pixel driving circuit 021.

[0123] In one of the above possible scenarios, in the direction perpendicular to the substrate 01, the second shielding part P2 is located between the first part L1 in the first pixel driving circuit 021 and the power supply auxiliary line SIP, and the signal loaded on the second shielding part P2 is the first power supply signal. In this way, the overlapping part of the first part L1 in the first pixel driving circuit 021 and the second shielding part P2 can also form a storage capacitor C1, thereby increasing the capacitance value of the storage capacitor C1, which can further ensure the stability of the first node N1 in the first pixel driving circuit 021.

[0124] As shown in Figure 17, the film structure at the second overlapping region S2 may include a substrate 01, and the following materials stacked on one side of the substrate 01 in a direction perpendicular to and away from the substrate 01: a second light-shielding trace B2, a buffer layer 03, a first part L1 of the first node N1 in the first pixel driving circuit 021, a first gate insulating layer 04, a second gate insulating layer 05, a second shielding part P2, an interlayer dielectric layer 06, a power auxiliary line SIP, a first planarization layer 07, and a second planarization layer 08.

[0125] As shown in Figure 17, in the direction perpendicular to the substrate 01, the power auxiliary line SIP overlaps with the second light-shielding trace B2, thereby improving the transmittance of the display panel. The second shielding part P2 is located between the first part L1 in the first pixel driving circuit 021 and the power auxiliary line SIP, so the second shielding part P2 can shield the influence of the power auxiliary line SIP on the first part L1 in the first pixel driving circuit 021. The first part L1 in the first pixel driving circuit 021 is located between the second light-shielding trace B2 and the second shielding part P2, so the first part L1 in the first pixel driving circuit 021, together with the second light-shielding trace B2 and the second shielding part P2, can form a storage capacitor C1, thereby increasing the capacitance value of the storage capacitor C1.

[0126] It should also be noted that, referring to Figures 5, 7, and 11, the light-shielding layer BSM may also include a light-shielding block B3. A first light-shielding trace B1 and a second light-shielding trace B2 can be connected to a light-shielding block B3 at their intersection. The orthographic projection of the light-shielding block B3 on the substrate 01 may overlap with the orthographic projection of the first gate layer GATE1 on the substrate 01. Since the light-shielding block B3 is also electrically connected to the first power line VDD, the light-shielding block B3 and the first gate layer GATE1 in the overlapping area can also form a storage capacitor C1, thereby further increasing the capacitance value of the storage capacitor C1 and better ensuring the stability of the first node N1 in the first pixel driving circuit 021.

[0127] Referring to Figures 8 and 12, the orthographic projection of the power auxiliary line SIP on the substrate 01 also includes a transition region M connected to the second overlapping region S2. This transition region M is located outside the orthographic projection of the second light-shielding trace B2 on the substrate 01. Therefore, to improve transmittance, the transition region M can overlap with the orthographic projection of the second shielding portion P2 on the substrate 01, reducing the area of ​​the trace's orthographic projection on the substrate 01, thereby improving the transmittance of the display panel and enhancing the display effect. Simultaneously, in the direction perpendicular to the substrate 01, the second shielding portion P2 is located between the power auxiliary line SIP and the substrate 01. Therefore, the second shielding portion P2 can shield the power auxiliary line SIP from the influence of the trace located between the second shielding portion P2 and the substrate 01, ensuring the normal operation of the pixel driving circuit 02.

[0128] Referring to Figures 6 and 11, at least a portion of the second node N2 in the first pixel driving circuit 021 is located in the active layer POLY. The second node N2 may include a third body portion 30 and a fourth body portion 40. The third body portion 30 extends along a first direction X, and the fourth body portion 40 extends along a second direction Y. The third body portion 30 and the fourth body portion 40 are electrically connected to each other. One end of the third body portion 30 is electrically connected to the fourth body portion 40, and the other end of the third body portion 30 is electrically connected to the second electrode of the third transistor T3. One end of the fourth body portion 40 is electrically connected to the second electrode of the fourth transistor T4, and the other end of the fourth body portion 40 is electrically connected to the second electrode of the fifth transistor T5.

[0129] For any first pixel driving circuit 021, if the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 onto the substrate 01 coincides with the orthographic projection of the first data line DT1 onto the substrate 01, that is, if the overlapping area of ​​the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 onto the substrate 01 and the orthographic projection of the first data line DT1 onto the substrate 01 is large, it will result in a large coupling capacitance between the fourth body portion 40 and the first data line DT1. The data signal loaded on the first data line DT1 will have a significant impact on the second node N2 in the first pixel driving circuit 021, thus affecting the display effect.

[0130] Therefore, in this embodiment, referring to FIG12, for any first pixel driving circuit 021, the orthographic projection of the fourth body portion 40 in the first pixel driving circuit 021 onto the substrate 01 is ensured not to coincide with the orthographic projection of the first data line DT1 onto the substrate 01. This ensures that in the first direction X, there is a certain distance between the fourth body portion 40 in the first pixel driving circuit 021 and the first data line DT1, avoiding a large overlap between the orthographic projections of the fourth body portion 40 and the first data line DT1 onto the substrate 01. This reduces the impact of the data signal loaded on the first data line DT1 on the second node N2 in the first pixel driving circuit 021, ensuring the stability of the potential of the second node N2, thereby improving the display effect of the display panel.

[0131] As shown in Figure 12, for any first pixel driving circuit 021, the orthographic projection of the third body portion 30 in the first pixel driving circuit 021 onto the substrate 01 and the orthographic projection of the first data line DT1 onto the substrate 01 can have a third overlapping region S3. In this way, the first data line DT1 will generate a coupling capacitance with the third body portion 30 in the first pixel driving circuit 021, thereby affecting the total capacitance of the second node N2 in the first pixel driving circuit 021, causing the potential of the second node N2 to be unstable.

[0132] In this embodiment, the first power line VDD may further have a third shielding portion P3, which may be located within the second gate layer GATE2 and electrically connected to the first shielding portion P1. The third shielding portion P3 may be located between the third strip portion 30 in the first pixel driving circuit 021 and the first data line DT1 in a direction perpendicular to the substrate 01, and the third overlapping region S3 may be located within the orthographic projection of the third shielding portion P3 onto the substrate 01. Thus, the third shielding portion P3 can shield the coupling capacitance generated between the third strip portion 30 in the first pixel driving circuit 021 and the first data line DT1, thereby reducing the influence of the data signal loaded on the first data line DT1 on the second node N2 in the first pixel driving circuit 021, ensuring the stability of the potential of the second node N2, and improving the display effect of the display panel.

[0133] In one possible scenario, the power supply auxiliary line SIP and the fourth body portion 40 in the first pixel driving circuit 021 are at a certain distance in the first direction X. This can avoid a large overlap area between the power supply auxiliary line SIP and the fourth body portion 40 in the first pixel driving circuit 021 on the substrate 01, thereby reducing the influence of the second power signal loaded on the power supply auxiliary line SIP on the second node N2 in the first pixel driving circuit 021 and ensuring that the potential of the second node N2 is relatively stable. Meanwhile, the orthographic projection of the power auxiliary line SIP on the substrate 01 and the orthographic projection of the third body portion 30 in the first pixel driving circuit 021 on the substrate 01 can have a fourth overlapping region S4. In the direction perpendicular to the substrate 01, the third shielding portion P3 is also located between the power auxiliary line SIP and the third body portion 30 in the first pixel driving circuit 021. The fourth overlapping region S4 can be located on the orthographic projection of the third shielding portion P3 on the substrate 01. In this way, the third shielding portion P3 can shield the influence of the second power signal loaded on the power auxiliary line SIP on the second node N2 in the first pixel driving circuit 021, thereby further ensuring the stability of the potential of the second node N2.

[0134] In one possible implementation, in the second direction Y, the third shielding portion P3 can be located between the fourth transistor T4 and the fifth transistor T5, and the orthogonal projection of the third body portion 30 in the first pixel driving circuit 021 onto the substrate 01 can be completely located within the orthogonal projection of the third shielding portion P3 onto the substrate 01. At least a portion of the orthogonal projection of the fourth body portion 40 in the first pixel driving circuit 021 onto the substrate 01 can be located within the orthogonal projection of the third shielding portion P3 onto the substrate 01. Thus, the third shielding portion P3 can effectively shield the first data line DT1 and the power auxiliary line SIP from the influence of the first data line DT1 and the power auxiliary line SIP on the third body portion 30 and the fourth body portion 40 in the first pixel driving circuit 021. That is, the third shielding portion P3 can effectively shield the first data line DT1 and the power auxiliary line SIP from the influence of the first node N2 in the first pixel driving circuit 021, ensuring the stability of the potential of the second node N2. Simultaneously, it can also prevent the width of the third shielding portion P3 in the second direction Y from being too large, which would be detrimental to improving transmittance.

[0135] It should be noted that the driving backplane 100 can have multiple periodic partitions, and eight pixel driving circuits 02 can be distributed within one periodic partition. These eight pixel driving circuits 02 can be arranged in two rows and four columns. Within the same periodic partition, the two pixel driving circuits 02 arranged in the second direction Y are respectively a first pixel driving circuit 021 and a second pixel driving circuit 022; the four pixel driving circuits 02 arranged in the first direction X are respectively two consecutive first pixel driving circuits 021 and two consecutive second pixel driving circuits 022. Thus, the multiple pixel driving circuits 02 in the driving backplane 100 can be periodically arranged with eight pixel driving circuits 02 as one arrangement period.

[0136] For example, please refer to Figure 18, which shows eight pixel driving circuits 02 distributed within a periodic partition. The eight pixel driving circuits 02 are: pixel driving circuit M1, pixel driving circuit M2, pixel driving circuit M3, pixel driving circuit M4, pixel driving circuit M5, pixel driving circuit M6, pixel driving circuit M7, and pixel driving circuit M8.

[0137] Here, pixel driving circuits M1, M2, M3, and M4 are arranged in a row along the first direction X, and pixel driving circuits M5, M6, M7, and M8 are arranged in a row along the first direction X; pixel driving circuits M1 and M5 are arranged in a column along the second direction Y, pixel driving circuits M2 and M6 are arranged in a column along the second direction Y, pixel driving circuits M3 and M7 are arranged in a column along the second direction Y, and pixel driving circuits M4 and M8 are arranged in a column along the second direction Y.

[0138] In this configuration, pixel driving circuits M1, M2, M7, and M8 can all be first pixel driving circuits 021, and pixel driving circuits M3, M4, M5, and M6 can all be second pixel driving circuits 022. Thus, in the second direction Y, the first pixel driving circuits 021 and the second pixel driving circuits 022 are arranged alternately; that is, in the second direction Y, any two adjacent pixel driving circuits 02 are of different types.

[0139] Since the fourth transistor T4 in each pixel driving circuit 02 needs to be connected to a data line, and the fourth transistor T4 in the first pixel driving circuit 021 needs to be connected to the first data line DT1, while the fourth transistor T4 in the second pixel driving circuit 022 needs to be connected to the second data line DT2, the two different types of pixel driving circuits 02 require different types of data lines. To ensure that the loads on the first data line DT1 and the second data line DT2 are essentially the same, and to make the driving effect of the two data lines on the different types of pixel driving circuits 02 more consistent, it is necessary to ensure that the lengths of the two data lines are essentially the same.

[0140] For a single pixel driving circuit 02, the positions of the two data lines corresponding to the single pixel driving circuit 02 are different. Therefore, the load of the first data line DT1 and the second data line DT2 can be ensured to be the same by adjusting the distribution of the signal output points 023 in the first pixel driving circuit 021 and the second pixel driving circuit 022.

[0141] Please refer to Figure 18. In the first direction X, the fourth transistor T4 in the first pixel driving circuit 021 can be located on the side of the corresponding first data line DT1 away from the signal output point 023 in the first pixel driving circuit 021, while the fourth transistor T4 in the second pixel driving circuit 022 can be located on the side of the corresponding second data line DT2 away from the signal output point 023 in the second pixel driving circuit 022.

[0142] In the first direction X, the minimum distance between the fourth transistor T4 in the first pixel driving circuit 021 and the corresponding first data line DT1 can be equal to the minimum distance between the fourth transistor T4 in the second pixel driving circuit 022 and the corresponding second data line DT2.

[0143] In this way, the fourth transistor T4 in the first pixel driving circuit 021 and the fourth transistor T4 in the second pixel driving circuit 022 are positioned relatively symmetrically in the first direction X. This makes the path of the first data line DT1 corresponding to the first pixel driving circuit 021 connecting to the fourth transistor T4 of the first pixel driving circuit 021 relatively consistent with the path of the second data line DT2 corresponding to the second pixel driving circuit 022 connecting to the fourth transistor T4 of the second pixel driving circuit 022. This ensures that the lengths of the first data line DT1 and the second data line DT2 are basically the same, and their loads are also basically the same.

[0144] Therefore, the patterns of the POLY layer in the first pixel driving circuit 021 and the POLY layer in the second pixel driving circuit 022 can be symmetrically distributed in the first direction X, so that the fourth transistor T4 in the first pixel driving circuit 021 and the fourth transistor T4 in the second pixel driving circuit 022 are symmetrically distributed in the first direction X. In this way, without changing the position and length of the second data line DT2, it can be ensured that the path of the first data line DT1 into the first pixel driving circuit 021 is consistent with the path of the second data line DT2 into the second pixel driving circuit 022.

[0145] Meanwhile, data lines may overlap with other traces, generating coupling capacitance that affects the load on the data lines and potentially the capacitance of the nodes. Therefore, shielding is required between the film layer containing the data lines and the film layers containing other traces to shield the coupling capacitance. In the first pixel driving circuit 021, referring to Figure 8, the first shield P1, the second shield P2, and the third shield P3 can all be located on the GATE2 layer. Based on considerations of various traces and nodes, the size and location of the three shields differ. Furthermore, for a column of pixel driving circuits 02, the location distribution of the two types of data lines corresponding to that column is also different.

[0146] Therefore, in order to ensure that the loads of the first data line DT1 and the second data line DT2 are basically the same, the shielding part in the first pixel driving circuit 021 and the shielding part in the second pixel driving circuit 022 can also be symmetrically distributed in the first direction X. That is, the part of the GATE2 layer in the first pixel driving circuit 021 and the part of the GATE2 layer in the second pixel driving circuit 022 are symmetrically distributed in the first direction X.

[0147] For example, referring to Figures 8 and 18, in pixel driving circuit M2, which is also the first pixel driving circuit 021, a portion of the first data line DT1 overlaps with the third shielding portion P3, and a portion of the second data line DT2 overlaps with both the first shielding portion P1 and the second shielding portion P2. In pixel driving circuit M3, which is also the second pixel driving circuit 022, a portion of the second data line DT2 overlaps with the third shielding portion P3, and a portion of the first data line DT1 overlaps with both the first shielding portion P1 and the second shielding portion P2. That is, the three shielding portions in pixel driving circuit M2 are symmetrically distributed with the three shielding portions in pixel driving circuit M3. The first power line VDD has multiple second shielding portions P2, which correspond to multiple pixel driving circuits 02, and the second shielding portions P2 and their corresponding pixel driving circuits 02 can be distributed within the same sub-pixel region.

[0148] For two second shielding parts P2 arranged adjacently in the second direction Y within the same periodic partition, the orthographic projection of one second shielding part P2 on the substrate 01 overlaps with the orthographic projection of the first data line DT1 on the substrate 01, but does not coincide with the orthographic projection of the second data line DT2 on the substrate 01; the orthographic projection of the other second shielding part P2 on the substrate 01 overlaps with the orthographic projection of the second data line DT2 on the substrate 01, but does not coincide with the orthographic projection of the first data line DT1 on the substrate 01.

[0149] For example, referring to FIG18, for the periodic partition shown in FIG18, the orthographic projection of the second shield P2 corresponding to the pixel driving circuit M1 on the substrate 01 overlaps with the orthographic projection of the second data line DT2 on the substrate 01, and does not coincide with the orthographic projection of the first data line DT1 on the substrate 01. The orthographic projection of the second shield P2 corresponding to the pixel driving circuit M5 on the substrate 01 overlaps with the orthographic projection of the first data line DT1 on the substrate 01, and does not coincide with the orthographic projection of the second data line DT2 on the substrate 01.

[0150] For the two second shielding parts P2 arranged adjacently in the first direction X within the same periodic partition, the orthographic projection of the second shielding part P2 corresponding to the pixel driving circuit M2 on the substrate 01 overlaps with the orthographic projection of the second data line DT2 on the substrate 01, and does not coincide with the orthographic projection of the first data line DT1 on the substrate 01. Combining the above-mentioned overlap between the second shielding part P2 corresponding to the pixel driving circuit M1 and the first data line DT1 and the second data line DT2, it can be seen that the second shielding part P2 corresponding to the pixel driving circuit M1 and the second shielding part P2 corresponding to the pixel driving circuit M2 are not connected.

[0151] If the second shielding part P2 corresponding to the pixel driving circuit M1 is connected to the second shielding part P2 corresponding to the pixel driving circuit M2, the orthographic projection of the first data line DT1 corresponding to the pixel driving circuit M2 on the substrate O1 will overlap with the second shielding part P2, thereby increasing the overlap area between the first data line DT1 and the second shielding part P2, resulting in an increase in the load of the first data line DT1.

[0152] Therefore, in this embodiment, it is necessary to ensure that the second shielding part P2 corresponding to pixel driving circuit M1 is not connected to the second shielding part P2 corresponding to pixel driving circuit M2. Similarly, the second shielding part P2 corresponding to pixel driving circuit M3 is not connected to the second shielding part P2 corresponding to pixel driving circuit M4, the second shielding part P2 corresponding to pixel driving circuit M5 is not connected to the second shielding part P2 corresponding to pixel driving circuit M6, the second shielding part P2 corresponding to pixel driving circuit M6 is not connected to the second shielding part P2 corresponding to pixel driving circuit M7, and the second shielding part P2 corresponding to pixel driving circuit M7 is not connected to the second shielding part P2 corresponding to pixel driving circuit M8.

[0153] It should also be noted that the second shielding part P2 corresponding to the pixel driving circuit M2 and the second shielding part P2 corresponding to the pixel driving circuit M3 can be connected. This will not affect the overlap area between the data line and the second shielding part P2, and at the same time, it can reduce the load on the second shielding part P2.

[0154] Since the POLY layer portion in the first pixel driving circuit 021 and the POLY layer portion in the second pixel driving circuit 022 are symmetrically distributed in the first direction X, and the GATE2 layer portion in the first pixel driving circuit 021 and the GATE2 layer portion in the second pixel driving circuit 022 are also symmetrically distributed in the first direction X, in order to ensure that the overall driving effect of the first pixel driving circuit 021 and the second pixel driving circuit 022 is relatively consistent, other traces in the pixel driving circuit 02, such as the power auxiliary line SIP, the power auxiliary line SIP portion in the first pixel driving circuit 021 and the power auxiliary line SIP portion in the second pixel driving circuit 022 also need to be symmetrically distributed in the first direction X.

[0155] Therefore, for the first pixel driving circuit 021 and the second pixel driving circuit 022 arranged adjacent to each other in a column of pixel driving circuits 02, the pattern in the sub-pixel region where the first pixel driving circuit 021 is located and the pattern in the sub-pixel region where the second pixel driving circuit 022 is located are basically symmetrically distributed in the first direction X.

[0156] For example, referring to Figure 18, for pixel driving circuits M1 and M5 arranged adjacent to each other in the second direction Y, the pattern in the sub-pixel region where pixel driving circuit M1 is located is symmetrically distributed with respect to the pattern in the sub-pixel region where pixel driving circuit M5 is located in the first direction X. Similarly, pixel driving circuits M2 and M6 are symmetrically distributed, pixel driving circuits M3 and M7 are symmetrically distributed, and pixel driving circuits M4 and M8 are symmetrically distributed.

[0157] It should also be noted that, in one arrangement cycle shown in Figure 18, the pattern within the sub-pixel region where a row of pixel driving circuits 02 is located in the first direction X can be symmetrically distributed about a central first power line VDD. That is, pixel driving circuits M1 and M4 are symmetrically distributed, pixel driving circuits M2 and M3 are symmetrically distributed, pixel driving circuits M5 and M8 are symmetrically distributed, and pixel driving circuits M6 and M7 are symmetrically distributed.

[0158] Therefore, the routing and node distribution of the second pixel driving circuit 022 are similar to those of the first pixel driving circuit 021. Please refer to the description of the first pixel driving circuit 021 in the above embodiments, which will not be repeated here.

[0159] Referring to Figure 19, the driving backplane 100 may include a display area 100a and a non-display area 100b distributed around the display area 100a. Multiple pixel driving circuits 02, multiple first data lines DT1, and multiple second data lines DT2 are all located at least within the display area 100a.

[0160] The driver backplane 100 may further include a multiplexer 110 and multiple bonding pads 120. Both the multiplexer 110 and the bonding pads 120 can be located within the non-display area 100b, with the multiplexer 110 closer to the display area 100a than the bonding pads 120. One end of the multiplexer 110 can be electrically connected to a corresponding data line, and the other end can be electrically connected to a corresponding bonding pad 120. Simultaneously, the bonding pads 120 can be electrically connected to corresponding pads of the driver chip. In this way, the driver chip can transmit data signals to the data line through the bonding pads 120 and the multiplexer 110, enabling the pixel driving circuit 02 to start and charge.

[0161] It should be noted that the multiplexer 110 may have multiple first ports 111 on the side facing the display area 100a, and multiple second ports 112 on the side facing away from the display area 100a, with the number of second ports 112 being less than the number of first ports 111. The multiple first ports 111 can be electrically connected to multiple first data lines DT1 and multiple second data lines DT2, and the multiple second ports 112 can be electrically connected to multiple bonding pads 120. In this way, the driver chip can provide data signals to the multiple first data lines DT1 and multiple second data lines DT2 through the multiple bonding pads 120 and the multiplexer 110. Simultaneously, because the number of second ports 112 is smaller, the number of bonding pads 120 electrically connected to the second ports 112 is smaller, and consequently, the number of pads on the driver chip electrically connected to the bonding pads 120 is also reduced.

[0162] In summary, this application provides a driving backplane, which may include a substrate, and multiple pixel driving circuits, multiple first data lines, and multiple second data lines located on one side of the substrate. Multiple first pixel driving circuits in a column of pixel driving circuits can be electrically connected to a corresponding first data line, and multiple second pixel driving circuits in a column of pixel driving circuits can be electrically connected to a corresponding second data line. Thus, the two data lines can provide data signals to different pixel driving circuits respectively, ensuring that each pixel driving circuit has sufficient charging time, thereby improving the display effect of the display panel. Simultaneously, the signal output points of the first and / or second pixel driving circuits can be distributed between the corresponding first and second data lines in a first direction, and the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line, can both be greater than 0 in the first direction. This ensures a large distance between the first and second data lines, preventing them from interfering with each other; it also ensures a certain distance between the signal output point and both the first and second data lines, thereby reducing the impact of the data signals loaded on the first and second data lines on the signal output point, making the potential of the signal output point more stable, and further improving the display effect.

[0163] Please refer to Figures 1 to 2 and Figures 20 to 21. This application embodiment also provides a display panel 000, which may include the driving backplate 100 in the above embodiment and a plurality of light-emitting devices 200, which may be electrically connected to the driving backplate 100.

[0164] The driving backplane 100 may include a substrate 01, and multiple pixel driving circuits 02, multiple first data lines DT1 and multiple second data lines DT2 located on one side of the substrate 01.

[0165] Multiple pixel driving circuits 02 can be arranged in multiple columns along a first direction X and in multiple rows along a second direction Y. The extension directions of the first data line DT1 and the second data line DT2 can both be parallel to the second direction Y. Multiple columns of pixel driving circuits 02 can correspond to multiple first data lines DT1 and multiple second data lines DT2. A column of pixel driving circuits 02 can include multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022, and the multiple first pixel driving circuits 021 and multiple second pixel driving circuits 022 can be alternately arranged. Each of the multiple first pixel driving circuits 021 in a column of pixel driving circuits 02 can be electrically connected to a corresponding first data line DT1, and each of the multiple second pixel driving circuits 022 in a column of pixel driving circuits 02 can be electrically connected to a corresponding second data line DT2, and a first data line DT1 and a second data line DT2 can be located on both sides of the corresponding column of pixel driving circuits 02.

[0166] Thus, a row of pixel driving circuits 02 can correspond to a first data line DT1 and a second data line DT2, and these two data lines can provide data signals to different pixel driving circuits 02 respectively, thereby ensuring that each pixel driving circuit 02 has sufficient charging time, which in turn can improve the display effect of the display panel 000.

[0167] Any pixel driving circuit 02 can have a signal output point 023, which can be used to electrically connect to the light-emitting device 200.

[0168] The signal output points 023 in the first pixel driving circuit 021 and / or the second pixel driving circuit 022 can be distributed in the first direction X between the corresponding first data line DT1 and the corresponding second data line DT2. This ensures a large distance between the first data line DT1 and the second data line DT2, preventing mutual interference. Simultaneously, in the first direction X, the minimum distance between the signal output point 023 and the corresponding first data line DT1 can be greater than 0, and the minimum distance between the signal output point 023 and the corresponding second data line DT2 can also be greater than 0. This ensures that the signal output point 023 has a certain distance from both the first data line DT1 and the second data line DT2, thereby reducing the influence of the data signals loaded on the first data line DT1 and the second data line DT2 on the signal output point 023, making the potential of the signal output point 023 more stable, and further improving the display effect.

[0169] The light-emitting device 200 can be located on one side of the driving backplate 100. The light-emitting device 200 may include an anode 201, a light-emitting layer 202, and a cathode 203 stacked in a direction perpendicular to and away from the driving backplate 100. There may be multiple anodes 201. When a corresponding voltage is applied to the anode 201 and the cathode 203, the light-emitting layer 202 located between the anode 201 and the cathode 203 can emit light.

[0170] Multiple light-emitting devices 200 are electrically connected to multiple pixel driving circuits 02 of the driving backplate 100 in a one-to-one correspondence. The signal output point 023 of the pixel driving circuit 02 can be electrically connected to the first electrode 201 of the light-emitting device 200. Thus, the pixel driving circuit 02 can apply a corresponding voltage to the first electrode 201 of the corresponding light-emitting device 200 through the signal output point 023, thereby driving the corresponding light-emitting device 200 to emit light.

[0171] Multiple light-emitting devices 200 can be of different types, and different types of light-emitting devices 200 can emit light of different colors. Multiple pixel driving circuits 02 can drive multiple different types of light-emitting devices 200 to emit light, and the emitted light of different colors is mixed and superimposed, so that the display panel 000 can display the corresponding display image.

[0172] Please refer to Figure 21. The display panel 000 may also include a plurality of separately arranged first electrode blocks 300. The plurality of first electrode blocks 300 may correspond to a plurality of light-emitting devices 200, and the anode 201 in the light-emitting device 200 is at least a portion of the corresponding first electrode block 300.

[0173] Referring to Figures 21 and 22, the drive backplane 100 may include a first power line VDD, which may include multiple first sub-power lines VDD1 extending along the second direction Y, and multiple second sub-power lines VDD2 extending along the first direction X. The first sub-power lines VDD1 and the second sub-power lines VDD2 may be electrically connected at their intersections.

[0174] Optionally, the orthographic projection of the first electrode block 300 on the substrate 01 overlaps with the orthographic projections of the adjacent first data line DT1 and second data line DT2 on the substrate 01, and also overlaps with the orthographic projections of the two adjacent first sub-power lines VDD1 on the substrate 01.

[0175] In the first direction X, the adjacent first data lines DT1 and DT2 are distributed between two adjacent first sub-power lines VDD1. That is, the orthographic projections of the two adjacent first sub-power lines VDD1 on the substrate O1 overlap with the edge portion of the orthographic projection of the first electrode block 300 on the substrate O1. Simultaneously, in the first direction X, the width of the first sub-power line VDD1 is greater than the width of the first data line DT1 and greater than the width of the second data line DT2. This allows the edge of the first electrode block 300 to be formed more gently, improving the flatness of the first electrode block 300.

[0176] In summary, this application provides a display panel that may include a driving backplane and a plurality of light-emitting devices electrically connected to the driving backplane. A plurality of first pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding first data line, and a plurality of second pixel driving circuits in a column of pixel driving circuits may be electrically connected to a corresponding second data line. Thus, the two data lines can provide data signals to different pixel driving circuits respectively, thereby ensuring that each pixel driving circuit has sufficient charging time, and thus improving the display effect of the display panel. Simultaneously, the signal output points in the first pixel driving circuit and / or the second pixel driving circuit may be distributed between the corresponding first data line and the corresponding second data line in a first direction, and in the first direction, the minimum distance between the signal output point and the corresponding first data line, and the minimum distance between the signal output point and the corresponding second data line, may both be greater than 0. This ensures a large distance between the first and second data lines, preventing them from interfering with each other; it also ensures a certain distance between the signal output point and both the first and second data lines, thereby reducing the impact of the data signals loaded on the first and second data lines on the signal output point, making the potential of the signal output point more stable, and further improving the display effect.

[0177] This application also provides a display device, which can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0178] The display device may include a driver chip and a display panel. The display panel may be the display panel 000 described in the above embodiments, and the driver chip may be electrically connected to the display panel 000 to drive the display panel 000 to display an image.

[0179] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0180] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0181] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A drive backplane, characterized in that, Includes: a substrate, and multiple pixel driving circuits, multiple first data lines, and multiple second data lines located on one side of the substrate; The plurality of pixel driving circuits are arranged in multiple columns along a first direction and in multiple rows along a second direction; the extension directions of the first data line and the second data line are both parallel to the second direction; a column of the pixel driving circuits includes a plurality of first pixel driving circuits and a plurality of second pixel driving circuits, the plurality of first pixel driving circuits are electrically connected to a first data line, the plurality of second pixel driving circuits are electrically connected to a second data line, and the first data line and the second data line are located on both sides of a column of the pixel driving circuits; Both the first pixel driving circuit and the second pixel driving circuit have a signal output point, which is used to be electrically connected to the light-emitting device. The signal output points in the first pixel driving circuit and / or the second pixel driving circuit are distributed between the first data line and the second data line in the first direction, and in the first direction, the minimum distance between the signal output point and the first data line, and the minimum distance between the signal output point and the second data line are both greater than 0.

2. The drive backplane according to claim 1, characterized in that, In the first direction, the minimum distance between the signal output point in the first pixel driving circuit and the first data line is greater than or equal to the minimum distance between the signal output point in the first pixel driving circuit and the second data line. And / or, in the first direction, the minimum distance between the signal output point in the second pixel driving circuit and the second data line is greater than or equal to the minimum distance between the signal output point in the second pixel driving circuit and the first data line.

3. The drive backplane according to claim 1, characterized in that, The first pixel driving circuit and / or the second pixel driving circuit include: The first transistor has its gate electrically connected to the first reset signal line, its first terminal electrically connected to the first initial power line, and its second terminal electrically connected to the first node. The second transistor has its gate electrically connected to the gate signal line, its first terminal electrically connected to the third node, and its second terminal electrically connected to the first node. The third transistor has its gate electrically connected to the first node, its first electrode electrically connected to the third node, and its second electrode electrically connected to the second node. The fourth transistor has its gate electrically connected to the gate signal line, its first terminal electrically connected to the first data line or the second data line, and its second terminal electrically connected to the second node. The fifth transistor has its gate electrically connected to the light-emitting control signal line, its first terminal electrically connected to the first power supply line, and its second terminal electrically connected to the second node. The sixth transistor has its gate electrically connected to the light-emitting control signal line, its first electrode electrically connected to the third node, and its second electrode electrically connected to the signal output point. The seventh transistor has its gate electrically connected to the second reset signal line, its first terminal electrically connected to the second initial power supply line, and its second terminal electrically connected to the signal output point. A storage capacitor, wherein the first capacitor electrode of the storage capacitor is connected to the first power line, and the second capacitor electrode of the storage capacitor is electrically connected to the first node.

4. The drive backplane according to claim 3, characterized in that, The third node includes a first strip portion and a second strip portion, the first strip portion extending along the first direction and the second strip portion extending along the second direction; one end of the first strip portion is electrically connected to the second strip portion, the other end of the first strip portion is electrically connected to the first electrode of the third transistor, one end of the second strip portion is electrically connected to the first electrode of the second transistor, and the other end of the second strip portion is electrically connected to the first electrode of the sixth transistor. The orthographic projection of the second body portion in the first pixel driving circuit onto the substrate does not coincide with the orthographic projection of the second data line onto the substrate.

5. The drive backplane according to claim 4, characterized in that, The orthographic projection of the first body portion in the first pixel driving circuit onto the substrate has a first overlapping area with the orthographic projection of the second data line onto the substrate; The first power line has a first shielding portion, which is located between the first strip portion and the second data line in a direction perpendicular to the substrate, and the first overlapping area is located within the orthographic projection of the first shielding portion on the substrate.

6. The drive backplane according to claim 4, characterized in that, In the first direction, the minimum distance between the signal output point in the first pixel driving circuit and the second data line is greater than or equal to the minimum distance between the second body portion in the first pixel driving circuit and the second data line.

7. The drive backplane according to claim 4, characterized in that, The driving backplane further includes: a light-shielding layer, which is electrically connected to the first power line; the orthographic projections of the channel regions of the first transistor, the second transistor, the third transistor, and the fourth transistor on the substrate are all located within the orthographic projection of the light-shielding layer on the substrate; The light-shielding layer has a first light-shielding trace, the overall extension direction of the first light-shielding trace is parallel to the first direction, and the orthographic projection of the first light-shielding trace on the substrate does not coincide with the orthographic projection of the first strip portion on the substrate.

8. The drive backplate according to any one of claims 3 to 7, characterized in that, The driving backplane further includes: a power auxiliary line, the overall extension direction of which is parallel to the second direction, and the power auxiliary line has: auxiliary line segments distributed in the first direction between the first data line and the signal output points in the first pixel driving circuit. In the first direction, the minimum distance between the signal output point of the first pixel driving circuit and the auxiliary line segment is less than or equal to the minimum distance between the signal output point of the first pixel driving circuit and the second data line.

9. The drive backplane according to claim 8, characterized in that, The drive backplate further includes a light-shielding layer, which is electrically connected to the first power line. The light-shielding layer has a second light-shielding trace, the overall extension direction of the second light-shielding trace is parallel to the second direction, and the orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the power auxiliary line on the substrate.

10. The drive backplane according to claim 9, characterized in that, The first node includes a first part, a second part, and a third part. The first end of the first part, the first end of the second part, and the first end of the third part are electrically connected to each other. The second end of the first part is electrically connected to the second electrode of the first transistor. The second end of the second part is electrically connected to the second electrode of the second transistor. The second end of the third part is electrically connected to the gate of the third transistor. Wherein, the orthographic projection of the second light-shielding trace on the substrate overlaps with the orthographic projection of the first portion on the substrate.

11. The drive backplane according to claim 10, characterized in that, The orthographic projection of the first portion onto the substrate and the orthographic projection of the power supply auxiliary line onto the substrate have a second overlapping region; The first power line also has a second shielding portion, which is located between the first portion and the power auxiliary line in a direction perpendicular to the substrate, and the second overlapping area is located within the orthographic projection of the second shielding portion on the substrate.

12. The drive backplane according to claim 11, characterized in that, The power auxiliary line also has a transition region in its orthographic projection on the substrate that connects with the second overlapping region. The transition region is located outside the orthographic projection of the second light-shielding trace on the substrate and overlaps with the orthographic projection of the second shielding portion on the substrate.

13. The drive backplate according to any one of claims 3-7 and 9-12, characterized in that, The second node includes a third body portion and a fourth body portion, the third body portion extending along the first direction and the fourth body portion extending along the second direction; one end of the third body portion is electrically connected to the fourth body portion, the other end of the third body portion is electrically connected to the second electrode of the third transistor, one end of the fourth body portion is electrically connected to the second electrode of the fourth transistor, and the other end of the fourth body portion is electrically connected to the second electrode of the fifth transistor; Wherein, the orthographic projection of the third body portion in the first pixel driving circuit onto the substrate has a third overlapping area with the orthographic projection of the first data line onto the substrate; The first power line also has a third shielding portion, which is located between the third strip portion and the first data line in a direction perpendicular to the substrate, and the third overlapping area is located within the orthographic projection of the third shielding portion on the substrate.

14. The drive backplate according to any one of claims 3-7 and 9-12, characterized in that, In the first direction, the fourth transistor in the first pixel driving circuit is located on the side of the first data line away from the signal output point in the first pixel driving circuit, and the fourth transistor in the second pixel driving circuit is located on the side of the second data line away from the signal output point in the second pixel driving circuit. In the first direction, the minimum distance between the fourth transistor in the first pixel driving circuit and the first data line is equal to the minimum distance between the fourth transistor in the second pixel driving circuit and the second data line.

15. The drive backplate according to any one of claims 1-7 and 9-12, characterized in that, The driving backplane has multiple periodic partitions, and eight pixel driving circuits are distributed in one periodic partition, with the eight pixel driving circuits arranged in two rows and four columns. Within the same periodic partition, the two pixel driving circuits arranged in the second direction are respectively: a first pixel driving circuit and a second pixel driving circuit; the four pixel driving circuits arranged in the first direction are respectively: two first pixel driving circuits and two second pixel driving circuits arranged in succession.

16. The drive backplane according to claim 15, characterized in that, The driving backplate further includes: a first power line; the first power line has a plurality of second shielding portions, the plurality of second shielding portions corresponding to the plurality of pixel driving circuits, and the second shielding portions and the corresponding pixel driving circuits are distributed in the same sub-pixel region; Specifically, for two second shielding portions arranged adjacent to each other in the second direction within the same periodic partition, the orthographic projection of one second shielding portion on the substrate overlaps with the orthographic projection of the first data line on the substrate, but does not coincide with the orthographic projection of the second data line on the substrate; the orthographic projection of the other second shielding portion on the substrate overlaps with the orthographic projection of the second data line on the substrate, but does not coincide with the orthographic projection of the first data line on the substrate.

17. The drive backplate according to any one of claims 1-7 and 9-12, characterized in that, The drive backplate has a display area and a non-display area distributed around the display area; The plurality of pixel driving circuits, the plurality of first data lines, and the plurality of second data lines are all located at least within the display area; The drive backplane also includes a multiplexer and multiple bonding pads, wherein the multiplexer and the multiple bonding pads are both located in the non-display area, and the multiplexer is closer to the display area than the multiple bonding pads. The multiplexer has multiple first ports on the side facing the display area and multiple second ports on the side away from the display area. The multiple first ports are electrically connected to the multiple first data lines and the multiple second data lines, and the multiple second ports are electrically connected to the multiple bonding pads.

18. A display panel, characterized in that, include: The driving backplane according to any one of claims 1 to 17, and a plurality of light-emitting devices electrically connected to the driving backplane.

19. The display panel according to claim 18, characterized in that, The display panel further includes: a plurality of separately disposed first electrode blocks; the plurality of first electrode blocks correspond to the plurality of light-emitting devices, and the anode of the light-emitting device is at least a portion of the corresponding first electrode block; The drive backplane further includes: a first power line; the first power line includes: a plurality of first sub-power lines extending along the second direction, and a plurality of second sub-power lines extending along the first direction; the first sub-power lines and the second sub-power lines are electrically connected at their intersections; in the first direction, the width of the first sub-power line is greater than the width of the first data line and greater than the width of the second data line. Wherein, the orthographic projection of the first electrode block on the substrate overlaps with the orthographic projections of the adjacent first data lines and second data lines on the substrate, and also overlaps with the orthographic projections of the two adjacent first sub-power lines on the substrate; in the first direction, the adjacent first data lines and second data lines are distributed between the two adjacent first sub-power lines.

Images