Display substrate and display apparatus

Abstract

Disclosed in the present application are a display substrate and a display apparatus. The display substrate comprises a display region, a transition region, and a hole region, wherein the transition region surrounds the hole region, and the display region surrounds the transition region. The display substrate further comprises a base and a plurality of first signal lines located on one side of the base. Some of the first signal lines each comprise a first section, a connecting section, and a second section, which are connected in sequence, wherein the first section and the second section are located in the display region and both extend in a first direction, and the connecting section is located in the transition region. The first sections and the connecting sections of some of the first signal lines are located in different film layers, and the first sections and the second sections thereof are located in the same film layer. During part of the driving period of a picture frame, the valid periods of some adjacent first signal lines partially overlap with each other. By arranging the first signal lines in different film layers in the display region and the transition region, the present application controls the coupling between the first signal lines, thereby improving the display effect of a display panel.

Description

Display substrate and display device Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the development of mobile smart terminal devices such as smartphones and tablets, users have increasingly higher requirements for screen-to-body ratio. In order to improve the screen-to-body ratio of display devices, openings are usually set in the display devices, and cameras or sensors are placed below the openings.

[0003] However, one of the problems with this design is that the openings in the display device can cause display mura (a phenomenon where the brightness of the display is uneven, resulting in various marks) in some areas of the display panel. Summary of the Invention

[0004] The purpose of this application is to provide a display substrate with uniform display brightness and a display device.

[0005] This application discloses a display substrate, which includes a display area, a transition area, and an aperture area. The transition area surrounds the aperture area, and the display area surrounds the transition area. The display substrate includes: a substrate; a plurality of first signal lines located on one side of the substrate; some of the first signal lines include a first segment, a connecting segment, and a second segment connected in sequence, the first segment and the second segment being located in the display area and both extending along a first direction, and the connecting segment being located in the transition area; the first segment and the connecting segment of some of the first signal lines are located in different film layers, and the first segment and the second segment are located in the same film layer; during a portion of the driving time of a frame, the effective time periods of some adjacent first signal lines partially overlap.

[0006] Optionally, the first signal line includes a data signal line.

[0007] Optionally, the display substrate includes a substrate, a first conductive layer located on one side of the substrate, and a second source / drain metal layer located on the side of the first conductive layer away from the substrate; the first conductive layer and the second source / drain metal layer are insulated from each other; wherein in a portion of the first signal line, a first segment and a second segment are located in the second source / drain metal layer, and a connection segment is located in the first conductive layer.

[0008] Optionally, the display substrate includes a substrate, a metal conductive layer located on one side of the substrate, and a second source / drain metal layer located on the side of the metal conductive layer away from the substrate; the metal conductive layer and the second source / drain metal layer are insulated from each other; wherein in a portion of the first signal line, a first segment and a second segment are located in the second source / drain metal layer, and a connection segment is located in the metal conductive layer.

[0009] Optionally, the display substrate further includes a first source / drain metal layer located between the first conductive layer and the second source / drain metal layer; the first source / drain metal layer is provided with shielded signal lines.

[0010] Optionally, the display substrate further includes a second conductive layer located between the metal conductive layer and the second source / drain metal layer, and a first source / drain metal layer located between the second conductive layer and the second source / drain metal layer; the second conductive layer and / or the first source / drain metal layer are provided with shielded signal lines.

[0011] Optionally, the orthogonal projection of the shielded signal line onto the substrate overlaps the orthogonal projection of the connection segment located in the second source / drain metal layer onto the substrate.

[0012] Optionally, the orthographic projection of the shielded signal line onto the substrate overlaps with the orthographic projection of the connection segment located in the second source / drain metal layer onto the substrate.

[0013] Optionally, the shielded signal line is a first power signal line and / or a second power signal line, wherein one of the first power signal line and the second power signal line is connected to the anode of the light-emitting unit, and the other is connected to the cathode of the light-emitting unit.

[0014] Optionally, the shielded signal line is a reset signal line, which is connected to the pixel driving circuit and used to reset the pixel circuit.

[0015] Optionally, the data signal lines of the display substrate are divided into multiple data signal line groups, each data signal line group including eight data signal lines. The same data signal line group includes data signal lines 8k-7 to 8k, which are sequentially arranged along a second direction in the second source / drain metal layer within the display area. In the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to the same column of pixels, and data signal lines 8k-5 and 8k-4 are connected to the same column of pixels. The data signal lines are connected as follows: the (8k-3)th and (8k-2)th data signal lines are connected to the same column of pixels; the (8k-1)th and (8k)th data signal lines are connected to the same column of pixels; the (8k-7), (8k-5), (8k-2), and (8k)th data signal lines are connected to one of the odd-numbered and even-numbered rows of pixels; the (8k-6), (8k-4), (8k-3), and (8k-1)th data signal lines are connected to the other of the odd-numbered and even-numbered rows of pixels; the second direction intersects the first direction; k is an integer greater than 0.

[0016] Optionally, the display substrate further includes: a source driving circuit, the source driving circuit including a plurality of source driving transistors; a plurality of source signal lines, divided into a plurality of source signal line groups, each source signal line group including a first source signal line and a second source signal line; in the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line, and the first source signal line and the second source signal line connected to the data line number line of the same data signal line group belong to the same source signal line group; each data signal line is connected to the source signal line through a source driving transistor; a first multiplexed signal line to a fourth multiplexed signal line are connected to the gate of the source driving transistor and configured to control the connection between the source signal line and the data signal line; in the same data signal line group, the 8k-7th data signal line is connected to the first source signal line in the first source signal line group. The 8k-6 data signal line is connected to the first source signal line under the control of a third multiplexed signal line; the 8k-5 data signal line is connected to the first source signal line under the control of a second multiplexed signal line; the 8k-4 data signal line is connected to the first source signal line under the control of a fourth multiplexed signal line; the 8k-3 data signal line is connected to the second source signal line under the control of a third multiplexed signal line; the 8k-2 data signal line is connected to the second source signal line under the control of a first multiplexed signal line; the 8k-1 data signal line is connected to the second source signal line under the control of a fourth multiplexed signal line; and the 8k data signal line is selectively connected to the second source signal line under the control of a second multiplexed signal line.

[0017] Optionally, within the transition region, the data signal lines in each data signal line group are arranged in the order of 8k-7, 8k-5, 8k-6, 8k-4, 8k-3, 8k-1, 8k-2, and 8k data signal lines; wherein the connection segments of the 8k-7, 8k-6, 8k-3, and 8k-2 data signal lines are disposed in one of the second source / drain metal layers and the first conductive layer, and the connection segments of the 8k-5, 8k-4, 8k-1, and 8k data signal lines are disposed in the other of the second source / drain metal layers and the first conductive layer.

[0018] Optionally, within the transition zone, the orthographic projections of the 8k-5 data signal line and the 8k-6 data signal line on the substrate at least partially overlap, and the orthographic projections of the 8k-2 data signal line and the 8k-1 data signal line on the substrate at least partially overlap.

[0019] Optionally, within the transition region, the data signal lines in each data signal line group are arranged in the order of 8k-7, 8k-6, 8k-4, 8k-5, 8k-2, 8k-3, 8k-1, and 8k data signal lines; wherein the connection segments of the 8k-7, 8k-4, 8k-2, and 8k-1 data signal lines are disposed in one of the second source / drain metal layers and the first conductive layer, and the connection segments of the 8k-6, 8k-5, 8k-3, and 8k data signal lines are disposed in the other of the second source / drain metal layers and the first conductive layer.

[0020] Optionally, within the transition zone, the orthographic projections of the 8k-4 data signal line and the 8k-5 data signal line on the substrate at least partially overlap, and the orthographic projections of the 8k-2 data signal line and the 8k-3 data signal line on the substrate at least partially overlap.

[0021] Optionally, within the transition region, the data signal lines in each data signal line group are arranged in the following order: the 8k data signal line from the previous data signal line group, the 8k-6, 8k-5, 8k-3, 8k-4, 8k-2, and 8k-1 data signal lines of the current group, and the 8k-7 data signal line of the next group. The connection segments of the 8k data signal lines from the previous group, the 8k-5, 8k-4, and 8k-1 data signal lines of the current group are disposed in one of the second source / drain metal layers and the first conductive layer, while the connection segments of the 8k-6, 8k-3, 8k-2, and 8k-7 data signal lines of the next group are disposed in the other of the second source / drain metal layers and the first conductive layer.

[0022] Optionally, within the transition zone, the orthographic projections of the 8k data signal line in the previous data signal line group and the 8k-7 data signal line in this group on the substrate at least partially overlap, and the orthographic projections of the 8k-3 data signal line and the 8k-4 data signal line in this group on the substrate at least partially overlap.

[0023] This application also discloses a display substrate, the display substrate including a display area, a transition area, and an aperture area, the transition area surrounding the aperture area, and the display area surrounding the transition area; the display substrate includes: a substrate; a plurality of data signal lines located on one side of the substrate; the plurality of data signal lines are divided into a plurality of data signal line groups, each data signal line group including eight data signal lines, the same data signal line group including data signal lines 8k-7 to 8k, the data signal lines 8k-7 to 8k are arranged sequentially in a second direction within the display area; in the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to the same column of pixels, data signal lines 8k-5 and 8k-4 are connected to the same column of pixels, data signal lines 8k-3 and 8k-2 are connected to the same column of pixels, and so on. Data signal lines 8k-1 and 8k are connected to pixels in the same column; data signal lines 8k-7, 8k-5, 8k-2, and 8k are connected to one of the odd-numbered and even-numbered rows of pixels; data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are connected to the other of the odd-numbered and even-numbered rows of pixels; k is an integer greater than 0; some of the data signal lines include a first segment, a connecting segment, and a second segment connected in sequence, the first segment and the second segment are located in the display area and both extend along a first direction, and the connecting segment is located in the transition area; the first segment and the connecting segment of some data signal lines are located in different film layers, and the first segment and the second segment are located in the same film layer; the second direction intersects the first direction.

[0024] This application also discloses a display device, which includes the display substrate described above.

[0025] Compared with related technologies, this application improves the display effect of the display panel by setting the first signal line on different film layers in the display area and the transition area.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0028] Figure 1 is a planar schematic diagram of the display substrate of this application.

[0029] Figure 2 is a schematic diagram of partial circuit connections of the display substrate of this application.

[0030] Figure 3 is a schematic diagram of partial circuit connections of the display substrate of this application.

[0031] Figure 4 is a schematic diagram of the layer hierarchy of the display substrate of this application in one embodiment.

[0032] Figure 5 is a schematic diagram of the pixel driving circuit of the display substrate of this application.

[0033] Figure 6 is a partially enlarged schematic diagram of region A in Figure 1 in one embodiment.

[0034] Figure 7 is a timing diagram of the operation of the display substrate of this application.

[0035] Figure 8 is a cross-sectional schematic diagram of the display substrate of this application along line BB in Figure 1.

[0036] Figure 9 is a cross-sectional schematic diagram of the display substrate of this application along the CC line in Figure 1 in one embodiment.

[0037] Figure 10 is a cross-sectional schematic diagram of the display substrate of this application along line CC in Figure 1 in one embodiment.

[0038] Figure 11 is a cross-sectional schematic diagram of the display substrate of this application along line CC in Figure 1 in one embodiment.

[0039] Figure 12 is a cross-sectional schematic diagram of the display substrate of this application along the CC line in Figure 1 in one embodiment.

[0040] Figure 13 is a cross-sectional schematic diagram of the display substrate of this application along line CC in Figure 1 in one embodiment.

[0041] Figure 14 is a partially enlarged schematic diagram of region A in Figure 1 in one embodiment.

[0042] Figure 15 is a schematic diagram of the layer hierarchy of the display substrate of this application in one embodiment. Detailed Implementation

[0043] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0044] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0045] As shown in Figure 1, a display substrate typically includes a display area 1000 and a bezel area 4000. Some display substrates have holes punched within the display area 1000 to form hole areas 3000. These hole areas 3000 can be used to house front-facing cameras or other sensors. The display panel also includes a transition area 2000 located between the display area 1000 and the hole areas. The traces on the display substrate are located within the transition area 2000 surrounding the hole areas 3000 to avoid them.

[0046] As shown in Figures 1 to 3, the display substrate includes a plurality of first signal lines 100 extending along a first direction F1. Some of the first signal lines 100 include a first segment 110, a connecting segment 120, and a second segment 130 connected in sequence. Both the first segment 110 and the second segment 130 are located in the display area 1000 and extend along the first direction F1. The connecting segment 120 is located in the transition area 2000 and is disposed around the hole area 3000, and its shape matches the shape of a portion of the edge of the hole area 3000. For example, please also refer to Figure 6, which is a partially enlarged schematic diagram of area A in Figure 1. In an optional embodiment, the hole area 3000 is a circular hole area, and the side of the connecting segment 120 away from the hole area 3000 continues the extending direction of the first segment 110 and the second segment 130. The side of the connecting segment 120 near the hole area 3000 can be arc-shaped around the circular hole area. When the hole area 3000 has other shapes, the connecting segment 120 can also be in other suitable shapes surrounding the hole area 3000. The first section 110 and the second section 130 are connected by a connecting section 120. The first section 110 and the second section 130 can be connected to the connecting section 120 through a via 140, which can be set by an adapter block.

[0047] The display substrate also includes a plurality of second signal lines 200 extending along a second direction F2. A first direction F1 intersects with the second direction F2; the first direction F1 can be the length direction of the display substrate, and the second direction F2 can be the width direction of the display substrate. The first signal lines 100 can be data signal lines, and the second signal lines 200 can be scan signal lines, etc.

[0048] When the first signal line 100 is a data signal line and the second signal line 200 is a scan signal line, the data signal lines and scan signal lines jointly control the pixels on the control panel. Specifically, the data signal lines extend along the first direction F1, and the data signal lines (D1, D2, ...) are arranged along the second direction F2. The scan signal lines extend along the second direction F2, and the scan signal lines (G1, G2, ...) are arranged along the first direction F1. Each data signal line cooperates with each scan signal line to control the light emission of a light-emitting unit 300. For example, D1 cooperates with G1, D1 cooperates with G2, D2 cooperates with G2, and so on.

[0049] The scan signal line can be connected to the shift register unit GOA located in the border area 4000. Specifically, a shift register unit GOA is connected to a scan signal line to control the light-emitting units 300 located in the same row of the display panel.

[0050] Data signal lines can be connected to a source driver module IC located in the frame area 4000. Specifically, for example, data signal line D1 is connected to the second terminal of a source driver transistor, the control terminal of which is connected to a multiplexed signal line MUX1, and the first terminal of which is connected to a source signal line S1. The source signal line S1 is then connected to the source driver module IC. Thus, data signal line S1 is connected to the source driver module IC under the control of the multiplexed signal in multiplexed signal line MUX1. Other data signal lines are also connected to the source driver module IC through this configuration.

[0051] As shown in Figure 5, Figure 5 illustrates a pixel driving circuit for a display panel pixel in one embodiment. The pixel driving circuit includes a first transistor T1 to an eighth transistor T8. The third transistor T3 is a driving transistor. The gate driving signal line is connected to the control electrode Gate_N of the second transistor T2 and the control electrode Gate_P of the fourth transistor T4, and the data signal line is connected to the first electrode Data of the fourth transistor T4. Thus, the gate driving signal GT can control the data signal Data to be written to the first node N1. The first node N1 is connected to the control electrode of the third transistor T3, so the data signal Data can control the driving transistor and thus control the light emission of the light-emitting unit 300. Of course, in other embodiments, the pixel driving circuit can be a circuit with other structures, such as a 2T1C, 4T1C, 7T1C, etc.

[0052] As shown in Figure 4, the display substrate may include a substrate 10, an active layer 11 located on the side of the substrate 10 near the display side, a first gate insulating layer 12 located on the side of the active layer 11 away from the substrate 10, a first conductive layer 20 (GT1) located on the side of the first gate insulating layer 12 away from the active layer 11, a second gate insulating layer 21 located on the side of the first conductive layer 20 away from the first gate insulating layer 12, a second conductive layer 30 (GT2) located on the side of the second gate insulating layer 21 away from the first conductive layer 20, and interlayer insulation located on the side of the second conductive layer 30 away from the second gate insulating layer 21. The system comprises: a layer 31; a first source / drain metal layer 40 (SD1) located on the side of the interlayer insulating layer 31 away from the second conductive layer 30; a passivation layer 41 located on the side of the first source / drain metal layer 40 away from the interlayer insulating layer 31; a first planarization layer 42 located on the side of the passivation layer 41 away from the first source / drain metal layer 40; a second source / drain metal layer 50 (SD2) located on the side of the first planarization layer 42 away from the passivation layer 41; a second planarization layer 51 located on the side of the second source / drain metal layer 50 away from the first planarization layer 42; a light-emitting device located on the side of the second planarization layer 51 away from the second source / drain metal layer 50; and a packaging structure 60. The third direction F3 can be the thickness direction of the display substrate. Signal lines such as the first signal line 100 and the second signal line 200, which transmit signals, can be disposed on the first conductive layer 20 (GT1), the second conductive layer 30 (GT2), the first source / drain metal layer 40 (SD1), or the second source / drain metal layer 50 (SD2). The first segment 110 and the connecting segment 120 of the first signal line 100 are located in different film layers, while the first segment 110 and the second segment 130 are located in the same film layer.

[0053] As shown in Figure 7, this figure illustrates the timing of the data signal Data, the multiplexed signal MUX, and the gate drive signal GT on the display substrate. The data signal Data is transmitted via the data signal line, the multiplexed signal MUX is transmitted via the multiplexed signal line, and the gate drive signal GT is transmitted via the scan signal line.

[0054] During the period from H(i-2) to H(i), the multiplexed signal MUX1 first enters the falling edge, maintains a low potential for a period, and then enters the rising edge. When the multiplexed signal MUX1 first enters the falling edge, the data signal line and the source signal line are connected, and the corresponding data signal Data R enters the active segment. For example, in this embodiment, the data signal Data R changes from a high potential to a low potential. When the multiplexed signal MUX1 enters the rising edge, the active segment of the corresponding data signal Data R is in a floating state until the next falling edge of the multiplexed signal MUX1 arrives. When the active segment of the data signal Data R is in a floating state, the multiplexed signals MUX2, MUX3, and MUX4 enter the falling edge one after another, and the data signals Data G1, Data B, and Data G2 change from a high potential to a low potential and enter the active segment one after another, respectively undergoing potential changes of ΔV1, ΔV2, and ΔV3. In the panel, Data R, Data G1, Data B, and Data G2 are located in adjacent data signal lines, as shown in Figure 7. During part of the driving period of a frame, their low potential segments, i.e., the active segments, will partially overlap in timing. Of course, in other embodiments, the effective segment can be a high-potential segment or other forms of potential segment. Referring to Figure 6, since some data signal lines change their routes to bypass the hole area 3000 in the display panel, the distance between the connection segments 120 of some data signal lines will be smaller than the distance between the first segment 110 and the second segment 130. Since the connection segments 120 of the data signal lines containing data signals Data G1, Data B, and Data G2 are closer to the connection segments 120 of the data signal line containing data signal Data R, ΔV1, ΔV2, and ΔV3 will interfere with the floating data signal Data R. When the gate drive signal GT(E) corresponding to the data signal Data R changes to a low-potential segment, the interfered data signal DataR is written into the first node N1 of the pixel drive circuit, thereby affecting the opening degree of the drive transistor T3, and ultimately affecting the normal light emission of the light-emitting unit 300, causing uneven display on the display panel.

[0055] As shown in Figures 1 to 3 and Figure 8, Figure 8 is a cross-sectional view along line BB in Figure 1. The data signal lines of the display substrate are divided into multiple data signal line groups, each data signal line group includes eight data signal lines, and the same data signal line group includes data signal lines 8k-7 to 8k.

[0056] As shown in Figure 8, data signal lines 8k-7 to 8k are arranged sequentially along the second direction F2 within the display area 1000. Specifically, data signal lines 8k-7 to 8k are arranged sequentially along the second direction F2 on the second source-drain metal layer SD2. Each square cross-section in Figure 8 represents a data signal line, and the number in the square cross-section indicates which multiplexed signal line controls the connection to the source driver module IC. k is an integer greater than 0.

[0057] As shown in Figure 3, in the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to pixels in the same column; data signal lines 8k-5 and 8k-4 are connected to pixels in the same column; data signal lines 8k-3 and 8k-2 are connected to pixels in the same column; and data signal lines 8k-1 and 8k are connected to pixels in the same column. Data signal lines 8k-7, 8k-5, 8k-2, and 8k are connected to one of the odd-numbered and even-numbered rows of pixels, while data signal lines 8k-6, 8k-4, 8k-3, and 8k-1 are connected to the other of the odd-numbered and even-numbered rows of pixels. Optionally, data signal lines 8k-7, 8k-6, 8k-3, and 8k-2 control red and blue pixels, while data signal lines 8k-5, 8k-4, 8k-1, and 8k control green pixels. In the display panel, odd-numbered columns are set with red and blue pixels, and even-numbered columns are set with green pixels. Of course, the positions of the green pixels and the red and blue pixels can be interchanged, simply by correspondingly swapping the positions of the data signal lines.

[0058] The display substrate also includes a source driving circuit, multiple source signal lines, and multiple multiplexed signal lines. The source driving circuit includes multiple source driving transistors. For example, the source driving circuit can be located in the lower border area of ​​the display substrate border area 4000, or it can be located in the display area 1000, without limitation.

[0059] Multiple source signal lines are divided into multiple source signal line groups. Each source signal line group includes a first source signal line and a second source signal line. Within the same data signal line group, four adjacent data signal lines are connected to the first source signal line, and another four adjacent data signal lines are connected to the second source signal line. The first and second source signal lines connected to the data lines of the same data signal line group belong to the same source signal line group. Each data signal line is connected to the source signal line through a source driver transistor.

[0060] The first multiplexed signal lines MUX1 to MUX4 are connected to the gates of the source drive transistors and are configured to control the connection between the source signal lines and the data signal lines. Within the same data signal line group, data signal line 8k-7 is connected to the first source signal line under the control of the first multiplexed signal line MUX1. Data signal line 8k-6 is connected to the first source signal line under the control of the third multiplexed signal line MUX3. Data signal line 8k-5 is connected to the first source signal line under the control of the second multiplexed signal line MUX2. Data signal line 8k-4 is connected to the first source signal line under the control of the fourth multiplexed signal line MUX4. Data signal line 8k-3 is connected to the second source signal line under the control of the third multiplexed signal line MUX3. Data signal line 8k-2 is connected to the second source signal line under the control of the first multiplexed signal line MUX1. Data signal line 8k-1 is connected to the second source signal line under the control of the fourth multiplexed signal line MUX4. The 8k data signal line is selectively connected to the second source signal line under the control of the second multiplexed signal line MUX2.

[0061] For example, as shown in Figure 3, data signal lines D1 to D8 belong to the same data signal line group, and source signal lines S1 and S2 belong to the same source signal line group. Data signal lines D1 to D4 are connected to source signal line S1 through four source drive transistors, respectively. The control terminals of the four source drive transistors are connected to multiplexed signal lines MUX1, MUX3, MUX2, and MUX4, respectively. Data signal lines D5 to D8 are connected to source signal line S2 through four source drive transistors, respectively. The control terminals of the four source drive transistors are connected to multiplexed signal lines MUX3, MUX1, MUX4, and MUX2, respectively.

[0062] As shown in Figures 6, 8, 9, and 10, some data signal lines in the display area 1000 are wound when entering the transition area 2000. Specifically, the first segment 110 and the second segment 130 of the data signal lines are wound at the junction with the connecting segment 120. Some data signal lines are wound from the second source / drain metal layer SD2 through via 140 to the first conductive layer GT1. The via 140 can be configured using an adapter block. For example, in this embodiment, the arrangement of the data signal lines in the display area 1000, i.e., the arrangement of the first segment 110 and the second segment 130 of the display area 1000, is shown in Figure 8. Data signal lines 8k-7 to 8k are arranged sequentially along the second direction F2 within the display area 1000. The specific arrangement has been described above and will not be repeated here. As shown in Figure 9, Figure 9 is a cross-sectional schematic diagram along line CC in Figure 1 in an optional embodiment. Within the transition region 2000, the data signal lines, i.e., the connection segments 120, in each data signal line group are arranged in the order of the 8k-7 data signal line, the 8k-5 data signal line, the 8k-6 data signal line, the 8k-4 data signal line, the 8k-3 data signal line, the 8k-1 data signal line, the 8k-2 data signal line, and the 8k data signal line. Specifically, the connection segments 120 for the 8k-7, 8k-6, 8k-3, and 8k-2 data signal lines are located in one of the second source / drain metal layers SD2 and the first conductive layer GT1, while the connection segments 120 for the 8k-5, 8k-4, 8k-1, and 8k data signal lines are located in the other of the second source / drain metal layers SD2 and the first conductive layer GT1. In an optional embodiment, a metal conductive layer 101 (BSM) is further disposed between the substrate 10 and the active layer 11 within the transition region 2000. The connection segment 120 disposed in the first conductive layer GT1 in the above example can be disposed in the metal conductive layer BSM. As shown in FIG6, because the winding changes the arrangement order of the data signal lines, the orthographic projections of some data signal lines onto the substrate 10 after winding will partially overlap. In this embodiment, within the transition region 200, the orthographic projections of the 8k-5 data signal line and the 8k-6 data signal line on the substrate at least partially overlap, and the orthographic projections of the 8k-2 data signal line and the 8k-1 data signal line on the substrate at least partially overlap, thereby achieving the interchange of the data signal line arrangement order.

[0063] As shown in Figures 8 and 11, in an optional embodiment, the arrangement of the data signal lines of the display area 1000, i.e., the arrangement of the first segment 110 and the second segment 130 of the display area 1000, is shown in Figure 8. The specific arrangement has been described above and will not be repeated here. As shown in Figure 11, Figure 11 is a cross-sectional schematic diagram along line CC in Figure 1 in an optional embodiment. Within the transition area 2000, the data signal lines in each data signal line group, i.e., the connecting segment 120, are arranged in the order of the 8k-7 data signal line, the 8k-6 data signal line, the 8k-4 data signal line, the 8k-5 data signal line, the 8k-2 data signal line, the 8k-3 data signal line, the 8k-1 data signal line, and the 8k data signal line. The connection segment 120 of the 8k-7 data signal line, the 8k-4 data signal line, the 8k-2 data signal line, and the 8k-1 data signal line is disposed in one of the second source / drain metal layers SD2 and the first conductive layer GT1, and the connection segment 120 of the 8k-6 data signal line, the 8k-5 data signal line, the 8k-3 data signal line, and the 8k data signal line is disposed in the other of the second source / drain metal layers SD2 and the first conductive layer GT1. In an optional embodiment, a metal conductive layer 101 (BSM) is further disposed between the substrate 10 and the active layer 11 within the transition region 2000. The connection segment 120 of data signal lines 8k-7, 8k-4, 8k-1, and 8k-2 is disposed in one of the second source / drain metal layers SD2 and the metal conductive layer BSM, and the connection segment 120 of data signal lines 8k-5, 8k-6, 8k-3, and 8k is disposed in the other of the second source / drain metal layers SD2 and the metal conductive layer BSM. As shown in Figure 6, because the winding changes the arrangement order of the data signal lines, the orthographic projections of some data signal lines onto the substrate 10 after winding will partially overlap. In this embodiment, within the transition region 200, the orthographic projections of data signal lines 8k-4 and 8k-5 onto the substrate at least partially overlap, and the orthographic projections of data signal lines 8k-2 and 8k-3 onto the substrate at least partially overlap, thereby achieving the interchange of the data signal line arrangement order.

[0064] As shown in Figures 8 and 12. In an optional embodiment, the arrangement of the data signal lines of the display area 1000, i.e., the arrangement of the first segment 110 and the second segment 130 of the display area 1000, is shown in Figure 8. The specific arrangement has been described above and will not be repeated here. As shown in Figure 12, Figure 12 is a cross-sectional schematic diagram along line CC in Figure 1 in an optional embodiment. Within the transition area 2000, the data signal lines in each data signal line group, i.e., the connecting segment 120, are arranged in the following order: the 8k data signal line in the previous data signal line group, the 8k-6 data signal line, the 8k-5 data signal line, the 8k-3 data signal line, the 8k-4 data signal line, the 8k-2 data signal line, the 8k-1 data signal line in this group, and the 8k-7 data signal line in the next group. In this embodiment, the connection segment 120 of the 8k data signal line in the previous group, the 8k-5 data signal line, the 8k-4 data signal line, and the 8k-1 data signal line in this group is disposed in one of the second source / drain metal layers SD2 and the first conductive layer GT1. The connection segment 120 of the 8k-6 data signal line, the 8k-3 data signal line, the 8k-2 data signal line, and the 8k-7 data signal line in the next group is disposed in the other of the second source / drain metal layers SD2 and the first conductive layer GT1. In an optional embodiment, a metal conductive layer 101 (BSM) is further disposed between the substrate 10 and the active layer 11 within the transition region 2000. The connection segment 120 of the 8k data signal line in the previous group, the 8k-6 data signal line, the 8k-4 data signal line, and the 8k-2 data signal line in this group is disposed in one of the second source / drain metal layers SD2 and the metal conductive layer BSM. The connection segment 120 of the 8k-5 data signal line, the 8k-3 data signal line, the 8k-1 data signal line, and the 8k-7 data signal line in the next group is disposed in the other of the second source / drain metal layers SD2 and the metal conductive layer BSM. As shown in Figure 6, because the winding changes the arrangement order of the data signal lines, the orthographic projection of some data signal lines onto the substrate 10 after winding will partially overlap. In this embodiment, within the transition region 200, the orthographic projections of the 8k data signal line in the previous group and the 8k-7 data signal line in this group on the substrate at least partially overlap, and the orthographic projections of the 8k-3 data signal line and the 8k-4 data signal line in this group on the substrate at least partially overlap, thereby realizing the interchange of the data signal line arrangement order.

[0065] The winding method shown in Figures 9, 10, 11, and 12 can reduce the coupling between data signal lines within the aperture area, improve the display unevenness of some pixels, and improve the brightness difference and color shift of pixels controlled by the data signal lines in the aperture area 3000. When a portion of the connection segment 120 is disposed on the metal conductive layer BSM, since the distance between the metal conductive layer BSM and the second source / drain metal layer SD2 is greater than the distance between the first conductive layer GT1 and the second source / drain metal layer SD2, the coupling between data signal lines of different layers can be reduced more effectively.

[0066] As shown in Figures 4, 13, and 14, in an optional embodiment, the first segment 110 and the second segment 130 of some data signal lines are disposed on the second source-drain metal layer SD2, and the connecting segment 120 is disposed on the first conductive layer GT1. The first segment 110 and the second segment 130 of some data signal lines are disposed on the second source-drain metal layer SD2, and the connecting segment 120 is also disposed on the second source-drain metal layer SD2. The second conductive layer GT2 and the first source-drain metal layer SD1 are further disposed between the first conductive layer GT1 and the second source-drain metal layer SD2, and are mutually insulated. The first source-drain metal layer SD1 is provided with a shielded signal line 150. The shielded signal line 150 can minimize the mutual interference between the connecting segment 120 located between the first conductive layer GT1 and the second source-drain metal layer SD2, thereby ensuring the normal writing of data signals and thus ensuring uniform light emission of the display panel. Actual measurements showed that after setting the shielded signal line to 150, the coupling capacitance between adjacent data signal lines on the same layer decreased by about 1 / 3, and the coupling capacitance between adjacent data signal lines on different layers decreased by about 1 / 4.

[0067] As shown in Figures 13, 14, and 15, in an optional embodiment, the first segment 110 and the second segment 130 of some data signal lines are disposed on the second source-drain metal layer SD2, and the connecting segment 120 is disposed on the metal conductive layer BSM. The first segment 110 and the second segment 130 of some data signal lines are disposed on the second source-drain metal layer SD2, and the connecting segment 120 is also disposed on the second source-drain metal layer SD2. A first conductive layer GT1, a second conductive layer GT2, and a first source-drain metal layer SD1 are further disposed between the metal conductive layer BSM and the second source-drain metal layer SD2, and these layers are mutually insulated. The second conductive layer GT2 and / or the first source-drain metal layer SD1 are provided with a shielded signal line 150. The shielded signal line 150 can minimize the mutual interference between the connection segment 120 located between the metal conductive layer BSM and the second source / drain metal layer SD2, thereby ensuring the normal writing of data signals and thus ensuring the uniform illumination of the display panel.

[0068] Referring to Figure 14, optionally, the shielded signal line 150 can be a first power signal line VDD and / or a second power signal line VSS and / or a reset signal line Vinit. Referring to Figure 5, the first power signal line VDD is a signal line connected to the anode of the light-emitting unit 300, the second power signal line VSS is a signal line connected to the cathode of the light-emitting unit 300, and the reset signal line Vinit is a signal line connected to the reset signal terminals (Vinit1, Vinit2, Vinit3) of the pixel driving circuit, which is used to reset the pixel driving circuit. Since the first power signal line VDD, the second power signal line VSS, and the reset signal line Vinit all transmit regulated DC signals, the side effect of the shielded signal line 150 coupling to the data signal line can be ignored.

[0069] As shown in Figures 4 and 13, the orthogonal projection of the shielded signal line 150 onto the substrate 10 can cover the orthogonal projection of the connection segment 120 located in the second source / drain metal layer SD2 onto the substrate 10. Optionally, the orthogonal projection of the shielded signal line 150 onto the substrate 10 covers the orthogonal projection of the connection segment 120 located in the first conductive layer GT1 or the metal conductive layer BSM onto the substrate 10. That is, the width of the shielded signal line 150 is greater than the width of the connection segment 120, thereby minimizing the coupling between data signal lines of different layers. Optionally, the orthogonal projection of the shielded signal line 150 onto the substrate 10 partially overlaps with the orthogonal projection of the connection segment 120 located in the second source / drain metal layer SD2 onto the substrate 10. Furthermore, the orthogonal projection of the shielded signal line 150 onto the substrate 10 partially overlaps with the orthogonal projection of the connection segment 120 located in the first conductive layer GT1 or the metal conductive layer BSM onto the substrate 10.

[0070] As shown in Figures 1, 4, 8 and 9, this application also provides a display substrate, the display substrate including a display area 1000, a transition area 2000 and an aperture area 3000, the transition area 2000 surrounding the aperture area 3000, and the display area 1000 surrounding the transition area 2000.

[0071] The display substrate includes:

[0072] Base 10;

[0073] Multiple data signal lines are located on one side of the substrate 10; the multiple data signal lines are divided into multiple data signal line groups, each data signal line group includes eight data signal lines, and the same data signal line group includes data signal lines 8k-7 to 8k, which are arranged sequentially along a second direction within the display area; in the same data signal line group, data signal lines 8k-7 and 8k-6 are connected to the same column of pixels, and data signal lines 8k-5 and 8k-4 are connected to the same column of pixels. According to the signal lines, the 8k-3 data signal line and the 8k-2 data signal line are connected to the same column of pixels; the 8k-1 data signal line and the 8k data signal line are connected to the same column of pixels; the 8k-7, 8k-5, 8k-2, and 8k data signal lines are connected to one of the odd-numbered and even-numbered rows of pixels; the 8k-6, 8k-4, 8k-3, and 8k-1 data signal lines are connected to the other of the odd-numbered and even-numbered rows of pixels; k is an integer greater than 0.

[0074] The data signal line includes a first segment 110, a connecting segment 120, and a second segment 130 connected in sequence. The first segment 110 and the second segment 130 are located in the display area 1000 and both extend along a first direction. The connecting segment 120 is located in the transition area 2000. The first segment 110 and the connecting segment 120 of the data signal line are located in different film layers, while the first segment 110 and the second segment 130 are located in the same film layer. The second direction intersects the first direction.

[0075] This application also provides a display device, which includes the display substrate described above.

[0076] In one embodiment, the display device further includes a housing, and the display panel is disposed within the housing.

[0077] The display device provided in this application embodiment can be any device with display function, such as a mobile phone, tablet computer, television, laptop computer, or vehicle-mounted equipment.

[0078] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Images