Display substrate and display method therefor, pixel driving circuit and driving method therefor, and display device

Abstract

Provided is a display substrate, comprising: a base substrate; a driving circuit layer, located on the base substrate, the driving circuit layer comprising a plurality of pixel driving circuits; and a light-emitting device layer, located on the side of the driving circuit layer away from the base substrate, the light-emitting device layer comprising a plurality of light-emitting devices, and the plurality of light-emitting devices being respectively electrically connected to the plurality of pixel driving circuits, wherein at least one light-emitting device comprises a stacked light-emitting device, the stacked light-emitting device comprises a first electrode, a first light-emitting unit located on the side of the first electrode away from the base substrate, a second electrode located on the side of the first light-emitting unit away from the base substrate, a second light-emitting unit located on the side of the second electrode away from the base substrate, and a third electrode located on the side of the second light-emitting unit away from the base substrate, each pixel driving circuit comprises a plurality of transistors, the first electrode is electrically connected to at least one transistor, the second electrode is electrically connected to at least one transistor, and the transistor electrically connected to the first electrode is different from the transistor electrically connected to the second electrode.

Description

Display substrate and display method thereof, pixel driving circuit and driving method thereof, and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and display method thereof, a pixel driving circuit and driving method thereof, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays have become the mainstream display products in the smart terminal sector due to their advantages such as high brightness, long lifespan, and low power consumption. As consumers demand increasingly higher display quality, dual-layer and multi-layer OLED devices are receiving more and more attention. However, how to solve the problems of high power consumption and poor image quality with low grayscale in dual-layer and multi-layer OLED devices remains a key issue for display product developers.

[0003] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, comprising:

[0005] Substrate;

[0006] A driving circuit layer, located on the substrate, includes a plurality of pixel driving circuits; and

[0007] The light-emitting device layer is located on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices arranged at intervals, and the plurality of light-emitting devices are electrically connected to a plurality of pixel driving circuits respectively.

[0008] Wherein, at least one light-emitting device includes a stacked light-emitting device, the stacked light-emitting device including a first electrode, a first light-emitting unit located on the side of the first electrode away from the substrate, a second electrode located on the side of the first light-emitting unit away from the substrate, a second light-emitting unit located on the side of the second electrode away from the substrate, and a third electrode located on the side of the second light-emitting unit away from the substrate;

[0009] The pixel driving circuit includes a plurality of transistors, the first electrode is electrically connected to at least one of the transistors, the second electrode is electrically connected to at least one of the transistors, and the transistors electrically connected to the first electrode and the transistors electrically connected to the second electrode are different.

[0010] According to some exemplary embodiments, the display substrate further includes a pixel defining layer located between the first electrode and the first light-emitting unit, the pixel defining layer including a plurality of openings, each of the plurality of openings exposing a portion of a plurality of the first electrodes; and

[0011] The orthogonal projection of at least one of the second electrodes on the substrate covers the orthogonal projection of at least one of the openings on the substrate.

[0012] According to some exemplary embodiments, the display substrate further includes a pixel defining layer located between the first electrode and the first light-emitting unit, the pixel defining layer including a plurality of openings, each of the plurality of openings exposing a portion of a plurality of the first electrodes; and

[0013] At least one of the second electrodes has its orthographic projection on the substrate overlaps with the orthographic projection portion of at least one of the openings on the substrate.

[0014] According to some exemplary embodiments, the overlapping portion of the orthographic projection of at least one of the second electrodes on the substrate and the orthographic projection of at least one of the openings on the substrate is annular; and / or,

[0015] At least one of the second electrodes' orthogonal projections onto the substrate falls within the orthogonal projection of at least one of the openings onto the substrate; and / or,

[0016] At least one of the second electrodes has its orthogonal projection onto the substrate covering a portion of the edge of the orthogonal projection of at least one of the openings onto the substrate.

[0017] According to some exemplary embodiments, the plurality of light-emitting devices include a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices, wherein the first light-emitting devices, the second light-emitting devices, and the third light-emitting devices all include the stacked light-emitting devices.

[0018] According to some exemplary embodiments, the plurality of light-emitting devices include a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices, wherein at least one of the first light-emitting devices, the second light-emitting devices, and the third light-emitting devices includes the stacked light-emitting device; and

[0019] At least one of the first light-emitting device, the second light-emitting device, and the third light-emitting device includes a single-layer light-emitting device, the single-layer light-emitting device including a fourth electrode, a third light-emitting unit located on the side of the fourth electrode away from the substrate, and a fifth electrode located on the side of the third light-emitting unit away from the substrate, the fourth electrode being electrically connected to at least one of the transistors.

[0020] According to some exemplary embodiments, the first light-emitting device includes the stacked light-emitting device, the second light-emitting device includes the stacked light-emitting device, and the third light-emitting device includes the single-layer light-emitting device; and

[0021] The first light-emitting device emits red light, the second light-emitting device emits green light, and the third light-emitting device emits blue light.

[0022] According to some exemplary embodiments, the first light-emitting device includes the single-layer light-emitting device, the second light-emitting device includes the single-layer light-emitting device, and the third light-emitting device includes the stacked light-emitting device; and

[0023] The first light-emitting device emits red light, the second light-emitting device emits green light, and the third light-emitting device emits blue light.

[0024] According to some exemplary embodiments, the pixel defining layer includes a first via, the first via being spaced apart from the opening; and

[0025] The array substrate further includes a second electrode lead, which is connected to the second electrode as an integral structure. The second electrode lead is electrically connected to the transistor of the pixel driving circuit through the first via.

[0026] According to some exemplary embodiments, in at least two adjacent stacked light-emitting devices, the first light-emitting unit of one stacked light-emitting device is spaced apart from the first light-emitting unit of the other stacked light-emitting device; and

[0027] The orthographic projection of the first via on the substrate is located in the interval region between the orthographic projections of two adjacent first light-emitting units on the substrate.

[0028] According to some exemplary embodiments, in at least two adjacent stacked light-emitting devices, the second light-emitting unit of one stacked light-emitting device is spaced apart from the second light-emitting unit of the other stacked light-emitting device.

[0029] According to some exemplary embodiments, the third electrodes of a plurality of stacked light-emitting devices are connected to form a third electrode layer with an integral structure. The third electrode layer has a cutout portion, and the orthographic projection of the cutout portion on the substrate overlaps at least partially with the orthographic projection of the second electrode lead on the substrate. The third electrode layer and the second electrode lead are spaced apart.

[0030] In another aspect, a display method for a display substrate is provided, applied to the display substrate as described in any of the preceding claims, the display method comprising:

[0031] Obtain the image information to be displayed;

[0032] Based on the image information to be displayed, multiple stacked light-emitting devices are divided into at least one first stacked light-emitting device and at least one second stacked light-emitting device; and

[0033] In response to the image information to be displayed, both the first and second light-emitting units in the first stacked light-emitting device emit light and reach the target brightness, and either the first or second light-emitting unit in the second stacked light-emitting device emits light and reaches the target brightness.

[0034] In another aspect, a pixel driving circuit is provided, the pixel driving circuit being configured to drive a light-emitting device to emit light, the light-emitting device including a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on a side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on a side of the second electrode away from the first electrode, and a third electrode located on a side of the second light-emitting unit away from the first electrode; the pixel driving circuit includes:

[0035] The driving sub-circuit is electrically connected to the light-emitting device;

[0036] A data writing sub-circuit is electrically connected to a data signal terminal, a scan signal terminal, and the driving sub-circuit. The data writing sub-circuit is configured to write a data signal from the data signal terminal into the driving sub-circuit under the control of a scan signal from the scan signal terminal.

[0037] A first light-emitting control sub-circuit is electrically connected to the driving sub-circuit, the first light-emitting control signal terminal, and the first electrode of the light-emitting device; and

[0038] The second light-emitting control sub-circuit is electrically connected to the driving sub-circuit, the second light-emitting control signal terminal, and the second electrode of the light-emitting device.

[0039] According to some exemplary embodiments, the driving sub-circuit includes a third transistor;

[0040] The first light-emitting control sub-circuit includes a fifth transistor, the first electrode of the fifth transistor is electrically connected to the second electrode of the third transistor, the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting device, and the gate of the fifth transistor is electrically connected to the first light-emitting signal control terminal;

[0041] The second light-emitting control sub-circuit includes an eighth transistor, the first electrode of which is electrically connected to the second electrode of the third transistor, the second electrode of which is electrically connected to the second electrode of the light-emitting device, and the gate of which is electrically connected to the second light-emitting signal control terminal.

[0042] On the other hand, a driving method for a pixel driving circuit is provided, the driving method comprising:

[0043] Under the control of the scanning signal, the data writing sub-circuit writes the data signal into the driving sub-circuit;

[0044] In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned off, the second light-emitting control sub-circuit is turned on, and the second light-emitting control sub-circuit controls the driving sub-circuit to output driving current only to the second light-emitting unit; and

[0045] In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned on and the second light-emitting control sub-circuit is turned off. The first light-emitting control sub-circuit controls the driving sub-circuit to output driving current to the first light-emitting unit and the second light-emitting unit.

[0046] In another aspect, a pixel driving circuit is provided, the pixel driving circuit being configured to drive a light-emitting device to emit light, the light-emitting device including a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on a side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on a side of the second electrode away from the first electrode, and a third electrode located on a side of the second light-emitting unit away from the first electrode; the pixel driving circuit includes:

[0047] The driving sub-circuit is electrically connected to the light-emitting device;

[0048] A data writing sub-circuit is electrically connected to a data signal terminal, a scan signal terminal, and the driving sub-circuit. The data writing sub-circuit is configured to write a data signal from the data signal terminal into the driving sub-circuit under the control of a scan signal from the scan signal terminal.

[0049] A first light-emitting control sub-circuit is electrically connected to the driving sub-circuit, the first light-emitting control signal terminal, and the first electrode of the light-emitting device; and

[0050] The second light-emitting control sub-circuit is electrically connected to the second electrode, the second power supply terminal, and the second light-emitting control signal terminal of the light-emitting device.

[0051] According to some exemplary embodiments, the driving sub-circuit includes a third transistor;

[0052] The first light-emitting control sub-circuit includes a fifth transistor, the first electrode of which is electrically connected to the second electrode of the third transistor, the second electrode of which is electrically connected to the first electrode of the light-emitting device, and the gate of which is electrically connected to the first light-emitting signal control terminal; and

[0053] The second light-emitting control sub-circuit includes an eighth transistor, the first electrode of which is electrically connected to the second electrode of the light-emitting device, the second electrode of which is electrically connected to the second power supply terminal, and the gate of which is electrically connected to the second light-emitting signal control terminal.

[0054] On the other hand, a driving method for a pixel driving circuit is provided, the driving method comprising:

[0055] Under the control of the scanning signal, the data writing sub-circuit writes the data signal into the driving sub-circuit;

[0056] In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned on, the second light-emitting control sub-circuit is turned on, and the first light-emitting control sub-circuit and the second light-emitting control sub-circuit control the driving sub-circuit to output driving current only to the first light-emitting unit; and

[0057] In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned on and the second light-emitting control sub-circuit is turned off. The first light-emitting control sub-circuit controls the driving sub-circuit to output driving current to the first light-emitting unit and the second light-emitting unit.

[0058] In another aspect, a display device is provided, wherein the display device includes a display substrate as described in any of the preceding claims, or includes a pixel driving circuit as described in any of the preceding claims. Attached Figure Description

[0059] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0060] Figure 1 schematically shows a planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0061] Figure 2 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0062] Figure 3 schematically shows a cross-sectional view of a stacked light-emitting device in a display substrate according to some embodiments of the present disclosure.

[0063] Figure 4 schematically shows a planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0064] Figure 5 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0065] Figure 6 schematically shows a planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0066] Figure 7 schematically shows a planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0067] Figures 8A-8E schematically show plan views of the second electrode of a display substrate according to some embodiments of the present disclosure.

[0068] Figure 9 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0069] Figure 10 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0070] Figure 11 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0071] Figures 12A-12C schematically illustrate planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0072] Figure 13 schematically illustrates a flowchart of a display method for a display substrate according to some embodiments of the present disclosure.

[0073] Figure 14 schematically illustrates a structural diagram of a pixel circuit according to some embodiments of the present disclosure.

[0074] Figure 15 schematically illustrates an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0075] Figures 16A-16B schematically illustrate signal timing diagrams of pixel driving circuits according to some embodiments of the present disclosure.

[0076] Figure 17 schematically illustrates a structural diagram of a pixel circuit according to some embodiments of the present disclosure.

[0077] Figure 18 schematically illustrates an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0078] Figures 19A-19B schematically illustrate signal timing diagrams of pixel driving circuits according to some embodiments of the present disclosure.

[0079] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0080] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0081] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0082] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements present. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Additionally, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0083] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0084] Figure 1 schematically shows a plan view of the light-emitting devices in a display substrate according to some embodiments of the present disclosure. Figure 2 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure. Figure 3 schematically shows a cross-sectional view of the stacked light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0085] Referring to Figures 1 and 2, the display substrate includes a substrate 100 and a driving circuit layer 200 and a light-emitting device layer 300 located on the substrate 100. The driving circuit layer 200 includes a plurality of pixel driving circuits, which may include a plurality of transistor TFTs and at least one storage capacitor. The light-emitting device layer 300 is located on the side of the driving circuit layer 200 away from the substrate 100, and includes a plurality of light-emitting devices 310 spaced apart. The plurality of light-emitting devices 310 are electrically connected to the plurality of pixel driving circuits respectively, and emit light independently under the drive of the plurality of pixel driving circuits to perform display.

[0086] Figure 1 illustrates one arrangement of multiple light-emitting devices 310. Depending on the actual display requirements, the multiple light-emitting devices 310 can also be arranged in other ways, and this embodiment does not limit this arrangement.

[0087] Referring to Figures 1, 2, and 3, among the plurality of light-emitting devices 310, at least one light-emitting device 310 is a stacked light-emitting device 400. The stacked light-emitting device 400 includes a first electrode 410, a first light-emitting unit 420 located on the side of the first electrode 410 away from the substrate 100, a second electrode 430 located on the side of the first light-emitting unit 420 away from the substrate 100, a second light-emitting unit 440 located on the side of the second electrode 430 away from the substrate 100, and a third electrode 450 located on the side of the second light-emitting unit 440 away from the substrate 100. The first electrode 410 is electrically connected to at least one transistor TFT, the second electrode 430 is electrically connected to at least one transistor TFT, and the transistor TFT electrically connected to the first electrode 410 and the transistor TFT electrically connected to the second electrode 430 are different.

[0088] With this configuration, the pixel driving circuit can control the potentials of the first electrode 410 and the second electrode 430 respectively, enabling the stacked light-emitting device 400 to switch between single-layer and dual-layer devices. In some cases, such as when the luminous brightness is low, the stacked device can use a single-layer device to emit light (either the first light-emitting unit 420 or the second light-emitting unit 440 emits light), thereby reducing power consumption. Furthermore, using only a single-layer device results in a larger luminous current, effectively mitigating crosstalk and improving the display effect under low grayscale display conditions. In some cases, such as when the luminous brightness is high, the stacked device can use dual-layer devices to emit light (both the first light-emitting unit 420 and the second light-emitting unit 440 emit light), which helps to achieve higher luminous brightness and thus improves the display contrast of the display substrate.

[0089] According to some exemplary embodiments, the first light-emitting unit 420 may include a first hole transport layer HTL1 located on the first electrode 410, a first light-emitting layer EML1 located on the side of the first hole transport layer HTL1 away from the first electrode 410, and a first charge generation layer CGL1 located on the side of the first light-emitting layer EML1 away from the first electrode 410. Of course, depending on actual needs, the first light-emitting unit 420 may also include other functional film layers.

[0090] According to some exemplary embodiments, the second light-emitting unit 440 may include a second charge-generating layer CGL2 located on the second electrode 430, a second light-emitting layer EML2 located on the side of the second charge-generating layer CGL2 away from the second electrode 430, and a first electron transport layer ETL1 located on the side of the second light-emitting layer EML2 away from the second electrode 430. Of course, depending on actual needs, the second light-emitting unit 440 may also include other functional film layers.

[0091] According to some exemplary embodiments, the material of the first electrode 410 may include a conductive metal oxide material, for example, the material of the first electrode 410 may include indium tin oxide.

[0092] According to some exemplary embodiments, the material of the third electrode 450 may include a metallic material, for example, the material of the third electrode 450 may include magnesium and silver.

[0093] According to some exemplary embodiments, the material of the second electrode 430 may include at least one of a metallic material and a conductive metal oxide material. For example, the material of the second electrode 430 may include indium tin oxide, or the material of the second electrode 430 may include magnesium and silver. The material of the second electrode 430 may be consistent with the material of the first electrode 410 or the third electrode 450, or the material of the second electrode 430 may be selected as a material that combines the properties of the materials of the first electrode 410 and the third electrode 450.

[0094] According to some exemplary embodiments, referring to FIG1, the plurality of light-emitting devices 310 may include a plurality of first light-emitting devices 311, a plurality of second light-emitting devices 312, and a plurality of third light-emitting devices 313. The first light-emitting devices 311, the second light-emitting devices 312, and the third light-emitting devices 313 emit different colors; for example, the first light-emitting device 311 emits red light, the second light-emitting device 312 emits green light, and the third light-emitting device 313 emits blue light.

[0095] Figure 4 schematically shows a planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0096] According to some exemplary embodiments, referring to Figures 2 and 4, the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 all include a stacked light-emitting device 400. Thus, during display, the multiple first light-emitting devices 311, the multiple second light-emitting devices 312, and the multiple third light-emitting devices 313 can be independently controlled to display the image as needed, using either single-layer or double-layer devices.

[0097] Figure 5 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure. Figure 6 schematically shows a plan view of the light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0098] According to some exemplary embodiments, referring to Figures 2, 5, and 6, at least one of the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 includes a stacked light-emitting device 400, and at least one of the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 includes a single-layer light-emitting device 500. Depending on the performance differences of the different light-emitting devices 310, only a portion of the light-emitting devices 310 can be configured as stacked light-emitting devices 400, while the other portion can be configured as single-layer light-emitting devices 500. Thus, during display, multiple stacked light-emitting devices 400 can be independently controlled to display as single-layer or double-layer devices according to the image to be displayed, while multiple single-layer light-emitting devices 500 are always displayed as single-layer devices.

[0099] Referring to FIG5, the single-layer light-emitting device 500 may include a fourth electrode 510, a third light-emitting unit 520 located on the side of the fourth electrode 510 away from the substrate 100, and a fifth electrode 530 located on the side of the third light-emitting unit 520 away from the substrate 100. The fourth electrode 510 is electrically connected to at least one transistor TFT.

[0100] For example, the third light-emitting unit 520 may include a second hole transport layer HTL2 located on the fourth electrode 510, a third light-emitting layer EML3 located on the side of the second hole transport layer HTL2 away from the fourth electrode 510, and a second electron transport layer ETL2 located on the side of the third light-emitting layer EML3 away from the fourth electrode 510.

[0101] For example, the fourth electrode 510 of the single-layer light-emitting device 500 can be located in the same layer as the first electrode 410 of the stacked light-emitting device 400.

[0102] For example, the fifth electrode 530 of the single-layer light-emitting device 500 can be located on the same layer as the third electrode 450 of the stacked light-emitting device 400, and multiple fifth electrodes 530 and multiple third electrodes 450 can be connected into an integral structure.

[0103] For example, some functional layers in the third light-emitting unit 520 of the single-layer light-emitting device 500 may be located in the same layer as some functional layers in the first light-emitting unit 420 and the second light-emitting unit 440 of the stacked light-emitting device 400. For example, the first hole transport layer HTL1 and the second hole transport layer HTL2 may be located in the same layer, and the first electron transport layer ETL1 and the second electron transport layer ETL2 may be located in the same layer.

[0104] It should be noted that being in the same layer should be understood as a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, and their materials may be the same or different.

[0105] According to some exemplary embodiments, referring to Figures 2, 5, and 6, the first light-emitting device 311 includes a single-layer light-emitting device 500, the second light-emitting device 312 includes a single-layer light-emitting device 500, and the third light-emitting device 313 includes a multilayer light-emitting device 400. That is, if only the blue light-emitting device is configured as a multilayer light-emitting device 400, the luminous efficiency of the blue light-emitting device can be increased by configuring it as a multilayer light-emitting device 400. The green and red light-emitting devices have higher luminous efficiency and can still be configured as single-layer light-emitting devices 500, which helps to reduce the power consumption of the display substrate.

[0106] Figure 7 schematically shows a planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0107] According to some exemplary embodiments, referring to Figures 2, 5, and 7, the first light-emitting device 311 includes a stacked light-emitting device 400, the second light-emitting device 312 includes a stacked light-emitting device 400, and the third light-emitting device 313 includes a single-layer light-emitting device 500. That is, the blue light-emitting device is set as a single-layer light-emitting device 500, and the red and green light-emitting devices are set as a stacked light-emitting device 400.

[0108] Of course, depending on the actual display requirements, a portion of the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 can be configured as a stacked light-emitting device 400, and another portion can be configured as a single-layer light-emitting device 500.

[0109] Figures 8A-8E schematically show plan views of the second electrode of a display substrate according to some embodiments of the present disclosure.

[0110] According to some exemplary embodiments, referring to Figures 2 and 8A, the display substrate further includes a pixel defining layer (PDL) located between the first electrode 410 and the first light-emitting unit 420. The PDL includes a plurality of openings KK, each exposing a portion of one of the first electrodes 410. The first light-emitting unit 420 contacts the first electrode 410 through the openings KK. The orthographic projection of a second electrode 430 onto the substrate 100 covers the orthographic projection of one opening KK onto the substrate 100, and the second electrode 430 is fully distributed over the area where the openings KK of the pixel defining layer PDL are located.

[0111] It should be noted that in the method where the second electrode 430 fully covers the area where the opening KK of the pixel defining layer PDL is located, the multiple second electrodes 430 in the multiple stacked light-emitting devices 400 are arranged at intervals, and the multiple second electrodes 430 respectively cover the multiple openings KK.

[0112] It should be noted that in Figures 8A-8E, the edge of the opening KK of the pixel boundary layer PDL is indicated by a bold black outline to more clearly illustrate the projection relationship between the second electrode 430 and the opening KK of the pixel boundary layer PDL.

[0113] Furthermore, due to variations in the process of forming the second electrode 430, it is difficult for the second electrode 430 to be formed precisely within the area of ​​the opening KK of the pixel defining layer PDL. In other words, a portion of the second electrode 430 will be located outside the area of ​​the opening KK of the pixel defining layer PDL. For example, as shown in Figure 2, when the second electrode 430 fully covers the area of ​​the opening KK of the pixel defining layer PDL, the edge of the orthographic projection of the second electrode 430 onto the substrate 100 surrounds the outer side of the orthographic projection of the opening KK onto the substrate 100. However, in Figures 8A-8E, to more clearly illustrate the projection relationship between the second electrode 430 and the opening KK of the pixel defining layer PDL, only a portion of the second electrode 430 within the opening KK area of ​​the pixel defining layer PDL is shown.

[0114] Figure 9 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0115] According to some exemplary embodiments, referring to Figures 8B, 8C, 8D, 8E, and 9, the orthographic projection of a second electrode 430 on the substrate 100 partially overlaps with the orthographic projection of an opening KK on the substrate 100. The second electrode 430 only covers a portion of the opening KK of the pixel defining layer PDL. This effectively avoids the problem of light emission being blocked by the second electrode 430, thus reducing light emission efficiency. Furthermore, referring to Figure 9, in the area not covered by the second electrode 430, a portion of the first charge generation layer CGL1 in the first light-emitting unit 420 and the second charge generation layer CGL2 in the second light-emitting unit 440 are in direct contact, which is beneficial for improving efficiency when using a multilayer display device.

[0116] According to some exemplary embodiments, referring to Figures 8B and 9, the orthographic projection of the second electrode 430 on the substrate is annular, and the outer edge of the second electrode 430 on the substrate surrounds the outer edge of the orthographic projection of the opening KK on the substrate, while the inner edge of the second electrode 430 on the substrate lies within the orthographic projection of the opening KK on the substrate. That is, the overlapping portion of the orthographic projection of the second electrode 430 on the substrate and the orthographic projection of the opening KK on the substrate is annular, and the second electrode 430 only covers the edge region of the opening KK of the pixel defining layer (PDL).

[0117] Figure 10 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0118] According to some exemplary embodiments, referring to Figures 8C, 8D and 10, the orthographic projection of a second electrode 430 on the substrate falls within the orthographic projection of at least one opening KK on the substrate. The second electrode 430 only covers a portion of the interior area of ​​the opening KK of the pixel defining layer PDL, and the edge area of ​​the opening KK of the pixel defining layer PDL is not covered by the second electrode 430.

[0119] For example, referring to FIG8C, the shape of the second electrode 430 (referring to the shape of its orthogonal projection on the substrate) can be consistent with the shape of the opening KK of the pixel defining layer PDL, and the edge of the second electrode 430 can extend within the opening KK along the edge of the opening KK of the pixel defining layer PDL. Exemplarily, the shape of the opening KK is a rounded rectangle, and the shape of the second electrode 430 located within the opening KK is also a rounded rectangle.

[0120] For example, referring to FIG8D, the shape of the second electrode 430 may be different from the shape of the opening KK of the pixel definition layer PDL. For example, when the shape of the opening KK is a rectangle or other polygon, the shape of the second electrode 430 may be circular.

[0121] According to some exemplary embodiments, referring to FIG8E, the orthographic projection of the second electrode 430 on the substrate covers a portion of the edge of the orthographic projection of the opening KK on the substrate. The orthographic projection of the second electrode 430 on the substrate only covers a portion of the orthographic projection of the opening KK on the substrate located in a specific direction. For example, in FIG8E, the orthographic projection of the second electrode 430 on the substrate covers the right half of the orthographic projection of the opening KK on the substrate.

[0122] Of course, the orientation and coverage area ratio of the second electrode 430 covering the opening KK can be set according to actual process requirements, and this embodiment does not limit this.

[0123] According to some exemplary embodiments, referring to FIG2, the pixel defining layer PDL includes a first via VO1, the first via VO1 being spaced apart from the opening KK, and the array substrate further includes a second electrode lead 431, the second electrode lead 431 and the second electrode 430 being connected as an integral structure, and the second electrode lead 431 being electrically connected to the transistor TFT of the pixel driving circuit through the first via VO1.

[0124] In the embodiments of this disclosure, "integrated structure" refers to a structure formed by two (or more) structures through the same deposition process and patterned through the same patterning process, which are connected to each other and may be made of the same or different materials.

[0125] According to some exemplary embodiments, referring to FIG10, when the second electrode 430 is located within the opening KK of the pixel defining layer PDL, the second electrode lead 431 needs to extend into the opening KK to connect with the second electrode 430.

[0126] It should be noted that the second electrode 430 and the second electrode lead 431 are formed by the same deposition and patterning process. In the actual product, there is no obvious boundary between the second electrode 430 and the second electrode lead 431. However, the width of the second electrode lead 431 (the dimension perpendicular to its extension direction) is smaller than the dimension of the second electrode 430 (the side length or diameter of the second electrode 430). For example, the width of the second electrode lead 431 is less than or equal to half the dimension of the second electrode 430. The boundary between the second electrode 430 and the second electrode lead 431 should be considered to be at the location where the dimension changes abruptly. In the cross-sectional view of Figure 2, the second electrode lead 431 and the second electrode lead 431 are schematically distinguished by the density of the filling pattern.

[0127] According to some exemplary embodiments, referring to FIG2, the driving circuit layer 200 may include a buffer layer Buf located on the substrate 100, an active layer ACT located on the side of the buffer layer Buf away from the substrate 100, a first gate insulating layer GI1 located on the side of the active layer ACT away from the substrate 100, a first gate metal layer Gate1 located on the side of the first gate insulating layer GI1 away from the substrate 100, a second gate insulating layer GI2 located on the side of the first gate metal layer Gate1 away from the substrate 100, and a first gate metal layer Gate1 located on the side of the second gate insulating layer GI2 away from the substrate 100. The second gate metal layer, the third gate insulating layer GI3 located on the side of the second gate metal layer away from the substrate 100, the third gate metal layer located on the side of the third gate insulating layer GI3 away from the substrate 100, the interlayer dielectric layer ILD located on the side of the third gate metal layer away from the substrate 100, the first source / drain metal layer SD1 located on the side of the interlayer dielectric layer ILD away from the substrate 100, the first planarization layer PLN1 located on the side of the first source / drain metal layer SD1 away from the substrate 100, and the second source / drain metal layer SD2 located on the side of the first planarization layer PLN1 away from the substrate 100.

[0128] Since there are no related structures for the second and third gate metal layers at the location shown in Figure 2, the second and third gate metal layers are not illustrated in Figure 2.

[0129] The pixel driving unit includes a transistor TFT, which includes an active portion A, a gate G, a source S, and a drain D. The active portion A is located in the active layer ACT and includes a channel portion A1 and two conductive portions A2 connected to both sides of the channel portion A1. The gate G is located in the first gate metal layer Gate1, and the orthographic projection of the gate G on the substrate 100 covers the orthographic projection of the channel portion A1 on the substrate 100. The source S and drain D are located in the first source-drain metal layer SD1, and the source S and drain D are electrically connected to the two conductive portions A2, respectively.

[0130] According to some exemplary embodiments, referring to FIG2, the display substrate further includes a first transition portion L01 and a second transition portion L02. The first transition portion L01 and the first electrode 410 are located on the same layer and are spaced apart. The second electrode lead 431 is electrically connected to the first transition portion L01 through a first via V01. The second transition portion L02 is located in the second source / drain metal layer SD2. The first transition portion L01 is electrically connected to the second transition portion L02 through a second via V02 located in the second planarization layer PLN2. The second transition portion L02 is then electrically connected to the drain D of the corresponding transistor TFT through a third via V03 located in the first planarization layer PLN1. The second electrode lead 431 is electrically connected to the transistor TFT in sequence through the first transition portion L01 and the second transition portion L02. In this way, the depth of a single connection via can be reduced, which is beneficial to improving the connection reliability between the second electrode lead 431 and the transistor TFT.

[0131] According to some exemplary embodiments, referring to FIG2, in at least two adjacent stacked light-emitting devices 400, the first light-emitting unit 420 of one stacked light-emitting device 400 is spaced apart from the first light-emitting unit 420 of the other stacked light-emitting device 400. FIG2 schematically shows the first light-emitting unit 420 of one stacked light-emitting device 400. The first light-emitting units 420 of the adjacent stacked light-emitting device 400 have the same structure and are spaced apart. The orthographic projection of the first via VO1 on the substrate 100 is located in the spaced region between the orthographic projections of the two adjacent first light-emitting units 420 on the substrate 100. That is, each layer in the first light-emitting unit 420 is formed by vapor deposition using a fine metal mask (FMM). The plurality of first light-emitting units 420 are independently spaced apart, and the spaced region of the first light-emitting units 420 exposes the first via VO1, so that the second electrode lead 431 can be electrically connected to the lower layer transistor TFT through the first via VO1.

[0132] Figure 11 schematically shows a cross-sectional view of a display substrate according to some embodiments of the present disclosure.

[0133] According to some exemplary embodiments, referring to FIG11, in at least two adjacent stacked light-emitting devices 400, the second light-emitting unit 440 of one stacked light-emitting device 400 is spaced apart from the second light-emitting unit 440 of the other stacked light-emitting device 400. FIG11 schematically shows the second light-emitting unit 440 of one stacked light-emitting device 400, and the second light-emitting unit 440 of the adjacent stacked light-emitting device 400 has the same structure and is spaced apart. That is, each layer in the second light-emitting unit 440 is formed by fine FMM evaporation, and the multiple first light-emitting units 420 are independently spaced apart, which can effectively avoid the crosstalk problem of adjacent stacked light-emitting devices 400.

[0134] According to some exemplary embodiments, referring to FIG11, the third electrodes 450 of a plurality of stacked light-emitting devices 400 are connected to form a third electrode layer 450A with an integral structure. The third electrode layer 450A has a cutout portion 451. The orthographic projection of the cutout portion 451 on the substrate 100 at least partially overlaps with the orthographic projection of the second electrode lead 431 on the substrate 100. The third electrode layer 450A and the second electrode lead 431 are spaced apart. The third electrode layer 450A is patterned, and the cutout portion 451 is provided in the third electrode layer 450A to avoid short circuit between the third electrode 450 and the second electrode 430.

[0135] Figures 12A-12C schematically illustrate planar distribution of light-emitting devices in a display substrate according to some embodiments of the present disclosure.

[0136] The schemes described above regarding setting the first part of the light-emitting device 310 as a stacked light-emitting device 400 and setting the other part of the light-emitting device 310 as a single-layer light-emitting device 500, as well as the schemes regarding the second electrode 430 fully or partially covering the opening KK of the pixel delimiting layer PDL, can be arbitrarily combined according to actual needs, as illustrated below.

[0137] For example, referring to Figure 4, the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 are all stacked light-emitting devices 400. The opening KK of the pixel defining layer PDL includes a first opening KK1, a second opening KK2, and a third opening KK3. The first opening KK1 serves as the pixel opening KK of the first light-emitting device 311, the second opening KK2 serves as the pixel opening KK of the second light-emitting device 312, and the third opening KK3 serves as the pixel opening KK of the third light-emitting device 313. The second electrode 430 in the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 all only cover a part of the area inside the opening KK of the pixel defining layer PDL. Specifically, the orthographic projection of the second electrode 430 of the first light-emitting device 311 on the substrate 100 falls within the orthographic projection of the first opening KK1 on the substrate 100, the orthographic projection of the second electrode 430 of the second light-emitting device 312 on the substrate 100 falls within the orthographic projection of the second opening KK2 on the substrate 100, and the orthographic projection of the second electrode 430 of the third light-emitting device 313 on the substrate 100 falls within the orthographic projection of the third opening KK3 on the substrate 100.

[0138] For example, referring to FIG12A, the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 are all stacked light-emitting devices 400. The second electrode 430 in the first light-emitting device 311, the second light-emitting device 312, and the third light-emitting device 313 only covers the edge region of the opening KK of the pixel defining layer PDL. Specifically, the overlapping portion of the orthographic projection of the second electrode 430 of the first light-emitting device 311 on the substrate 100 and the orthographic projection of the first opening KK1 on the substrate 100 is annular; the overlapping portion of the orthographic projection of the second electrode 430 of the second light-emitting device 312 on the substrate 100 and the orthographic projection of the second opening KK2 on the substrate 100 is annular; and the overlapping portion of the orthographic projection of the second electrode 430 of the third light-emitting device 313 on the substrate 100 and the orthographic projection of the third opening KK3 on the substrate 100 is annular.

[0139] For example, referring to FIG6, the first light-emitting device 311 and the second light-emitting device 312 are single-layer light-emitting devices 500, and the third light-emitting device 313 is a stacked light-emitting device 400. The orthographic projection of the second electrode 430 of the third light-emitting device 313 on the substrate 100 falls within the orthographic projection of the third opening KK3 on the substrate 100.

[0140] For example, referring to FIG12B, the first light-emitting device 311 and the second light-emitting device 312 are single-layer light-emitting devices 500, and the third light-emitting device 313 is a stacked light-emitting device 400. The overlapping portion of the orthographic projection of the second electrode 430 of the third light-emitting device 313 on the substrate 100 and the orthographic projection of the third opening KK3 on the substrate 100 is annular.

[0141] For example, referring to FIG7, the first light-emitting device 311 and the second light-emitting device 312 are stacked light-emitting devices 400, and the third light-emitting device 313 is a single-layer light-emitting device 500. The orthographic projection of the second electrode 430 of the first light-emitting device 311 on the substrate 100 falls within the orthographic projection of the first opening KK1 on the substrate 100, and the orthographic projection of the second electrode 430 of the second light-emitting device 312 on the substrate 100 falls within the orthographic projection of the second opening KK2 on the substrate 100.

[0142] For example, referring to FIG12C, the first light-emitting device 311 and the second light-emitting device 312 are stacked light-emitting devices 400, and the third light-emitting device 313 is a single-layer light-emitting device 500. The overlapping portion of the orthographic projection of the second electrode 430 of the first light-emitting device 311 on the substrate 100 and the orthographic projection of the first opening KK1 on the substrate 100 is annular, and the overlapping portion of the orthographic projection of the second electrode 430 of the second light-emitting device 312 on the substrate 100 and the orthographic projection of the second opening KK2 on the substrate 100 is annular.

[0143] The above is merely an illustrative example; other combinations can be made according to actual process requirements, and this disclosure does not limit the specific implementation of the embodiments.

[0144] Figure 13 schematically illustrates a flowchart of a display method for a display substrate according to some embodiments of the present disclosure.

[0145] At least some embodiments of this disclosure also provide a display method for a display substrate, applied to the display substrate described above. Referring to FIG13, the display method includes steps S11-S13.

[0146] In step S11, the image information to be displayed is obtained.

[0147] In step S12, the multiple stacked light-emitting devices are divided into at least one first stacked light-emitting device and at least one second stacked light-emitting device according to the image information to be displayed.

[0148] For example, a critical brightness value can be set, classifying stacked light-emitting devices with a target brightness less than or equal to the critical brightness value as second stacked light-emitting devices, and classifying stacked light-emitting devices with a target brightness greater than or equal to the critical brightness value as first stacked light-emitting devices. For example, the critical brightness value can be 300 nits. Of course, other methods can also be used to classify the first and second stacked light-emitting devices, and this disclosure does not limit this approach.

[0149] In step S13, in response to the image information to be displayed, both the first and second light-emitting units in the first stacked light-emitting device emit light and reach the target brightness, and either the first or second light-emitting unit in the second stacked light-emitting device emits light and reaches the target brightness.

[0150] For this display substrate, during gamma tuning, a first gamma curve is obtained when both the first and second light-emitting units emit light, and a second gamma curve is obtained when only one of the first or second light-emitting units emits light. Both the first and second gamma curves are then programmed into the driver chip. During display, for the first stacked light-emitting device, the driver chip outputs a corresponding data signal based on the first gamma curve; for the second stacked light-emitting device, the driver chip outputs a corresponding data signal based on the second gamma curve.

[0151] Figure 14 schematically illustrates a structural diagram of a pixel circuit according to some embodiments of the present disclosure.

[0152] According to some exemplary embodiments, referring to FIG14, the pixel circuit includes a pixel driving circuit 210 and a light-emitting device 310, wherein the pixel driving circuit 210 is configured to drive the light-emitting device 310 to emit light. The cross-sectional structure of the light-emitting device 310 can be seen in FIG3. The light-emitting device 310 includes a first electrode 410, a first light-emitting unit 420 located on the first electrode 410, a second electrode 430 located on the side of the first light-emitting unit 420 away from the first electrode 410, a second light-emitting unit 440 located on the side of the second electrode 430 away from the first electrode 410, and a third electrode 450 located on the side of the second light-emitting unit 440 away from the first electrode 410. The pixel driving circuit 210 includes a driving sub-circuit 211, a data writing sub-circuit 212, a first light-emitting control sub-circuit 213, and a second light-emitting control sub-circuit 214.

[0153] The third electrode 450 of the light-emitting device 310 is electrically connected to the second power supply terminal VSS. The driving sub-circuit 211 is electrically connected to the light-emitting device 310 and the first power supply terminal VDD, and is configured to control the driving current that drives the light-emitting device 310 to emit light. The data writing sub-circuit 212 is electrically connected to the data signal terminal Data, the scan signal terminal Gate, and the driving sub-circuit 211, and is configured to write the data signal from the data signal terminal Data into the driving sub-circuit 211 under the control of the scan signal from the scan signal terminal Gate.

[0154] The first light-emitting control sub-circuit 213 is electrically connected to the driver sub-circuit 211, the first light-emitting control signal terminal EM1, and the first electrode 410 of the light-emitting device 310. The second light-emitting control sub-circuit 214 is electrically connected to the driver sub-circuit 211, the second light-emitting control signal terminal EM2, and the second electrode 430 of the light-emitting device 310.

[0155] The first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214 are configured to, under the control of a first light-emitting control signal from the first light-emitting control signal terminal EM1 and a second light-emitting control signal from the second light-emitting control signal terminal EM2, control the driving subcircuit 211 to output driving current only to the second light-emitting unit 440, or control the driving subcircuit 211 to output driving current to both the first light-emitting unit 420 and the second light-emitting unit 440. Through the configuration of the first light-emitting control subcircuit 213 and the second light-emitting control subcircuit 214, the light-emitting mode of the light-emitting device 310 can be dynamically switched between single-layer and double-layer light emission.

[0156] According to embodiments of this disclosure, the pixel driving circuit 210 includes a first driving mode and a second driving mode.

[0157] Referring to Figure 14, in the first driving mode, the driving method includes: under the control of the scanning signal, the data writing sub-circuit 212 writes the data signal into the driving sub-circuit 211; under the control of the first light emission control signal and the second light emission control signal, the first light emission control sub-circuit 213 is turned off, the second light emission control sub-circuit 214 is turned on, and the second light emission control sub-circuit 214 controls the driving sub-circuit 211 to output driving current only to the second light emission unit 440, so that the second light emission unit 440 emits light.

[0158] Referring to Figure 14, in the second driving mode, the driving method includes: under the control of the scanning signal, the data writing sub-circuit 212 writes the data signal into the driving sub-circuit 211; under the control of the first light emission control signal and the second light emission control signal, the first light emission control sub-circuit 213 is turned on and the second light emission control sub-circuit 214 is turned off; the first light emission control sub-circuit 213 controls the driving sub-circuit 211 to output driving current to the first light emission unit 420 and the second light emission unit 440, so that both the first light emission unit 420 and the second light emission unit 440 emit light.

[0159] Figure 15 schematically illustrates an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0160] According to some exemplary embodiments, referring to Figures 14 and 15, the driving sub-circuit 211 includes a third transistor T3 (i.e., the driving transistor) and a storage capacitor C. The gate of the third transistor T3 is electrically connected to the first terminal of the storage capacitor C at a fourth node N4, the first terminal of the third transistor T3 is electrically connected to the first power supply terminal VDD at a fifth node N5, and the second terminal of the storage capacitor C is electrically connected to the first power supply terminal VDD.

[0161] The data writing sub-circuit 212 includes a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is electrically connected to the scan signal terminal Gate, the first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3 at the sixth node N6, and the second terminal of the second transistor T2 is electrically connected to the fourth node N4. The gate of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the fifth node N5.

[0162] The first light-emitting control sub-circuit 213 includes a fifth transistor T5. The gate of the fifth transistor T5 is electrically connected to the first light-emitting control signal terminal EM1. The first electrode of the fifth transistor T5 is electrically connected to the sixth node N6. The second electrode of the fifth transistor T5 is electrically connected to the first electrode 410 of the light-emitting device 310 at the first node N1.

[0163] The second light-emitting control sub-circuit 214 includes an eighth transistor T8, the gate of which is electrically connected to the second light-emitting control signal terminal EM2, the first electrode of which is electrically connected to the sixth node N6, and the second electrode of which is electrically connected to the second electrode 430 of the light-emitting device 310 at the second node N2.

[0164] The third electrode 450 of the light-emitting device 310 is electrically connected to the second power supply terminal VSS at the third node N3.

[0165] According to some exemplary embodiments, referring to Figures 14 and 15, the pixel driving circuit 210 may further include a first transistor T1, a sixth transistor T6, and a seventh transistor T7. The gate of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4. The gate of the sixth transistor T6 is electrically connected to the third light emission control signal terminal EM3, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The gate of the seventh transistor T7 is electrically connected to the scan signal terminal Gate, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0166] Figures 16A-16B schematically illustrate signal timing diagrams of pixel driving circuits according to some embodiments of the present disclosure.

[0167] Next, with reference to Figures 16A-16B, the driving process of the pixel driving circuit 210 according to an embodiment of the present disclosure will be described in detail.

[0168] Referring to FIG16A, a signal timing diagram of the pixel driving circuit 210 in the first driving mode is shown. The display process of each frame of image may include an initialization stage, a data writing stage, and a light emission stage.

[0169] During the initialization phase, the low level of the Reset signal terminal is valid, while the Gate signal terminal, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are all high. Under the control of the Reset signal terminal, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0170] During the data writing phase, the low level of the scan signal terminal Gate is an effective level, while the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are at high levels. Under the control of the scan signal terminal Gate, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data through the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit through the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0171] During the light-emitting phase, the low levels of the second light-emitting control signal terminal EM2 and the third light-emitting control signal terminal EM3 are active levels, while the Reset signal terminal, the Gate signal terminal, and the first light-emitting control signal terminal EM1 are high levels. Under the control of the second light-emitting control signal terminal EM2, the eighth transistor T8 is turned on; under the control of the third light-emitting control signal terminal EM3, the sixth transistor T6 is turned on; and the fifth transistor T5 is turned off by the high level of the first light-emitting control signal terminal EM1. The third transistor T3 is turned on by the voltage signal stored in the storage capacitor C. The driving current is applied to the second light-emitting unit 440 along the path from the sixth transistor T6, the third transistor T3, and the eighth transistor T8, causing the second light-emitting unit 440 to emit light.

[0172] Referring to Figure 16B, a signal timing diagram of the pixel driving circuit 210 in the second driving mode is shown.

[0173] During the initialization phase, the low level of the Reset signal terminal is valid, while the Gate signal terminal, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are all high. Under the control of the Reset signal terminal, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0174] During the data writing phase, the low level of the scan signal terminal Gate is an effective level, while the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are at high levels. Under the control of the scan signal terminal Gate, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data through the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit through the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0175] During the light-emitting phase, the low levels of the first light-emitting control signal terminal EM1 and the third light-emitting control signal terminal EM3 are active levels, while the Reset signal terminal, the Gate signal terminal, and the second light-emitting control signal terminal EM2 are high levels. Under the control of the first light-emitting control signal terminal EM1, the fifth transistor T5 is turned on; under the control of the third light-emitting control signal terminal EM3, the sixth transistor T6 is turned on; and the eighth transistor T8 is turned off by the high level of the second light-emitting control signal terminal EM2. The third transistor T3 is turned on by the voltage signal stored in the storage capacitor C. The driving current is applied along the path from the sixth transistor T6, the third transistor T3, and the fifth transistor T5 to the second light-emitting unit 440 and the first light-emitting unit 420, causing the first light-emitting unit 420 and the second light-emitting unit 440 to emit light.

[0176] Figure 17 schematically illustrates a structural diagram of a pixel circuit according to some embodiments of the present disclosure.

[0177] According to some exemplary embodiments, referring to FIG17, the pixel circuit includes a pixel driving circuit 210 and a light-emitting device 310, wherein the pixel driving circuit 210 is configured to drive the light-emitting device 310 to emit light. The cross-sectional structure of the light-emitting device 310 can be seen in FIG3. The light-emitting device 310 includes a first electrode 410, a first light-emitting unit 420 located on the first electrode 410, a second electrode 430 located on the side of the first light-emitting unit 420 away from the first electrode 410, a second light-emitting unit 440 located on the side of the second electrode 430 away from the first electrode 410, and a third electrode 450 located on the side of the second light-emitting unit 440 away from the first electrode 410. The pixel driving circuit 210 includes a driving sub-circuit 211, a data writing sub-circuit 212, a first light-emitting control sub-circuit 213, and a second light-emitting control sub-circuit 214.

[0178] The third electrode 450 of the light-emitting device 310 is electrically connected to the second power supply terminal VSS. The driving sub-circuit 211 is electrically connected to the light-emitting device 310 and the first power supply terminal VDD, and is configured to control the driving current that drives the light-emitting device 310 to emit light. The data writing sub-circuit 212 is electrically connected to the data signal terminal Data, the scan signal terminal Gate, and the driving sub-circuit 211, and is configured to write the data signal from the data signal terminal Data into the driving sub-circuit 211 under the control of the scan signal from the scan signal terminal Gate.

[0179] The first light-emitting control sub-circuit 213 is electrically connected to the driving sub-circuit 211, the first light-emitting control signal terminal EM1, and the first electrode 410 of the light-emitting device 310. The second light-emitting control sub-circuit 214 is electrically connected to the second electrode 430 of the light-emitting device 310, the second power supply terminal VSS, and the second light-emitting control signal terminal EM2.

[0180] The first light-emitting control sub-circuit 213 and the second light-emitting control sub-circuit 214 are configured to, under the control of a first light-emitting control signal from the first light-emitting control signal terminal EM1 and a second light-emitting control signal from the second light-emitting control signal terminal EM2, control the driving sub-circuit 211 to output driving current only to the first light-emitting unit 420, or control the driving sub-circuit 211 to output driving current to both the first light-emitting unit 420 and the second light-emitting unit 440. Through the configuration of the first light-emitting control sub-circuit 213 and the second light-emitting control sub-circuit 214, the light-emitting mode of the light-emitting device 310 can be dynamically switched between single-layer light emission and double-layer light emission.

[0181] According to embodiments of this disclosure, the pixel driving circuit 210 includes a first driving mode and a second driving mode.

[0182] Referring to Figure 17, in the first driving mode, the driving method includes: under the control of the scanning signal, the data writing sub-circuit 212 writes the data signal into the driving sub-circuit 211; under the control of the first light emission control signal and the second light emission control signal, the first light emission control sub-circuit 213 is turned on, the second light emission control sub-circuit 214 is turned on, and the first light emission control sub-circuit 213 and the second light emission control sub-circuit 214 control the driving sub-circuit 211 to output driving current only to the first light emission unit 420, so that the first light emission unit 420 emits light.

[0183] Referring to Figure 17, in the second driving mode, the driving method includes: under the control of the scanning signal, the data writing sub-circuit 212 writes the data signal into the driving sub-circuit 211; under the control of the first light emission control signal and the second light emission control signal, the first light emission control sub-circuit 213 is turned on and the second light emission control sub-circuit 214 is turned off; the first light emission control sub-circuit 213 controls the driving sub-circuit 211 to output driving current to the first light emission unit 420 and the second light emission unit 440, so that the first light emission unit 420 and the second light emission unit 440 emit light.

[0184] Figure 18 schematically illustrates an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0185] According to some exemplary embodiments, referring to Figures 17 and 18, the driving sub-circuit 211 includes a third transistor T3 (i.e., the driving transistor) and a storage capacitor C. The gate of the third transistor T3 is electrically connected to the first terminal of the storage capacitor C at a fourth node N4, the first terminal of the third transistor T3 is electrically connected to the first power supply terminal VDD at a fifth node N5, and the second terminal of the storage capacitor C is electrically connected to the first power supply terminal VDD.

[0186] The data writing sub-circuit 212 includes a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is electrically connected to the scan signal terminal Gate, the first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3 at the sixth node N6, and the second terminal of the second transistor T2 is electrically connected to the fourth node N4. The gate of the fourth transistor T4 is electrically connected to the scan signal terminal Gate, the first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is electrically connected to the fifth node N5.

[0187] The first light-emitting control sub-circuit 213 includes a fifth transistor T5. The gate of the fifth transistor T5 is electrically connected to the first light-emitting control signal terminal EM1. The first electrode of the fifth transistor T5 is electrically connected to the sixth node N6. The second electrode of the fifth transistor T5 is electrically connected to the first electrode 410 of the light-emitting device 310 at the first node N1.

[0188] The second light-emitting control sub-circuit 214 includes an eighth transistor T8. The gate of the eighth transistor T8 is electrically connected to the second light-emitting control signal terminal EM2. The first electrode of the eighth transistor T8 is electrically connected to the second electrode 430 of the light-emitting device 310 at the second node N2. The second electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VSS at the third node N3.

[0189] The third electrode 450 of the light-emitting device 310 is electrically connected to the second power supply terminal VSS at the third node N3.

[0190] According to some exemplary embodiments, referring to Figures 17 and 18, the pixel driving circuit 210 may further include a first transistor T1, a sixth transistor T6, and a seventh transistor T7. The gate of the first transistor T1 is electrically connected to the reset signal terminal Reset, the first electrode of the first transistor T1 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4. The gate of the sixth transistor T6 is electrically connected to the first light emission control signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is electrically connected to the fifth node N5. The gate of the seventh transistor T7 is electrically connected to the scan signal terminal Gate, the first electrode of the seventh transistor T7 is electrically connected to the initialization signal terminal Vinit, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0191] Figures 19A-19B schematically illustrate signal timing diagrams of pixel driving circuits according to some embodiments of the present disclosure.

[0192] Next, with reference to Figures 19A-19B, the driving process of the pixel driving circuit 210 according to an embodiment of the present disclosure will be described in detail.

[0193] Referring to FIG19A, a signal timing diagram of the pixel driving circuit 210 in the first driving mode is shown. The display process of each frame of image may include an initialization stage, a data writing stage, and a light emission stage.

[0194] During the initialization phase, the low level of the Reset signal terminal is valid, while the Gate signal terminal, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are all high. Under the control of the Reset signal terminal, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0195] During the data writing phase, the low level of the scan signal terminal Gate is an effective level, while the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are at high levels. Under the control of the scan signal terminal Gate, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data through the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit through the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0196] During the light-emitting phase, the low level of the second light-emitting control signal terminal EM2 is an effective level, while the reset signal terminal Reset and the scan signal terminal Gate are high levels. Under the control of the second light-emitting control signal terminal EM2, the eighth transistor T8 is turned on, and under the control of the first light-emitting control signal terminal EM1, the sixth transistor T6 and the fifth transistor T5 are turned on. The third transistor T3 is turned on driven by the voltage signal stored in the storage capacitor C. The turning on of the eighth transistor T8 makes the potentials of the second node N2 and the third node N3 the same, that is, short-circuiting the second light-emitting unit 440. The driving current is applied to the first light-emitting unit 420 along the path from the sixth transistor T6, the third transistor T3, the fifth transistor T5, the first light-emitting unit 420, and the eighth transistor T8, so that the first light-emitting unit 420 emits light.

[0197] Referring to Figure 19B, a signal timing diagram of the pixel driving circuit 210 in the second driving mode is shown.

[0198] During the initialization phase, the low level of the Reset signal terminal is valid, while the Gate signal terminal, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are all high. Under the control of the Reset signal terminal, the first transistor T1 is turned on, and the initialization signal is written to the fourth node N4 along the path from the initialization signal terminal Vinit through the first transistor T1, thereby resetting the gate voltage of the third transistor T3.

[0199] During the data writing phase, the low level of the scan signal terminal Gate is an effective level, while the reset signal terminal Reset, the first light-emitting control signal terminal EM1, the second light-emitting control signal terminal EM2, and the third light-emitting control signal terminal EM3 are at high levels. Under the control of the scan signal terminal Gate, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. The data signal is written to the fourth node N4 along the path from the data signal terminal Data through the fourth transistor T4, the fifth node N5, the third transistor T3, the sixth node N6, and the second transistor T2. At the same time, the initialization signal is written to the first node N1 along the path from the initialization signal terminal Vinit through the seventh transistor T7, thereby resetting the voltage of the first electrode 410 of the light-emitting device 310.

[0200] During the light-emitting phase, the low level of the first light-emitting control signal terminal EM1 is an effective level, while the Reset signal terminal, the Gate signal terminal, and the second light-emitting control signal terminal EM2 are at high levels. Under the control of the first light-emitting control signal terminal EM1, the fifth transistor T5 and the sixth transistor T6 are turned on, and the eighth transistor T8 is turned off by the high level of the second light-emitting control signal terminal EM2. The third transistor T3 is turned on by the voltage signal stored in the storage capacitor C. The driving current is applied to the second light-emitting unit 440 and the first light-emitting unit 420 along the path from the sixth transistor T6, the third transistor T3, and the fifth transistor T5, so that the first light-emitting unit 420 and the second light-emitting unit 440 emit light.

[0201] At least some embodiments of this disclosure also provide a display device comprising the display substrate described above. The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0202] At least some embodiments of this disclosure also provide a display device including the pixel driving circuit described above.

[0203] It should be understood that the display device according to some exemplary embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be referred to in the above description of the display substrate and will not be repeated here.

[0204] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0205] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate; A driving circuit layer, located on the substrate, includes a plurality of pixel driving circuits; and The light-emitting device layer is located on the side of the driving circuit layer away from the substrate. The light-emitting device layer includes a plurality of light-emitting devices arranged at intervals, and the plurality of light-emitting devices are electrically connected to a plurality of pixel driving circuits respectively. Wherein, at least one light-emitting device includes a stacked light-emitting device, the stacked light-emitting device including a first electrode, a first light-emitting unit located on the side of the first electrode away from the substrate, a second electrode located on the side of the first light-emitting unit away from the substrate, a second light-emitting unit located on the side of the second electrode away from the substrate, and a third electrode located on the side of the second light-emitting unit away from the substrate; The pixel driving circuit includes a plurality of transistors, the first electrode is electrically connected to at least one of the transistors, the second electrode is electrically connected to at least one of the transistors, and the transistors electrically connected to the first electrode and the transistors electrically connected to the second electrode are different.

2. The display substrate according to claim 1, wherein, The display substrate further includes a pixel defining layer, which is located between the first electrode and the first light-emitting unit. The pixel defining layer includes a plurality of openings, each of which exposes a portion of a plurality of the first electrodes. as well as The orthogonal projection of at least one of the second electrodes on the substrate covers the orthogonal projection of at least one of the openings on the substrate.

3. The display substrate according to claim 1, wherein, The display substrate further includes a pixel defining layer, which is located between the first electrode and the first light-emitting unit. The pixel defining layer includes a plurality of openings, each of which exposes a portion of a plurality of the first electrodes. as well as At least one of the second electrodes has its orthographic projection on the substrate overlaps with the orthographic projection portion of at least one of the openings on the substrate.

4. The display substrate according to claim 3, wherein, The overlapping portion of the orthographic projection of at least one of the second electrodes on the substrate and the orthographic projection of at least one of the openings on the substrate is annular; and / or, The orthographic projection of at least one of the second electrodes on the substrate falls within the orthographic projection of at least one of the openings on the substrate; And / or, At least one of the second electrodes has its orthogonal projection onto the substrate covering a portion of the edge of the orthogonal projection of at least one of the openings onto the substrate.

5. The display substrate according to any one of claims 1-4, wherein, The plurality of light-emitting devices include a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices, wherein the first light-emitting devices, the second light-emitting devices, and the third light-emitting devices all include the stacked light-emitting devices.

6. The display substrate according to any one of claims 1-4, wherein, The plurality of light-emitting devices include a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices, wherein at least one of the first light-emitting devices, the second light-emitting devices, and the third light-emitting devices includes the stacked light-emitting device; and At least one of the first light-emitting device, the second light-emitting device, and the third light-emitting device includes a single-layer light-emitting device, the single-layer light-emitting device including a fourth electrode, a third light-emitting unit located on the side of the fourth electrode away from the substrate, and a fifth electrode located on the side of the third light-emitting unit away from the substrate, the fourth electrode being electrically connected to at least one of the transistors.

7. The display substrate according to claim 6, wherein, The first light-emitting device includes the stacked light-emitting device, the second light-emitting device includes the stacked light-emitting device, and the third light-emitting device includes the single-layer light-emitting device; and The first light-emitting device emits red light, the second light-emitting device emits green light, and the third light-emitting device emits blue light.

8. The display substrate according to claim 6, wherein, The first light-emitting device includes the single-layer light-emitting device, the second light-emitting device includes the single-layer light-emitting device, and the third light-emitting device includes the stacked light-emitting device; and The first light-emitting device emits red light, the second light-emitting device emits green light, and the third light-emitting device emits blue light.

9. The display substrate according to claim 6, wherein, The pixel defining layer includes a first via, and the first via is spaced apart from the opening; as well as The array substrate further includes a second electrode lead, which is connected to the second electrode as an integral structure. The second electrode lead is electrically connected to the transistor of the pixel driving circuit through the first via.

10. The display substrate according to claim 9, wherein, In at least two adjacent stacked light-emitting devices, the first light-emitting unit of one stacked light-emitting device is spaced apart from the first light-emitting unit of the other stacked light-emitting device; as well as The orthographic projection of the first via on the substrate is located in the interval region between the orthographic projections of two adjacent first light-emitting units on the substrate.

11. The display substrate according to claim 10, wherein, In at least two adjacent stacked light-emitting devices, the second light-emitting unit of one stacked light-emitting device is spaced apart from the second light-emitting unit of the other stacked light-emitting device.

12. The display substrate according to claim 11, wherein, The third electrodes of the plurality of stacked light-emitting devices are connected to form a third electrode layer with an integral structure. The third electrode layer has a hollow portion. The orthographic projection of the hollow portion on the substrate overlaps at least partially with the orthographic projection of the second electrode lead on the substrate. The third electrode layer and the second electrode lead are spaced apart.

13. A display method for a display substrate, wherein, Applied to a display substrate according to any one of claims 1-12, the display method includes: Obtain the image information to be displayed; Based on the image information to be displayed, multiple stacked light-emitting devices are divided into at least one first stacked light-emitting device and at least one second stacked light-emitting device; and In response to the image information to be displayed, both the first and second light-emitting units in the first stacked light-emitting device emit light and reach the target brightness, and either the first or second light-emitting unit in the second stacked light-emitting device emits light and reaches the target brightness.

14. A pixel driving circuit, wherein, The pixel driving circuit is configured to drive a light-emitting device to emit light. The light-emitting device includes a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on the side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on the side of the second electrode away from the first electrode, and a third electrode located on the side of the second light-emitting unit away from the first electrode. The pixel driving circuit includes: The driving sub-circuit is electrically connected to the light-emitting device; A data writing sub-circuit is electrically connected to a data signal terminal, a scan signal terminal, and the driving sub-circuit. The data writing sub-circuit is configured to write a data signal from the data signal terminal into the driving sub-circuit under the control of a scan signal from the scan signal terminal. A first light-emitting control sub-circuit is electrically connected to the driving sub-circuit, the first light-emitting control signal terminal, and the first electrode of the light-emitting device; and The second light-emitting control sub-circuit is electrically connected to the driving sub-circuit, the second light-emitting control signal terminal, and the second electrode of the light-emitting device.

15. The pixel driving circuit according to claim 14, wherein, The driving sub-circuit includes a third transistor; The first light-emitting control sub-circuit includes a fifth transistor, the first electrode of the fifth transistor is electrically connected to the second electrode of the third transistor, the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting device, and the gate of the fifth transistor is electrically connected to the first light-emitting signal control terminal; The second light-emitting control sub-circuit includes an eighth transistor, the first electrode of which is electrically connected to the second electrode of the third transistor, the second electrode of which is electrically connected to the second electrode of the light-emitting device, and the gate of which is electrically connected to the second light-emitting signal control terminal.

16. A driving method for a pixel driving circuit, wherein, The driving method, applied to the pixel driving circuit according to claim 14 or 15, comprises: Under the control of the scanning signal, the data writing sub-circuit writes the data signal into the driving sub-circuit; In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned off, the second light-emitting control sub-circuit is turned on, and the second light-emitting control sub-circuit controls the driving sub-circuit to output driving current only to the second light-emitting unit; and In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned on and the second light-emitting control sub-circuit is turned off. The first light-emitting control sub-circuit controls the driving sub-circuit to output driving current to the first light-emitting unit and the second light-emitting unit.

17. A pixel driving circuit, wherein, The pixel driving circuit is configured to drive a light-emitting device to emit light. The light-emitting device includes a first electrode, a first light-emitting unit located on the first electrode, a second electrode located on the side of the first light-emitting unit away from the first electrode, a second light-emitting unit located on the side of the second electrode away from the first electrode, and a third electrode located on the side of the second light-emitting unit away from the first electrode. The pixel driving circuit includes: The driving sub-circuit is electrically connected to the light-emitting device; A data writing sub-circuit is electrically connected to a data signal terminal, a scan signal terminal, and the driving sub-circuit. The data writing sub-circuit is configured to write a data signal from the data signal terminal into the driving sub-circuit under the control of a scan signal from the scan signal terminal. A first light-emitting control sub-circuit is electrically connected to the driving sub-circuit, the first light-emitting control signal terminal, and the first electrode of the light-emitting device; and The second light-emitting control sub-circuit is electrically connected to the second electrode, the second power supply terminal, and the second light-emitting control signal terminal of the light-emitting device.

18. The pixel driving circuit according to claim 17, wherein, The driving sub-circuit includes a third transistor; The first light-emitting control sub-circuit includes a fifth transistor, the first electrode of the fifth transistor is electrically connected to the second electrode of the third transistor, the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting device, and the gate of the fifth transistor is electrically connected to the first light-emitting signal control terminal; as well as The second light-emitting control sub-circuit includes an eighth transistor, the first electrode of which is electrically connected to the second electrode of the light-emitting device, the second electrode of which is electrically connected to the second power supply terminal, and the gate of which is electrically connected to the second light-emitting signal control terminal.

19. A driving method for a pixel driving circuit, wherein, The driving method, applied to the pixel driving circuit according to claim 17 or 18, comprises: Under the control of the scanning signal, the data writing sub-circuit writes the data signal into the driving sub-circuit; In response to the first driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned on, the second light-emitting control sub-circuit is turned on, and the first light-emitting control sub-circuit and the second light-emitting control sub-circuit control the driving sub-circuit to output driving current only to the first light-emitting unit; and In response to the second driving mode, under the control of the first light-emitting control signal and the second light-emitting control signal, the first light-emitting control sub-circuit is turned on and the second light-emitting control sub-circuit is turned off. The first light-emitting control sub-circuit controls the driving sub-circuit to output driving current to the first light-emitting unit and the second light-emitting unit.

20. A display device, wherein, The display device includes a display substrate according to any one of claims 1-12, or includes a pixel driving circuit according to any one of claims 14-15 and 17-18.

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