Display substrate, display panel, display apparatus, and manufacturing method for display panel

Abstract

Disclosed are a display substrate, a display panel, a display apparatus, and a manufacturing method for the display panel. The display substrate comprises: a plurality of heating trace groups, each heating trace group comprising: at least two heating traces extending in a second direction, and a first lead-out terminal and a second lead-out terminal connected to the heating tracings; a first bonding terminal group, the first bonding terminal group comprising: a first bonding terminal pair, the first bonding terminal pair comprising two first bonding terminals; one end of one of the first bonding terminals in the first bonding terminal pair is electrically connected to the first lead-out terminal, and one end of the other of the first bonding terminals in the first bonding terminal pair is electrically connected to the second lead-out terminal; and a test pad group, comprising two test pads arranged in the second direction.

Description

Method for manufacturing display substrate, display panel, display device, and display panel

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510105465.1, filed on January 22, 2025, with the State Intellectual Property Office of the People's Republic of China, entitled "Display Substrate, Display Panel, Display Device and Method for Manufacturing Display Panel", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display technology, and more particularly to a display substrate, a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0004] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] This disclosure provides an embodiment of the present invention.

[0006] A display substrate, a display panel, a display device, and a method for manufacturing the display panel. The display substrate has a display area and a peripheral area surrounding the display area; wherein, it includes:

[0007] Substrate;

[0008] Multiple heating trace groups, at least a portion of which are located in the display area, are arranged along a first direction and extend along a second direction; each heating trace group includes at least two heating traces extending along the second direction, and a first lead-out terminal and a second lead-out terminal connected to the heating traces.

[0009] A first bonding terminal group is located in the peripheral area; the first bonding terminal group includes: a plurality of first bonding terminal pairs arranged along a first direction, each first bonding terminal pair including two first bonding terminals; one end of one of the first bonding terminals in the first bonding terminal pair is electrically connected to the first lead-out terminal, and one end of the other first bonding terminal in the first bonding terminal pair is electrically connected to the second lead-out terminal;

[0010] A detection pad assembly includes two detection pads arranged along the second direction; wherein one of the detection pads is configured to receive a first detection signal to provide the first detection signal to one of the first bonding terminals in each of the first bonding terminal pairs, and wherein the other detection pad is configured to receive a second detection signal to provide the second detection signal to the other of the first bonding terminal pairs.

[0011] In one possible implementation, a plurality of first adapter electrodes are located in the peripheral region and on the side of the first bonding terminal opposite to the substrate; at least a portion of the first adapter electrodes in the orthographic projection onto the substrate overlaps with the orthographic projection of the first bonding terminal onto the substrate, and are electrically connected via vias at the overlap locations.

[0012] The first adapter electrode includes a first adapter portion and a second adapter portion; both the first adapter portion and the second adapter portion extend along the second direction, and the first adapter portion is located on the side of the first adapter portion away from the display area;

[0013] The width of the second adapter in the first direction is less than the width of the second adapter in the first direction; in the first direction, the minimum spacing between adjacent second adapters is greater than the minimum distance between adjacent first adapters.

[0014] In one possible implementation, the detection pad includes: a first detection electrode, and a second transfer electrode located on the side of the first detection electrode opposite to the substrate;

[0015] The second transfer electrode overlaps with the first detection electrode in the substrate in at least a portion of its orthogonal projection onto the substrate, and is electrically connected via a via at the overlapping position.

[0016] In one possible implementation, the second adapter electrode includes a third adapter portion and a fourth adapter portion; the fourth adapter portion is located on the side of the third adapter portion away from the display area;

[0017] The width of the fourth transition portion in the second direction is smaller than the width of the third transition portion in the second direction; and the minimum distance between adjacent fourth transition portions in the second direction is greater than the minimum distance between adjacent third transition portions.

[0018] In one possible implementation, the first detection electrode includes: a first hollow portion and a first surrounding portion located around the first hollow portion; the orthographic projection of the third adapter portion on the substrate covers the orthographic projection of the first surrounding portion on the substrate.

[0019] In one possible implementation, the detection pad further includes a second detection electrode located on the side of the first detection electrode facing the substrate;

[0020] The orthographic projection of the second detection electrode onto the substrate overlaps with the orthographic projection of the first detection electrode onto the substrate.

[0021] In one possible implementation, the second detection electrode includes: a second hollow portion and a second surrounding portion located around the second hollow portion; the orthographic projection of the second surrounding portion on the substrate overlaps with the orthographic projection of the first surrounding portion on the substrate.

[0022] In one possible implementation, the display substrate further includes an electrostatic structure and a first grounding wire; the detection pad is connected to the first grounding wire through the electrostatic structure.

[0023] In one possible implementation, the display substrate includes: a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction, a common electrode, and a plurality of pixel electrodes;

[0024] The display substrate further includes: a first detection circuit and a second detection circuit located in the peripheral area; the first detection circuit includes: a plurality of first transistors, a first signal line, and a second signal line; the second detection circuit includes: a plurality of second transistors, a third signal line, and a fourth signal line; the first transistor includes: a first control electrode, a first source electrode, and a first drain electrode; the second transistor includes: a second control electrode, a second source electrode, and a second drain electrode.

[0025] The first control electrode of each first transistor is electrically connected to the first signal line; the first source of each first transistor is electrically connected to the second signal line; the first drain of each first transistor is electrically connected to the gate line; the second control electrode of each second transistor is electrically connected to the third signal line; the second source of each second transistor is electrically connected to the fourth signal line; and the second drain of each second transistor is electrically connected to the data line.

[0026] In one possible implementation, the plurality of gate lines includes: a plurality of first sub-gate lines and a plurality of second sub-gate lines; the plurality of data lines includes: a plurality of first sub-data lines, a plurality of second sub-data lines, and a plurality of third sub-data lines; the plurality of first transistors includes: a plurality of first sub-transistors and a plurality of second sub-transistors; the second signal line includes: a first sub-signal line and a second sub-signal line; the plurality of second transistors includes: a plurality of third sub-transistors, a plurality of fourth sub-transistors, and a plurality of fifth sub-transistors; the fourth signal line includes: a third sub-signal line, a fourth sub-signal line, and a fifth sub-signal line.

[0027] The first source of each first sub-transistor is electrically connected to the first sub-signal line, and the first drain of each first sub-transistor is electrically connected to the first sub-gate line; the first source of each second sub-transistor is electrically connected to the second sub-signal line, and the first drain of each second sub-transistor is electrically connected to the second sub-gate line.

[0028] The second source of each of the third sub-transistors is electrically connected to the third sub-signal line, and the second drain of each of the third sub-transistors is electrically connected to the first sub-data line; the second source of each of the fourth sub-transistors is electrically connected to the fourth sub-signal line, and the second drain of each of the fourth sub-transistors is electrically connected to the second sub-data line; the second source of each of the fifth sub-transistors is electrically connected to the fifth sub-signal line, and the second drain of each of the fifth sub-transistors is electrically connected to the third sub-data line.

[0029] In one possible implementation, the data line is located on the side of the layer containing the gate line away from the substrate, the common electrode is located on the side of the layer containing the data line away from the layer containing the gate line, the pixel electrode is located on the side of the common electrode away from the layer containing the data line, and the heating trace is located between the layer containing the data line and the layer containing the common electrode.

[0030] The heating trace and the first bonding terminal are in the same layer and made of the same material; the first adapter electrode is in the same layer and made of the same material as either the pixel electrode or the common electrode.

[0031] This disclosure also provides a display panel, which includes the display substrate as provided in this disclosure, and a counter substrate disposed opposite to the display substrate.

[0032] This disclosure also provides a display device, which includes the display panel as described in this disclosure.

[0033] This disclosure also provides a method for manufacturing a display panel, comprising:

[0034] The front-end display substrate and the opposing substrate are assembled; wherein, the front-end display substrate includes the display substrate provided in the embodiments of the present invention, and further includes: a first detection line and a second detection line; the first detection line is connected to one of the detection pads, and the second detection line is connected to the other detection pad; one of the first bonding terminals in each of the first bonding terminal pairs is connected to the first detection line, and the other first bonding terminal in each of the first bonding terminal pairs is connected to the second detection line;

[0035] Inspect the display panel behind the box assembly;

[0036] When the display panel is confirmed to be a first type of display panel, the display panel is cut, wherein at least a portion of the first detection line and at least a portion of the second detection line are cut off.

[0037] In one possible implementation, the detection of the display panel behind the box includes:

[0038] Among the first signal line, the second signal line, the third signal line, and the fourth signal line, an effective level signal is provided to the first signal line, the second signal line, and the third signal line, and a first detection signal is provided to one of the detection pads, and a second detection signal is provided to the other detection pad;

[0039] When the display panel displays a black screen, it is confirmed that the display panel is the first type of display panel;

[0040] If the display panel has poor linearity or displays a grayscale image, the display panel is confirmed to be a second type of display panel.

[0041] In one possible implementation, the detection of the display panel behind the box includes:

[0042] Among the first signal line, the second signal line, the third signal line, and the fourth signal line, an effective level signal is provided to the first signal line, the second signal line, and the fourth signal line, and a first detection signal is provided to one of the detection pads, and a second detection signal is provided to the other detection pad;

[0043] When the display panel displays a black screen, it is confirmed that the display panel is the first type of display panel;

[0044] When the display panel displays a white screen, it is confirmed that the display panel is a second type of display panel. Attached Figure Description

[0045] Figure 1A is a schematic diagram of the front-end display substrate provided in an embodiment of this disclosure;

[0046] Figure 1B is a connection diagram of a heating wiring assembly provided in an embodiment of this disclosure;

[0047] Figure 1C is a connection diagram of another heating wiring assembly provided in an embodiment of this disclosure;

[0048] Figure 2A is an enlarged view of the location S01 within the dashed line frame in Figure 1A;

[0049] Figure 2B is a schematic diagram of the first bonding terminal in Figure 2A;

[0050] Figure 2C is a schematic diagram of the single film layer of the first transfer electrode in Figure 2A;

[0051] Figure 2D is a cross-sectional view along the dashed line A1-A1' in Figure 2A;

[0052] Figure 3A is an enlarged view of the location S02 within the dashed line frame in Figure 1A;

[0053] Figure 3B is a schematic diagram of the layer where the second detection electrode is located in Figure 3A;

[0054] Figure 3C is a schematic diagram of the active layer in Figure 3A;

[0055] Figure 3D is a schematic diagram of the layer where the first detection electrode is located in Figure 3A;

[0056] Figure 3E is a schematic diagram of the film layers containing the first and second detection lines in Figure 3A.

[0057] Figure 3F is a schematic diagram of the film layer where the second transfer electrode is located in Figure 3A;

[0058] Figure 4 is a schematic diagram of the manufacturing process of the display substrate provided in an embodiment of the present invention;

[0059] Figure 5A is one of the schematic diagrams of the display substrate structure provided in the embodiments of this disclosure;

[0060] Figure 5B is a schematic diagram of the film layer where the gate lines are located in Figure 5A;

[0061] Figure 5C is a schematic diagram of the film layer containing the active layer in Figure 5A;

[0062] Figure 5D is a schematic diagram of the film layer where the data line is located in Figure 5A;

[0063] Figure 5E is a schematic diagram of the film layer in Figure 5A where the lower left layer is heated;

[0064] Figure 5F is a schematic diagram of the film layer where the common electrode is located in Figure 5A;

[0065] Figure 5G is a schematic diagram of the film layer where the pixel electrode is located in Figure 5A;

[0066] Figure 5H is a schematic cross-sectional view along the dashed line A2-A2' in Figure 5A;

[0067] Figure 6 is a schematic diagram of the first detection circuit provided in an embodiment of the present invention;

[0068] Figure 7 is a schematic diagram of the second detection circuit provided in an embodiment of the present invention;

[0069] Figure 8 is a schematic diagram of the detection signal line corresponding to Figure 5A;

[0070] Figure 9A can be a partial schematic diagram of the second peripheral area BB2;

[0071] Figure 9B is a cross-sectional view of Figure 9A along the dashed line A3-A3';

[0072] Figure 10 is a schematic diagram of the detection signal corresponding to Figure 9A;

[0073] Figure 11A can be a partial schematic diagram of the fourth peripheral area BB4;

[0074] Figure 11B is a schematic diagram of the stacking of heating trace J and common electrode 5 in Figure 11A;

[0075] Figure 11C can be a partial schematic diagram of the first peripheral area BB1;

[0076] Figure 11D is a schematic diagram of the stacking of heating trace J and common electrode 5 in Figure 11C;

[0077] Figure 11E can be a cross-sectional view of Figure 11A or Figure 11C along the dashed line A4-A4';

[0078] Figure 12 is a schematic diagram of the detection signal corresponding to Figure 11A;

[0079] Figure 13 is a schematic diagram of the display panel manufacturing process provided in the embodiments of this disclosure. Detailed Implementation

[0080] for

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0082] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0083] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0084] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0085] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0086] Referring to Figures 5A-5H, where Figure 5A is a schematic diagram of one of the display substrate structures provided in the embodiments of this disclosure, Figure 5B is a schematic diagram of the film layer of the gate line in Figure 5A, Figure 5C is a schematic diagram of the film layer of the active layer in Figure 5A, Figure 5D is a schematic diagram of the film layer of the data line in Figure 5A, Figure 5E is a schematic diagram of the film layer of the lower left heating element in Figure 5A, Figure 5F is a schematic diagram of the film layer of the common electrode in Figure 5A, Figure 5G is a schematic diagram of the film layer of the pixel electrode in Figure 5A, and Figure 5H is a cross-sectional schematic diagram along the dashed line A2-A2' in Figure 5A.

[0087] This disclosure provides a display substrate comprising: multiple gate lines 2 extending along a first direction X, multiple data lines 3 extending along a second direction Y, multiple heating traces J, a common electrode 5, and multiple pixel electrodes 4; the data lines 3 are located on the side of the layer containing the gate lines 2 away from the substrate 1, the common electrode 5 is located on the side of the layer containing the data lines 3 away from the layer containing the gate lines 2; the pixel electrodes 4 are located on the side of the common electrode 5 away from the layer containing the data lines 3; the heating traces J are located between the layer containing the data lines 3 and the layer containing the common electrode 5; the heating traces J and the first bonding terminal C1 are in the same layer and made of the same material; the first adapter electrode D1 is in the same layer and made of the same material as either the pixel electrode 4 or the common electrode 5.

[0088] Optionally, as shown in Figure 4, during the fabrication of the display substrate, a gate line layer (which may include multiple gate lines 2 extending along a first direction), a gate insulating layer 91, an active layer (which may include multiple active patterns 60), a data line layer (which may include multiple data lines 3 extending along a second direction), a first passivation layer 92, a heating structure layer (which may include heating traces J), a second passivation layer 93, a common electrode layer (which may be a transparent conductive layer), a third passivation layer 94, and a pixel electrode layer (which may include multiple pixel electrodes 4) can be sequentially formed on the substrate 1. The above is only one film layer stacking structure of the display substrate provided in this embodiment. In specific implementation, the display substrate may also be stacked in other ways, and this embodiment does not limit it here.

[0089] In low-temperature environments, liquid crystal viscosity is high, requiring in-cell heating to increase the liquid crystal temperature for normal display. Incorporating heating wires within the cell is a highly effective solution. However, adding heating wires increases process complexity and the number of masks, leading to a higher defect rate. Furthermore, particles present during manufacturing can cause short circuits between the heating wires and other signal layers, resulting in defective modules and wasting IC, FPC, and backlight components. Therefore, screening out these heating wire-related defects before bonding is crucial to prevent material waste and save costs.

[0090] Referring to Figures 1A, 2A-2D, and 3A-3F, where Figure 1A is a schematic diagram of the front-end display substrate provided in an embodiment of this disclosure, Figure 2A is an enlarged schematic diagram of the position of the dashed frame S01 in Figure 1A, Figure 2B is a schematic diagram of the first bonding terminal in Figure 2A, Figure 2C is a schematic diagram of the single film layer of the first transition electrode in Figure 2A, Figure 2D is a cross-sectional schematic diagram along the dashed line A1-A1' in Figure 2A, Figure 3A is an enlarged schematic diagram of the position of the dashed frame S02 in Figure 1A, Figure 3B is a schematic diagram of the layer where the second detection electrode is located in Figure 3A, Figure 3C is a schematic diagram of the film layer of the active layer in Figure 3A, Figure 3D is a schematic diagram of the layer where the first detection electrode is located in Figure 3A, Figure 3E is a schematic diagram of the film layer of the layers where the first detection line and the second detection line are located in Figure 3A, and Figure 3F is a schematic diagram of the film layer of the layer where the second transition electrode is located in Figure 3A, this embodiment of the invention provides a display substrate having a display area AA and a peripheral area BB located around the display area AA; wherein, it includes:

[0091] Substrate 1;

[0092] Multiple heating trace groups JZ, at least a portion of which are located in display area AA, are arranged along a first direction X and extend along a second direction Y. Each heating trace group JZ includes at least two heating traces J extending along the second direction Y, and a first lead-out terminal JO1 and a second lead-out terminal JO2 connected to the heating traces J. Optionally, the multiple heating trace groups JZ may include multiple first heating trace groups JZ1 and multiple second heating trace groups JZ2. Each first heating trace group JZ1 may include multiple first heating traces J1 extending along the second direction Y. At least a portion of the first heating trace group JZ1 is located in display area AA and is used to heat display area AA. Each second heating trace group JZ2 may include multiple second heating traces J2 extending along the second direction Y. The multiple second heating trace groups JZ2 may be located in peripheral area BB and are used to heat peripheral area BB. Each heating trace J includes a first heating trace J1 and a second heating trace J2.

[0093] The first bonding terminal group C is located in the peripheral area BB; the first bonding terminal group C includes: a plurality of first bonding terminal pairs C0 arranged along the first direction X, each first bonding terminal pair C0 including two first bonding terminals C1; one end of one of the first bonding terminals C1 in the first bonding terminal pair C0 is electrically connected to the first lead JO1, and one end of the other first bonding terminal C1 in the first bonding terminal pair C0 is electrically connected to the second lead JO2;

[0094] The detection pad group E includes two detection pads E1 arranged along the second direction Y; wherein one detection pad E1 is configured to receive a first detection signal to provide the first detection signal to one of the first binding terminals C1 in each first binding terminal pair C0, and the other detection pad E1 is configured to receive a second detection signal to provide the second detection signal to the other first binding terminal C1 in each first binding terminal pair C0.

[0095] In this embodiment, the display substrate includes: multiple heating trace groups, multiple first bonding terminal pairs C0, and two detection pads E1. A first detection signal (e.g., a positive polarity signal) can be applied to one of the detection pads E1, and a second detection signal (e.g., a negative polarity signal) can be applied to the other detection pad E1. The first detection signal can be applied to a first lead-out terminal JO1 through one of the first bonding terminal pairs C0, and the second detection signal can be applied to a second lead-out terminal JO2 through the other first bonding terminal pair C0, forming a detection loop. That is, by connecting the two ends of at least two heating traces J in parallel and then connecting them to the two detection pads E1 respectively, it is possible to detect whether the heating traces J are short-circuited with the gate line, data line, or common electrode (or common trace) before the display panel is bonded to the control chip IC. This can reduce the waste of materials such as control chip IC and flexible circuit board.

[0096] In one possible implementation, referring to Figures 1A, 2A-2D, and 3A-3F, the display panel, before being cut (which can serve as a pre-drive substrate), may include: a first detection line H1 and a second detection line H2; the first detection line H1 is connected to one of the detection pads E1, and the second detection line H2 is connected to the other detection pad E1; one of the first bonding terminals C1 in each first bonding terminal pair C0 is connected to the first detection line H1, and the other first bonding terminal C1 in each first bonding terminal pair C0 is connected to the second detection line H2. After the display panel is inspected, the periphery of the display panel can be cut, for example, along the first dashed line S1 and the second dashed line S2 in Figure 1A, wherein at least a portion of the first detection line H1 and the second detection line H2 can be removed. The first detection line H1 and the second detection line H2 may be in the same layer and made of the same material as the heating trace J.

[0097] In one possible implementation, as shown in Figure 1A, the peripheral area BB may further include: a first peripheral area BB1, a second peripheral area BB2, a third peripheral area BB3, and a fourth peripheral area BB4; the first peripheral area BB1 and the fourth peripheral area BB4 are disposed opposite to each other, and the second peripheral area BB2 and the third peripheral area BB3 may be connected to the first peripheral area BB1 and the fourth peripheral area BB4; the first peripheral area BB1 may be provided with a terminal group for connecting to a data line, and the second peripheral area BB2 and the third peripheral area BB3 may be provided with a terminal group for connecting to a gate line (the gate drive circuit GOA may not be integrated on the display substrate), and the first bonding terminal group C connected to the heating trace J may be located in the fourth peripheral area BB4.

[0098] In one possible implementation, referring to Figures 1B and 1C, the heating trace group JZ may include multiple heating traces J; within the same heating trace group JZ, one end of each heating trace J (e.g., the end near the first peripheral region BB1) is interconnected, and the other end of each heating trace J (e.g., the end near the fourth peripheral region BB4) can be divided into two groups, with the same group interconnected to form two output terminals; for example, as shown in Figure 1B, the heating trace group JZ may include two heating traces J, and one end of the two heating traces J (e.g., the end near the first peripheral region BB1) One end of each heating trace is connected to the other end of the heating trace (e.g., the end near the fourth peripheral area BB4) and the other end of the heating trace is connected to the other end of the heating trace (e.g., the end near the fourth peripheral area BB4) respectively, forming the first lead-out terminal JO1 and the second lead-out terminal JO2. In another possible implementation, as shown in FIG1C, the heating trace group JZ includes four heating traces J. One end of each heating trace J (e.g., the end near the first peripheral area BB1) is connected to the other end of the heating trace (e.g., the end near the fourth peripheral area BB4) and the other end of the heating trace is connected to the other end of the heating trace (e.g., the end near the fourth peripheral area BB4) respectively, forming the first lead-out terminal JO1 and the second lead-out terminal JO2 respectively.

[0099] In this embodiment of the present disclosure, the display substrate has multiple heating trace groups JZ. In the same heating trace group JZ, the ends of each heating trace J near the first peripheral area BB1 are electrically connected, and the ends of some adjacent heating traces J near the fourth peripheral area BB4 are electrically connected. That is, by connecting some heating traces J in parallel, the density of heating traces J can be reduced, the spacing between heating traces J in the display area AA can be increased, and more wiring space can be provided for other structures (such as photosensitive structures).

[0100] In one possible implementation, the display substrate includes: a plurality of pixel electrode columns extending along a second direction Y and arranged along a first direction X; the pixel electrode columns include: a plurality of pixel electrodes 4 arranged along the second direction Y; the orthographic projection of the first heating trace J1 onto the substrate 1 may be located at the orthographic projection of the gap between two adjacent pixel electrode columns onto the substrate 1; optionally, each pixel (a pixel may include three sub-pixels) may be provided with one first heating trace J1; optionally, each pixel (a pixel may include three sub-pixels) may be provided with three first heating traces J1, that is, each sub-pixel may be provided with one first heating trace J1.

[0101] In one possible implementation, referring to Figures 2A-2D, the display substrate further includes: a plurality of first transition electrodes D1 located in the peripheral area BB and on the side of the first bonding terminal C1 facing away from the substrate 1; at least a portion of the first transition electrode D1 projected onto the substrate 1 overlaps with the first bonding terminal C1 projected onto the substrate 1, and is electrically connected at the overlapping position through vias; for example, the first transition electrode D1 and the first bonding terminal C1 are electrically connected at the overlapping position through a first via group K10, the first via group K10 may include a plurality of first vias K1; optionally, the resistance of the first transition electrode D1 may be greater than the resistance of the first detection line H1, the second detection line H2 and / or the first bonding terminal C1, and the first transition electrode D1 may be disposed in the same layer and with the same material as one of the pixel electrode 4 and the common electrode 5;

[0102] The first adapter electrode D1 includes a first adapter portion D11 and a second adapter portion D12; both the first adapter portion D11 and the second adapter portion D12 extend along the second direction Y, and the second adapter portion D12 is located on the side of the first adapter portion D1 away from the display area AA.

[0103] The width a2 of the second transition part D12 in the first direction X is smaller than the width a1 of the first transition part D11 in the first direction X; in the first direction X, the minimum distance a4 between adjacent second transition parts D12 is greater than the minimum distance a3 between adjacent first transition parts D11.

[0104] In this embodiment, the display substrate further includes a plurality of first transfer electrodes D1, that is, the first bonding terminal C1 is transferred to the location of the first detection line H1 and the second detection line H2 through the first transfer electrodes D1. Since the resistance of the first transfer electrode D1 (for example, the first transfer electrode D1 can be indium tin oxide in the same layer as one of the pixel electrode 4 and the common electrode 5) is greater than the metal resistance, it can prevent static electricity from entering and damaging the first bonding terminal C1. Moreover, the first transfer electrode D1 includes a first transfer portion D11 and a second transfer portion D12. The second transfer portion D12 is located on the side of the first transfer portion D1 away from the display area AA. The minimum distance a4 between adjacent second transfer portions D12 is greater than the minimum distance a3 between adjacent first transfer portions D11. That is, increasing the distance between adjacent second transfer portions D12 can reduce the problem that when debris or particles generated by cutting the display panel fall on two adjacent second transfer portions D12, it is easy to cause a short circuit between the second transfer portions D12, thereby causing the display panel to have display defects.

[0105] In one possible implementation, as shown in Figures 2A-2D, before the display panel is cut, the display substrate may have multiple pads F. This can improve the situation where the antenna effect is prone to occur due to the long traces of the first detection line H1 and the second detection line H2, resulting in a large amount of charge and electrostatic breakdown. The pads F can concentrate other charges on the first detection line H1 and the second detection line H2 to the location with the pads F, thereby preventing the risk of electrostatic accumulation on the first bonding terminal C1 and causing damage to the first bonding terminal C1.

[0106] In one possible implementation, as shown in Figures 3A-3F, the detection pad E1 includes: a first detection electrode E11, and a second transfer electrode D2 located on the side of the first detection electrode E11 facing away from the substrate 1; optionally, the first detection electrode E11 can be in the same layer and material as the data line 3; the second transfer electrode D2 can be in the same layer and material as the first transfer electrode D1.

[0107] At least a portion of the second transfer electrode D2 projected onto the substrate 1 overlaps with the projected image of the first detection electrode E11 onto the substrate 1, and they are electrically connected at the overlapping location via vias. For example, the second transfer electrode D2 and the first detection electrode E11 are electrically connected at the overlapping location via a second via group K20, which may include a plurality of second vias K2. In this embodiment, the detection pad E1 includes: a first detection electrode E11, and a second transfer electrode D2 located on the side of the first detection electrode E11 facing away from the substrate 1; wherein, since the resistance of the second transfer electrode D2 (for example, the second transfer electrode D2 may be indium tin oxide in the same layer as one of the pixel electrode 4 and the common electrode 5) is greater than the metal resistance, the probability of electrostatic discharge damaging the first bonding terminal C1 can be reduced.

[0108] In one possible implementation, as shown in Figures 3A-3F, the second adapter electrode D2 includes a third adapter portion D21 and a fourth adapter portion D22; the fourth adapter portion D22 is located on the side of the third adapter portion D21 away from the display area AA; the width b2 of the fourth adapter portion D22 in the second direction Y is smaller than the width b1 of the third adapter portion D21 in the second direction Y; in the second direction Y, the minimum distance b4 between adjacent fourth adapter portions D22 is greater than the minimum distance b4 between adjacent third adapter portions D21. In this embodiment of the present disclosure, the second adapter electrode D2 includes a third adapter portion D21 and a fourth adapter portion D22; the fourth adapter portion D22 is located on the side of the third adapter portion D21 away from the display area AA; the minimum distance b4 between adjacent fourth adapter portions D22 is greater than the minimum distance b4 between adjacent third adapter portions D21, that is, increasing the spacing between adjacent fourth adapter portions D22 can reduce the problem that when debris or particles generated by cutting the display panel fall on two adjacent fourth adapter portions D22, it is easy to cause a short circuit between the fourth adapter portions D22, thereby causing the display panel to have display defects.

[0109] In one possible implementation, as shown in Figures 3A-3F, the first detection electrode E11 includes: a first hollow portion E111, and a first surrounding portion E112 located around the first hollow portion E111; the orthographic projection of the third adapter portion D21 onto the substrate 1 covers the orthographic projection of the first surrounding portion E112 onto the substrate 1.

[0110] In one possible implementation, as shown in Figures 3A-3F, the detection pad E1 further includes a second detection electrode E12 located on the side of the first detection electrode E11 facing the substrate 1; the orthographic projection of the second detection electrode E12 onto the substrate 1 overlaps with the orthographic projection of the first detection electrode E11 onto the substrate 1. Optionally, the second detection electrode E12 may be in the same layer and made of the same material as the gate line 2.

[0111] In one possible implementation, as shown in Figures 3A-3F, the second detection electrode E12 includes: a second hollow portion E121, and a second surrounding portion E122 located around the second hollow portion E121; the orthographic projection of the second surrounding portion E122 onto the substrate 1 overlaps with the orthographic projection of the first surrounding portion E112 onto the substrate 1.

[0112] In one possible implementation, as shown in Figures 3A-3F, the detection pad E1 may further include a first mark 61 (“+” in Figure 3A) and a second mark 62 (“-” in Figure 3A) for alignment during the film fabrication process. The first mark 61 and the second mark 62 may be in the same layer and made of the same material as the active pattern 60.

[0113] In one possible implementation, as shown in Figures 3A-3F, the display substrate further includes: an electrostatic discharge (ESD) structure and a first grounding line GND; the detection pad E1 is connected to the first grounding line GND via the ESD structure. In this embodiment, the other side of the detection pad E1 is connected to the first grounding line GND via the ESD structure, which can conduct away static electricity on the first detection line H1 and the second detection line H2, preventing electrostatic discharge from causing electrostatic breakdown of the first bonding terminal C1.

[0114] In one possible implementation, as shown in Figures 3A-3F, the display substrate further includes a first common trace 51 located on the side of the first ground trace GND away from the detection pad E1; the first ground trace GND, the first common trace 51, and the gate line 2 may be of the same layer and material.

[0115] In one possible implementation, referring to Figures 6 and 7, the display substrate further includes: a first detection circuit Q1 located in the peripheral region BB, and a second detection circuit Q2; optionally, the first detection circuit Q1 can be a second peripheral region BB2 or a third peripheral region BB3; the second detection circuit Q2 can be the first peripheral region BB1; the first detection circuit Q1 includes: a plurality of first transistors T1, a first signal line G1, and a second signal line G2; the second detection circuit Q2 includes: a plurality of second transistors T2, a third signal line G3, and a fourth signal line G4; the first transistor T1 includes: a first control electrode T1A, a first source electrode T1B, and a first drain electrode T1C; the second transistor T2 includes: a second control electrode T2A, a second source electrode T2B, and a second drain electrode T2C;

[0116] The first control electrode T1A of each first transistor T1 is electrically connected to the first signal line G1; the first source electrode T1B of each first transistor T1 is electrically connected to the second signal line G2; and the first drain electrode T1C of each first transistor T1 is electrically connected to the gate line 2. The second control electrode T2A of each second transistor T2 is electrically connected to the third signal line G3; the second source electrode T2B of each second transistor T2 is electrically connected to the fourth signal line G4; and the second drain electrode T2C of each second transistor T2 is electrically connected to the data line 3.

[0117] In this embodiment, the first signal line G1 is the switching voltage that turns on the first transistor T1, and the third signal line G3 is the switching voltage that turns on the second transistor T2. When the first signal line G1 and the third signal line G3 are loaded with a valid signal (e.g., a high-level voltage VGH), the first transistor T1 and the second transistor T2 are turned on, and the voltages of the second signal line G2 and the fourth signal line G4 can be input to the display area AA. When the first signal line G1 and the third signal line G3 are loaded with an invalid signal (e.g., a low-level voltage VGL), the first transistor T1 and the second transistor T2 are turned off, and the voltages of the second signal line G2 and the fourth signal line G4 cannot be input to the display area AA. When the second signal line G2 is loaded with a valid signal (e.g., a high-level voltage VGH), the pixel transistors in the display area AA are turned on, and the voltage of the fourth signal line G4 can be input to the pixel electrode. When the second signal line G2 is loaded with an invalid signal (e.g., a low-level voltage VGL), the pixel transistors in the display area AA are turned off, and the voltage of the fourth signal line G4 cannot be input to the pixel electrode. The voltage of the fourth signal line G4 can be -5V (VDH) to 5V (VDL), and the voltage of the common electrode 5 (VCOM) can be 0V.

[0118] In one possible implementation, referring to Figures 6 and 7, the plurality of gate lines 2 include: a plurality of first sub-gate lines 21 (e.g., providing GO signals) and a plurality of second sub-gate lines 22 (e.g., providing GE signals); the plurality of data lines 3 include: a plurality of first sub-data lines 31 (data lines that can provide data signals for red sub-pixels), a plurality of second sub-data lines 32 (data lines that can provide data signals for green sub-pixels), and a plurality of third sub-data lines 33 (data lines that can provide data signals for blue sub-pixels); the plurality of first transistors T1 include: a plurality of first sub-transistors T11 and a plurality of second sub-transistors T12; the second signal line G2 includes: a first sub-signal line G21 and a second sub-signal line G22; the plurality of second transistors T2 includes: a plurality of third sub-transistors T2R, a plurality of fourth sub-transistors T2G, and a plurality of fifth sub-transistors T2B; the fourth signal line includes: a third sub-signal line G4R, a fourth sub-signal line G4G, and a fifth sub-signal line G4B;

[0119] The first source T1B of each first sub-transistor T11 is electrically connected to the first sub-signal line G21, and the first drain T1C of each first sub-transistor T11 is electrically connected to the first sub-gate line 21; the first source T1B of each second sub-transistor T12 is electrically connected to the second sub-signal line G22, and the first drain of each second sub-transistor T12 is electrically connected to the second sub-gate line 22.

[0120] The second source T2B of each third sub-transistor T2R is electrically connected to the third sub-signal line G4R, and the second drain T2C of each third sub-transistor T2R is electrically connected to the first sub-data line 31; the second source T2B of each fourth sub-transistor T2G is electrically connected to the fourth sub-signal line G4G, and the second drain T2C of each fourth sub-transistor T2G is electrically connected to the second sub-data line 32; the second source T2B of each fifth sub-transistor T2B is electrically connected to the fifth sub-signal line G4B, and the second drain T2C of each fifth sub-transistor T2B is electrically connected to the third sub-data line 33.

[0121] The detection method of this disclosure embodiment is illustrated by the following examples:

[0122] For example, referring to Figures 5A and 8, it is detected whether the heating trace J is short-circuited with the data line 3; wherein, an effective voltage (e.g., a high-level voltage VGH) is applied to the first signal line G1 and the third signal line G3, an effective voltage (e.g., a high-level voltage VGH) is applied to the second signal line G2, an ineffective voltage (e.g., a low-level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an ineffective voltage (e.g., a low-level voltage VGL, e.g., 0V) is applied to the common electrode 5, and 0V and 0V are applied to the two detection pads E1 respectively. 28V; As shown in Figure 5A, the heating trace J is directly above the data line 3. When the heating trace J and the data line 3 are not short-circuited, the voltage difference between the common electrode 5 and the pixel electrode 4 is 0V, the liquid crystal does not deflect, and the screen is black. When the second passivation layer 93 is damaged, causing the heating trace J and the data line 3 to short-circuit, the voltage of the data line 3 and the heating trace J is the same. Since the voltage on the heating trace J is not 0V, the voltage difference between the common electrode 5 and the pixel electrode 4 is not 0V. Therefore, the screen with the LED lit has a vertical linearity defect, and it can be determined that the product is defective.

[0123] For example, referring to Figures 9A, 9B, and 10, where Figure 9A can be a partial schematic diagram of the second peripheral area BB2, and Figure 9B is a cross-sectional schematic diagram of Figure 9A along the dashed line A3-A3', the detection process involves checking whether the heating trace J (the second heating trace J2) is short-circuited with the first fan-out trace FG (for example, the first fan-out trace FG can be a fan-out trace located in the second peripheral area BB2 connected to the gate line 2); applying an effective voltage (e.g., a high-level voltage VGH) to the first signal line G1 and the third signal line G3, applying an ineffective voltage (e.g., a low-level voltage VGL, for example, 0V, corresponding to the signal applied to the gate line 2) to the second signal line G2, applying an effective voltage (e.g., a high-level voltage VGH, for example, 5V, corresponding to the signal applied to the data line 3) to the fourth signal line G4, applying an ineffective voltage (e.g., a low-level voltage VGL, for example, 0V) to the common electrode 5, and applying 0V and 28V to the two detection pads E1 respectively; as shown in Figure 9A. As shown, the heating trace J (second heating trace J2) overlaps with the first fan-out trace FG (the first fan-out trace FG connected to the gate line 2, located in the layer where the gate line 2 is located). When there is no short circuit between the heating trace J (second heating trace J2) and the first fan-out trace FG, the pixel transistor of the display area AA is turned off because the voltage of the second signal line G2 (corresponding to the gate line 2) is VGL. Therefore, the voltage of the fourth signal line G4 (corresponding to the data line 3) cannot be input to the pixel electrode, so the detection screen is displayed as a black screen. When there is a crack in the gate insulating layer 91 and the first passivation layer 92, the heating trace J (second heating trace J2) and the first fan-out trace FG are short-circuited. Since the first fan-out trace FG is connected to the gate line 2, the voltage on the gate line 2 is the same as the voltage on the heating trace J (second heating trace J2), which is VGH. At this time, the pixel transistor of the display area is turned on, and the voltage (5V) of the fourth signal line G4 can be input to the pixel electrode, so the detection screen is displayed as a white screen. The display screen can be used to determine whether the product is defective. In this test screen, the voltage of the fourth signal line G4 can also be any other non-zero voltage value;

[0124] For example, referring to Figures 11A-11C and 12, where Figure 11A can be a partial schematic diagram of the fourth peripheral region BB4, Figure 11B can be a partial schematic diagram of the first peripheral region BB1, and Figure 11C can be a cross-sectional schematic diagram of Figure 11A or Figure 11B along the dashed line A4-A4', the system detects whether the heating trace J is short-circuited with the common trace 50 or the common electrode 5 (the common trace 50 can be connected to the common electrode 5); wherein, an effective voltage (e.g., a high-level voltage VGH) is applied to the first signal line G1 and the third signal line G3, an effective voltage (e.g., a high-level voltage VGH) is applied to the second signal line G2, an ineffective voltage (e.g., a low-level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an ineffective voltage (e.g., a low-level voltage VGL, e.g., 0V) is applied to the common electrode 5, and the two detection pads E1 are... Do not load 0V and 28V; as shown in Figures 11A and 11B, the heating trace J overlaps with the common trace 50 or the common electrode 5. When there is no short circuit between the heating trace J and the common trace 50 or the common electrode 5, the voltage of the second signal line G2 (corresponding to gate line 2) is VGH, and the pixel transistor of the display area AA is turned on. Therefore, the voltage (0V) of the fourth signal line G4 (corresponding to data line 3) is input to the pixel electrode, so the detection screen is displayed as a black screen. When there is a crack in the third passivation layer 93, the heating trace J and the common trace 50 (or the common electrode 5) are short-circuited. The voltage on the common trace 50 (or the common electrode 5) is the same as the voltage on the heating trace J, which is not 0V. At this time, the voltage difference between the pixel electrode and the common trace 50 (or the common electrode 5) is not 0V, and the detection screen is displayed as a grayscale screen. Based on the display screen, it can be determined whether the product is defective.

[0125] Based on the same inventive concept, this disclosure also provides a display panel, which includes a display substrate as provided in this disclosure, and a counter substrate disposed opposite to the display substrate.

[0126] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0127] Based on the same inventive concept, this disclosure also provides a method for manufacturing a display panel, as shown in Figure 13. The manufacturing method includes:

[0128] Step S100: Align the front-end display substrate with the opposing substrate; wherein, the front-end display substrate includes the display substrate as claimed in any one of claims 1-11, and further includes: a first detection line H1 and a second detection line H2; the first detection line H1 is connected to one of the detection pads E1, and the second detection line H2 is connected to the other detection pad E1; one of the first bonding terminals C1 in each first bonding terminal pair C0 is connected to the first detection line H1, and the other first bonding terminal C1 in each first bonding terminal pair C0 is connected to the second detection line H2;

[0129] Step S200: Inspect the display panel behind the box assembly;

[0130] Step S300: When it is confirmed that the display panel is a first-type display panel, the display panel is cut, wherein at least a portion of the first detection line and at least a portion of the second detection line are cut off. The first-type display panel can be a display panel without display defects.

[0131] In one possible implementation, step S200, detecting the display panel after the box assembly, includes:

[0132] Among the first signal line, second signal line, second signal line, and fourth signal line, an effective level signal is provided to the first signal line, second signal line, and third signal line, and a first detection signal is provided to one of the detection pads, and a second detection signal is provided to the other detection pad;

[0133] When the display panel displays a black screen, confirm that the display panel is a first-class display panel; second-class display panels can be display panels with poor display quality.

[0134] If the display panel has poor linearity or displays a grayscale image, confirm that the display panel is a Class II display panel.

[0135] For example, referring to Figures 5A and 8, it is detected whether the heating trace J is short-circuited with the data line 3; wherein, an effective voltage (e.g., a high-level voltage VGH) is applied to the first signal line G1 and the third signal line G3, an effective voltage (e.g., a high-level voltage VGH) is applied to the second signal line G2, an ineffective voltage (e.g., a low-level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, an ineffective voltage (e.g., a low-level voltage VGL, e.g., 0V) is applied to the common electrode 5, and 0V and 0V are applied to the two detection pads E1 respectively. 28V; As shown in Figure 5A, the heating trace J is directly above the data line 3. When the heating trace J and the data line 3 are not short-circuited, the voltage difference between the common electrode 5 and the pixel electrode 4 is 0V, the liquid crystal does not deflect, and the screen is black. When the second passivation layer 93 is damaged, causing the heating trace J and the data line 3 to short-circuit, the voltage of the data line 3 and the heating trace J is the same. Since the voltage on the heating trace J is not 0V, the voltage difference between the common electrode 5 and the pixel electrode 4 is not 0V. Therefore, the screen with the LED lit has a vertical linearity defect, and it can be determined that the product is defective.

[0136] For example, referring to Figures 11A-11E and 12, Figure 11A can be a partial schematic diagram of the fourth peripheral region BB4, Figure 11B is a schematic diagram of the stack of heating trace J and common electrode 5 in Figure 11A, Figure 11C can be a partial schematic diagram of the first peripheral region BB1, Figure 11D is a schematic diagram of the stack of heating trace J and common electrode 5 in Figure 11C, and Figure 11E can be a cross-sectional schematic diagram of Figure 11A or Figure 11C along the dashed line A4-A4', detecting whether heating trace J is short-circuited with common trace 50 or common electrode 5 (common trace 50 can be connected to common electrode 5); wherein, an effective voltage (e.g., high-level voltage VGH) is applied to the first signal line G1 and the third signal line G3, an effective voltage (e.g., high-level voltage VGH) is applied to the second signal line G2, an ineffective voltage (e.g., low-level voltage VGL, e.g., 0V) is applied to the fourth signal line G4, and an ineffective voltage (e.g., low-level voltage VGL, e.g., 0V) is applied to the common electrode 5. For example, a low-level voltage VGL (e.g., 0V) is applied to the two detection pads E1, with 0V and 28V respectively. As shown in Figures 11A and 11B, the heating trace J overlaps with the common trace 50 or the common electrode 5. When there is no short circuit between the heating trace J and the common trace 50 or the common electrode 5, the pixel transistor of the display area AA is turned on because the voltage of the second signal line G2 (corresponding to the gate line 2) is VGH. Therefore, the voltage (0V) of the fourth signal line G4 (corresponding to the data line 3) is input to the pixel electrode, so the detection screen is displayed as a black screen. When there is a crack in the third passivation layer 93, the heating trace J and the common trace 50 (or the common electrode 5) are short-circuited. The voltage on the common trace 50 (or the common electrode 5) is the same as the voltage on the heating trace J, which is not 0V. At this time, the voltage difference between the pixel electrode and the common trace 50 (or the common electrode 5) is not 0V, and the detection screen is displayed as a grayscale screen. Based on the display screen, it can be determined whether the product is defective.

[0137] In one possible implementation, step S200, detecting the display panel after the box assembly, includes:

[0138] Among the first signal line, second signal line, third signal line, and fourth signal line, an effective level signal is provided to the first signal line, second signal line, and fourth signal line, and a first detection signal is provided to one of the detection pads, and a second detection signal is provided to the other detection pad;

[0139] If the display panel shows a black screen, confirm that the display panel is a Class 1 display panel.

[0140] If the display panel shows a white screen, confirm that the display panel is a type 2 display panel.

[0141] For example, referring to Figures 9A, 9B, and 10, where Figure 9A can be a partial schematic diagram of the second peripheral area BB2, and Figure 9B is a cross-sectional schematic diagram of Figure 9A along the dashed line A3-A3', the detection process involves checking whether the heating trace J (the second heating trace J2) is short-circuited with the first fan-out trace FG (for example, the first fan-out trace FG can be a fan-out trace located in the second peripheral area BB2 connected to the gate line 2); applying an effective voltage (e.g., a high-level voltage VGH) to the first signal line G1 and the third signal line G3, applying an ineffective voltage (e.g., a low-level voltage VGL, for example, 0V, corresponding to the signal applied to the gate line 2) to the second signal line G2, applying an effective voltage (e.g., a high-level voltage VGH, for example, 5V, corresponding to the signal applied to the data line 3) to the fourth signal line G4, applying an ineffective voltage (e.g., a low-level voltage VGL, for example, 0V) to the common electrode 5, and applying 0V and 28V to the two detection pads E1 respectively; as shown in Figure 9A. As shown, the heating trace J (second heating trace J2) overlaps with the first fan-out trace FG (the first fan-out trace FG connected to the gate line 2, located in the layer where the gate line 2 is located). When there is no short circuit between the heating trace J (second heating trace J2) and the first fan-out trace FG, the pixel transistor of the display area AA is turned off because the voltage of the second signal line G2 (corresponding to the gate line 2) is VGL. Therefore, the voltage of the fourth signal line G4 (corresponding to the data line 3) cannot be input to the pixel electrode, so the detection screen is displayed as a black screen. When there is a crack in the gate insulating layer 91 and the first passivation layer 92, the heating trace J (second heating trace J2) and the first fan-out trace FG are short-circuited. Since the first fan-out trace FG is connected to the gate line 2, the voltage on the gate line 2 is the same as the voltage on the heating trace J (second heating trace J2), which is VGH. At this time, the pixel transistor of the display area is turned on, and the voltage (5V) of the fourth signal line G4 can be input to the pixel electrode, so the detection screen is displayed as a white screen. The display screen can be used to determine whether the product is defective. In this test screen, the voltage of the fourth signal line G4 can also be any other non-zero voltage value.

[0142] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Implementation of this display device can refer to the embodiments of the display panel described above; repeated details will not be repeated.

[0143] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0144] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0145] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A display substrate having a display area and a peripheral area located around the display area; wherein, include: Substrate; Multiple heating trace groups, at least a portion of which are located in the display area, are arranged along a first direction and extend along a second direction; each heating trace group includes at least two heating traces extending along the second direction, and a first lead-out terminal and a second lead-out terminal connected to the heating traces. A first bonding terminal group is located in the peripheral area; the first bonding terminal group includes: a plurality of first bonding terminal pairs arranged along a first direction, each first bonding terminal pair including two first bonding terminals; one end of one of the first bonding terminals in the first bonding terminal pair is electrically connected to the first lead-out terminal, and one end of the other first bonding terminal in the first bonding terminal pair is electrically connected to the second lead-out terminal; A detection pad assembly includes two detection pads arranged along the second direction; wherein one of the detection pads is configured to receive a first detection signal to provide the first detection signal to one of the first bonding terminals in each of the first bonding terminal pairs, and wherein the other detection pad is configured to receive a second detection signal to provide the second detection signal to the other of the first bonding terminal pairs.

2. The display substrate as claimed in claim 1, wherein, Multiple first adapter electrodes are located in the peripheral region and on the side of the first bonding terminal opposite to the substrate; At least a portion of the first adapter electrode's orthographic projection onto the substrate overlaps with the first bonding terminal's orthographic projection onto the substrate, and they are electrically connected via vias at the overlap location. The first adapter electrode includes a first adapter portion and a second adapter portion; both the first adapter portion and the second adapter portion extend along the second direction, and the first adapter portion is located on the side of the first adapter portion away from the display area; The width of the second adapter in the first direction is less than the width of the second adapter in the first direction; in the first direction, the minimum spacing between adjacent second adapters is greater than the minimum distance between adjacent first adapters.

3. The display substrate as described in claim 1 or 2, wherein, The detection pad includes: a first detection electrode, and a second transfer electrode located on the side of the first detection electrode opposite to the substrate; The second transfer electrode overlaps with the first detection electrode in the substrate in at least a portion of its orthogonal projection onto the substrate, and is electrically connected via a via at the overlapping position.

4. The display substrate as described in claim 3, wherein, The second adapter electrode includes a third adapter portion and a fourth adapter portion; the fourth adapter portion is located on the side of the third adapter portion away from the display area; The width of the fourth transition portion in the second direction is smaller than the width of the third transition portion in the second direction; and the minimum distance between adjacent fourth transition portions in the second direction is greater than the minimum distance between adjacent third transition portions.

5. The display substrate as claimed in claim 4, wherein, The first detection electrode includes: a first hollow portion and a first surrounding portion located around the first hollow portion; the orthographic projection of the third adapter portion on the substrate covers the orthographic projection of the first surrounding portion on the substrate.

6. The display substrate as claimed in claim 5, wherein, The detection pad further includes a second detection electrode located on the side of the first detection electrode facing the substrate; The orthographic projection of the second detection electrode onto the substrate overlaps with the orthographic projection of the first detection electrode onto the substrate.

7. The display substrate as claimed in claim 6, wherein, The second detection electrode includes: a second hollow portion and a second surrounding portion located around the second hollow portion; the orthographic projection of the second surrounding portion on the substrate overlaps with the orthographic projection of the first surrounding portion on the substrate.

8. The display substrate according to any one of claims 1-7, wherein, The display substrate further includes an electrostatic structure and a first grounding wire; the detection pad is connected to the first grounding wire through the electrostatic structure.

9. The display substrate according to any one of claims 1-8, wherein, The display substrate includes: a plurality of gate lines extending along a first direction, a plurality of data lines extending along a second direction, a common electrode, and a plurality of pixel electrodes; The display substrate further includes: a first detection circuit and a second detection circuit located in the peripheral area; the first detection circuit includes: a plurality of first transistors, a first signal line, and a second signal line; the second detection circuit includes: a plurality of second transistors, a third signal line, and a fourth signal line; the first transistor includes: a first control electrode, a first source electrode, and a first drain electrode; the second transistor includes: a second control electrode, a second source electrode, and a second drain electrode. The first control electrode of each first transistor is electrically connected to the first signal line; the first source of each first transistor is electrically connected to the second signal line; the first drain of each first transistor is electrically connected to the gate line; the second control electrode of each second transistor is electrically connected to the third signal line; the second source of each second transistor is electrically connected to the fourth signal line; and the second drain of each second transistor is electrically connected to the data line.

10. The display substrate as claimed in claim 9, wherein, The plurality of gate lines include: a plurality of first sub-gate lines and a plurality of second sub-gate lines; the plurality of data lines include: a plurality of first sub-data lines, a plurality of second sub-data lines, and a plurality of third sub-data lines; the plurality of first transistors include: a plurality of first sub-transistors and a plurality of second sub-transistors; the second signal line includes: a first sub-signal line and a second sub-signal line; the plurality of second transistors include: a plurality of third sub-transistors, a plurality of fourth sub-transistors, and a plurality of fifth sub-transistors; the fourth signal line includes: a third sub-signal line, a fourth sub-signal line, and a fifth sub-signal line. The first source of each first sub-transistor is electrically connected to the first sub-signal line, and the first drain of each first sub-transistor is electrically connected to the first sub-gate line; the first source of each second sub-transistor is electrically connected to the second sub-signal line, and the first drain of each second sub-transistor is electrically connected to the second sub-gate line. The second source of each of the third sub-transistors is electrically connected to the third sub-signal line, and the second drain of each of the third sub-transistors is electrically connected to the first sub-data line; the second source of each of the fourth sub-transistors is electrically connected to the fourth sub-signal line, and the second drain of each of the fourth sub-transistors is electrically connected to the second sub-data line; the second source of each of the fifth sub-transistors is electrically connected to the fifth sub-signal line, and the second drain of each of the fifth sub-transistors is electrically connected to the third sub-data line.

11. The display substrate as claimed in claim 9 or 10, wherein, The data line is located on the side of the layer containing the gate line away from the substrate; the common electrode is located on the side of the layer containing the data line away from the layer containing the gate line; the pixel electrode is located on the side of the common electrode away from the layer containing the data line; the heating trace is located between the layer containing the data line and the layer containing the common electrode. The heating trace and the first bonding terminal are in the same layer and made of the same material; the first adapter electrode is in the same layer and made of the same material as either the pixel electrode or the common electrode.

12. A display panel, wherein, The display substrate includes the display substrate as described in any one of claims 1-11, and further includes a counter substrate disposed opposite to the display substrate.

13. A display device, wherein, Includes the display panel as described in claim 12.

14. A method for manufacturing a display panel, wherein, include: The front-end display substrate and the opposing substrate are assembled; wherein, the front-end display substrate includes the display substrate as described in any one of claims 1-11, and further includes: a first detection line and a second detection line; the first detection line is connected to one of the detection pads, and the second detection line is connected to the other detection pad; one of the first bonding terminals in each of the first bonding terminal pairs is connected to the first detection line, and the other first bonding terminal in each of the first bonding terminal pairs is connected to the second detection line; Inspect the display panel behind the box assembly; When the display panel is confirmed to be a first type of display panel, the display panel is cut, wherein at least a portion of the first detection line and at least a portion of the second detection line are cut off.

15. The manufacturing method as described in claim 14, wherein, The detection of the display panel behind the matching box includes: Among the first signal line, the second signal line, the third signal line, and the fourth signal line, an effective level signal is provided to the first signal line, the second signal line, and the third signal line, and a first detection signal is provided to one of the detection pads, and a second detection signal is provided to the other detection pad; When the display panel displays a black screen, it is confirmed that the display panel is the first type of display panel; If the display panel has poor linearity or displays a grayscale image, the display panel is confirmed to be a second type of display panel.

16. The manufacturing method as described in claim 14, wherein, The detection of the display panel behind the matching box includes: Among the first signal line, the second signal line, the third signal line, and the fourth signal line, an effective level signal is provided to the first signal line, the second signal line, and the fourth signal line, and a first detection signal is provided to one of the detection pads, and a second detection signal is provided to the other detection pad; When the display panel displays a black screen, it is confirmed that the display panel is the first type of display panel; When the display panel displays a white screen, it is confirmed that the display panel is a second type of display panel.

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