Display panel, fabrication method therefor, and display apparatus

Abstract

The present disclosure relates to the technical field of displays, and provides a display panel, a fabrication method therefor, and a display apparatus. The display panel of the present disclosure comprises a base substrate, a driving layer disposed on the base substrate, and a plurality of light-emitting devices disposed on a side of the driving layer away from the base substrate, wherein the driving layer comprises a plurality of pixel driver circuits configured for driving the plurality of light-emitting devices; at least one of the plurality of pixel driving circuits at least comprises a driving transistor; an anode of at least one of the plurality of light-emitting devices is electrically connected to a first power signal line, a cathode of the at least one of the plurality of light-emitting devices is electrically connected to a first electrode of the driving transistor, a second electrode of the driving transistor is electrically connected to a second power signal line, and a first power supply voltage of the first power signal line is greater than a second power supply voltage transmitted by the second power signal line.

Description

Display panel and its manufacturing method, display device Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and its manufacturing method, and a display device. Background Technology

[0002] Traditional organic light-emitting diodes (OLEDs) have a cathode structure that is deposited on the entire surface. After the display panel is lit, the screen temperature gradually increases over time, and the brightness and cathode current rise until saturation. The brightness performance varies at different locations on the screen. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display panel and its manufacturing method, as well as a display device.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a display panel, including a substrate, a driving layer disposed on the substrate, and a plurality of light-emitting devices disposed on the driving layer on a side away from the substrate. The driving layer includes a plurality of pixel driving circuits for driving the plurality of light-emitting devices. At least one of the plurality of pixel driving circuits includes at least a driving transistor.

[0005] The anode of at least one of the plurality of light-emitting devices is electrically connected to a first power signal line, the cathode of at least one of the plurality of light-emitting devices is electrically connected to the first electrode of the driving transistor, the second electrode of the driving transistor is electrically connected to a second power signal line, and the first power supply voltage of the first power signal line is greater than the second power supply voltage transmitted by the second power signal line.

[0006] In some embodiments, the display panel further includes a pixel defining layer and a transition electrode layer disposed on the side of the pixel defining layer opposite to the driving layer; the pixel defining layer includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, the plurality of pixel openings being used to define the plurality of light-emitting devices;

[0007] The transition electrode layer includes an isolation pillar, and the orthographic projection of the barrier structure on the substrate covers the orthographic projection of the isolation pillar on the substrate; the cathode of the at least one light-emitting device extends from the corresponding pixel opening to the surrounding barrier structure and is separated by the isolation pillar; the isolation pillar overlaps with the separated cathode and is electrically connected to the first electrode of the driving transistor.

[0008] An insulating structure is provided between two adjacent light-emitting devices, and the insulating structure isolates the cathodes of the two adjacent light-emitting devices.

[0009] In some embodiments, the isolation pillars are arranged in a one-to-one correspondence with the light-emitting devices, and the orthographic projection of the isolation pillar on the substrate surrounds the orthographic projection of the corresponding light-emitting device on the substrate; adjacent isolation pillars are spaced apart.

[0010] In some embodiments, the insulating structure is an insulating layer;

[0011] The insulating layer covers the side surface of the isolation pillar away from the cathode overlap and at least a portion of the surface of the isolation pillar facing away from the substrate.

[0012] In some embodiments, the display panel further includes an encapsulation layer disposed on the side of the at least one light-emitting device facing away from the substrate.

[0013] The light-emitting layer and cathode of the at least one light-emitting device, as well as the encapsulation layer, all extend from the corresponding pixel opening to the surrounding barrier structure, and the light-emitting layer, cathode, and encapsulation layer extending to the barrier structure constitute a stacked structure;

[0014] The insulating structure is a first etched trench, which extends through the stacked structure located between two adjacent isolation pillars in the thickness direction of the substrate.

[0015] In some embodiments, the insulating structure is a second etched channel that penetrates the isolation pillar in the thickness direction of the substrate.

[0016] The isolation pillar includes a first half and a second half; the first half and the second half are separated by the second etched channel; the orthographic projections of the first half and the second half on the substrate respectively surround the orthographic projections of different light-emitting devices on the substrate;

[0017] The display panel further includes an encapsulation layer disposed on the side of the at least one light-emitting device away from the substrate, the encapsulation layer falling into the second etched trench and covering the opposing side surfaces of the first half and the second half.

[0018] In some embodiments, the display panel further includes a pixel defining layer, a first transition electrode disposed on the side of the pixel defining layer opposite to the driving layer, and a partition structure; the pixel defining layer includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, the plurality of pixel openings being used to define the plurality of light-emitting devices;

[0019] The orthographic projection of the partition structure on the substrate surrounds the orthographic projection of the corresponding light-emitting device on the substrate; the cathode of the at least one light-emitting device extends from the pixel opening toward the surrounding barrier structure and is partitioned by the partition structure;

[0020] The first transition electrode is disposed between the partition structure and the light-emitting device, and the first transition electrode is connected to the cathode that is separated by the partition structure, and is electrically connected to the first electrode of the driving transistor.

[0021] In some embodiments, the first transition electrode is an isolation pillar; the height of the isolation pillar is lower than the height of the partition structure, and the partition structure covers the side surface of the isolation pillar away from the cathode overlap side and at least a portion of the surface of the isolation pillar away from the substrate.

[0022] In some embodiments, the isolation pillar includes a bottom, a main body, and a partition portion arranged sequentially along a direction away from the substrate; both the bottom and the partition portion protrude from the main body.

[0023] The partition portion blocks the cathode of at least one light-emitting device extending to the retaining wall structure. The cathode of the at least one light-emitting device overlaps with the main body portion and is electrically connected to the first electrode of the driving transistor through the main body portion and the bottom.

[0024] In some embodiments, the display panel further includes an encapsulation layer disposed on the side of the at least one light-emitting device facing away from the substrate, the encapsulation layer filling the recessed notch between the partition portion and the main body portion.

[0025] In some embodiments, the isolation pillar includes a main body and a partition portion located on the side of the main body facing away from the substrate; the partition portion protrudes from the main body.

[0026] The partition portion blocks the cathode of at least one light-emitting device extending to the retaining wall structure. The cathode of the at least one light-emitting device overlaps with the main body portion and is electrically connected to the first electrode of the driving transistor through the main body portion.

[0027] In some embodiments, the display panel further includes a second transition electrode and a planarization layer disposed on the side of the driving layer near the pixel defining layer;

[0028] The second adapter electrode is electrically connected to the first electrode of the driving transistor and the isolation post through the first connection via through the retaining wall structure and the second connection via through the planarization layer.

[0029] Secondly, embodiments of this disclosure also provide a method for manufacturing a display panel, used to manufacture a display panel as described in any one of the first aspects; wherein, the method for manufacturing the display panel includes:

[0030] Provide one of the aforementioned substrates;

[0031] A driving layer is formed on the substrate; the driving layer includes a plurality of pixel driving circuits for driving a plurality of light-emitting devices; at least one of the plurality of pixel driving circuits includes at least a driving transistor.

[0032] A plurality of light-emitting devices are formed on the side of the driving layer away from the substrate; wherein, the anode of at least one of the plurality of light-emitting devices is electrically connected to a first power signal line, the cathode of at least one of the plurality of light-emitting devices is electrically connected to the first electrode of the driving transistor, the second electrode of the driving transistor is electrically connected to a second power signal line, and the first power supply voltage of the first power signal line is greater than the second power supply voltage transmitted by the second power signal line.

[0033] In some embodiments, before forming the light-emitting layer of the light-emitting device, the method further includes:

[0034] A planarization layer is formed on the side of the driving layer opposite to the substrate.

[0035] The anodes of each of the light-emitting devices are formed on the side of the planarization layer opposite to the driving layer;

[0036] A pixel defining material layer and a transition electrode material layer are sequentially formed on the side of the anode that is away from the planarization layer;

[0037] The transition electrode material layer and the pixel defining material layer are etched to form a pixel defining layer and a transition electrode layer;

[0038] The pixel defining layer includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, the plurality of pixel openings defining the plurality of light-emitting devices; the transition electrode layer includes an isolation pillar, the orthographic projection of the barrier structure on the substrate covers the orthographic projection of the isolation pillar on the substrate; the cathode of at least one light-emitting device extends from the corresponding pixel opening to the surrounding barrier structure and is separated by the isolation pillar; the isolation pillar overlaps with the separated cathode and is electrically connected to the first electrode of the driving transistor; an insulating structure is provided between two adjacent light-emitting devices, the insulating structure isolating the cathodes of the two adjacent light-emitting devices.

[0039] In some embodiments, the plurality of light-emitting devices include a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices;

[0040] Etching the transition electrode material layer and the pixel defining material layer to form a pixel defining layer and a transition electrode layer includes:

[0041] The transition electrode material layer is etched once to form multiple undercut structures; the orthographic projection of the undercut structure on the substrate is located between the orthographic projections of the anodes of the adjacent light-emitting devices on the substrate.

[0042] The transition electrode material layer and the pixel defining material layer having the undercut structure are etched a second time to form a plurality of first openings penetrating the transition electrode material layer and the pixel defining material layer to expose the anodes of the plurality of first light-emitting devices and to obtain a first isolation pillar that overlaps with the plurality of first light-emitting devices.

[0043] The transition electrode material layer and the pixel defining material layer having the undercut structure are etched three times to form a plurality of second openings penetrating the transition electrode material layer and the pixel defining material layer, so as to expose the anodes of the plurality of second light-emitting devices and obtain second isolation pillars that overlap with the plurality of second light-emitting devices;

[0044] The undercut structure's transition electrode material layer and pixel defining material layer are etched four times to form multiple third openings penetrating the transition electrode material layer and pixel defining material layer, thereby exposing the anodes of the multiple third light-emitting devices and obtaining third isolation pillars that overlap with the multiple third light-emitting devices.

[0045] In some embodiments, after the second etching and before the third etching, the method further includes:

[0046] On the side of the transition electrode material layer opposite to the pixel defining material layer, the light-emitting material layer and the cathode layer of the plurality of first light-emitting devices are sequentially formed;

[0047] The light-emitting material layer and the cathode layer outside the first sub-pixel region are removed to form the plurality of first light-emitting devices; the plurality of first light-emitting devices and the first isolation pillar are all located in the first sub-pixel region.

[0048] In some embodiments, after three etching steps and before four etching steps, the method further includes:

[0049] On the side of the transition electrode material layer opposite to the pixel defining material layer, the light-emitting material layer and the cathode layer of the plurality of second light-emitting devices are sequentially formed;

[0050] The light-emitting material layer and the cathode layer outside the second sub-pixel region are removed to form the plurality of second light-emitting devices; the plurality of second light-emitting devices and the second isolation pillar are all located in the second sub-pixel region.

[0051] In some embodiments, after four etching passes, the method further includes:

[0052] On the side of the transition electrode material layer opposite to the pixel defining material layer, the light-emitting material layer and the cathode layer of the plurality of third light-emitting devices are sequentially formed;

[0053] The light-emitting material layer and the cathode layer outside the third sub-pixel region are removed to form the plurality of third light-emitting devices; the plurality of third light-emitting devices and the third isolation pillar are all located in the third sub-pixel region.

[0054] In some embodiments, etching the transition electrode material layer and the pixel defining material layer to form a pixel defining layer and a transition electrode layer includes:

[0055] The transition electrode material layer is etched once to form multiple undercut structures; the orthographic projection of the undercut structure on the substrate is located between the orthographic projections of the anodes of the adjacent light-emitting devices on the substrate.

[0056] The transition electrode material layer and the pixel defining material layer having the undercut structure are etched a second time to form multiple openings penetrating the transition electrode material layer and the pixel defining material layer to expose the anode of each of the light-emitting devices, and to obtain the pixel defining layer and the transition electrode layer.

[0057] In some embodiments, after forming the transition electrode layer, the method further includes:

[0058] The light-emitting layer and cathode of the plurality of light-emitting devices are sequentially formed on the side of the transition electrode layer opposite to the pixel defining layer to obtain the plurality of light-emitting devices.

[0059] In some embodiments, prior to secondary etching, the method further includes:

[0060] An insulating layer is formed on the side of the transition electrode material layer having the undercut structure that is opposite to the pixel defining material layer; the orthogonal projection of the insulating layer on the substrate covers the orthogonal projection of the undercut structure on the substrate.

[0061] In some embodiments, after forming each of the light-emitting devices, the method further includes:

[0062] An inorganic encapsulation material layer is formed on the side of the light-emitting device away from the substrate; the light-emitting layer and cathode of the at least one light-emitting device, as well as the inorganic encapsulation material layer, all extend from the pixel opening to the surrounding barrier structure, and the light-emitting layer, the cathode, and the inorganic encapsulation material layer extending to the barrier structure constitute a stacked structure;

[0063] The stacked structure between adjacent isolation pillars is etched to form a first etching channel; the first etching channel penetrates the stacked structure located between two adjacent isolation pillars in the thickness direction of the substrate.

[0064] In some embodiments, the light-emitting layer and the cathode of the at least one light-emitting device both extend from the pixel opening toward the surrounding barrier structure, and the light-emitting layer and the cathode extending onto the barrier structure constitute a stacked structure;

[0065] After forming each of the aforementioned light-emitting devices, the process further includes:

[0066] The isolation pillar is etched to form a second etched channel; the second etched channel penetrates the isolation pillar in the thickness direction of the substrate; the second etched channel divides the isolation pillar into a first half and a second half.

[0067] In some embodiments, prior to forming each of the light-emitting devices, the method further includes:

[0068] A partition structure is formed on the side of the transition electrode layer away from the substrate, the partition structure enclosing the side surface of the isolation pillar away from the pixel opening and at least a portion of the surface of the isolation pillar away from the substrate.

[0069] Thirdly, embodiments of this disclosure also provide a display device, including a display panel as described in any one of the first aspects. Attached Figure Description

[0070] Figure 1 shows the circuit diagram of the relevant pixel driving circuit.

[0071] Figure 2 is a circuit diagram of a display driving circuit provided in an embodiment of this disclosure.

[0072] Figure 3 is a schematic diagram of the display panel of Example 1 provided in the embodiments of this disclosure.

[0073] Figure 4 is a schematic diagram of the display panel of Example 2 provided in the embodiments of this disclosure.

[0074] Figure 5a is a plan view of the display panel of Example 1 provided in the embodiments of this disclosure.

[0075] Figure 5b is a plan view of the display panel of Example 2 provided in the embodiments of this disclosure.

[0076] Figure 6 is a schematic diagram of an isolation column provided in an embodiment of this disclosure.

[0077] Figure 7 is a schematic diagram of another type of isolation column provided in an embodiment of this disclosure.

[0078] Figure 8 is a schematic diagram of the film layer of the display panel of Example 3 provided in the embodiments of this disclosure.

[0079] Figure 9 is a plan view of the display panel of Example 3 provided in the embodiments of this disclosure.

[0080] Figure 10 is a plan view of the display panel of Example 4 provided in the embodiments of this disclosure.

[0081] Figure 11 is a schematic diagram of the cross section in the A-A' direction of the structure in Figure 10.

[0082] Figures 12a to 12k are schematic diagrams of the step-by-step formation of isolation columns and the structure of each intermediate stage of the display panel in Example 1 provided by the embodiments of this disclosure.

[0083] Figures 13a and 13b are schematic diagrams of the integrally molded isolation column of the display panel and some intermediate stage structures under Example 1 provided in the embodiments of this disclosure.

[0084] Figures 14a and 14b are schematic diagrams of the structure of some intermediate stages in the manufacturing process of the display panel under Example 3 provided in the embodiments of this disclosure.

[0085] Figures 15a and 15b are schematic diagrams of the structure of a display panel in a partial intermediate stage of the manufacturing process according to Example 4 provided in the embodiments of this disclosure. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0087] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0088] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0089] In related technologies, because the cathode of the light-emitting device is a full-surface vapor deposition structure, the cathode voltage drop is relatively large, which affects the uniformity of display brightness. Meanwhile, as shown in Figure 1, taking a 2T1C (two transistors and one capacitor) circuit structure for the pixel driving circuit as an example, after the display panel is lit, the screen temperature gradually increases over time. The second electrode of the driving transistor DTFT (i.e., the source electrode of the N-type DTFT) is the voltage-crossing terminal of the OLED device. As the temperature increases, the OLED device voltage decreases, thus increasing the absolute value of the voltage at point N2. The fluctuation of the voltage at point N2 (i.e., the source voltage of the driving transistor) has a significant impact on the gate of the driving transistor DTFT, thereby affecting brightness uniformity. Furthermore, as the temperature increases, the threshold voltage Vth of the driving transistor DTFT becomes negatively biased, increasing the leakage current (Ion). After threshold compensation, the increased leakage current (Ion) leads to an increase in current, which also affects brightness uniformity.

[0090] In view of this, the present disclosure provides a display panel that, by changing the connection position between the conventional light-emitting device and the pixel driving circuit, sets the anode of the light-emitting device to be electrically connected to the first power signal line and the cathode of the light-emitting device to be electrically connected to the first pole of the driving transistor, overcomes the influence of the fluctuation of the driving voltage of the light-emitting device on the gate voltage of the driving transistor, thereby improving (thermal) image retention.

[0091] Figure 2 is a circuit diagram of a display driving circuit provided in an embodiment of this disclosure, and Figure 3 is a schematic diagram of a display panel of Example 1 provided in an embodiment of this disclosure. As shown in Figures 2 and 3, the display panel includes a substrate 1, a driving layer 2 disposed on the substrate 1, and a plurality of light-emitting devices 3 disposed on the side of the driving layer 2 away from the substrate 1. The driving layer 2 includes a plurality of pixel driving circuits for driving the plurality of light-emitting devices 3; at least one of the plurality of pixel driving circuits includes at least a driving transistor DTFT; the anode 31 of at least one of the plurality of light-emitting devices 3 is electrically connected to a first power signal line VDD, the cathode 33 of at least one of the plurality of light-emitting devices 3 is electrically connected to the first electrode D of the driving transistor DTFT, and the second electrode of the driving transistor DTFT is electrically connected to a second power signal line VSS.

[0092] As shown in Figure 2, the pixel driving circuit includes at least a driving transistor DTFT, a data writing transistor T1, and a storage capacitor Cst, i.e., a 2T1C (two transistors and one capacitor) circuit structure. For ease of understanding, this disclosure uses the simplest 2T1C circuit structure as an example for the pixel driving circuit. In practice, driving circuit structures such as 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, or 11T3C can also be used, which will not be listed here.

[0093] The display panel also includes a first power signal line VDD, a second power signal line VSS, a data line Data, and a gate scan line G1. The first terminal of the data writing transistor T1 is electrically connected to the data line Data, the second terminal of the data writing transistor T1 is electrically connected to the first node N1, and the gate of the data writing transistor T1 is electrically connected to the gate scan line G1. The first terminal D of the driving transistor DTFT is electrically connected to the cathode 33 of the light-emitting device 3, the second terminal of the driving transistor DTFT is electrically connected to the second power signal line VSS, and the gate of the driving transistor DTFT is electrically connected to the first node N1. The first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the second terminal (i.e., the second node N2) of the driving transistor DTFT. The first power signal line VDD is used to transmit the first power supply voltage, and the second power signal line VSS is used to transmit the second power supply voltage. The first power supply voltage is greater than the second power supply voltage. Specifically, the first power supply voltage is the anode voltage, such as +5V; the second power supply voltage is the cathode voltage, such as -5V. The data line Data is used to transmit data voltage signals to achieve screen display. The gate scan line G1 is used to transmit the gate scan signal to control the on / off state of the data writing transistor T1, and to drive the light-emitting device 3 with the help of the driving transistor DTFT and the storage capacitor Cst.

[0094] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between their source and drain. In the embodiments of this disclosure and the following description, to distinguish between the source and drain of the transistor, one of them is referred to as the first terminal and the other as the second terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0095] Furthermore, transistors can be classified into N-type and P-type based on their characteristics. When using a P-type transistor, the first electrode is the source and the second electrode is the drain. When a low-level signal is input to the gate, the source and drain are turned on. When using an N-type transistor, the first electrode is the drain and the second electrode is the source. When a high-level signal is input to the gate, the source and drain are turned on. This embodiment uses N-type transistors as an example for specific explanation. For example, the first electrode D of the driving transistor DTFT is the drain of the driving transistor DTFT, and the second electrode of the driving transistor DTFT is the source of the driving transistor DTFT. Therefore, the cathode 33 of the light-emitting device 3 is electrically connected to the drain of the driving transistor DTFT, and the source of the driving transistor DTFT is electrically connected to the second power supply signal line VSS.

[0096] The first power signal line VDD provides the first power supply voltage to the anode 31 of the light-emitting device 3. When the driving transistor DTFT is turned on, the cathode 33 of the light-emitting device 3 is connected to the second power signal line VSS, thereby connecting to the second power supply voltage to drive the light-emitting device 3 to light up.

[0097] This embodiment of the present disclosure changes the connection position between the conventional light-emitting device 3 and the pixel driving circuit. At least one anode 31 of the light-emitting device 3 is electrically connected to the first power signal line VDD, and at least one cathode 33 of the light-emitting device 3 is electrically connected to the first electrode D of the driving transistor DTFT. Therefore, at least some of the light-emitting devices 3 in this disclosure have independent cathodes 33, eliminating the large voltage drop across the entire structure of the cathode 33 of the light-emitting device 3, thus improving brightness uniformity. Simultaneously, the independent cathode 33 of the light-emitting device 3 is electrically connected to one end of the first electrode D of the driving transistor DTFT. Compared to the conventional method where the light-emitting device 3 is electrically connected to one end of the second electrode of the driving transistor DTFT, this disclosure can eliminate the N2 node voltage fluctuation caused by temperature influence on the light-emitting device 3. Since the N2 node voltage fluctuation is eliminated, the second electrode (source) voltage of the driving transistor DTFT is stabilized. Therefore, the influence of the N2 point voltage fluctuation on the gate voltage of the driving transistor DTFT can be improved, thereby improving brightness uniformity, reducing thermal retention, and ultimately improving display quality.

[0098] It should be noted that the light-emitting device 3 involved in the embodiments of this disclosure may include, but is not limited to, organic light-emitting diodes (OLEDs), quantum dot light-emitting diodes (QLEDs), or micro light-emitting diodes (Micro LEDs).

[0099] Optionally, the light-emitting device 3 is an OLED device. The display panel is an OLED display panel.

[0100] Figure 4 is a schematic diagram of the display panel of Example 2 provided in the embodiments of this disclosure, Figure 5a is a plan view of the display panel of Example 1 provided in the embodiments of this disclosure, and Figure 5b is a plan view of the display panel of Example 2 provided in the embodiments of this disclosure.

[0101] In some embodiments, as shown in Figures 3 to 5b, the display panel further includes a pixel defining layer (PDL) and a transition electrode layer 4 disposed on the side of the pixel defining layer (PDL) facing away from the driving layer 2. The pixel defining layer (PDL) includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, the plurality of pixel openings defining a plurality of light-emitting devices (LEDs) 3. Specifically, the pixel openings of the pixel defining layer (PDL) expose the anode 31 of the LEDs 3, and a light-emitting layer 32 and a cathode 33 are sequentially disposed on the anode 31, thus defining the LEDs 3. The location of the LEDs 3 in this disclosure specifically refers to the area where the pixel openings are located; the LEDs 3 specifically refer to the light-emitting unit composed of the anode 31, the light-emitting layer 32, and the cathode 33 located within the pixel openings. The transition electrode layer 4 includes an isolation pillar 40, the orthographic projection of the barrier structure on the substrate 1 covering the orthographic projection of the isolation pillar 40 on the substrate 1. The cathode 33 of at least one LED 3 extends from the corresponding pixel opening to the surrounding barrier structure and is separated by the isolation pillar 40; the isolation pillar 40 overlaps with the separated cathode 33 and is electrically connected to the first electrode D of the driving transistor DTFT. Furthermore, the cathodes 33 of two adjacent light-emitting devices 3 are spaced apart and insulated from each other. Here, the material of the isolation pillar 40 is a conductive material. At least one cathode 33 of the light-emitting device 3 is isolated by the isolation pillar 40 and overlaps with the side surface of the isolation pillar 40. It is then further electrically connected to the first electrode D of the driving transistor DTFT through the isolation pillar 40.

[0102] Here, the isolation pillar 40 can be a multi-layer structure, specifically a double-layer or triple-layer structure. Taking a triple-layer structure as an example, optionally, Figure 6 is a schematic diagram of an isolation pillar provided by an embodiment of this disclosure. As shown in Figure 6, the isolation pillar 40 includes a bottom 41, a main body 42, and a partition 43 arranged sequentially along the direction away from the substrate 1; both the bottom 41 and the partition 43 protrude from the main body 42; the partition 43 partitions the cathode 33 and the light-emitting layer 32 of at least one light-emitting device 3 extending to the barrier structure (PDL), the cathode 33 of at least one light-emitting device 3 overlaps with the main body 42, and is electrically connected to the first electrode D of the driving transistor DTFT through the main body 42 and the bottom 41. Optionally, the bottom 41, the main body 42, and the partition 43 are made of a titanium (Ti) / aluminum (Al) / titanium (Ti) triple-layer material structure. Through the toughness differences of multiple materials and the introduction of multi-layer interfaces, the strength, toughness, and high-temperature performance of the material are significantly improved, while also exhibiting good high-strength performance, which is beneficial for partitioning the stacked structure of the light-emitting layer 32 and the cathode 33. Taking a double-layer structure as an example, optionally, Figure 7 is a schematic diagram of another isolation pillar provided by an embodiment of this disclosure. As shown in Figure 7, the isolation pillar 40 includes a main body 42 and a partition 43 located on the side of the main body 42 facing away from the substrate 1. The partition 43 protrudes from the main body 42. The partition 43 partitions the cathode 33 and the light-emitting layer 32 of at least one light-emitting device 3 extending to the baffle structure. The cathode 33 of at least one light-emitting device 3 overlaps with the main body 42 and is electrically connected to the first electrode D of the driving transistor DTFT through the main body 42. Optionally, the main body 42 and the partition 43 are made of aluminum (Al) and titanium (Ti) double-layer material structure, or aluminum alloy and titanium (Ti) double-layer material structure. Through the toughness difference of multiple materials and the introduction of multiple interfaces, the strength, toughness and high temperature performance of the material are significantly improved, and it also has good high strength performance, which is beneficial to the double-layer structure of the light-emitting layer 32 and the cathode 33.

[0103] Optionally, the longitudinal section of the main body 42 of the isolation pillar 40 is trapezoidal. That is, the orthographic projection of the surface of the main body 42 near the partition 43 on the substrate 1 falls on the orthographic projection of the surface of the main body 42 near the bottom 41 on the substrate 1, which makes it easier for the cathode 33 isolated by the partition 43 to overlap at the position of the main body 42 near the bottom 41. At the same time, the partition 43 and the end of the main body 42 near the partition 43 form a concave notch, which facilitates the sealing tightness after the encapsulation layer 6 is filled.

[0104] An insulating structure 5 is provided between two adjacent light-emitting devices 3, and the insulating structure 5 isolates the cathodes 33 of the two adjacent light-emitting devices 3. Optionally, the insulating structure 5 is disposed on the side of the isolation pillar 40 away from the cathode 33 it overlaps with. The orthographic projection of the insulating structure 5 on the substrate 1 falls within the orthographic projection of the barrier structure on the substrate 1. Exemplarily, the insulating structure 5 can be an etched channel, an insulating layer 51, or a combination of an insulating layer 51 and an etched channel, to isolate the cathodes 33 between adjacent light-emitting devices 3. It should be noted that "etched channel" here refers to an opening formed by etching using an etching process, which can be an opening formed by etching the isolation pillar 40, or an opening formed by etching the cathode 33 and the light-emitting layer 32, etc. As long as the cathodes 33 between adjacent light-emitting devices 3 are isolated, this disclosure does not limit the process and morphology of the insulating structure 5.

[0105] At least one isolation pillar 40 is provided between any two adjacent light-emitting devices 3. Specifically, one isolation pillar 40 or multiple isolation pillars 40 can be provided between adjacent light-emitting devices 3. The orthographic projection of the isolation pillar 40 on the substrate 1 surrounds the orthographic projection of the light-emitting device 3 on the substrate 1.

[0106] As shown in Figures 3 and 4, the display panel also includes an encapsulation layer 6 disposed on the side of at least one light-emitting device 3 facing away from the substrate 1. The encapsulation layer 6 encapsulates all structures on its side closest to the substrate 1, including the light-emitting device 3, the isolation pillar 40 located on the barrier structure, the cathode 33, and the insulating layer 51. Furthermore, as shown in Figure 6, the encapsulation layer 6 (e.g., the first inorganic encapsulation layer CVD1) also fills the recessed notch between the partition portion 43 and the main body portion 42, and is in direct contact with the main body portion 42 and the partition portion 43, which helps to improve sealing. Here, the fluidity of the encapsulation material is utilized to encapsulate and wrap the exposed surfaces of the structure above the substrate 1. The morphology of the isolation pillar 40 of this disclosure can be an "I" shape as shown in Figure 6 or a "T" shape as shown in Figure 7. Utilizing this type of isolation pillar 40 morphology increases the sealing range of the encapsulation layer 6, thereby improving the moisture intrusion path and enhancing the encapsulation effect of the light-emitting device 3.

[0107] In some embodiments, as shown in Figures 3 and 4, the isolation pillars 40 are arranged in a one-to-one correspondence with the light-emitting devices 3, and the orthographic projection of the isolation pillars 40 on the substrate 1 surrounds the orthographic projection of the corresponding light-emitting device 3 on the substrate 1; adjacent isolation pillars 40 are arranged at intervals.

[0108] As shown in Figures 5a and 5b, it includes multiple pixel units, each pixel unit including multiple sub-pixels. Each sub-pixel includes a light-emitting device 3 and a pixel driving circuit for driving the light-emitting device 3. Examples include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R includes a red light-emitting device 3 and a pixel driving circuit for driving the red light-emitting device; the green sub-pixel G includes a green light-emitting device and a pixel driving circuit for driving the green light-emitting device; and the blue sub-pixel B includes a blue light-emitting device and a pixel driving circuit for driving the blue light-emitting device. Figures 5a and 5b only show two rows and two columns of sub-pixels. For ease of understanding, some layers are made transparent, but this does not constitute a limitation on the layer material. The orthographic projections of different isolation pillars 40 on the substrate 1 surround the orthographic projections of different light-emitting devices 3 on the substrate 1. For example, a first isolation pillar 401 surrounds the red light-emitting device, a second isolation pillar 402 surrounds the green light-emitting device, and a third isolation pillar 403 surrounds the blue light-emitting device. The first isolation pillar 401 can block the cathode of the red light-emitting device (red sub-pixel R), the second isolation pillar 402 can block the cathode of the green light-emitting device (green sub-pixel G), and the third isolation pillar 403 can block the cathode of the blue light-emitting device (blue sub-pixel B).

[0109] Optionally, as shown in FIG3, the insulating structure 5 is an insulating layer 51. The insulating layer 51 covers the side surface of the isolation pillar 40 away from the cathode 33 and at least a portion of the surface of the isolation pillar 40 facing away from the substrate 1. For example, the insulating layer 51 covers the side surface of the isolation pillar 40 away from the cathode 33 and the entire upper surface of the isolation pillar 40 facing away from the substrate 1, preventing the cathode 33 of adjacent light-emitting devices 3 from being connected through the conductive isolation pillar 40. As shown in FIG5a, the orthographic projection of the insulating layer 51 on the substrate 1 covers the orthographic projection of the isolation pillar 40 between two adjacent light-emitting devices 3 on the substrate 1.

[0110] For example, the material of the insulating layer 51 can be an inorganic insulating material.

[0111] As shown in Figures 3 and 4, the display panel also includes a second transition electrode 62 and a planarization layer PLN disposed between the pixel defining layer PDL and the driving layer 2. The second transition electrode 62 passes through the first connection via V1 through the barrier structure and the second connection via V2 of the planarization layer PLN, electrically connecting the first electrode D of the driving transistor DTFT and the isolation pillar 40. That is, the cathode 33 of the light-emitting device 3 is electrically connected to the first electrode D of the driving transistor DTFT through the isolation pillar 40 and the second transition electrode 62. Here, the second transition electrode 62 is in direct contact with the bottom 41 of the isolation pillar near the surface of the substrate 1, and the cathode 33 of the light-emitting device 3 is in direct contact with at least the surface of the bottom 41 away from the substrate 1 and / or the side surface of the main body 42.

[0112] Optionally, the second adapter electrode 62 can be an integral structure that runs through the first connecting via V1 and the second connecting via V2.

[0113] Optionally, the display panel also includes a third transfer electrode 63 (not shown in Figure 3, but can be found in the structure shown in Figure 8). The third transfer electrode 63 is on the same layer as the anode 31 and is spaced apart. The second transfer electrode 62 is electrically connected to the third transfer electrode 63 through the first connection via V1. The third transfer electrode 63 is then transferred and electrically connected to the first electrode D of the driving transistor DTFT through the second connection via V2.

[0114] As shown in Figure 4, the display panel further includes an encapsulation layer 6 disposed on the side of at least one light-emitting device 3 facing away from the substrate 1. The light-emitting layer 32 and cathode 33 of at least one light-emitting device 3, as well as the encapsulation layer 6, all extend from the corresponding pixel openings towards the surrounding barrier structure, forming a stacked structure. Optionally, the insulating structure 5 is a first etched trench 52. The first etched trench 52 penetrates the stacked structure located between two adjacent isolation pillars 40 in the thickness direction of the substrate 1 to isolate the cathodes 33 of adjacent light-emitting devices 3, preventing the isolated cathodes 33 from communicating with the cathodes 33 of other light-emitting devices 3 through the conductive isolation pillars 40.

[0115] Here, the first etched trench 52 refers to an opening that penetrates the stacked structure in the thickness direction of the substrate 1. This opening can be further filled with an organic encapsulation layer IJP to improve the isolation effect.

[0116] Optionally, the encapsulation layer 6 in the display panel can be a single-layer structure or a multi-layer structure. When the encapsulation layer 6 is a multi-layer structure, the encapsulation layer 6 may include a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 arranged sequentially along the direction away from the substrate 1, for example, silicon nitride SiN (inorganic material) + ink (organic material) + silicon nitride SiN (inorganic material). As shown in FIG4, the first etched trench 52 penetrates the first inorganic encapsulation layer CVD1, the cathode 33, and the light-emitting layer 32 in the thickness direction of the substrate 1, exposes the barrier structure, and is encapsulated with the organic encapsulation layer IJP.

[0117] The difference between Example 2 and Example 1 is that the insulating structure 5 uses the first etched channel 52 instead of the insulating layer 51. Other structural features are the same, and repeated parts will not be described again.

[0118] The embodiments disclosed herein employ a design of an isolation pillar 40 + an insulating layer 51 or a first etched channel 52, which isolates the cathode 33 of the adjacent light-emitting device 3 while extending the path of water vapor intrusion and improving sealing.

[0119] In some embodiments, FIG8 is a schematic diagram of the film layer of the display panel of Example 3 provided in the present disclosure, and FIG9 is a planar schematic diagram of the display panel of Example 3 provided in the present disclosure. As shown in FIG8 and FIG9, the insulating structure 5 includes a second etched channel 53, which penetrates the isolation pillar 40 in the thickness direction of the substrate 1. Here, the second etched channel 53 refers to an opening penetrating the isolation pillar 40 in the thickness direction of the substrate 1. This opening can be further filled with an organic encapsulation layer IJP to improve the isolation effect.

[0120] As shown in Figure 8, the isolation pillars 40 between adjacent light-emitting devices 3 were originally a single structure. By etching the isolation pillars 40, a second etching channel 53 is formed, thereby forming a first half 40a and a second half 40b that are spaced apart, thus separating the cathodes 33 of adjacent light-emitting devices 3. Specifically, the isolation pillar 40 includes a first half 40a and a second half 40b; the first half 40a and the second half 40b are separated by the second etching channel 53 to isolate the cathodes 33 of adjacent light-emitting devices 3, preventing the isolated cathodes 33 from being reconnected through the conductive isolation pillars 40. As shown in Figure 9, the orthographic projections of the first half 40a and the second half 40b on the substrate 1 respectively surround the orthographic projections of the different light-emitting devices 3 on the substrate 1.

[0121] In this embodiment, an isolation pillar 40 is provided between adjacent light-emitting devices 3, which simplifies the structure and can shorten the spacing between adjacent pixel openings, thus improving pixel density (PPI). The isolation pillar 40 also isolates the cathodes 33 of two adjacent light-emitting devices 3. The isolated cathodes 33 overlap on both sides of the isolation pillar 40. Then, the second etched channel 53 penetrating the isolation pillar 40 is used to isolate the cathodes 33 of the two adjacent light-emitting devices 3, preventing the isolated cathodes 33 of the adjacent light-emitting devices 3 from being connected through the conductive isolation pillar 40.

[0122] Optionally, the display panel further includes an encapsulation layer 6 disposed on the side of at least one light-emitting device 3 facing away from the substrate 1. The encapsulation layer 6 falls within the second etched trench 53 and covers the opposing side surfaces of the first half 40a and the second half 40b. Specifically, the encapsulation layer 6 includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer 1JP, and a second inorganic encapsulation layer CVD2 disposed sequentially along the direction facing away from the substrate 1. The first inorganic encapsulation layer CVD1 falls within the second etched trench 53 and covers the opposing side surfaces of the first half 40a and the second half 40b to improve the encapsulation effect. The actual structure of the isolation pillar 40 in this embodiment can be the structure shown in Figure 6 or Figure 7, and repeated parts will not be described again. The encapsulation layer 6 also fills the recessed notch between the partition portion 43 and the main body portion 42 and is in direct contact with the main body portion 42 and the partition portion 43, which is beneficial to improving the sealing performance. Here, the fluidity of the encapsulation material is utilized to encapsulate and cover all exposed surfaces of the structure above the substrate 1. The morphology of the isolation pillar 40 disclosed herein can be an "I" shape as shown in Figure 6 or a "T" shape as shown in Figure 7. By utilizing this type of isolation pillar 40 morphology, the sealing range of the encapsulation layer 6 is increased, thereby improving the moisture intrusion path and improving the encapsulation effect of the light-emitting device 3.

[0123] The subpixel arrangement of this embodiment can be, but is not limited to, the rectangular array arrangement shown in Figures 5a and 5b. It can also be a blue diamond arrangement, as shown in Figure 9. The pixel unit includes multiple subpixels of different colors, such as red subpixel R, first green subpixel G1, second green subpixel G2 and blue subpixel B. The cut first half 40a and second half 40b surround different subpixels respectively, so as to connect the cathode 33 of each light-emitting device 3 while improving the hermetic encapsulation effect.

[0124] As shown in Figure 8, the display panel further includes a second transition electrode 62 and a planarization layer PLN disposed between the pixel defining layer PDL and the driving layer 2. The second transition electrode 62 passes through the first connection via V1 through the barrier structure and the second connection via V2 of the planarization layer PLN, and is electrically connected to the first electrode D of the driving transistor DTFT and the isolation pillar 40. That is, the cathode 33 of the light-emitting device 3 is electrically connected to the first electrode D of the driving transistor DTFT through the isolation pillar 40 and the second transition electrode 62. Optionally, the display panel further includes a third transition electrode 63, which is disposed on the same layer as the anode 31 and spaced apart. The second transition electrode 62 is electrically connected to the third transition electrode 63 through the first connection via V1, and the third transition electrode 63 is then connected to the first electrode D of the driving transistor DTFT through the second connection via V2.

[0125] This embodiment adopts the design of isolation pillar 40 + second etched channel 53, which isolates the cathode 33 of adjacent light-emitting device 3, while extending the water vapor intrusion path and improving the sealing performance.

[0126] In some embodiments, FIG10 is a plan view of the display panel of Example 4 provided in the present disclosure, and FIG11 is a cross-sectional view along the A-A' direction in the structure of FIG10. As shown in FIG10 and FIG11, the display panel further includes a pixel defining layer PDL, a first transition electrode 61 disposed on the side of the pixel defining layer PDL away from the driving layer 2, and a partition structure 7. The pixel defining layer PDL includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, and the plurality of pixel openings are used to define a plurality of light-emitting devices 3. The orthogonal projection of the partition structure 7 on the substrate 1 surrounds the orthogonal projection of the corresponding light-emitting device 3 on the substrate 1. The cathode 33 of at least one light-emitting device 3 extends from the corresponding pixel opening to the surrounding barrier structure and is partitioned by the partition structure 7. The first transition electrode 61 is disposed between the partition structure 7 and the light-emitting device 3, and the first transition electrode 61 overlaps with the cathode 33 partitioned by the partition structure 7 and is electrically connected to the first electrode D of the driving transistor DTFT. Here, the material of the partition structure 7 is an insulating material, such as a negative photoresist material. The first transfer electrode 61 is located between the partition structure 7 and the pixel opening. Since the light-emitting layer 32 and the cathode 33 of the light-emitting device 3 extend from the corresponding pixel opening to the surrounding barrier structure, the cathode 33 of the light-emitting device 3 is isolated by the partition structure 7 and falls on the first transfer electrode 61 and is electrically connected to it. It is also electrically connected to the first electrode D of the driving transistor DTFT through the first transfer electrode 61.

[0127] Optionally, the orthographic projection of the partition structure 7 on the substrate 1 overlaps with the orthographic projection of the first transfer electrode 61 on the substrate 1.

[0128] Here, the first transition electrode 61 can be a single-layer structure or a multi-layer structure. Optionally, the first transition electrode 61 is a multi-layer isolation pillar 40; the height of the isolation pillar 40 is lower than the height of the partition structure 7, and the partition structure 7 covers the side surface of the isolation pillar 40 away from the cathode 33 and at least a portion of the surface of the isolation pillar 40 facing away from the substrate 1. Specifically, the partition structure 7 covers the side surface of the isolation pillar 40 away from the cathode 33 and the portion of the surface of the isolation pillar 40 facing away from the substrate 1, so as to further isolate the cathode 33 of the light-emitting device 3 by means of the isolation pillar 40. Here, the isolation pillar 40 is a conductive material, and while the cathode 33 of the light-emitting device 3 is isolated by the isolation pillar 40, it overlaps with the side surface of the isolation pillar 40, and is further electrically connected to the first electrode of the driving transistor DTFT through the isolation pillar 40.

[0129] Here, the structure of the isolation column 40 can be seen in Figure 6 or Figure 7, and the repeated parts will not be described again.

[0130] Optionally, as shown in FIG11, the display panel further includes a second transition electrode 62 and a planarization layer PLN disposed between the pixel defining layer PDL and the driving layer 2. The second transition electrode 62 passes through the first connection via V1 through the barrier structure and the second connection via V2 of the planarization layer PLN, and is electrically connected to the first electrode D of the driving transistor DTFT and the isolation pillar 40.

[0131] As shown in Figure 10, it includes multiple pixel units, each pixel unit including multiple sub-pixels. Each sub-pixel includes a light-emitting device 3 and a pixel driving circuit for driving the light-emitting device 3. Examples include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. The red sub-pixel R includes a red light-emitting device 3 and a pixel driving circuit for driving the red light-emitting device 3; the green sub-pixel G includes a green light-emitting device 3 and a pixel driving circuit for driving the green light-emitting device 3; and the blue sub-pixel B includes a blue light-emitting device 3 and a pixel driving circuit for driving the blue light-emitting device 3. Figure 10 only shows two rows and two columns of sub-pixels. For ease of understanding, some film layers in Figure 10 are made transparent, but this does not constitute a limitation on the film layer material. The orthographic projection of the partition structure 7 on the substrate 1 surrounds the orthographic projection of each light-emitting device 3 on the substrate 1, and the partition structures 7 are connected as a single integral structure. The first transition electrode 61 (isolation post 40) is arranged one-to-one with each light-emitting device 3. The overlapping first transition electrodes 61 corresponding to different light-emitting devices 3 are spaced apart, for example, spaced apart by the size (length or width) of one light-emitting device. For example, a first transition electrode 611 is provided for a red light-emitting device (red sub-pixel R), a first transition electrode 612 is provided for a green light-emitting device (green sub-pixel G), and a first transition electrode 613 is provided for a blue light-emitting device (blue sub-pixel B). The first transition electrode 611 and the first transition electrode 612 are spaced apart by the length of a red light-emitting device (or the width of a blue light-emitting device), the first transition electrode 611 and the first transition electrode 613 are spaced apart by the width of a red light-emitting device (or the width of a green light-emitting device), and the first transition electrode 612 and the first transition electrode 613 are spaced apart by the diagonal length of a red light-emitting device.

[0132] The difference between Example 4 and Examples 1-3 is that the isolation post 40 adopts a non-circular structure, using an independent isolation structure 7 to isolate the cathode 33. The isolation post 40 plays an auxiliary isolation role. Most importantly, the isolation post 40 acts as a transfer electrode, connecting the cathode 33 attached to it to the first electrode D of the driving transistor DTFT through the second transfer electrode 62. Other structural features are the same, and repeated parts will not be described again.

[0133] In addition, this disclosure also provides a method for preparing a display panel, including steps S11 to S13.

[0134] S11. Provide a substrate 1.

[0135] S12. A driving layer 2 is formed on a substrate 1. The driving layer 2 includes multiple pixel driving circuits for driving multiple light-emitting devices 3. At least one of the multiple pixel driving circuits includes multiple transistors, such as a driving transistor DTFT.

[0136] S13. Multiple light-emitting devices 3 are formed on the side of the driving layer 2 away from the substrate 1.

[0137] In this configuration, the anode 31 of at least one of the multiple light-emitting devices 3 is electrically connected to the first power signal line VDD, the cathode 33 of at least one of the multiple light-emitting devices 3 is electrically connected to the first electrode D of the driving transistor DTFT, and the second electrode of the driving transistor DTFT is electrically connected to the second power signal line VSS. The first power supply voltage of the first power signal line VDD is greater than the second power supply voltage transmitted through the second power signal line VSS.

[0138] In this embodiment, the anode 31 of at least one light-emitting device 3 is electrically connected to the first power signal line VDD, and the cathode 33 of at least one light-emitting device 3 is electrically connected to the first electrode D of the driving transistor DTFT, thus forming at least one light-emitting device 3 with an independent cathode 33. This eliminates the influence of the large voltage drop across the entire structure of the cathode 33 of the light-emitting device 3, thereby improving brightness uniformity. At the same time, the independent cathode 33 of the light-emitting device 3 is electrically connected to one end of the first electrode D of the driving transistor DTFT. Compared with the conventional method where the light-emitting device 3 is electrically connected to one end of the second electrode of the driving transistor DTFT, this disclosure can eliminate the voltage fluctuation of the second electrode of the driving transistor DTFT caused by temperature, that is, stabilize the voltage of the second electrode (source) of the driving transistor DTFT. Therefore, it can improve the influence of the voltage fluctuation of the second electrode (source) of the driving transistor DTFT on the gate voltage of the driving transistor DTFT, thereby improving brightness uniformity, improving thermal retention, and thus improving display quality.

[0139] In some embodiments, before forming the driving layer 2, a buffer layer Buffer is formed on the substrate 1.

[0140] In some embodiments, forming the driving layer 2 specifically includes: forming an active layer of a driving transistor DTFT on the side of the buffer layer away from the substrate 1; forming a first gate insulating layer GI1 on the side of the active layer away from the substrate 1; forming the gate of the driving transistor DTFT and the first electrode of the storage capacitor Cst on the side of the first gate insulating layer GI1 away from the substrate 1; forming a second gate insulating layer GI2 on the side of the gate of the driving transistor DTFT away from the substrate 1; forming a second electrode of the storage capacitor Cst on the side of the second gate insulating layer GI2 away from the substrate 1; forming an interlayer insulating layer ILD on the side of the second electrode of the storage capacitor Cst away from the substrate 1; and forming a first electrode D and a second electrode S of the light-emitting device 1 on the side of the interlayer insulating layer ILD away from the substrate 1, thereby obtaining the driving layer 2.

[0141] In some embodiments, before forming the light-emitting layer 32 of the light-emitting device 3, the method further includes:

[0142] S21. As shown in Figure 12a, a planarization layer PLN is formed on the side of the driving layer 2 away from the substrate 1 to planarize the underlying film structure.

[0143] S22. As shown in Figure 12b, the anodes 31 of each light-emitting device 3 are formed on the side of the planarization layer PLN away from the driving layer 2.

[0144] The anodes 31 of each light-emitting device 3 are set independently and spaced apart from each other.

[0145] S23. As shown in Figure 12c, a pixel-defining material layer PDL' and a transition electrode material layer 4' are sequentially formed on the side of the anode 31 away from the planarization layer PLN.

[0146] It should be noted that, as shown in Figure 12c, after forming the pixel-defining material layer PDL' and before forming the transition electrode material layer 4', it is also necessary to etch the first connection via V1 and the second connection via V2, and form the second transition electrode 62 that penetrates the first connection via V1 and the second connection via V2.

[0147] S24. Etch the transition electrode material layer 4' and the pixel defining material layer PDL' to form the pixel defining layer PDL and the transition electrode layer 4.

[0148] The transition electrode layer 4 includes an isolation pillar 40, the orthographic projection of the barrier structure on the substrate 1 covers the orthographic projection of the isolation pillar 40 on the substrate 1; the cathode 33 of at least one light-emitting device 3 extends from the corresponding pixel opening to the surrounding barrier structure and is separated by the isolation pillar 40; the isolation pillar 40 overlaps with the separated cathode 33 and is electrically connected to the first electrode D of the driving transistor DTFT; an insulating structure 5 is provided between two adjacent light-emitting devices 3, and the insulating structure 5 isolates the cathode 33 of the two adjacent light-emitting devices 3.

[0149] The display panel includes multiple first light-emitting devices 301, multiple second light-emitting devices 302, and multiple third light-emitting devices 303. The first light-emitting devices 301, 302, and 303 are light-emitting devices 3 of different colors, such as red, green, and blue, respectively. Optionally, each light-emitting device 3 has a corresponding isolation pillar 40. For example, the first light-emitting device 301 corresponds to the first isolation pillar 401, the second light-emitting device 302 corresponds to the second isolation pillar 402, and the third light-emitting device 303 corresponds to the third isolation pillar 403. The orthographic projection of the first isolation pillar 401 on the substrate 1 surrounds the orthographic projection of the first light-emitting device 301 on the substrate 1; the orthographic projection of the second isolation pillar 402 on the substrate 1 surrounds the orthographic projection of the second light-emitting device 302 on the substrate 1; and the orthographic projection of the third isolation pillar 403 on the substrate 1 surrounds the orthographic projection of the third light-emitting device 303 on the substrate 1.

[0150] In one possible implementation, the first isolation pillar 401, the second isolation pillar 402, and the third isolation pillar 403 are formed in steps, and after the first isolation pillar 401 is formed, a plurality of first light-emitting devices 301 are prepared; after the second isolation pillar 402 is formed, a plurality of second light-emitting devices 302 are prepared; and after the third isolation pillar 403 is formed, a plurality of third light-emitting devices 303 are prepared.

[0151] Here, taking the display panel in Example 1 as an example, the specific process includes S24-1-1 to S24-1-5.

[0152] S24-1-1 As shown in Figure 12d, the transition electrode material layer 4' is etched once to form multiple undercut structures 120; the orthogonal projection of the undercut structure 120 on the substrate 1 is located between the orthogonal projections of the anode 31 of the adjacent light-emitting device 3 on the substrate 1.

[0153] S24-1-2, As shown in Figure 12e, an insulating layer 51 is formed on the side of the transition electrode material layer 4' with the undercut structure 120 that faces away from the pixel defining material layer PDL'. The orthogonal projection of the insulating layer 51 on the substrate 1 covers the orthogonal projection of the undercut structure 120 on the substrate 1.

[0154] S24-1-3 As shown in Figure 12f, the transition electrode material layer 4' and pixel limiting material layer PDL' with undercut structure 120 are etched a second time to form a plurality of first openings penetrating the transition electrode material layer 4' and pixel limiting material layer PDL' to expose the anode 31 of a plurality of first light-emitting devices 301 and to obtain a first isolation pillar 401 that overlaps with the plurality of first light-emitting devices 301.

[0155] After forming the first isolation pillar 401 and before forming the second isolation pillar 402, the process includes forming a plurality of first light-emitting devices 301, as shown in FIG12g: First, a light-emitting material layer and a cathode layer of a plurality of first light-emitting devices 301 are sequentially formed on the side of the transition electrode material layer 4' facing away from the pixel defining material layer PDL'. Here, an open mask can be used to vapor-deposit the entire light-emitting material layer and cathode layer. Second, a photolithography or etching process can be used to remove the light-emitting material layer and cathode layer outside the first sub-pixel region to form a plurality of first light-emitting devices 301. The plurality of first light-emitting devices 301 and the first isolation pillar 401 are all located in the first sub-pixel region.

[0156] Optionally, before removing the light-emitting material layer and cathode layer outside the first sub-pixel region, an encapsulation material layer (such as an inorganic encapsulation material layer) is formed on the side of the cathode layer of the plurality of first light-emitting devices 301 facing away from the substrate 1. Here, an open mask can be used to vapor-deposit the entire encapsulation material layer, thereby protecting the cathode layer and light-emitting material layer of the plurality of first light-emitting devices 301. The light-emitting material layer, cathode layer, and encapsulation material layer outside the first sub-pixel region are then removed to form the plurality of first light-emitting devices 301.

[0157] In this embodiment, the isolation pillar 40 and the light-emitting device 3 are prepared in steps. An open mask can be used, which is more cost-effective than a fine mask (FMM), which is more expensive.

[0158] S24-1-4 As shown in Figure 12h, the transition electrode material layer 4' and pixel limiting material layer PDL' with undercut structure 120 are etched three times to form multiple second openings penetrating the transition electrode material layer 4' and pixel limiting material layer PDL', so as to expose the anode 31 of multiple second light-emitting devices 302 and obtain the second isolation pillar 402 overlapping with the multiple second light-emitting devices 302.

[0159] After forming the second isolation pillar 402 and before forming the third isolation pillar 403, the process includes forming a plurality of second light-emitting devices 302, as shown in FIG12i: First, a light-emitting material layer and a cathode layer of a plurality of second light-emitting devices 302 are sequentially formed on the side of the transition electrode material layer 4' facing away from the pixel defining material layer PDL'. Here, an open mask can be used to vapor-deposit the entire light-emitting material layer and cathode layer. Second, a photolithography or etching process can be used to remove the light-emitting material layer and cathode layer outside the second sub-pixel region to form a plurality of second light-emitting devices 302; the plurality of second light-emitting devices 302 and the second isolation pillar 402 are all located in the second sub-pixel region.

[0160] Optionally, before removing the light-emitting material layer and cathode layer outside the second sub-pixel region, an encapsulation material layer (such as an inorganic encapsulation material layer) is formed on the side of the cathode layer of the plurality of second light-emitting devices 302 facing away from the substrate 1. Here, an open mask can be used to vapor-deposit the entire encapsulation material layer, thereby protecting the cathode layer and light-emitting material layer of the plurality of second light-emitting devices 302. The light-emitting material layer, cathode layer, and encapsulation material layer outside the second sub-pixel region are then removed to form the plurality of second light-emitting devices 302.

[0161] S24-1-5 As shown in Figure 12j, the undercut structure 120 undergoes four etching processes to form multiple third openings that penetrate the undercut electrode material layer 4' and the pixel limiting material layer PDL', thereby exposing the anode 31 of multiple third light-emitting devices 303 and obtaining third isolation pillars 403 that overlap with the multiple third light-emitting devices 303.

[0162] After forming the third isolation pillar 403, the process further includes forming multiple third light-emitting devices 303, as shown in Figure 12k: First, a light-emitting material layer and a cathode layer of multiple third light-emitting devices 303 are sequentially formed on the side of the transition electrode material layer 4' facing away from the pixel defining material layer PDL'. Here, an open mask can be used to vapor deposit the entire light-emitting material layer and cathode layer. Second, a photolithography or etching process can be used to remove the light-emitting material layer and cathode layer outside the third sub-pixel region to form multiple third light-emitting devices 303; the multiple third light-emitting devices 303 and the third isolation pillar 403 are all located in the third sub-pixel region.

[0163] Optionally, before removing the light-emitting material layer and cathode layer outside the third sub-pixel region, an encapsulation material layer (such as an inorganic encapsulation material layer) is formed on the side of the cathode layer of the plurality of third light-emitting devices 303 facing away from the substrate 1. Here, an open mask can be used to vapor-deposit the entire encapsulation material layer, thereby protecting the cathode layer and light-emitting material layer of the plurality of third light-emitting devices 303. After removing the light-emitting material layer, cathode layer, and encapsulation material layer outside the third sub-pixel region, a plurality of second light-emitting devices 303 are formed.

[0164] The final display panel shown in Figure 12k is formed, wherein a first isolation pillar 401 is arranged around the first light-emitting device 301, a second isolation pillar 402 is arranged around the second light-emitting device 302, and a third isolation pillar 403 is arranged around the third light-emitting device 303. An insulating layer 51 is arranged between two adjacent isolation pillars 40, and the orthographic projection of the insulating layer 51 on the substrate 1 covers the orthographic projection of the two adjacent isolation pillars 40 on the substrate 1, so as to isolate the cathode 33 overlapping on the isolation pillar 40 and the cathode 33 of other adjacent light-emitting devices 3 that are isolated.

[0165] Optionally, after the first inorganic encapsulation layer CVD1 is prepared, an organic encapsulation layer IJP and a second inorganic encapsulation layer CVD2 are sequentially formed on the side of the first inorganic encapsulation layer CVD1 away from the substrate 1, as shown in Figure 3.

[0166] In another possible implementation, the first isolation pillar 401, the second isolation pillar 402, and the third isolation pillar 403 are formed in one step, and then the first light-emitting device 301, the second light-emitting device 302, and the third light-emitting device 303 are formed in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region respectively using the fine masks corresponding to the different colored light-emitting devices 3.

[0167] Here, taking the display panel in Example 1 as an example, the specific process includes S24-2-1 to S24-2-6.

[0168] S24-2-1 As shown in Figure 12d, the transition electrode material layer 4' is etched once to form multiple undercut structures 120; the orthogonal projection of the undercut structure 120 on the substrate 1 is located between the orthogonal projections of the anode 31 of the adjacent light-emitting device 3 on the substrate 1.

[0169] S24-2-2, As shown in Figure 12e, an insulating layer 51 is formed on the side of the transition electrode material layer 4' with the undercut structure 120 that faces away from the pixel defining material layer PDL'. The orthogonal projection of the insulating layer 51 on the substrate 1 covers the orthogonal projection of the undercut structure 120 on the substrate 1.

[0170] S24-2-3, As shown in Figure 13a, the transition electrode material layer 4' and the pixel defining material layer PDL' with the undercut structure 120 are etched a second time to form multiple openings penetrating the transition electrode material layer 4' and the pixel defining material layer PDL'. For example, multiple first openings, multiple second openings and multiple third openings are formed to expose the anodes 31 of multiple first light-emitting devices 301, the anodes 31 of multiple second light-emitting devices 302 and the anodes 31 of multiple third light-emitting devices 303, and the pixel defining layer PDL and the transition electrode layer 4 are obtained. The transition electrode layer 4 includes a first isolation pillar 401, a second isolation pillar 402 and a third isolation pillar 403.

[0171] Following step S24-2-3, multiple light-emitting layers 32 and cathodes 33 of light-emitting devices 3 are sequentially formed on the side of the transition electrode layer 4 away from the pixel limiting layer PDL to obtain multiple light-emitting devices 3, as shown in Figure 13b. Specifically, this includes the following steps S24-2-4 to S24-2-6.

[0172] S24-2-4. Using a first fine mask (FMM) process, a plurality of light-emitting layers 32 and cathodes 33 of a plurality of first light-emitting devices 301 are formed in a plurality of first openings, thereby obtaining a plurality of first light-emitting devices 301. The first fine mask includes mask openings that are directly opposite each of the first openings.

[0173] S24-2-5. Using a second fine mask (FMM) process, a plurality of light-emitting layers 32 and cathodes 33 of a plurality of second light-emitting devices 302 are formed within a plurality of second openings, thereby obtaining a plurality of second light-emitting devices 302. The second fine mask includes mask openings that are directly opposite each of the second openings.

[0174] S24-2-6. Using a third fine mask (FMM) process, a plurality of light-emitting layers 32 and cathodes 33 of a plurality of third light-emitting devices 303 are formed within a plurality of third openings, thereby obtaining a plurality of third light-emitting devices 303. The third fine mask includes mask openings that are directly opposite each of the third openings.

[0175] In some embodiments, the difference between the display panel of Example 2 and the display panel of Example 1 lies in the different insulating structure 5. Taking the display panel of Example 2 as an example, it is similar to Example 1, including S24-3-1 to S24-3-6.

[0176] S24-3-1, Etch the transition electrode material layer 4' once to form multiple undercut structures 120; The orthogonal projection of the undercut structure 120 on the substrate 1 is located between the orthogonal projections of the anode 31 of the adjacent light-emitting device 3 on the substrate 1.

[0177] S24-3-2, perform secondary etching on the transition electrode material layer 4' and pixel limiting material layer PDL' with undercut structure 120 to form multiple first openings penetrating the transition electrode material layer 4' and pixel limiting material layer PDL' to expose the anode 31 of multiple first light-emitting devices 301, and obtain the first isolation pillar 401 that overlaps with the multiple first light-emitting devices 301.

[0178] S24-3-3, the transition electrode material layer 4' and pixel limiting material layer PDL' with undercut structure 120 are etched three times to form multiple second openings penetrating the transition electrode material layer 4' and pixel limiting material layer PDL' to expose the anode 31 of multiple second light-emitting devices 302, and to obtain second isolation pillars 402 that overlap with multiple second light-emitting devices 302.

[0179] S24-3-4. The transition electrode material layer 4' and the pixel limiting material layer PDL' with the undercut structure 120 are etched four times to form multiple third openings that penetrate the transition electrode material layer 4' and the pixel limiting material layer PDL', so as to expose the anode 31 of multiple third light-emitting devices 303 and obtain the third isolation pillar 403 that overlaps with the multiple third light-emitting devices 303.

[0180] The above S24-4-2 to S24-3-4 can be performed by evaporating the entire light-emitting material layer and cathode layer using an open mask. Alternatively, photolithography or etching processes can be used to remove the light-emitting material layer and cathode layer outside the sub-pixel region.

[0181] S24-3-5. An inorganic encapsulation material layer is formed on the side of each light-emitting device 3 facing away from the substrate 1. The light-emitting layer 32 and cathode 33 of at least one light-emitting device 3, as well as the inorganic encapsulation material layer, extend from the corresponding pixel opening to the surrounding barrier structure, and the light-emitting layer 32, cathode 33 and inorganic encapsulation material layer extending to the barrier structure constitute a stacked structure.

[0182] S24-3-6. Etch the stacked structure between adjacent isolation pillars 40 to form the first etched channel 52 and obtain the first inorganic encapsulation layer CVD1.

[0183] Optionally, a photolithography or etching process can be used to remove the light-emitting material layer, cathode layer, and inorganic encapsulation material layer located between two adjacent isolation pillars 40 to form the first etching channel 52.

[0184] Optionally, a laser can be used to remove the light-emitting material layer, cathode layer and inorganic encapsulation material layer located between two adjacent isolation pillars 40 to form a first etched trench 52.

[0185] Similarly, the steps for forming the isolation pillars 40 in steps and the steps for forming the isolation pillars 40 in one step in the preparation of the display panel of Example 2 are the same as those for the preparation of the display panel of Example 1, and the repeated parts will not be described again.

[0186] Optionally, after the first inorganic encapsulation layer CVD1 is prepared, an organic encapsulation layer IJP and a second inorganic encapsulation layer CVD2 are sequentially formed on the side of the first inorganic encapsulation layer CVD1 away from the substrate 1.

[0187] In some embodiments, the difference between the display panel of Example 3 and the display panel of Example 1 lies in the different patterns of the isolation pillars 40 and the different insulating structures 5. Taking the display panel of Example 3 as an example, as shown in FIG14a, the isolation pillars 40 can be fabricated by one-time molding, and the light-emitting device 3 can be formed using a fine mask (FMM). For details, please refer to the detailed descriptions of S24-2-1 to S24-2-6 related to Example 1, which will not be repeated here.

[0188] After the individual light-emitting devices 3 are formed, as shown in Figure 14b, an etching process is used to etch the isolation pillars 40 to form a second etched channel 53. The second etched channel 53 penetrates the isolation pillars 40 in the thickness direction of the substrate 1. The second etched channel 53 divides the isolation pillars 40 into a first half 40a and a second half 40b to isolate the cathodes 33 of adjacent light-emitting devices 3, preventing the isolated cathodes 33 from being reconnected through the conductive isolation pillars 40.

[0189] Optionally, after the first inorganic encapsulation layer CVD1 is prepared, an organic encapsulation layer IJP and a second inorganic encapsulation layer CVD2 are sequentially formed on the side of the first inorganic encapsulation layer CVD1 away from the substrate 1.

[0190] In some embodiments, the difference between the display panel of Example 4 and the display panel of Example 1 lies in the different patterns of the isolation pillars 40 and the different insulating structures 5. Taking the display panel of Example 4 as an example, the isolation pillars 40 can be fabricated by one-time molding, as detailed in the specific descriptions of S24-2-1 to S24-2-3 related to Example 1, which will not be repeated here.

[0191] The transition electrode material layer 4' with undercut structure 120 and the pixel defining material layer PDL' are etched a second time to obtain the pixel defining layer PDL and the transition electrode layer 4, wherein the transition electrode layer 4 includes a first isolation pillar 401, a second isolation pillar 402 and a third isolation pillar 403. Then, as shown in FIG15a, a partition structure 7 is formed on the side of the transition electrode layer 4 (or isolation pillar 40) facing away from the substrate 1. The orthogonal projection of the partition structure 7 on the substrate 1 surrounds the orthogonal projection of the light-emitting device 3 on the substrate 1; the cathode 33 of at least one light-emitting device 3 extends from the corresponding pixel opening to the surrounding barrier structure and is simultaneously partitioned by the partition structure 7 and the isolation pillar 40, mainly by the partition structure 7, while the isolation pillar 40 only partitions the cathode 33 in part 43, playing an auxiliary partitioning role. The height of the isolation pillar 40 is lower than the height of the partition structure 7, and the partition structure 7 covers the side surface of the isolation pillar 40 away from the cathode 33 and at least part of the surface of the isolation pillar 40 facing away from the substrate 1. Subsequently, as shown in FIG15b, a plurality of light-emitting layers 32 and cathodes 33 of light-emitting devices 3 are sequentially formed on the side of the partition structure 7 facing away from the substrate 1 to obtain a plurality of first light-emitting devices 301, a plurality of second light-emitting devices 302 and a plurality of third light-emitting devices 303. Optionally, a fine mask (FMM) can be used to form the plurality of light-emitting devices 3, as detailed in S24-2-4 to S24-2-6 related to Example 1, which will not be repeated here.

[0192] This disclosure also provides a display device, which includes the display panel of any of the above embodiments. The display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0193] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel, comprising a substrate, a driving layer disposed on the substrate, and a plurality of light-emitting devices disposed on a side of the driving layer opposite to the substrate, the driving layer including a plurality of pixel driving circuits for driving the plurality of light-emitting devices; at least one of the plurality of pixel driving circuits includes at least a driving transistor. The anode of at least one of the plurality of light-emitting devices is electrically connected to a first power signal line, the cathode of at least one of the plurality of light-emitting devices is electrically connected to the first electrode of the driving transistor, the second electrode of the driving transistor is electrically connected to a second power signal line, and the first power supply voltage of the first power signal line is greater than the second power supply voltage transmitted by the second power signal line.

2. The display panel according to claim 1, wherein, The display panel further includes a pixel defining layer and a transition electrode layer disposed on the side of the pixel defining layer opposite to the driving layer; The pixel defining layer includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, wherein the plurality of pixel openings are used to define the plurality of light-emitting devices; The transition electrode layer includes an isolation pillar, and the orthographic projection of the barrier structure on the substrate covers the orthographic projection of the isolation pillar on the substrate; the cathode of the at least one light-emitting device extends from the corresponding pixel opening to the surrounding barrier structure and is separated by the isolation pillar; the isolation pillar overlaps with the separated cathode and is electrically connected to the first electrode of the driving transistor. An insulating structure is provided between two adjacent light-emitting devices, and the insulating structure isolates the cathodes of the two adjacent light-emitting devices.

3. The display panel according to claim 2, wherein, The isolation pillars are arranged in a one-to-one correspondence with the light-emitting devices, and the orthographic projection of the isolation pillar on the substrate surrounds the orthographic projection of the corresponding light-emitting device on the substrate; adjacent isolation pillars are spaced apart.

4. The display panel according to claim 3, wherein, The insulating structure is an insulating layer; The insulating layer covers the side surface of the isolation pillar away from the cathode overlap and at least a portion of the surface of the isolation pillar facing away from the substrate.

5. The display panel according to claim 3, wherein, The display panel further includes an encapsulation layer disposed on the side of the at least one light-emitting device facing away from the substrate. The light-emitting layer and cathode of the at least one light-emitting device, as well as the encapsulation layer, all extend from the corresponding pixel opening to the surrounding barrier structure, and the light-emitting layer, cathode, and encapsulation layer extending to the barrier structure constitute a stacked structure; The insulating structure is a first etched trench, which extends through the stacked structure located between two adjacent isolation pillars in the thickness direction of the substrate.

6. The display panel according to claim 2, wherein, The insulating structure is a second etched channel, which penetrates the isolation pillar in the thickness direction of the substrate. The isolation pillar includes a first half and a second half; the first half and the second half are separated by the second etched channel; the orthographic projections of the first half and the second half on the substrate respectively surround the orthographic projections of different light-emitting devices on the substrate; The display panel further includes an encapsulation layer disposed on the side of the at least one light-emitting device away from the substrate, the encapsulation layer falling into the second etched trench and covering the opposing side surfaces of the first half and the second half.

7. The display panel according to claim 1, wherein, The display panel further includes a pixel defining layer, a first transition electrode disposed on the side of the pixel defining layer opposite to the driving layer, and a partition structure; the pixel defining layer includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, the plurality of pixel openings being used to define the plurality of light-emitting devices; The orthographic projection of the partition structure on the substrate surrounds the orthographic projection of the corresponding light-emitting device on the substrate; the cathode of the at least one light-emitting device extends from the pixel opening toward the surrounding barrier structure and is partitioned by the partition structure; The first transition electrode is disposed between the partition structure and the light-emitting device, and the first transition electrode is connected to the cathode that is separated by the partition structure, and is electrically connected to the first electrode of the driving transistor.

8. The display panel according to claim 7, wherein, The first transition electrode is an isolation pillar; the height of the isolation pillar is lower than the height of the partition structure, and the partition structure covers the side surface of the isolation pillar away from the cathode overlap side and at least a portion of the surface of the isolation pillar away from the substrate.

9. The display panel according to claim 2 or 8, wherein, The isolation pillar includes a bottom, a main body, and a partition portion arranged sequentially along a direction away from the substrate; both the bottom and the partition portion protrude from the main body. The partition portion blocks the cathode of at least one light-emitting device extending to the retaining wall structure. The cathode of the at least one light-emitting device overlaps with the main body portion and is electrically connected to the first electrode of the driving transistor through the main body portion and the bottom.

10. The display panel according to claim 9, wherein, The display panel further includes an encapsulation layer disposed on the side of the at least one light-emitting device facing away from the substrate, the encapsulation layer filling the recessed notch between the partition portion and the main body portion.

11. The display panel according to claim 2 or 8, wherein, The isolation pillar includes a main body and a partition portion located on the side of the main body facing away from the substrate; the partition portion protrudes from the main body. The partition portion blocks the cathode of at least one light-emitting device extending to the retaining wall structure. The cathode of the at least one light-emitting device overlaps with the main body portion and is electrically connected to the first electrode of the driving transistor through the main body portion.

12. The display panel according to claim 2 or 8, wherein, The display panel also includes a second transfer electrode and a planarization layer disposed on the side of the driving layer near the pixel defining layer; The second adapter electrode is electrically connected to the first electrode of the driving transistor and the isolation post through the first connection via through the retaining wall structure and the second connection via through the planarization layer.

13. A method for manufacturing a display panel, used to manufacture the display panel as described in any one of claims 1 to 12; wherein, The method for manufacturing the display panel includes: Provide one of the aforementioned substrates; A driving layer is formed on the substrate; the driving layer includes a plurality of pixel driving circuits for driving a plurality of light-emitting devices; at least one of the plurality of pixel driving circuits includes at least a driving transistor. A plurality of light-emitting devices are formed on the side of the driving layer away from the substrate; wherein, the anode of at least one of the plurality of light-emitting devices is electrically connected to a first power signal line, the cathode of at least one of the plurality of light-emitting devices is electrically connected to the first electrode of the driving transistor, the second electrode of the driving transistor is electrically connected to a second power signal line, and the first power supply voltage of the first power signal line is greater than the second power supply voltage transmitted by the second power signal line.

14. The method for manufacturing a display panel according to claim 13, wherein, Before forming the light-emitting layer of the light-emitting device, the following is also included: A planarization layer is formed on the side of the driving layer opposite to the substrate. The anodes of each of the light-emitting devices are formed on the side of the planarization layer opposite to the driving layer; A pixel defining material layer and a transition electrode material layer are sequentially formed on the side of the anode that is away from the planarization layer; The transition electrode material layer and the pixel defining material layer are etched to form a pixel defining layer and a transition electrode layer; The pixel defining layer includes a plurality of pixel openings and a barrier structure for forming the plurality of pixel openings, the plurality of pixel openings defining the plurality of light-emitting devices; the transition electrode layer includes an isolation pillar, the orthographic projection of the barrier structure on the substrate covers the orthographic projection of the isolation pillar on the substrate; the cathode of at least one light-emitting device extends from the corresponding pixel opening to the surrounding barrier structure and is separated by the isolation pillar; the isolation pillar overlaps with the separated cathode and is electrically connected to the first electrode of the driving transistor; an insulating structure is provided between two adjacent light-emitting devices, the insulating structure isolating the cathodes of the two adjacent light-emitting devices.

15. The method for manufacturing a display panel according to claim 14, wherein, The plurality of light-emitting devices include a plurality of first light-emitting devices, a plurality of second light-emitting devices, and a plurality of third light-emitting devices; Etching the transition electrode material layer and the pixel defining material layer to form a pixel defining layer and a transition electrode layer includes: The transition electrode material layer is etched once to form multiple undercut structures; the orthographic projection of the undercut structure on the substrate is located between the orthographic projections of the anodes of the adjacent light-emitting devices on the substrate. The transition electrode material layer and the pixel defining material layer having the undercut structure are etched a second time to form a plurality of first openings penetrating the transition electrode material layer and the pixel defining material layer to expose the anodes of the plurality of first light-emitting devices and to obtain a first isolation pillar that overlaps with the plurality of first light-emitting devices. The transition electrode material layer and the pixel defining material layer having the undercut structure are etched three times to form a plurality of second openings penetrating the transition electrode material layer and the pixel defining material layer, so as to expose the anodes of the plurality of second light-emitting devices and obtain second isolation pillars that overlap with the plurality of second light-emitting devices; The undercut structure's transition electrode material layer and pixel defining material layer are etched four times to form multiple third openings penetrating the transition electrode material layer and pixel defining material layer, thereby exposing the anodes of the multiple third light-emitting devices and obtaining third isolation pillars that overlap with the multiple third light-emitting devices.

16. The method for manufacturing a display panel according to claim 15, wherein, After the second etching and before the third etching, the process also includes: On the side of the transition electrode material layer opposite to the pixel defining material layer, the light-emitting material layer and the cathode layer of the plurality of first light-emitting devices are sequentially formed; The light-emitting material layer and the cathode layer outside the first sub-pixel region are removed to form the plurality of first light-emitting devices; the plurality of first light-emitting devices and the first isolation pillar are all located in the first sub-pixel region.

17. The method for manufacturing a display panel according to claim 15, wherein, After three etching operations and before the fourth etching operation, the process also includes: On the side of the transition electrode material layer opposite to the pixel defining material layer, the light-emitting material layer and the cathode layer of the plurality of second light-emitting devices are sequentially formed; The light-emitting material layer and the cathode layer outside the second sub-pixel region are removed to form the plurality of second light-emitting devices; the plurality of second light-emitting devices and the second isolation pillar are all located in the second sub-pixel region.

18. The method for manufacturing a display panel according to claim 15, wherein, After four etching processes, the process also includes: On the side of the transition electrode material layer opposite to the pixel defining material layer, the light-emitting material layer and the cathode layer of the plurality of third light-emitting devices are sequentially formed; The light-emitting material layer and the cathode layer outside the third sub-pixel region are removed to form the plurality of third light-emitting devices; the plurality of third light-emitting devices and the third isolation pillar are all located in the third sub-pixel region.

19. The method for manufacturing a display panel according to claim 14, wherein, Etching the transition electrode material layer and the pixel defining material layer to form a pixel defining layer and a transition electrode layer includes: The transition electrode material layer is etched once to form multiple undercut structures; the orthographic projection of the undercut structure on the substrate is located between the orthographic projections of the anodes of the adjacent light-emitting devices on the substrate. The transition electrode material layer and the pixel defining material layer having the undercut structure are etched a second time to form multiple openings penetrating the transition electrode material layer and the pixel defining material layer to expose the anode of each of the light-emitting devices, and to obtain the pixel defining layer and the transition electrode layer.

20. The method for manufacturing a display panel according to claim 19, wherein, After forming the aforementioned transition electrode layer, the method further includes: The light-emitting layer and cathode of the plurality of light-emitting devices are sequentially formed on the side of the transition electrode layer opposite to the pixel defining layer to obtain the plurality of light-emitting devices.

21. The method for manufacturing a display panel according to claim 15 or 19, wherein, Before the second etching process, the following is also included: An insulating layer is formed on the side of the transition electrode material layer having the undercut structure that is opposite to the pixel defining material layer; the orthogonal projection of the insulating layer on the substrate covers the orthogonal projection of the undercut structure on the substrate.

22. The method for manufacturing a display panel according to claim 15 or 19, wherein, After forming each of the aforementioned light-emitting devices, the process further includes: An inorganic encapsulation material layer is formed on the side of the light-emitting device away from the substrate; the light-emitting layer and cathode of the at least one light-emitting device, as well as the inorganic encapsulation material layer, all extend from the pixel opening to the surrounding barrier structure, and the light-emitting layer, the cathode, and the inorganic encapsulation material layer extending to the barrier structure constitute a stacked structure; The stacked structure between adjacent isolation pillars is etched to form a first etching channel; the first etching channel penetrates the stacked structure located between two adjacent isolation pillars in the thickness direction of the substrate.

23. The method for manufacturing a display panel according to claim 15 or 20, wherein, The light-emitting layer and cathode of the at least one light-emitting device both extend from the pixel opening toward the surrounding barrier structure, and the light-emitting layer and cathode extending onto the barrier structure form a stacked structure; After forming each of the aforementioned light-emitting devices, the process further includes: The isolation pillar is etched to form a second etched channel; the second etched channel penetrates the isolation pillar in the thickness direction of the substrate; the second etched channel divides the isolation pillar into a first half and a second half.

24. The method for manufacturing a display panel according to claim 15 or 20, wherein, Before forming each of the aforementioned light-emitting devices, the process also includes: A partition structure is formed on the side of the transition electrode layer away from the substrate, the partition structure enclosing the side surface of the isolation pillar away from the pixel opening and at least a portion of the surface of the isolation pillar away from the substrate.

25. A display device, wherein, Includes the display panel as described in any one of claims 1 to 12.

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