Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display device. The display panel comprises: a base substrate, a plurality of pixel driving circuit groups, data line groups, and a plurality of data connection lines. The plurality of pixel driving circuit groups are distributed in an array along row and column directions. Each pixel driving circuit group comprises a plurality of pixel driving circuit subgroups distributed in the row direction, and each pixel driving circuit subgroup comprises one or more rows of pixel driving circuits. The data line groups correspond to the pixel driving circuit groups. Each data line group comprises a plurality of data lines, and orthographic projections of the data lines on the base substrate extend along the column direction. The data lines in each data line group are located on one side or two sides of the corresponding pixel driving circuit group along the row direction. The plurality of data connection lines extend along the row direction. The data lines correspond to the pixel driving circuit subgroups, and each data line is connected, via a data connection line, to pixel driving circuits located in the same row within the corresponding pixel driving circuit subgroup. The display panel has a good display effect.

Description

Display panel, display device

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Application No. 202510122940.6, filed on January 24, 2025, entitled "Display Panel, Display Device", the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0004] In related technologies, some display panels require high brightness of sub-pixel units. These panels typically use multiple pixel driving circuits to drive one or a small number of light-emitting units. Within this sub-pixel unit, multiple pixel driving circuits can be connected in parallel to drive one or a small number of light-emitting units. In this type of display panel, the multiple rows of pixel driving circuits in the sub-pixel unit require corresponding multiple data lines. These data lines, the pixel driving circuits, and other signal lines form large parasitic capacitances, resulting in significant lateral crosstalk (H-talk) and longitudinal crosstalk (V-talk) in the display panel.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0007] Substrate;

[0008] Multiple pixel driving circuit groups are arrayed along the row and column directions. Each pixel driving circuit group includes multiple pixel driving circuit subgroups distributed along the row direction. Each pixel driving circuit subgroup includes one or more rows of pixel driving circuits. Each row of pixel driving circuits includes multiple pixel driving circuits distributed along the row direction. The output terminals of multiple pixel driving circuits in the same pixel driving circuit subgroup are connected in parallel.

[0009] A data line group is provided corresponding to the pixel driving circuit group. The data line group includes multiple data lines. The orthographic projection of the data lines on the substrate extends along the column direction. The orthographic projection of the data lines in the data line group on the substrate is located on one or both sides of the orthographic projection of the corresponding pixel driving circuit group on the substrate in the row direction.

[0010] Multiple data connection lines extend along the row direction in the orthographic projection on the substrate. The data lines and the pixel driving circuit subgroups are correspondingly arranged. The data lines are connected to the pixel driving circuits located in the same row in their corresponding pixel driving circuit subgroups through the data connection lines.

[0011] In one exemplary embodiment of this disclosure, the display panel further includes a plurality of constant voltage signal lines, among which at least one first constant voltage signal line is included. The orthographic projection of the first constant voltage signal line on the substrate extends along the column direction, and the orthographic projection of the first constant voltage signal line on the substrate is located between the orthographic projections of two adjacent data lines on the substrate.

[0012] In one exemplary embodiment of this disclosure, the display panel further includes a plurality of constant voltage signal lines, among which at least one second constant voltage signal line is included. The orthographic projection of the second constant voltage signal line on the substrate extends along the row direction, and the orthographic projection of the second constant voltage signal line on the substrate is located between the orthographic projections of two adjacent data connection lines on the substrate.

[0013] In one exemplary embodiment of this disclosure, the constant voltage signal line is used to provide a power signal or an initial signal to the pixel driving circuit.

[0014] In one exemplary embodiment of this disclosure, the plurality of constant voltage signal lines include at least one first constant voltage signal line;

[0015] The orthogonal projection of the first constant voltage signal line on the substrate extends along the column direction, and the orthogonal projection of the first constant voltage signal line on the substrate is located between the orthogonal projections of the adjacent data lines on the substrate.

[0016] At least a portion of the second constant voltage signal line is connected to at least a portion of the first constant voltage signal line that intersects with it.

[0017] In one exemplary embodiment of this disclosure, the display panel further includes:

[0018] A bridging wire extends along the column direction, and the data connection line is connected to the pixel driving circuit through the bridging wire;

[0019] The orthographic projection of the second constant voltage signal line on the substrate and the orthographic projection of the bridging line on the substrate intersect, and the portion of the second constant voltage signal line intersecting with the bridging line is located in a different conductive layer from the bridging line.

[0020] In one exemplary embodiment of this disclosure, the display panel further includes:

[0021] A first initial signal line extends along the row direction in the orthogonal projection on the substrate, and the first initial signal line is used to provide a first initial signal to the pixel driving circuit.

[0022] The first initial connection line extends along the row direction in its orthogonal projection onto the substrate.

[0023] The first initial bridging line extends along the column direction in the orthographic projection on the substrate, and the first initial bridging line connects the first initial connection line and the first initial connection line in the same pixel driving circuit group.

[0024] The first initial connection line forms a second constant voltage signal line.

[0025] In one exemplary embodiment of this disclosure, the data line group includes a first data line and a second data line located on the same side of the pixel driving circuit group;

[0026] The plurality of data connection lines include a first data connection line and a second data connection line, wherein the first data connection line is connected to the first data line and the second data connection line is connected to the second data line;

[0027] In the connected data connection line and pixel driving circuit, the orthographic projection of the first data connection line on the substrate is located between the orthographic projection of the pixel driving circuit on the substrate and the orthographic projection of the second data connection line on the substrate.

[0028] The orthographic projection of the first data connection line on the substrate and the orthographic projection of the pixel driving circuit connected thereto on the substrate are arranged opposite each other in the column direction, and the orthographic projection of the first data connection line on the substrate and the orthographic projection of the pixel driving circuit connected to the second data connection line on the substrate are not arranged opposite each other in the column direction.

[0029] The orthographic projection of the second data connection line on the substrate and the orthographic projection of the pixel driving circuit connected thereto on the substrate are arranged opposite each other in the column direction, and the orthographic projection of the second data connection line on the substrate and the orthographic projection of the pixel driving circuit connected to the first data connection line on the substrate are arranged opposite each other in the column direction.

[0030] In one exemplary embodiment of this disclosure, the display panel further includes:

[0031] The first source / drain layer is located on one side of the substrate, and the data connection line is located in the first source / drain layer;

[0032] The second source / drain layer is located on the side of the first source / drain layer away from the substrate, and the data line is located in the second source / drain layer.

[0033] In an exemplary embodiment of this disclosure, the pixel driving circuit group includes a first pixel driving circuit subgroup, a second pixel driving circuit subgroup, and a third pixel driving circuit subgroup. The first pixel driving circuit subgroup is used to provide driving current to the red light-emitting unit, the second pixel driving circuit subgroup is used to provide driving current to the green light-emitting unit, and the third pixel driving circuit subgroup is used to provide driving current to the blue light-emitting unit.

[0034] The data line group includes a first data line, a second data line, and a third data line. The first data line is connected to the pixel driving circuit in the first pixel driving circuit subgroup, the second data line is connected to the pixel driving circuit in the second pixel driving circuit subgroup, and the third data line is connected to the pixel driving circuit in the third pixel driving circuit subgroup.

[0035] In the corresponding pixel driving circuit group and the data line group, the orthographic projection of the first data line and the second data line on the substrate is located on the same side of the orthographic projection of the pixel driving circuit group on the substrate in the row direction, and the orthographic projection of the first data line and the third data line on the substrate is located on opposite sides of the orthographic projection of the pixel driving circuit group on the substrate in the row direction.

[0036] In an exemplary embodiment of this disclosure, the pixel driving circuit group is provided with two sets of data line groups, and the orthographic projections of the two sets of data line groups on the substrate are respectively located on both sides of the orthographic projection of the corresponding pixel driving circuit group on the substrate in the row direction.

[0037] The same type of data lines located on both sides of the pixel driving circuit group are connected through the data connection line.

[0038] In an exemplary embodiment of this disclosure, the plurality of pixel driving circuit subgroups in the pixel driving circuit group include a first pixel driving circuit subgroup, a second pixel driving circuit subgroup, and a third pixel driving circuit subgroup;

[0039] The plurality of data connection lines include a first data connection line, a second data connection line, and a third data connection line;

[0040] In the connected data connection line and the pixel driving circuit, the orthographic projection of the second data connection line on the substrate is located on the side where the orthographic projection of the first data connection line on the substrate is far away from the orthographic projection of the pixel driving circuit on the substrate, and the orthographic projection of the third data connection line on the substrate is located on the side where the orthographic projection of the second data connection line on the substrate is far away from the orthographic projection of the pixel driving circuit on the substrate.

[0041] The display panel also includes:

[0042] A bridging wire extends along the column direction, and the data connection line is connected to the pixel driving circuit through the bridging wire. The bridging wire and the data connection line are located on different conductive layers.

[0043] In one exemplary embodiment of this disclosure, the display panel further includes:

[0044] The first ring power line is correspondingly arranged with the pixel driving circuit group, and the orthographic projection of the pixel driving circuit group on the substrate is located in the annular opening of the orthographic projection of the first ring power line on the substrate.

[0045] The second ring power line is correspondingly arranged with the pixel driving circuit group, and the orthographic projection of the first ring power line on the substrate is located within the annular opening of the orthographic projection of the second ring power line on the substrate.

[0046] The first ring power line and the second ring power line respectively provide power signals of opposite polarity to the pixel driving circuit.

[0047] In one exemplary embodiment of this disclosure, the plurality of constant voltage signal lines include at least one third constant voltage signal line, the orthographic projection of the third constant voltage signal line on the substrate extends along the column direction, the orthographic projection of the third constant voltage signal line on the substrate and the orthographic projection of the first constant voltage signal line on the substrate are located on opposite sides of the orthographic projection of the pixel driving circuit group on the substrate, and the third constant voltage signal line and the first constant voltage signal line are connected.

[0048] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0049] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0051] Figure 1 is a schematic diagram of the pixel driving circuit in the display panel of this disclosure;

[0052] Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0053] Figure 3 is a structural layout of the active layer in the display panel shown in Figure 2;

[0054] Figure 4 is a structural layout of the first gate layer in the display panel shown in Figure 2;

[0055] Figure 5 is a structural layout of the second gate layer in the display panel shown in Figure 2;

[0056] Figure 6 is a structural layout of the first source / drain layer in the display panel shown in Figure 2;

[0057] Figure 7 is a structural layout of the second source / drain layer in the display panel shown in Figure 2;

[0058] Figure 8 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 2;

[0059] Figure 9 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 2.

[0060] Figure 10 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 2;

[0061] Figure 11 is a schematic diagram of the structure of a sub-pixel unit in an exemplary embodiment of the display panel of this disclosure;

[0062] Figure 12 is a schematic diagram of the structure of a display panel in the related technology;

[0063] Figure 13 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0064] Figure 14 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0065] Figure 15 is an enlarged view of a partial area AA of the display panel shown in Figure 14.

[0066] Figure 16 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0067] Figure 17 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0068] Figure 18 is an enlarged view of a partial area BB of the display panel shown in Figure 17;

[0069] Figure 19 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0070] Figure 20 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0071] Figure 21 is an enlarged view of a partial area CC of the display panel shown in Figure 20. Detailed Implementation

[0072] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0073] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0074] Figure 1 shows a schematic diagram of the pixel driving circuit in the display panel of this disclosure. The pixel driving circuit includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C1. Specifically, the first terminal of the driving transistor T3 is connected to the first power supply terminal VDD, the second terminal is connected to the third node N3, and the gate is connected to the first node N1; the first terminal of the second transistor T2 is connected to the first node N1, the second terminal is connected to the third node N3, and the gate is connected to the gate driving signal terminal Gate; the first terminal of the first transistor T1 is connected to the data signal terminal Data, the second terminal is connected to the second node N2, and the gate is connected to the gate driving signal terminal Gate; the capacitor C is connected between the first node N1 and the second node N2; the first terminal of the fourth transistor T4 is connected to the first initial signal terminal Vinit1, and the second terminal is connected to the first... Node N1 has its gate connected to the reset signal terminal Re; the first terminal of the fifth transistor T5 is connected to the reference voltage terminal Vref, the second terminal is connected to the second node N2, and the gate is connected to the reset signal terminal Re; the first terminal of the sixth transistor T6 is connected to the reference voltage terminal Vref, the second terminal is connected to the second node N2, and the gate is connected to the enable signal terminal EM; the first terminal of the seventh transistor T7 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the gate is connected to the enable signal terminal EM; the first terminal of the eighth transistor T8 is connected to the second initial signal terminal Vinit2, the second terminal is connected to the fourth node N4, and the gate is connected to the reset signal terminal Re. The first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be N-type transistors. This pixel driving circuit is used to drive the light-emitting unit L to emit light, and the light-emitting unit L is connected between the fourth node N4 and the second power supply terminal VSS.

[0075] The driving method of this pixel driving circuit includes a reset stage, a threshold compensation stage, and a light emission stage. In the reset stage: the reset signal terminal Re outputs a high-level signal, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to the first node N1, the second initial signal terminal Vinit2 inputs a second initial signal to the fourth node N4, and the reference signal terminal Vref inputs a reference voltage Vf to the second node N2. In the threshold compensation stage: the gate driving signal terminal outputs a high-level signal, the first transistor T1 and the second transistor T2 are turned on, the first power supply terminal VDD inputs a compensation voltage Vdd+Vth to the first node N1, where Vdd is the voltage of the first power supply terminal and Vth is the threshold voltage of the driving transistor. Simultaneously, the data signal terminal Data inputs a data signal to the second node N2. During the light-emitting phase: the enable signal terminal EM1 outputs a high-level signal, turning on the sixth transistor T6 and the seventh transistor T7. The reference voltage terminal inputs a reference voltage Vf to the second node N2, changing the voltage at the second node N2 from Vdata to Vf. Vdata is the voltage of the data signal. Under the coupling effect of capacitor C, the voltage at the first node N1 becomes Vdd + Vth + Vf - Vdata. According to the formula for the output current of the driving transistor in the saturation region, the output current of the driving transistor T3 is I = (μWCox / 2L)(Vgs - Vth). 2 =(μWCox / 2L)(Vdd+Vth+Vf-Vdata-Vdd-Vth) 2 =(μWCox / 2L)(Vf-Vdata) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current, where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0076] This exemplary embodiment also provides a display panel, which may include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, and a second source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 2-10, Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 3 is a structural layout diagram of the active layer in the display panel shown in Figure 2; Figure 4 is a structural layout diagram of the first gate layer in the display panel shown in Figure 2; Figure 5 is a structural layout diagram of the second gate layer in the display panel shown in Figure 2; Figure 6 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 2; Figure 7 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 2; Figure 8 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 2; Figure 9 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 2; and Figure 10 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 2.

[0077] The display panel may include multiple pixel driving circuits arranged in an array along the row direction (X) and column direction (Y). The equivalent circuit of the pixel driving circuit can be shown in Figure 1.

[0078] As shown in Figures 2, 3, and 8, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, a nineteenth active section 719, and a twentieth active section 720. The first active portion 71 is used to form the channel region of the first transistor T1, and the second active portion 72 is used to form the channel region of the second transistor T2. The second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722. The third active portion 73 can be used to form the channel region of the driving transistor T3. The fourth active portion 74 can be used to form the channel region of the fourth transistor T4. The fifth active portion 75 can be used to form the channel region of the fifth transistor T5. The sixth active portion 76 can be used to form the channel region of the sixth transistor T6. The seventh active portion 77 can be used to form the channel region of the seventh transistor T7. The eighth active portion 78 can be used to form the channel region of the eighth transistor T8.

[0079] As shown in Figures 2, 4, and 8, the first gate layer may include: a first conductive portion 11, a second conductive portion 12, an enable signal line EM, and a gate line. The gate line can be used to provide the gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1. The orthographic projection of the gate line EM on the substrate and the orthographic projection of the enable signal line EM on the substrate can both extend along the row direction X. A portion of the structure of the enable signal line EM is used to form the gates of the sixth transistor T6 and the seventh transistor T7, respectively; a portion of the structure of the gate line EM is used to form the gates of the first transistor T1 and the second transistor T2, respectively; the first conductive portion 11 is used to form the gate of the drive transistor T3; and a portion of the structure of the second conductive portion 12 is used to form the gates of the fifth transistor T5, the fourth transistor T4, and the eighth transistor T8, respectively. This display panel can use the first gate layer as a mask to perform conductor processing on the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0080] As shown in Figures 2, 4, and 8, the orthographic projection of the enable signal line EM on the substrate and the orthographic projection of the ninth active part 79 on the substrate overlap. During the light-emitting stage of the pixel driving circuit, the enable signal line EM changes from a low level to a high level, and the enable signal line EM can pull up the voltage of the driving transistor T3 through the ninth active part 79.

[0081] As shown in Figures 2, 5, and 9, the second gate layer may include: a third conductive portion 23, a fourth conductive portion 24, a fifth conductive portion 25, and a first initial connection line 2Vinit1. The orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate at least partially overlap. The first conductive portion 11 is used to form the first electrode of the capacitor C, and the third conductive portion 23 is used to form the second electrode of the capacitor C. The fifth conductive portion 25 is connected to the first initial connection line 2Vinit1. The orthographic projection of the fifth conductive portion 25 on the substrate and the orthographic projection of the twentieth active portion 720 on the substrate overlap. The fifth conductive portion 25 is used to regulate the voltage of the twentieth active portion 720 to reduce the leakage current from the twentieth active portion 720 to the source and drain of the second transistor.

[0082] As shown in Figures 2, 6, and 10, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a first initial signal line Vinit1, a second initial signal line Vinit2, a reset signal line Re, a reference voltage line Vref, a gate connection line 3G, and a first initial connection line 2 Vinit1. The orthogonal projections of the first initial signal line Vinit1, the second initial signal line Vinit2, the reset signal line Re, the reference voltage line Vref, the gate connection line 3G, and the first initial connection line 2 Vinit1 on the substrate extend along the row direction X. The first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1, the second initial signal line Vinit2 is used to provide the second initial signal terminal in Figure 1, the reset signal line Re is used to provide the reset signal terminal in Figure 1, the reference voltage line Vref is used to provide the reference voltage terminal in Figure 1, and the gate connection line 3G is used to provide the gate drive signal terminal in Figure 1.

[0083] As shown in Figures 2, 6, and 10, the first bridging portion 31 connects to the eighteenth active portion 718 via a via, thereby connecting to the first terminal of the first transistor T1. The second bridging portion 32 connects to the sixteenth active portion 716 via a via, thereby connecting to the first terminal of the driving transistor T3. The third bridging portion 33 connects to the fourteenth active portion 714 and the fourth conductive portion 24 via vias, respectively. The first initial signal line Vinit1 connects to the fourth conductive portion 24 via a via, thereby connecting the first initial signal terminal and the first terminal of the fourth transistor. The fourth bridging portion 34 connects to the thirteenth active portion 713 via a via. The fifth bridging portion 35 connects to the twelfth active portion 712, the first conductive portion 11, and the nineteenth active portion 719 via vias, respectively, thereby connecting to the second terminal of the fourth transistor T4, the gate of the driving transistor T3, and the first terminal of the second transistor T2. The sixth bridging part 36 is connected to the eleventh active part 711, the third conductive part 23, and the seventeenth active part 717 through vias, so as to connect the second electrode of the sixth transistor, the second electrode of the capacitor C, and the second electrode of the first transistor T1.

[0084] As shown in Figures 2, 6, and 10, the second initial signal line Vinit2 can be connected to the fifteenth active section 715 via a via, thereby connecting the second initial signal terminal and the first terminal of the eighth transistor T8. The reference voltage line Vref is connected to the tenth active section 710 via a via, thereby connecting the reference voltage terminal and the first terminals of the fifth transistor T5 and the sixth transistor T6. The gate connection line 3G is connected to the gate line Gate via a via, thereby reducing the resistance of the gate line Gate.

[0085] As shown in Figures 2 and 7, the second source / drain layer may include a data line Da and a first power line VDD. The orthographic projections of the data line Da and the first power line VDD on the substrate extend along the column direction Y. The data line Da provides the data signal terminal in Figure 1, and the first power line VDD provides the first power terminal in Figure 1. The data line Da is connected to the first bridging portion 31 via a via to connect to the first terminal of the first transistor T1. The first power line VDD is connected to the second bridging portion 32 via a via to connect to the first terminal of the driving transistor T3.

[0086] In related technologies, some display panels require high brightness of sub-pixel units. These panels typically use multiple pixel driving circuits to drive one or a small number of light-emitting units. For example, Figure 11 shows a schematic diagram of a sub-pixel unit in an exemplary embodiment of the display panel disclosed herein. In this sub-pixel unit, multiple pixel driving circuits can be connected in parallel to drive one or a small number of light-emitting units. It should be noted that this exemplary embodiment only provides an example of two pixel driving circuits driving one light-emitting unit; in other exemplary embodiments, the number of parallel pixel driving circuits can be other quantities.

[0087] Figure 12 shows a schematic diagram of a display panel in the related art. The sub-pixel unit of this display panel includes multiple arrayed pixel driving circuits Pix, with the pixel driving circuits in the same sub-pixel unit connected in parallel. For example, the red sub-pixel unit includes multiple arrayed first pixel driving circuits Pixr, the green sub-pixel unit includes multiple arrayed second pixel driving circuits Pixg, and the blue sub-pixel unit includes multiple arrayed third pixel driving circuits Pixb. The multiple data lines Da in this display panel also include a first data line Dar, a second data line Dag, and a third data line Dab. The first data line Dar provides driving data signals to the first pixel driving circuit Pixr, the second data line Dag provides driving data signals to the second pixel driving circuit Pixg, and the third data line Dab provides driving data signals to the third pixel driving circuit Pixb. As shown in Figure 12, each column of pixel driving circuits is equipped with a corresponding data line. Parasitic capacitance is formed between the data line Da and the first node N1 and the second node N2 in the pixel driving circuit Pix. Since multiple data lines in the same sub-pixel unit will form parasitic capacitance with the first node N1 and the second node N2 in the corresponding pixel driving circuit Pix, the accumulated parasitic capacitance of multiple data lines is large, which will lead to severe vertical crosstalk of the display panel. At the same time, the parasitic capacitance formed by multiple data lines and signal lines such as power lines and initial signal lines is large, which will lead to severe horizontal crosstalk of the display panel.

[0088] Based on this, this exemplary embodiment provides a display panel, as shown in FIG13, which is a structural schematic diagram of an exemplary embodiment of the display panel disclosed herein. The display panel includes: a substrate, multiple pixel driving circuit groups Pz, a data line group Daz, and multiple data connection lines Dal. Multiple pixel driving circuit groups Pz are arrayed along the row direction X and column direction Y. Each pixel driving circuit group Pz includes multiple pixel driving circuit subgroups Piz distributed along the row direction X. Each pixel driving circuit subgroup Piz includes one or more rows of pixel driving circuits Pix. Each row of pixel driving circuits includes multiple pixel driving circuits Pix distributed along the row direction X. The output terminals of multiple pixel driving circuits in the same pixel driving circuit subgroup Piz are connected in parallel. Data line group Daz is correspondingly arranged with the pixel driving circuit groups. Data line group Daz includes multiple data lines Da. The orthographic projection of data lines Da on the substrate extends along the column direction Y. The orthographic projection of data lines Da in data line group Daz on the substrate is located on the side of the orthographic projection of the corresponding pixel driving circuit group Pz on the substrate in the row direction. Multiple data connection lines Dal have orthographic projections on the substrate that extend along the row direction X. Data lines Da and pixel driving circuit subgroups Piz are correspondingly arranged. Data lines Da are connected to the pixel driving circuits Pix in the same row of their corresponding pixel driving circuit subgroup Piz through data connection lines Dal.

[0089] In this exemplary embodiment, the data line group Daz, which provides data signals to the pixel driving circuit group Pz, is located on the same side of the pixel driving circuit group Pz. This arrangement can reduce the parasitic capacitance between the data lines and the pixel driving circuit, thereby improving the problem of longitudinal crosstalk in the display panel. Simultaneously, this arrangement can reduce the number of intersections between the data lines, power lines, and initial signal lines, thereby improving the problem of lateral crosstalk in the display panel.

[0090] In this exemplary embodiment, as shown in FIG13, the display panel further includes multiple constant voltage signal lines Lh, among which at least one first constant voltage signal line Lh1 is included. The orthographic projection of the first constant voltage signal line Lh1 on the substrate extends along the column direction Y, and the orthographic projection of the first constant voltage signal line Lh1 on the substrate is located between the orthographic projections of two adjacent data lines Da on the substrate. The first constant voltage signal line Lh1 can shield signal crosstalk between two adjacent data lines Da.

[0091] In this exemplary embodiment, as shown in FIG13, the display panel further includes multiple constant voltage signal lines Lh, among which at least one second constant voltage signal line Lh2 is included. The orthographic projection of the second constant voltage signal line Lh2 on the substrate extends along the row direction X, and the orthographic projection of the second constant voltage signal line Lh2 on the substrate is located between the orthographic projections of two adjacent data connection lines Dal on the substrate. The second constant voltage signal line Lh2 can shield signal crosstalk between two adjacent data connection lines Dal.

[0092] In this exemplary embodiment, as shown in FIG13, the constant voltage signal line Lh can be used to provide a power signal or an initial signal to the pixel driving circuit. For example, the constant voltage signal line Lh can be connected to any one of the first power line VDD, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 in FIG2.

[0093] In this exemplary embodiment, as shown in FIG13, the plurality of constant voltage signal lines Lh further includes at least one third constant voltage signal line Lh3. The orthographic projection of the third constant voltage signal line Lh3 on the substrate extends along the column direction Y. The orthographic projection of the third constant voltage signal line Lh3 on the substrate and the orthographic projection of the first constant voltage signal line Lh1 on the substrate are located on opposite sides of the orthographic projection of the pixel driving circuit group Pz on the substrate, and the third constant voltage signal line Lh3 and the first constant voltage signal line Lh1 are connected. On the one hand, the third constant voltage signal line Lh3 and the first constant voltage signal line Lh1 can make the two sides of the pixel driving circuit group Pz have a more uniform electric field environment, thereby improving the display uniformity of the display panel; on the other hand, the third constant voltage signal line Lh3 can further reduce the resistance of the constant voltage signal line, that is, reduce the resistance of the power supply line and the initial signal line.

[0094] In this exemplary embodiment, as shown in FIG13, at least a portion of the second constant voltage signal line Lh2 can be connected to at least a portion of the first constant voltage signal line Lh1 that intersects with it, and at least a portion of the second constant voltage signal line Lh2 can be connected to at least a portion of the third constant voltage signal line Lh3 that intersects with it. That is, the first constant voltage signal line Lh1, the second constant voltage signal line Lh2, and the third constant voltage signal line Lh3 can form a grid structure, which can further reduce the resistance of the constant voltage signal lines.

[0095] In this exemplary embodiment, as shown in FIG13, the data line group Daz includes a first data line Da1 and a second data line Da2 located on the same side of the pixel driving circuit group; the multiple data connection lines include a first data connection line Da1 and a second data connection line Da2, with the first data connection line Da1 connected to the first data line Da1 and the second data connection line Da2 connected to the second data line Da2; in the connected data connection line Da1 and the pixel driving circuit Pix, the orthographic projection of the first data connection line Da1 on the substrate is located between the orthographic projection of the pixel driving circuit Pix on the substrate and the orthographic projection of the second data connection line Da2 on the substrate; the first data connection... The orthographic projection of line Dal1 on the substrate and the orthographic projection of the pixel driving circuit Pix connected to it on the substrate are arranged opposite each other in the column direction Y, and the orthographic projection of the first data connection line Dal1 on the substrate and the orthographic projection of the pixel driving circuit connected to the second data connection line Dal2 on the substrate are not arranged opposite each other in the column direction; the orthographic projection of the second data connection line Dal2 on the substrate and the orthographic projection of the pixel driving circuit connected to it on the substrate are arranged opposite each other in the column direction Y, and the orthographic projection of the second data connection line Dal2 on the substrate and the orthographic projection of the pixel driving circuit connected to the first data connection line Dal1 on the substrate are arranged opposite each other in the column direction. The orthographic projections of structure A and structure B on the substrate are arranged opposite each other in the column direction. This can be understood as the areas covered by the orthographic projections of structure A and structure B extending infinitely in the column direction overlapping. Conversely, if the orthographic projections of structure A and structure B are not arranged opposite each other in the column direction, this can be understood as the areas covered by the orthographic projections of structure A and structure B extending infinitely in the column direction not overlapping. On one hand, this arrangement can reduce the length of the first data connection line Dal1, thereby reducing signal interference between the first data connection line Dal1 and the second data connection line Dal2. On the other hand, this arrangement can prevent short circuits between the first data connection line Dal1 and the second data connection line Dal2.

[0096] As shown in Figures 14 and 15, Figure 14 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, and Figure 15 is an enlarged view of a partial area AA of the display panel shown in Figure 14. The structural layout diagram of the pixel driving circuit in this display panel can be as shown in Figure 2, which only shows a portion of the structural layout diagram of the pixel driving circuit. The display panel may further include a first initial signal line Vinit1, a first initial connection line 2Vinit1, and a first initial bridging line 1Vinit1. The orthographic projections of the first initial signal line Vinit1 and the first initial connection line 2Vinit1 on the substrate extend along the row direction X. The orthographic projection of the first initial bridging line 1Vinit1 on the substrate extends along the column direction Y. The first initial bridging line 1Vinit1 connects multiple first initial connection lines Vinit1 and multiple first initial connection lines 2Vinit1 in the same pixel driving circuit group; wherein, the first initial connection line 2Vinit1 can form a second constant voltage signal line Lh2.

[0097] As shown in Figures 14 and 15, the display panel may further include a first ring power line VDDh and a second ring power line VSSh. The first ring power line VDDh and the pixel driving circuit group Pz are correspondingly arranged, and the orthographic projection of the pixel driving circuit group Pz on the substrate is located within the annular opening of the orthographic projection of the corresponding first ring power line VDDh on the substrate. The second ring power line VSSh and the pixel driving circuit group Pz are correspondingly arranged, and the orthographic projection of the first ring power line VDDh on the substrate is located within the annular opening of the orthographic projection of the second ring power line VSSh on the substrate. The first ring power line VDDh can be connected to the first power line VDD corresponding to the pixel driving circuit, and the second ring power line VSSh can be connected to the common electrode layer in the display panel. The common electrode layer can be located on the side of the light-emitting unit away from the substrate, and the common electrode layer can provide the second power terminal shown in Figure 1.

[0098] As shown in Figures 14 and 15, the first constant voltage signal line Lh1 can be connected to the first ring power line VDDh via a via. Another second constant voltage signal line Lh2 can be connected to the first constant voltage signal line Lh1. The second constant voltage signal line Lh2 can be located in the first gate layer, and it can be connected to the first constant voltage signal line Lh1 located in the second source / drain layer via the first bridge wire 3L in the first source / drain layer.

[0099] As shown in Figures 14 and 15, the display panel may further include a second initial bridging line 1Vinit2 and a reference voltage bridging line 1Vref. The orthographic projections of the second initial bridging line 1Vinit2 and the reference voltage bridging line 1Vref on the substrate extend along the column direction Y. The second initial bridging line 1Vinit2 can connect to multiple second initial signal lines Vinit2 in the same pixel driving circuit group, and the first initial bridging line 1Vinit1 can connect to multiple first initial signal lines Vinit1 in the same pixel driving circuit group. The reference voltage bridging line 1Vref can connect to multiple reference voltage lines Vref in the same pixel driving circuit group.

[0100] As shown in Figures 14 and 15, the data line Da, the first constant voltage signal line Lh1, the third constant voltage signal line Lh3, the first ring power line VDDh, and the second ring power line VSSh can be located in the second source-drain layer, and the data connection line Dal can be located in the first source-drain layer. The first initial bridge line 1Vinit1, the second initial bridge line 1Vinit2, and the reference voltage bridge line 1Vref can be located in the first gate layer.

[0101] In this exemplary embodiment, in the same pixel driving circuit subgroup Piz, the fourth bridging portion 34 located in the same row of pixel driving circuits can be connected by bridging wires.

[0102] Figure 16 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Two sets of data line groups Daz are correspondingly provided for the pixel driving circuit group Pz. The orthographic projections of the two sets of data line groups Daz on the substrate are located on both sides of the orthographic projection of their corresponding pixel driving circuit group Pz on the substrate in the row direction. The same type of data lines Da located on both sides of the pixel driving circuit group Pz are connected by data connection lines Dal. The same type of data line Da refers to data lines connected to the same pixel driving circuit subgroup. This arrangement can reduce the resistance of the data lines, thereby improving the display uniformity of the display panel.

[0103] As shown in Figures 17 and 18, Figure 17 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, and Figure 18 is an enlarged view of a partial area BB of the display panel shown in Figure 17. The structural layout diagram of the pixel driving circuit in this display panel can be as shown in Figure 2, which only shows a portion of the structural layout diagram of the pixel driving circuit. The pixel driving circuit group Pz includes multiple pixel driving circuit subgroups Piz, such as a first pixel driving circuit subgroup Piz1, a second pixel driving circuit subgroup Piz2, and a third pixel driving circuit subgroup Piz3; multiple data connection lines Dal include a first data connection line Dal1, a second data connection line Dal2, and a third data connection line Dal3; in the connected data connection line Dal and pixel driving circuit, the orthographic projection of the second data connection line Dal2 on the substrate is located on the side of the first data connection line Dal1 on the substrate away from the orthographic projection of the pixel driving circuit on the substrate, and the orthographic projection of the third data connection line Dal3 on the substrate is located on the side of the second data connection line Dal2 on the substrate away from the orthographic projection of the pixel driving circuit on the substrate; the display panel also includes a bridging wire Daq, which extends along the column direction Y, and the data connection lines Dal are connected to the pixel driving circuit through the bridging wire Daq. The bridging wire Daq and the data connection lines Dal are located on different conductive layers. This arrangement can prevent short circuits between different data connection lines Dal.

[0104] In this exemplary embodiment, as shown in Figures 17 and 18, the bridging line Daq can be located in the active layer.

[0105] It should be understood that, in other exemplary embodiments, the orthographic projection of the data line Da in the data line group Daz onto the substrate may also be located on both sides of the orthographic projection of the corresponding pixel driving circuit group Pz onto the substrate in the row direction. Figure 19 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. The pixel driving circuit group Pz includes a first pixel driving circuit subgroup Piz1, a second pixel driving circuit subgroup Piz2, and a third pixel driving circuit subgroup Piz3. The first pixel driving circuit subgroup Piz1 provides driving current to the red light-emitting unit, the second pixel driving circuit subgroup Piz2 provides driving current to the green light-emitting unit, and the third pixel driving circuit subgroup Piz3 provides driving current to the blue light-emitting unit. The data lines in the data line group Daz include a first data line Da1, a second data line Da2, and a third data line Da3. The first data line Da1 is connected to the first pixel driving circuit. The pixel driving circuit in subgroup Piz1 is connected to the pixel driving circuit in subgroup Piz2 via a second data line Da2, and to the pixel driving circuit in subgroup Piz3 via a third data line Da3. In the corresponding pixel driving circuit group and data line group, the orthographic projections of the first data line Da1 and the second data line Da2 on the substrate are located on the same side of the orthographic projection of the pixel driving circuit group Pz on the substrate in the row direction X, and the orthographic projections of the first data line Da1 and the third data line Da3 on the substrate are located on opposite sides of the orthographic projection of the pixel driving circuit group Pz on the substrate in the row direction. Since the blue light-emitting unit is more sensitive, the third data line Da3, which connects to the third pixel driving circuit, is placed separately on one side of the pixel driving circuit group Pz. This arrangement reduces interference from other data lines to the third data line Da3.

[0106] As shown in Figures 20 and 21, Figure 20 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, and Figure 21 is an enlarged view of a partial area CC of the display panel shown in Figure 20. The structural layout diagram of the pixel driving circuit in this display panel can be shown in Figure 2, which only shows a portion of the structural layout diagram of the pixel driving circuit. The difference between this display panel and the display panels shown in Figures 14 and 15 is that the third data line Da3 and the first data line Da1 are located on both sides of the pixel driving circuit group Pz in the row direction X, respectively.

[0107] As shown in Figure 3-21, the black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate. The different vias represented by the black squares at different positions can penetrate different insulating layers.

[0108] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0109] In this exemplary embodiment, the display panel can be a video wall. This exemplary embodiment also provides a display device, which includes the aforementioned display panel. The display device can be a mobile phone, tablet computer, television, or other display device.

[0110] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0111] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple pixel driving circuit groups are arrayed along the row and column directions. Each pixel driving circuit group includes multiple pixel driving circuit subgroups distributed along the row direction. Each pixel driving circuit subgroup includes one or more rows of pixel driving circuits. Each row of pixel driving circuits includes multiple pixel driving circuits distributed along the row direction. The output terminals of multiple pixel driving circuits in the same pixel driving circuit subgroup are connected in parallel. A data line group is provided corresponding to the pixel driving circuit group. The data line group includes multiple data lines. The orthographic projection of the data lines on the substrate extends along the column direction. The orthographic projection of the data lines in the data line group on the substrate is located on one or both sides of the orthographic projection of the corresponding pixel driving circuit group on the substrate in the row direction. Multiple data connection lines extend along the row direction in the orthographic projection on the substrate. The data lines and the pixel driving circuit subgroups are correspondingly arranged. The data lines are connected to the pixel driving circuits located in the same row in their corresponding pixel driving circuit subgroups through the data connection lines.

2. The display panel of claim 1, wherein, The display panel also includes multiple constant voltage signal lines, among which at least one first constant voltage signal line is included. The orthographic projection of the first constant voltage signal line on the substrate extends along the column direction, and the orthographic projection of the first constant voltage signal line on the substrate is located between the orthographic projections of two adjacent data lines on the substrate.

3. The display panel of claim 1, wherein, The display panel also includes multiple constant voltage signal lines, among which at least one second constant voltage signal line is included. The orthographic projection of the second constant voltage signal line on the substrate extends along the row direction, and the orthographic projection of the second constant voltage signal line on the substrate is located between the orthographic projections of two adjacent data connection lines on the substrate.

4. The display panel of claim 2 or 3, wherein, The constant voltage signal line is used to provide a power signal or an initial signal to the pixel driving circuit.

5. The display panel according to claim 3, wherein, The plurality of constant voltage signal lines includes at least one first constant voltage signal line; The orthogonal projection of the first constant voltage signal line on the substrate extends along the column direction, and the orthogonal projection of the first constant voltage signal line on the substrate is located between the orthogonal projections of the adjacent data lines on the substrate. At least a portion of the second constant voltage signal line is connected to at least a portion of the first constant voltage signal line that intersects with it.

6. The display panel according to claim 3, wherein, The display panel also includes: A bridging wire extends along the column direction, and the data connection line is connected to the pixel driving circuit through the bridging wire; The orthographic projection of the second constant voltage signal line on the substrate and the orthographic projection of the bridging line on the substrate intersect, and the portion of the second constant voltage signal line intersecting with the bridging line is located in a different conductive layer from the bridging line.

7. The display panel according to claim 3, wherein, The display panel also includes: A first initial signal line extends along the row direction in the orthogonal projection on the substrate, and the first initial signal line is used to provide a first initial signal to the pixel driving circuit. The first initial connection line extends along the row direction in its orthogonal projection onto the substrate. The first initial bridging line extends along the column direction in the orthographic projection on the substrate, and the first initial bridging line connects the first initial connection line and the first initial connection line in the same pixel driving circuit group. The first initial connection line forms a second constant voltage signal line.

8. The display panel according to claim 1, wherein, The data line group includes a first data line and a second data line located on the same side of the pixel driving circuit group; The plurality of data connection lines include a first data connection line and a second data connection line, wherein the first data connection line is connected to the first data line and the second data connection line is connected to the second data line; In the connected data connection line and pixel driving circuit, the orthographic projection of the first data connection line on the substrate is located between the orthographic projection of the pixel driving circuit on the substrate and the orthographic projection of the second data connection line on the substrate. The orthographic projection of the first data connection line on the substrate and the orthographic projection of the pixel driving circuit connected thereto on the substrate are arranged opposite each other in the column direction, and the orthographic projection of the first data connection line on the substrate and the orthographic projection of the pixel driving circuit connected to the second data connection line on the substrate are not arranged opposite each other in the column direction. The orthographic projection of the second data connection line on the substrate and the orthographic projection of the pixel driving circuit connected thereto on the substrate are arranged opposite each other in the column direction, and the orthographic projection of the second data connection line on the substrate and the orthographic projection of the pixel driving circuit connected to the first data connection line on the substrate are arranged opposite each other in the column direction.

9. The display panel according to claim 1, wherein, The display panel also includes: The first source / drain layer is located on one side of the substrate, and the data connection line is located in the first source / drain layer; The second source / drain layer is located on the side of the first source / drain layer away from the substrate, and the data line is located in the second source / drain layer.

10. The display panel according to claim 1, wherein, The pixel driving circuit group includes a first pixel driving circuit subgroup, a second pixel driving circuit subgroup, and a third pixel driving circuit subgroup. The first pixel driving circuit subgroup is used to provide driving current to the red light-emitting unit, the second pixel driving circuit subgroup is used to provide driving current to the green light-emitting unit, and the third pixel driving circuit subgroup is used to provide driving current to the blue light-emitting unit. The data line group includes a first data line, a second data line, and a third data line. The first data line is connected to the pixel driving circuit in the first pixel driving circuit subgroup, the second data line is connected to the pixel driving circuit in the second pixel driving circuit subgroup, and the third data line is connected to the pixel driving circuit in the third pixel driving circuit subgroup. In the corresponding pixel driving circuit group and the data line group, the orthographic projection of the first data line and the second data line on the substrate is located on the same side of the orthographic projection of the pixel driving circuit group on the substrate in the row direction, and the orthographic projection of the first data line and the third data line on the substrate is located on opposite sides of the orthographic projection of the pixel driving circuit group on the substrate in the row direction.

11. The display panel according to claim 1, wherein, The pixel driving circuit group is provided with two sets of data line groups, and the orthographic projections of the two sets of data line groups on the substrate are respectively located on both sides of the orthographic projection of the corresponding pixel driving circuit group on the substrate in the row direction. The same type of data lines located on both sides of the pixel driving circuit group are connected through the data connection line.

12. The display panel according to claim 11, wherein, The pixel driving circuit group includes a first pixel driving circuit subgroup, a second pixel driving circuit subgroup, and a third pixel driving circuit subgroup. The plurality of data connection lines include a first data connection line, a second data connection line, and a third data connection line; In the connected data connection line and the pixel driving circuit, the orthographic projection of the second data connection line on the substrate is located on the side where the orthographic projection of the first data connection line on the substrate is far away from the orthographic projection of the pixel driving circuit on the substrate, and the orthographic projection of the third data connection line on the substrate is located on the side where the orthographic projection of the second data connection line on the substrate is far away from the orthographic projection of the pixel driving circuit on the substrate. The display panel also includes: A bridging wire extends along the column direction, and the data connection line is connected to the pixel driving circuit through the bridging wire. The bridging wire and the data connection line are located on different conductive layers.

13. The display panel according to claim 1, wherein, The display panel also includes: The first ring power line is correspondingly arranged with the pixel driving circuit group, and the orthographic projection of the pixel driving circuit group on the substrate is located in the annular opening of the orthographic projection of the first ring power line on the substrate. The second ring power line is correspondingly arranged with the pixel driving circuit group, and the orthographic projection of the first ring power line on the substrate is located within the annular opening of the orthographic projection of the second ring power line on the substrate. The first ring power line and the second ring power line respectively provide power signals of opposite polarity to the pixel driving circuit.

14. The display panel according to claim 2, wherein, The plurality of constant voltage signal lines include at least one third constant voltage signal line, wherein the orthographic projection of the third constant voltage signal line on the substrate extends along the column direction, and the orthographic projection of the third constant voltage signal line on the substrate and the orthographic projection of the first constant voltage signal line on the substrate are located on opposite sides of the orthographic projection of the pixel driving circuit group on the substrate, and the third constant voltage signal line and the first constant voltage signal line are connected.

15. A display device, wherein, The display device includes the display panel as described in any one of claims 1-14.

Images