Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises a plurality of subpixels arranged in an array, and a plurality of scan control lines, data signal lines, and initial signal lines. Each subpixel comprises a pixel circuit and a light-emitting device electrically connected to the pixel circuit. Each scan control line is electrically connected to at least one row of pixel circuits. The scan control lines include first scan signal lines and first reset control lines. The array substrate further comprises a first GOA circuit and a second GOA circuit. The first GOA circuit comprises a plurality of first GOA units connected in cascade, and each first GOA unit provides a first scan signal to a coupling sub-circuit in one row of pixel circuits. The second GOA circuit comprises a plurality of second GOA units connected in cascade. The second GOA units are arranged on one side of a display area and perform single-side driving on the first reset control lines, or each second GOA unit provides a first reset control signal to coupling sub-circuits in two or more rows of pixel circuits.

Description

Array substrate, display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 2025100968947, filed on January 21, 2025, entitled "Array Substrate, Display Panel and Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0003] For Active-Matrix Organic Light-Emitting Diode (AMOLED) displays, each pixel requires multiple driving signals. To generate these sequentially turning-on / off driving signals, Gate Driver on Array (GOA) circuits are needed on both sides of the Active Area (AA) to enable line-by-line scanning of the display panel. Generally, pixel circuits cannot be placed in the area where the GOA circuits are located, thus creating a bezel area around the display device that cannot emit light. To ensure image quality in the AA area, the number of different driving signals required in the pixel structure is increasing, and the number of GOA circuits required to exist simultaneously is also increasing, which contradicts the design concept of narrowing the bezel. However, if some important driving signals are forced to drive only one side in order to narrow the bezel, it will also affect the screen image quality. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides an array substrate including multiple sub-pixels arranged in an array and multiple scan control lines, data signal lines, and initial signal lines. Each sub-pixel includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit. Each scan control line is electrically connected to at least one row of pixel circuits. The scan control line includes a first scan signal line and a first reset control line. The array substrate further includes a GOA circuit group that drives the pixel circuits row by row. The GOA circuit group includes a first GOA circuit and a second GOA circuit, wherein:

[0006] The pixel circuit includes a first node, a second node, a third node, a driving sub-circuit, and a coupling sub-circuit. The driving sub-circuit is electrically connected to the first node, the second node, and the third node, and is configured to provide a driving signal to the third node under the control of the signals from the first node and the second node. The coupling sub-circuit is connected to a first scan signal line, a first reset control line, a data signal line, a first initial signal line, and the third node, and is configured to couple the signal from the first initial signal line to the third node under the control of a first reset control signal provided by the first reset control line, and to couple the signal from the data signal line to the third node under the control of a first scan signal provided by the first scan signal line.

[0007] The first GOA circuit includes a plurality of cascaded first GOA units, each of which is connected to a first scan signal line and is configured to provide a first scan signal to a coupling sub-circuit in a row pixel circuit;

[0008] The second GOA circuit includes a plurality of cascaded second GOA units, which are disposed on one side of the display area and drive the first reset control line on one side. Alternatively, each second GOA unit is connected to two or more first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuit in two or more rows of pixel circuits.

[0009] This disclosure also provides a display panel, including an array substrate as described in any embodiment of this disclosure.

[0010] This disclosure also provides a display device, including a display panel as described in any embodiment of this disclosure.

[0011] The array substrate, display panel, and display device of the present disclosure can achieve a narrow bezel effect without affecting the screen image quality by driving a portion of the GOA circuit in a single-sided manner or in a one-to-many manner.

[0012] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood.

[0013] Overview of the attached figures

[0014] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0015] Figure 1 is a schematic diagram of a display device;

[0016] Figure 2 is a schematic diagram of the structure of a display substrate;

[0017] Figure 3 is a schematic diagram of the planar structure of the display area in a display substrate;

[0018] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0019] Figure 5 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure;

[0020] Figure 6 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

[0021] Figure 7 is a driving timing diagram of the pixel circuit provided in Figure 6;

[0022] Figure 8A is a schematic diagram showing the effect of the first reset control signal provided by the first reset control line in Figure 6 on the drive current under different delay times.

[0023] Figure 8B is a schematic diagram showing the effect of the second reset control signal provided by the second reset control line in Figure 6 on the drive current under different delay times.

[0024] Figure 8C is a schematic diagram showing the effect of the third reset control signal provided by the third reset control line in Figure 6 on the drive current under different delay times.

[0025] Figure 8D is a schematic diagram showing the effect of the first light-emitting control signal provided by the first light-emitting control line in Figure 6 on the driving current under different delay times.

[0026] Figure 8E is a schematic diagram showing the effect of the second light emission control signal provided by the second light emission control line in Figure 6 on the driving current under different delay times;

[0027] Figure 8F is a schematic diagram showing the effect of the first scan signal provided by the first scan signal line in Figure 6 on the drive current under different delay times;

[0028] Figure 9 shows the simulation waveform results of the pixel circuit shown in Figure 6 when the six groups of GOA circuits connected to each scan control line are driven by a one-drive-two-scheme.

[0029] Figures 10 to 23 are schematic diagrams of several driving methods of GOA circuits according to exemplary embodiments of the present disclosure;

[0030] Figure 24 is a timing diagram of the signals of each scan control line when the pixel circuit provided in Figure 6 is driven by any of the driving methods shown in Figures 18 to 22.

[0031] Detailed Explanation

[0032] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0033] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0034] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0035] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0036] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0037] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0038] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0039] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0040] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0041] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0042] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0043] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0044] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The timing controller is connected to the data signal driver, the scan signal driver, and the light emission signal driver. The data signal driver is connected to multiple data signal lines (D1 to Dn), the scan signal driver is connected to multiple scan signal lines (S1 to Sm), and the light emission signal driver is connected to multiple light emission control lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission unit. The circuit unit may include at least a pixel circuit. The pixel circuit is connected to the scan signal lines, the light emission control lines, and the data signal lines. The light emission unit may include a light-emitting device, which is connected to the pixel circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data signal driver to the data signal driver, clock signals, scan start signals, etc. suitable for the specifications of the scan signal driver to the scan signal driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light emission signal driver to the light emission signal driver. The data signal driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver can sample the grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driver can generate transmit signals to be provided to the light-emitting control lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting signal driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting control lines E1 to Eo. For example, the light-emitting signal driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0045] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array. The plurality of sub-pixels are configured to display dynamic or still images, and the display area 100 may be referred to as the effective display (AA) area. In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0046] In an exemplary embodiment, the bonding region 200 may include a fan-out region, a bending region, a driver chip region, and a bonding pin region sequentially arranged along a direction away from the display region 100. The fan-out region is connected to the display region 100 and may include at least multiple data leads. The bending region is connected to the fan-out region and may include a composite insulating layer with grooves configured to bend the bonding region to the back of the display region. The driver chip region may include at least an integrated circuit (IC) configured to connect to the multiple data leads. The bonding pin region may include at least multiple bonding pads configured to bond to an external flexible printed circuit (FPC).

[0047] In an exemplary embodiment, the border region 300 may include at least a circuit region connected to the display region 100, and may include at least a gate driving circuit electrically connected to the pixel circuit in the display region 100.

[0048] In an exemplary embodiment, at least one isolation dam may be provided in the binding area 200 and the border area 300. The isolation dam may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the display area close to the binding area or the border area.

[0049] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel circuit. The pixel circuit is connected to a scan signal line, a light-emitting control line, a data signal line, and a high-potential power supply line, respectively. The pixel circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting control line. The light-emitting unit in each sub-pixel is connected to the pixel circuit of its respective sub-pixel. The light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the pixel circuit of its respective sub-pixel.

[0050] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. In some exemplary embodiments, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in any other arbitrary manner; this disclosure does not limit the specific arrangement.

[0051] In an exemplary embodiment, a pixel unit may include four sub-pixels. The four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement, or they may be arranged horizontally, vertically, or in any other arbitrary manner. This disclosure does not limit the scope of the invention.

[0052] Figure 4 is a cross-sectional view of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 4, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0053] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include multiple circuit units, each of which can include at least a pixel circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel circuit, and the organic light-emitting layer is connected to both the anode and the cathode. The organic light-emitting layer emits light of the corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0054] Figure 5 is a schematic diagram of a pixel circuit provided in an embodiment of this disclosure. As shown in Figure 5, the pixel circuit provided in this embodiment may include: a driving sub-circuit 1021 and a coupling sub-circuit 1022.

[0055] The driving sub-circuit 1021 is electrically connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide a driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2.

[0056] The coupling sub-circuit 1022 is electrically connected to the scan signal line Gate1, the first reset control line Reset1, the data signal line DL, the first initial signal line INIT1, and the third node N3, respectively. It is configured to couple the signal of the first initial signal line INIT1 to the third node N3 under the control of the first reset control signal provided by the first reset control line Reset1, and to couple the signal of the data signal line DL to the third node N3 under the control of the first scan signal provided by the first scan signal line Gate1.

[0057] In an exemplary embodiment, the coupling sub-circuit 1022 may include a data writing sub-circuit, a first reset sub-circuit, and a first coupling sub-circuit (not shown in the figure). The data writing sub-circuit is configured to write the signal of the data signal line DL to the fifth node (not shown in the figure) under the control of the first scan signal provided by the first scan signal line Gate1. The first reset sub-circuit is configured to write the signal of the first initial signal line INIT1 to the fifth node under the control of the first reset control signal provided by the first reset control line Reset1. The first coupling sub-circuit is configured to couple the signal of the fifth node to the third node N3.

[0058] In an exemplary embodiment, as shown in FIG5, the pixel circuit may further include: a second reset sub-circuit 1023, wherein the second reset sub-circuit 1023 is electrically connected to the second reset control line Reset2, the second initial signal line INIT2 and the first node N1 respectively, and is configured to provide the signal of the second initial signal line INIT2 to the first node N1 under the control of the second reset control signal provided by the second reset control line Reset2, that is, to reset the first node N1 using the signal of the second initial signal line INIT2.

[0059] In an exemplary embodiment, as shown in FIG5, the pixel circuit may further include a third reset sub-circuit 1024, wherein the third reset sub-circuit 1024 is electrically connected to the third reset control line Reset3, the third initial signal line INIT3 and the fourth node N4 (i.e., the anode of the light-emitting device), and is configured to provide the signal of the third initial signal line INIT3 to the fourth node N4 under the control of the third reset control signal provided by the third reset control line Reset3, that is, to reset the fourth node N4 using the signal of the third initial signal line INIT3.

[0060] In an exemplary embodiment, as shown in FIG5, the pixel circuit may further include: a holding sub-circuit 1025, wherein the holding sub-circuit 1025 is electrically connected to the first node N1 and the third node N3 respectively, and is configured to store the voltage difference of the signal between the first node N1 and the third node N3.

[0061] In an exemplary embodiment, as shown in FIG5, the pixel circuit may further include: a first light emission control sub-circuit 1026, wherein the first light emission control sub-circuit 1026 is electrically connected to the second node N2, the first light emission control line EM1 and the first power line VDD respectively, and is configured to provide the signal of the first power line VDD to the second node N2 under the control of the signal of the first light emission control line EM1.

[0062] In an exemplary embodiment, as shown in FIG5, the pixel circuit may further include: a second light-emitting control sub-circuit 1027, wherein the second light-emitting control sub-circuit 1027 is electrically connected to the third node N3, the fourth node N4 and the second light-emitting control line EM2 respectively, and is configured to conduct the third node N3 and the fourth node N4 under the control of the signal of the second light-emitting control line EM2, that is, to conduct the third node N3 and the anode of the light-emitting device.

[0063] In an exemplary embodiment, the first power line VDD can continuously provide a high-level signal, and the signal of the first power line VDD is a DC signal.

[0064] In this embodiment, the second reset sub-circuit 1023 connected to the first node is only electrically connected to the second initial signal line INIT2 and the second reset control line Reset2. This means that the number of transistors connected to the first node N1 is relatively small. Furthermore, the coupling sub-circuit 1022 can couple the data signal of the data signal line to the third node N3 connected to the driving sub-circuit 1021, reducing the number of transistors directly coupled to the first node N1 connected to the driving sub-circuit 1021. It also enables normal data writing and threshold compensation. Therefore, the pixel circuit provided in this embodiment can reduce the parasitic capacitance coupled to the first node N1 while ensuring normal display. This makes it less likely for the voltage of the driving signal maintained between the gate electrode and the source electrode of the driving sub-circuit 1021 to deviate, ensuring the consistency of the display brightness of the display product and improving the display effect of the display substrate.

[0065] In an exemplary embodiment, the pixel circuit is configured to drive the light-emitting device L to emit light.

[0066] In an exemplary embodiment, the light-emitting device may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together. Exemplarily, the anode of the light-emitting device is electrically connected to the pixel circuit, and the cathode of the light-emitting device is electrically connected to the second power supply terminal VSS.

[0067] In an exemplary embodiment, the second power supply terminal VSS can continuously provide a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0068] In exemplary embodiments, the light-emitting device may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED). Typical dimensions (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. Typical dimensions (e.g., length) of a Mini LED can be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0069] In an exemplary embodiment, the organic light-emitting layer may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the hole block layers of all sub-pixels may be a common layer connected together, and the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated. Similarly, the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0070] Figure 6 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 6, the driving sub-circuit 1021 includes a driving transistor T3. In some exemplary embodiments, the driving transistor T3 can be a single-gate transistor. The control electrode of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3.

[0071] In other exemplary embodiments, the driving transistor T3 can be a dual-gate transistor, and the driving transistor T3 includes a first control electrode and a second control electrode. The first control electrode of the driving transistor T3 can be electrically connected to a first node N1, and the second control electrode of the driving transistor T3 can be electrically connected to a third node N3 (not shown in the figure). The connection method of the driving transistor in this disclosure can improve the output saturation characteristics of the driving transistor T3.

[0072] In an exemplary embodiment, as shown in FIG6, the coupling sub-circuit 1022 may include: a first reset transistor T7, a data writing transistor T4, and a second capacitor C2. The control electrode of the first reset transistor T7 is electrically connected to the first reset control line Reset1, the first electrode of the first reset transistor T7 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T7 is electrically connected to the fifth node N5. The control electrode of the data writing transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the data writing transistor T4 is electrically connected to the data signal line DL, and the second electrode of the data writing transistor T4 is electrically connected to the fifth node N5. The first terminal of the second capacitor C2 is electrically connected to the fifth node N5, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0073] In an exemplary embodiment, the first initial signal line INIT1 can receive a first initial signal. The first reset transistor T7, under the control of the first reset control signal on the first reset control line Reset1, writes the first initial signal into the fifth node N5.

[0074] In an exemplary embodiment, the data signal line DL can receive data signals. Under the control of the first scan signal on the first scan signal line Gate1, the data writing transistor T4 writes the data signal to the fifth node N5.

[0075] In an exemplary embodiment, as shown in FIG6, the second reset sub-circuit 1023 may include a second reset transistor T1. The control terminal of the second reset transistor T1 is electrically connected to the second reset control line Reset2, the first terminal of the second reset transistor T1 is electrically connected to the second initial signal line INIT2, and the second terminal of the second reset transistor T1 is electrically connected to the first node N1.

[0076] In an exemplary embodiment, the second initial signal line INIT2 can receive a second initial signal. Under the control of the second reset control signal on the second reset control line Reset2, the second reset transistor T1 writes the second initial signal into the first node N1, that is, resets the first node N1.

[0077] In an exemplary embodiment, as shown in FIG6, the third reset sub-circuit 1024 may include a third reset transistor T2. The control electrode of the third reset transistor T2 is electrically connected to the third reset control line Reset3, the first electrode of the third reset transistor T2 is electrically connected to the third initial signal line INIT3, and the second electrode of the third reset transistor T2 is electrically connected to the fourth node N4.

[0078] In an exemplary embodiment, the third initial signal line INIT3 can receive a third initial signal. Under the control of the third reset control signal on the third reset control line Reset3, the third reset transistor T2 writes the third initial signal into the fourth node N4, i.e., resets the fourth node N4. In other exemplary embodiments, the third reset transistor T2 can also write the third initial signal into the third node N3 under the control of the third reset control signal on the third reset control line Reset3, i.e., reset the third node N3. That is, under the control of the signal on the third reset control line Reset3, the third reset transistor T2 writes the third initial signal into either the third node N3 or the fourth node N4, initializing either the third node N3 or the fourth node N4. Exemplarily, the third reset transistor T2 can be turned on once or multiple times in a display frame; this disclosure does not limit this. When the second terminal of the third reset transistor T2 is electrically connected to the third node N3, the conduction of the third reset transistor T2 can initialize the second terminal of the driving transistor T3 or bias the driving transistor T3. When the second terminal of the third reset transistor T2 is electrically connected to the fourth node N4, the third reset transistor T2 is turned on to initialize the anode of the light-emitting device.

[0079] In an exemplary embodiment, as shown in FIG6, the holding sub-circuit 1025 includes a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to a first node N1, and the second terminal of the first capacitor C1 is electrically connected to a third node N3.

[0080] In an exemplary embodiment, the first capacitor C1 can ensure the stability of the signal of the first node N1 and improve the reliability of the pixel circuit.

[0081] In an exemplary embodiment, as shown in FIG6, the first light-emitting control sub-circuit 1026 may include a first light-emitting control transistor T5. The control electrode of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control line EM1, the first electrode of the first light-emitting control transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the second node N2.

[0082] In an exemplary embodiment, as shown in FIG6, the second light-emitting control sub-circuit 1027 may include a second light-emitting control transistor T6. The control electrode of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control line EM2, the first electrode of the second light-emitting control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4.

[0083] In an exemplary embodiment, the signals received by the second initial signal line INIT2 and the first power line VDD, which are connected to the same pixel circuit, can be the same signal.

[0084] In an exemplary embodiment, the second initial signal received by the second initial signal line INIT2 is a positive voltage signal to ensure that the driving transistor T3 can be turned on normally, thereby improving the reliability of the pixel circuit.

[0085] In an exemplary embodiment, the signals received by the first initial signal line INIT1 and the second initial signal line INIT2, which are connected to the same pixel circuit, can be the same signal.

[0086] In an exemplary embodiment, the voltage value of the third initial signal received by the third initial signal line INIT3 is less than the sum of the voltage value of the signal of the second power line VSS and the voltage value between the two electrodes of the light-emitting device, so as to ensure that the light-emitting device does not emit light when the anode of the light-emitting device L is initialized.

[0087] In an exemplary embodiment, the voltage value of the second initial signal received by the second initial signal line INIT2 may be equal to the voltage value of the first initial signal received by the first initial signal line INIT1, and the voltage value of the second initial signal received by the second initial signal line INIT2 may be greater than the voltage value of the third initial signal received by the third initial signal line INIT3.

[0088] In an exemplary embodiment, the signals received by the first reset control line Reset1 connected to the same pixel circuit and the first light emission control line EM1 can be the same signal; or, the signals received by the first reset control line Reset1 connected to the i-th row pixel circuit and the second reset control line Reset2 connected to the (i-1)-th row pixel circuit can be the same signal.

[0089] In an exemplary embodiment, having at least two signal terminals connected to the pixel circuit receive the same signal can reduce the number of signal lines connected to the pixel circuit, thereby achieving a high PPI for the display device.

[0090] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0091] In an exemplary embodiment, the N-type transistor can be an oxide thin-film transistor. The active pattern of the oxide thin-film transistor uses oxide semiconductor. Oxide thin-film transistors have advantages such as low leakage current, which can reduce power consumption and improve display quality.

[0092] In an exemplary embodiment, either the first capacitor C1 or the second capacitor C2 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, either the first capacitor C1 or the second capacitor C2 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of either the first capacitor C1 or the second capacitor C2 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0093] In an exemplary embodiment, at least one of the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 in FIG6 is an N-type transistor. Exemplarily, the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 can all be N-type transistors, or the second reset transistor T1, the third reset transistor T2, the driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T6, and the first reset transistor T7 can be N-type transistors, while the first light-emitting control transistor T5 can be a P-type transistor. This disclosure does not impose any limitations on this.

[0094] Figure 7 is a driving timing diagram of the pixel circuit provided in Figure 6. Figure 7 illustrates this using the example where the first light-emitting control transistor T5 in Figure 6 is a P-type transistor and all other transistors are N-type transistors. Figure 7 also illustrates this using the example where the first reset control line Reset1 connected to the i-th row of pixel circuits and the second reset control line Reset2 connected to the (i-1)-th row of pixel circuits receive the same signal. As shown in Figure 7, the operation of the pixel circuit provided in Figure 6 can include:

[0095] In the first stage (H1), the initialization stage, the signals of the first light-emitting control line EM1, the first reset control line Reset1, the second reset control line Reset2, and the third reset control line Reset3 are high-level signals, while the signals of the second light-emitting control line EM2 and the first scan signal line Gate1 are low-level signals. The first reset transistor T7, the second reset transistor T1, and the third reset transistor T2 are turned on, while the data writing transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are turned off.

[0096] The first reset transistor T7 is turned on, and the signal of the first initial signal line INIT1 is written to the fifth node N5. The voltage value of the signal at the fifth node N5 is VN5 = Vinit1, where Vinit1 is the voltage value of the signal on the first initial signal line INIT1. The second reset transistor T1 is turned on, and the signal of the second initial signal line INIT2 is written to the first node N1. The voltage value of the signal at the first node N1 is VN1 = Vinit2, where Vinit2 is the voltage value of the signal on the second initial signal line INIT2. The third reset transistor T2 is turned on, and the signal of the third initial signal line INIT3 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is VN4 = Vinit3, where Vinit3 is the voltage value of the signal on the third initial signal line INIT3.

[0097] In the second stage, H2, the threshold compensation stage, the signals of the first reset control line Reset1, the second reset control line Reset2, and the third reset control line Reset3 are high-level signals, while the first light-emitting control line EM1, the second light-emitting control line EM2, and the first scan signal line Gate1 are low-level signals. The first reset transistor T7, the second reset transistor T1, the third reset transistor T2, and the first light-emitting control transistor T5 are turned on, while the data writing transistor T4 and the second light-emitting control transistor T6 are turned off.

[0098] The first reset transistor T7 is turned on, and the signal of the first initial signal line INIT1 is written to the fifth node N5, with the voltage value VN5 = Vinit1. The second reset transistor T1 is turned on, and the signal of the second initial signal line INIT2 is written to the first node N1, with the voltage value VN1 = Vinit2. The third reset transistor T2 is turned on, and the signal of the third initial signal line INIT3 is written to the fourth node N4, with the voltage value VN4 = Vinit3. The first light-emitting control transistor T5 is turned on, and the first power line VDD charges the third node N3 through the turned-on first light-emitting control transistor T5, the second node N2, and the turned-on driving transistor T3 until the voltage value VN3 of the third node N3 is VN3 = Vinit2 - Vth, where Vth is the threshold voltage of the driving transistor T3. At this time, the voltage value stored in the first capacitor C1 is Vth, and the voltage value stored in the second capacitor C2 is Vinit1 - Vinit2 + Vth.

[0099] In the third stage (H3), the data writing stage, the signals of the first light-emitting control line EM1, the second reset control line Reset2, the third reset control line Reset3, and the first scan signal line Gate1 are high-level signals, while the signals of the second light-emitting control line EM2 and the first reset control line Reset1 are low-level signals. The second reset transistor T1, the third reset transistor T2, and the data writing transistor T4 are turned on, while the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the first reset transistor T7 are turned off.

[0100] The second reset transistor T1 is turned on, and the signal of the second initial signal line INIT2 is written to the first node N1. The voltage value of the signal at the first node N1 is VN1 = Vinit2. The third reset transistor T2 is turned on, and the signal of the third initial signal line INIT3 is written to the fourth node N4. The voltage value of the signal at the fourth node N4 is VN4 = Vinit3. The data write transistor T4 is turned on, and the signal of the data signal line DL is written to the fifth node N5. The voltage value of the signal at the fifth node N5 is VN5 = Vdata. The voltage value of the signal at the fifth node N5 jumps from Vinit1 in the previous stage to Vdata. Under the coupling effect of the second capacitor C2, the voltage value of the signal at the third node N3, VN3, also jumps. VN3 = Vinit2 - Vth + (Vdata - Vinit1)(C2 / C1 + C2), where C1 is the capacitance value of the first capacitor C1 and C2 is the capacitance value of the second capacitor C2.

[0101] In the fourth stage (H4), the light-emitting stage, the signal of the second light-emitting control line EM2 is a high-level signal, while the signals of the first light-emitting control line EM1, the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, and the first scan signal line Gate1 are all low-level signals. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, while the first reset transistor T7, the second reset transistor T1, the third reset transistor T2, and the data write transistor T4 are turned off.

[0102] The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, so that the first power supply voltage output from the first power supply line VDD provides driving current to the first electrode of the light-emitting device EL through the turned-on first light-emitting control transistor T5, the turned-on drive transistor T3 and the turned-on second light-emitting control transistor T6, so as to drive the light-emitting device EL to emit light.

[0103] During pixel circuit driving, the driving current flowing through the driving transistor T3 of each pixel circuit is determined by the voltage difference between its gate electrode and its second electrode. The voltage value of the signal at the third node N3 is VN3 = Vss + VOLED, while the signal at the first node N1 undergoes a jump under the coupling effect of the first capacitor C1. The voltage value of the signal at the first node N1 is VN1 = Vinit2 + Vss + VOLED. OLED -[Vinit2-Vth+(Vdata-Vinit1)(C2 / C1+C2)]=Vss+V OLED +Vth-(Vdata-Vinit1)(C2 / C1+C2).

[0104] At this time, the driving current I flowing through the driving transistor T3 (which is also the driving current driving the light-emitting device EL) satisfies: I = K*(Vgs - Vth) 2 =K*(V1-V3-Vth) 2 =K*[(Vinit1-Vdata)(C2 / C1+C2)] 2

[0105] Where K is a constant related to the process and design, and Vgs is the voltage difference between the gate electrode and the second electrode of the driving transistor T3.

[0106] In the above formula, the driving current I is independent of the first power supply voltage Vdd and the threshold voltage Vth, thereby eliminating the influence of the voltage drop of the first power supply line VDD and the drift of the threshold voltage Vth of the driving transistor T3 on the driving signal, thus ensuring uniform display brightness and improving the display effect.

[0107] In this embodiment, the signal of the third initial voltage line INIT3 is provided to the fourth node N4 through the conducting third reset transistor T2, so that the fourth node N4 is reset to the third initial voltage Vinit3. On the one hand, the leakage current of the second light-emitting control transistor T6 is released from the third reset transistor T2, preventing the leakage current of the second light-emitting control transistor T6 from turning on the light-emitting device prematurely; on the other hand, the signal noise generated by the transition of the second light-emitting control signal EM2 can be filtered through the third reset transistor T2, preventing the signal noise from damaging the light-emitting device.

[0108] This disclosure provides an array substrate including multiple sub-pixels arranged in an array, and multiple scan control lines, data signal lines, and initial signal lines. Each sub-pixel includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit. Each scan control line is electrically connected to at least one row of pixel circuits. The scan control lines include a first scan signal line Gate1 and a first reset control line Reset1. The array substrate also includes a GOA circuit group for driving pixel circuits row by row. The GOA circuit group includes a first GOA circuit and a second GOA circuit, wherein:

[0109] The first GOA circuit includes a plurality of cascaded first GOA units, each first GOA unit being connected to a first scan signal line Gate1 and configured to provide a first scan signal to the coupling sub-circuit 1022 in a row pixel circuit;

[0110] The second GOA circuit includes multiple cascaded second GOA units. Each second GOA unit is connected to at least one first reset control line Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in at least one row of pixel circuits. The second GOA units are located on one side of the display area and drive the first reset control line Reset1 on one side. Alternatively, each second GOA unit is connected to two or more first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two or more rows of pixel circuits.

[0111] The array substrate of this disclosure can achieve the desired pixel display effect and narrow bezel by driving the GOA circuit connected to some scan control lines in a single-sided manner or in a one-to-many manner.

[0112] For example, each second GOA unit is connected to two or three first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the two or three rows of pixel circuits.

[0113] In some exemplary embodiments, the GOA circuit group further includes: a third GOA circuit, the third GOA circuit including a plurality of cascaded third GOA units, each third GOA unit being connected to at least one second reset control line Reset2 and configured to provide a second reset control signal to a second reset sub-circuit 1023 in at least one row of pixel circuits;

[0114] The third GOA unit is located on the left and right sides of the display area, and drives the second reset control line Reset2 on both sides.

[0115] For example, each third GOA unit is connected to two or three second reset control lines Reset2 and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the two or three rows of pixel circuits.

[0116] In some exemplary embodiments, the GOA circuit group further includes: a fourth GOA circuit, which includes a plurality of cascaded fourth GOA units, each fourth GOA unit being connected to at least one third reset control line Reset3 and configured to provide a third reset control signal to a third reset sub-circuit 1024 in at least one row of pixel circuits;

[0117] The fourth GOA unit is located on one side of the display area and drives the third reset control line Reset3 on one side. Alternatively, each fourth GOA unit is connected to two or more third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in two or more pixel circuits.

[0118] For example, each fourth GOA unit is connected to two or three third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the two or three rows of pixel circuits.

[0119] In some exemplary embodiments, the GOA circuit group further includes: a fifth GOA circuit, which includes a plurality of cascaded fifth GOA units, each fifth GOA unit being connected to at least one first light emission control line EM1 and configured to provide a first light emission control signal to a first light emission control sub-circuit 1026 in at least one row of pixel circuits;

[0120] The fifth GOA unit is located on one side of the display area and drives the first light emission control line EM1 on one side. Alternatively, each fifth GOA unit is connected to two or more first light emission control lines EM1 and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in two or more pixel circuits.

[0121] For example, each fifth GOA unit is connected to two or three first light emission control lines EM1 and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the two or three rows of pixel circuits.

[0122] In some exemplary embodiments, the GOA circuit group further includes: a sixth GOA circuit, the sixth GOA circuit including a plurality of cascaded sixth GOA units, each sixth GOA unit being connected to at least one second light emission control line EM2 and configured to provide a second light emission control signal to a second light emission control sub-circuit in at least one row of pixel circuits;

[0123] The sixth GOA unit is located on one side of the display area and drives the second light emission control line EM2 on one side. Alternatively, each sixth GOA unit is connected to two or more second light emission control lines EM2 and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in two or more rows of pixel circuits.

[0124] For example, each sixth GOA unit is connected to two or three second light emission control lines EM2 and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the two or three rows of pixel circuits.

[0125] Figures 8A to 8F are schematic diagrams illustrating the influence of the signals provided by the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first light emission control line EM1, the second light emission control line EM2, and the first scan signal line Gate1 in Figure 6 on the drive current under different delay times. Here, Tr represents the rising edge delay and Tf represents the falling edge delay. When the GOA circuit connected to a certain scan control line adopts a single-sided driving scheme, the difference between the rising edge delay and the falling edge delay corresponding to the input end and the far end of the scan control line is greater. When the GOA circuit connected to a certain scan control line adopts a double-sided driving scheme, both the left and right sides of the scan control line are input ends, and the far end is the center of the screen. Therefore, the difference between the rising edge delay and the falling edge delay on the left and right sides of the scan control line is smaller in this case. As shown in Figures 8A to 8F, simulations revealed that when the GOA circuits corresponding to the second reset control line Reset2 and the first scan signal line Gate1 adopt a single-sided driving scheme, the difference in pixel driving current between the input position and the opposite side of the input position of this group of GOAs is relatively large. However, when the other four groups of GOA circuits (first light emission control line EM1, second light emission control line EM2, first reset control line Reset1, and third reset control line Reset3) adopt a single-sided driving scheme, the difference in pixel driving current between the input position and the opposite side of the input position is relatively small. Therefore, these four groups of GOAs can adopt a single-sided driving scheme.

[0126] Figure 9 shows the simulation waveforms of the first node N1 to the fifth node N5 and the gate-source voltage Vgs when the six sets of GOA circuits connected to the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first light emission control line EM1, the second light emission control line EM2, and the first scan signal line Gate1 are driven by a one-drive-two-scheme. As shown in Figure 9, if the GOA circuits of the other scan control lines except the first scan signal line Gate1 are driven by a one-drive-two-scheme, within the time range a, due to the unequal voltage between the second node N2 and the third node N3 (at this time, the driving transistor T3 is in the open state, and the second node N2 slowly charges the third node N3), it will cause a difference in brightness between odd and even rows. However, extending the time range a can improve this problem. Table 1 shows the simulation results of the odd-even row current difference when the pixel circuit shown in Figure 6 is driven by a one-drive-two-segment scheme for the six groups of GOA circuits corresponding to the first reset control line Reset1, the second reset control line Reset2, the third reset control line Reset3, the first light emission control line EM1, the second light emission control line EM2, and the first scan signal line Gate1. In the table, 2H represents the scan time of two pixel rows, 3H represents the scan time of three pixel rows, and 4H represents the scan time of four pixel rows.

[0127] Table 1

[0128] As shown in Table 1, according to the simulation results, when the time range of segment a is extended to the scanning time of three or more pixel rows, the pixel circuit of this embodiment can be driven by a one-to-two or one-to-multiple scheme.

[0129] In some exemplary embodiments, for each row of pixel circuits, the start writing time of the first scan signal and the end writing time of the first reset control signal differ by at least three pixel rows of scan time (3H).

[0130] For example, for each row of pixel circuits, the start writing time of the first scan signal and the end writing time of the first reset control signal differ by four pixel rows of scan time (4H).

[0131] Figures 10 to 23 are schematic diagrams of driving methods for several GOA circuits according to exemplary embodiments of the present disclosure. In Figures 10 to 23, each GOA circuit is identified by the scan control line connected to it. For example, Gate1 in the figure represents the first GOA circuit (or first GOA unit) connected to the first scan signal line Gate1; Reset1 in the figure represents the second GOA circuit (or second GOA unit) connected to the first reset control line Reset1; Reset2 in the figure represents the third GOA circuit (or third GOA unit) connected to the second reset control line Reset2; Reset3 in the figure represents the fourth GOA circuit (or fourth GOA unit) connected to the third reset control line Reset3; EM1 in the figure represents the fifth GOA circuit (or fifth GOA unit) connected to the first light emission control line EM1; and EM2 in the figure represents the sixth GOA circuit (or sixth GOA unit) connected to the second light emission control line EM2.

[0132] As shown in Figure 10, the pixel circuit of this embodiment can be driven by six sets of GOA circuits. The six sets of GOA circuits include a first GOA circuit to a sixth GOA circuit. The first GOA circuit includes multiple cascaded first GOA units, each connected to a first scan signal line Gate1, and configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits. The second GOA circuit includes multiple cascaded second GOA units, each connected to a first reset control line Reset1, and configured to provide a first reset control signal to the coupling sub-circuit 1022 in a row of pixel circuits. The third GOA circuit includes multiple cascaded third GOA units, each connected to a second reset control line Reset2, and configured to provide a second reset control signal to the second reset sub-circuit 1023 in a row of pixel circuits. The fourth GOA circuit includes multiple cascaded fourth GOA units, each connected to a third reset control line Reset3, and configured to provide a third reset control signal to the third reset sub-circuit 1024 in a row of pixel circuits. The fifth GOA circuit includes multiple cascaded fifth GOA units, each connected to a first light emission control line EM1, and configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in a row pixel circuit. The sixth GOA circuit includes multiple cascaded sixth GOA units, each connected to a second light emission control line EM2, and configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in a row pixel circuit. In this embodiment, the first to sixth GOA circuits are located on the left and right sides of the display area, respectively, and perform bilateral driving on their connected scan control lines.

[0133] As shown in Figure 11, the pixel circuit of this embodiment can be driven by five sets of GOA circuits. The five sets of GOA circuits include a first GOA circuit, and third to sixth GOA circuits. The first GOA circuit includes multiple cascaded first GOA units, each connected to a first scan signal line Gate1, and configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits. The third GOA circuit includes multiple cascaded third GOA units, each connected to a second reset control line Reset2, and configured to provide a second reset control signal to the second reset sub-circuit 1023 in a row of pixel circuits. The fourth GOA circuit includes multiple cascaded fourth GOA units, each connected to a third reset control line Reset3, and configured to provide a third reset control signal to the third reset sub-circuit 1024 in a row of pixel circuits. The fifth GOA circuit includes multiple cascaded fifth GOA units, each connected to a first light emission control line EM1, and configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in a row pixel circuit. The sixth GOA circuit includes multiple cascaded sixth GOA units, each connected to a second light emission control line EM2, and configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in a row pixel circuit. In this embodiment, the first reset control line Reset1 and the second reset control line Reset2 share a third GOA unit, and the first reset control line Reset1 is driven by the advance stage of the second reset control line Reset2, thus saving one set of GOA circuits. In this embodiment, the first to fifth GOA circuits are located on the left and right sides of the display area, respectively, to drive the scan control lines connected to them on both sides.

[0134] As shown in Figure 12, the pixel circuit of this embodiment uses six sets of GOA circuits for driving. The correspondence between the six sets of GOA circuits and their respective connected scan control lines can be referred to the previous description, and will not be repeated here. In this embodiment, the second GOA circuit is only set on one side of the display area (e.g., the left side) to drive the first reset control line Reset1 on one side. The third GOA circuit is also only set on one side of the display area (e.g., the right side) to drive the second reset control line Reset2 on one side. The first, fourth, to sixth GOA circuits are set on the left and right sides of the display area, respectively, to drive their respective connected scan control lines on both sides. Since the second and third GOA circuits are each only set on one side of the display area, the GOA circuit driving method of this embodiment can achieve the effect of a narrow bezel.

[0135] As shown in Figure 13, the pixel circuit of this embodiment uses six sets of GOA circuits for driving. The correspondence between the six sets of GOA circuits and their respective connected scan control lines can be referred to the previous description, and will not be repeated here. In this embodiment, the second GOA circuit is only set on one side of the display area (e.g., the right side) to drive the first reset control line Reset1 on one side. The fourth GOA circuit is also only set on one side of the display area (e.g., the left side) to drive the third reset control line Reset3 on one side. The first, third, fifth, and sixth GOA circuits are set on the left and right sides of the display area, respectively, to drive their respective connected scan control lines on both sides. Since the second and fourth GOA circuits are each only set on one side of the display area, the GOA circuit driving method of this embodiment can achieve the effect of a narrow bezel.

[0136] In this embodiment, any one of the first GOA circuit, the fifth GOA circuit, and the sixth GOA circuit may be configured only on one side of the display area to drive the scan control lines connected to each side unilaterally. This disclosure does not impose any restrictions on this.

[0137] For example, the second GOA circuit can be set only on one side of the display area (such as the right side) to drive the first reset control line Reset1 on one side, and the fifth GOA circuit can also be set only on one side of the display area (such as the left side) to drive the first light emission control line EM1 on one side. The first GOA circuit, the third GOA circuit, the fourth GOA circuit and the sixth GOA circuit can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0138] Alternatively, the second GOA circuit can be set only on one side of the display area (such as the right side) to drive the first reset control line Reset1 on one side, and the sixth GOA circuit can also be set only on one side of the display area (such as the left side) to drive the second light emission control line EM2 on one side. The first GOA circuit, the third GOA circuit, the fourth GOA circuit and the fifth GOA circuit can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0139] Alternatively, the second GOA circuit can be set only on one side of the display area (such as the right side) to drive the first reset control line Reset1 on one side, and the first GOA circuit can also be set only on one side of the display area (such as the left side) to drive the first scan signal line Gate1 on one side. The third to sixth GOA circuits can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0140] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to drive the second light emission control line EM2 on one side, and the third GOA circuit can also be set only on one side of the display area (such as the left side) to drive the second reset control line Reset2 on one side. The first GOA circuit to the second GOA circuit and the fourth GOA circuit to the fifth GOA circuit can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0141] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to drive the second light emission control line EM2 on one side, and the fourth GOA circuit can also be set only on one side of the display area (such as the left side) to drive the third reset control line Reset3 on one side. The first to third GOA circuits and the fifth GOA circuit can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0142] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to drive the second light emission control line EM2 on one side, and the fifth GOA circuit can also be set only on one side of the display area (such as the left side) to drive the first light emission control line EM1 on one side. The first to fourth GOA circuits can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0143] Alternatively, the sixth GOA circuit can be set only on one side of the display area (such as the right side) to drive the second light emission control line EM2 on one side, the first GOA circuit can also be set only on one side of the display area (such as the left side) to drive the first scan signal line Gate1 on one side, and the second to fifth GOA circuits can be set on the left and right sides of the display area to drive the scan control lines connected to them on both sides.

[0144] As shown in Figure 14, the pixel circuit of this embodiment uses five GOA circuits for driving. The correspondence between the five GOA circuits and their respective connected scan control lines can be referred to the previous description, and will not be repeated here. In this embodiment, the sixth GOA circuit is only set on one side of the display area (e.g., the right side) to drive the second light emission control line EM2 on one side. The fourth GOA circuit is also only set on one side of the display area (e.g., the left side) to drive the third reset control line Reset3 on one side. The first, third, and fifth GOA circuits are set on the left and right sides of the display area, respectively, to drive their respective connected scan control lines on both sides. Since the first reset control line Reset1 and the second reset control line Reset2 share the third GOA circuit, and the fourth and sixth GOA circuits are each only set on one side of the display area, the GOA circuit driving method of this embodiment can achieve the effect of a narrow bezel.

[0145] In this embodiment of the disclosure, any one of the second, fourth to sixth GOA circuits can be driven on one side, thus achieving the effect of a narrow bezel.

[0146] As shown in Figure 15, the pixel circuit of this embodiment uses six groups of GOA circuits for driving. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the previous description, and will not be repeated here. In this embodiment, each of the six groups of GOA circuits is only set on one side of the display area, and drives the scan control lines connected to them on one side, thereby achieving the effect of a narrow bezel.

[0147] As shown in Figure 16, the pixel circuit of this embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the previous description, and will not be repeated here. In this embodiment, the six groups of GOA circuits are each arranged on the left and right sides of the display area, and perform bilateral driving on their respective connected scan control lines. Each first GOA unit is connected to a first scan signal line Gate1 and is configured to provide a first scan signal to the coupling sub-circuit 1022 in one row of pixel circuits. Each second GOA unit is connected to two first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two rows of pixel circuits. Each third GOA unit is connected to two second reset control lines Reset2 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in two rows of pixel circuits. The second reset sub-circuit 1023 provides a second reset control signal. Each fourth GOA unit is connected to two third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the two-row pixel circuit. Each fifth GOA unit is connected to two first light emission control lines EM1 and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the two-row pixel circuit. Each sixth GOA unit is connected to two second light emission control lines EM2 and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the two-row pixel circuit. Since the second to sixth GOA circuits are all driven in a one-to-two manner, the arrangement space of the GOA circuits in the column direction is increased, and the space in the row direction can be compressed, thereby achieving a narrow bezel effect.

[0148] In this embodiment, the nth second GOA unit is disposed on the left and right sides of the sub-pixels in the (2n-1)th row and the sub-pixels in the 2nth row, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuits of the (2n-1)th row and the 2nth row;

[0149] The nth third GOA unit is located on the left and right sides of the sub-pixels in the (2n-1)th row and the sub-pixels in the 2nth row, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the (2n-1)th row and the 2nth row.

[0150] The nth fourth GOA unit is located on the left and right sides of the sub-pixels in the (2n-1)th and (2n-1)th rows and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuits of the (2n-1)th and (2n-1)th rows and the pixel circuits of the 2nth row.

[0151] The nth fifth GOA unit is located on the left and right sides of the sub-pixels in the (2n-1)th row and the sub-pixels in the 2nth row, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuits of the (2n-1)th row and the 2nth row.

[0152] The nth sixth GOA unit is located on the left and right sides of the sub-pixels in the (2n-1)th and (2n-1)th rows and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the pixel circuits of the (2n-1)th and (2n-1)th rows and the pixel circuits of ... (2n-1)th and (2n-1)th rows.

[0153] In this embodiment of the disclosure, some of the GOA circuits from the second to the sixth GOA circuits can be driven in a one-to-one manner, and some can be driven in a one-to-two manner. For example, any four groups of GOA circuits from the second to the sixth GOA circuits can be driven in a one-to-two manner, and the other group of GOA circuits can be driven in a one-to-one manner. Alternatively, any three groups of GOA circuits from the second to the sixth GOA circuits can be driven in a one-to-two manner, and the other two groups of GOA circuits can be driven in a one-to-one manner. Alternatively, any two groups of GOA circuits from the second to the sixth GOA circuits can be driven in a one-to-two manner, and the other three groups of GOA circuits can be driven in a one-to-one manner. Alternatively, any one group of GOA circuits from the second to the sixth GOA circuits can be driven in a one-to-two manner, and the other four groups of GOA circuits can be driven in a one-to-one manner.

[0154] In this embodiment of the disclosure, among the second to sixth GOA circuits, some GOA circuits can be driven in a one-to-one manner, and some GOA circuits can be driven in a one-to-two manner. At the same time, some GOA circuits can be driven in a single-sided manner, and some GOA circuits can be driven in a double-sided manner. That is, a hybrid method of one-to-two and single-sided driving is used to achieve the effect of narrow bezel.

[0155] For example, as shown in Figure 17, the pixel circuit of this embodiment uses six groups of GOA circuits for driving. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first GOA circuit, the fourth to sixth GOA circuits are each disposed on the left and right sides of the display area, and drive their respective connected scan control lines on both sides. The second to third GOA circuits are each disposed on only one side of the display area, and drive their respective connected scan control lines on one side only. Each first GOA unit is connected to a first scan signal line Gate1 and is configured to provide a first scan signal to the coupling sub-circuit 1022 in a row of pixel circuits. Each second GOA unit is connected to two first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in a row of pixel circuits. Each third GOA unit is connected to two second reset control lines Reset2 and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in a row of pixel circuits. Each fourth GOA unit is connected to two third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in a row of pixel circuits. Each fifth GOA unit is connected to a first light emission control line EM1 and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in a row of pixel circuits. Each sixth GOA unit is connected to two second light emission control lines EM2 and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in a row of pixel circuits. Since the second to third GOA circuits are driven by a single side, and the second to fourth and sixth GOA circuits are driven by a one-to-two method, a narrow bezel effect can be achieved.

[0156] In this embodiment of the disclosure, some or all of the second to sixth GOA circuits can be driven by a one-drive-three-circuit method to achieve the effect of a narrow bezel.

[0157] For example, as shown in Figure 18, the pixel circuit of this embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first GOA circuit to the sixth GOA circuit are each disposed on the left and right sides of the display area, and perform bilateral driving on their respective connected scan control lines. Each first GOA unit is connected to a first scan signal line Gate1 and is configured to provide a first scan signal to the coupling sub-circuit 1022 in the row pixel circuit. Each second GOA unit is connected to three first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the row pixel circuit. Each third GOA unit is connected to three second reset control lines Reset2 and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the row pixel circuit. Each fourth GOA unit is connected to three third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the row pixel circuit. Each fifth GOA unit is connected to three first light emission control lines EM1 and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the row pixel circuit. Each sixth GOA unit is connected to three second light emission control lines EM2 and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the row pixel circuit. Since the second to sixth GOA circuits all use a one-drive-three-drive method, the arrangement space of the GOA circuits in the column direction is increased, while the space in the row direction can be compressed, thus achieving the effect of a narrow bezel.

[0158] In this embodiment, the nth second GOA unit is disposed on the left and right sides of the 3n-2nd row sub-pixel, the 3n-1st row sub-pixel and the 3nth row sub-pixel, and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the 3n-2nd row sub-pixel, the 3n-1st row sub-pixel and the 3nth row sub-pixel;

[0159] The nth third GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows, and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows.

[0160] The nth fourth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels;

[0161] The nth fifth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels;

[0162] The nth sixth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels, and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels.

[0163] In this embodiment of the disclosure, two or more GOA circuits can be placed in columns to achieve a narrow bezel effect in the second to sixth GOA circuits.

[0164] For example, as shown in Figure 19, the pixel circuit of this embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first to the sixth GOA circuits are each disposed on the left and right sides of the display area, and drive their respective connected scan control lines on one or both sides. Each first GOA unit is connected to a first scan signal line Gate1 and is configured to provide a first scan signal to the coupling sub-circuit 1022 in the row pixel circuit. Each second GOA unit is connected to three first reset control lines Reset1 and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the row pixel circuit. Each third GOA unit is connected to three second reset control lines Reset2 and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the row pixel circuit. Each fourth GOA unit is connected to three third reset control lines Reset3 and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the row pixel circuit. Each fifth GOA unit is connected to three first light emission control lines EM1 and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the row pixel circuit. Each sixth GOA unit is connected to three second light emission control lines EM2 and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the row pixel circuit. In this embodiment, the second to fourth GOA circuits on the left and / or right sides can be placed in columns. Since the second to sixth GOA circuits are all driven by a one-drive-three-drive method, and the second to fourth GOA circuits are arranged in columns, the arrangement space of the GOA circuits in both column and row directions is increased, which can achieve the effect of narrow bezels.

[0165] In this embodiment, the 2n-1th second GOA unit is located to the left of the sub-pixels in the 6n-5th and 6n-4th rows and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuits of the 6n-5th, 6n-3rd and 6n-1st rows. The 2nth second GOA unit is located to the right of the sub-pixels in the 6n-5th and 6n-4th rows and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuits of the 6n-4th, 6n-2nd and 6nth rows.

[0166] The 2n-1th third GOA unit is located to the left of the sub-pixels in the 6n-3rd and 6n-2nd rows and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the 6n-5th, 6n-3rd and 6n-1st rows. The 2nth third GOA unit is located to the right of the sub-pixels in the 6n-3rd and 6n-2nd rows and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the 6n-4th, 6n-2nd and 6nth rows.

[0167] The 2n-1th fourth GOA unit is located to the left of the sub-pixels in the 6n-1th and 6nth rows, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuits of the 6n-5th, 6n-3rd, and 6n-1st rows. The 2nth fourth GOA unit is located to the right of the sub-pixels in the 6n-1th and 6nth rows, and is configured to provide a third reset control signal to the third reset sub-circuit 1024 in the pixel circuits of the 6n-4th, 6n-2nd, and 6nth rows.

[0168] The nth fifth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels;

[0169] The nth sixth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows, and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows, where n is a natural number greater than or equal to 1.

[0170] For example, as shown in Figure 20, the pixel circuit of this embodiment uses six groups of GOA circuits for driving. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, the second to fourth GOA circuits on the left and right sides are placed in a column, and all of the second to fourth GOA circuits adopt a bilateral driving scheme. Since the second to sixth GOA circuits are all driven by a one-to-three method and a bilateral driving method, and the second to fourth GOA circuits are placed in a column, the arrangement space of the GOA circuits in the column direction and row direction is increased, which can achieve the effect of narrow bezel while ensuring the pixel display effect.

[0171] In this embodiment, the nth third GOA unit is located on the left and right sides of the (3n-2)th row of sub-pixels and is configured to provide a second reset control signal to the second reset sub-circuit 1023 in the pixel circuits of the (3n-2)th row of sub-pixels, the (3n-1)th row of sub-pixels and the (3n)th row of sub-pixels.

[0172] The nth fourth GOA unit is located on the left and right sides of the 3n-1 row sub-pixel and is configured to provide a third reset control signal to the third reset sub-circuit 1023 in the pixel circuits of the 3n-2 row sub-pixel, the 3n-1 row sub-pixel and the 3n row sub-pixel;

[0173] The nth second GOA unit is located on the left and right sides of the 3nth row sub-pixel and is configured to provide a first reset control signal to the coupling sub-circuit 1022 in the pixel circuit of the (3n-2)th row sub-pixel, the (3n-1)th row sub-pixel and the 3nth row sub-pixel;

[0174] The nth fifth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels;

[0175] The nth sixth GOA unit is located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows, and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the pixel circuits of the (3n-2)th, (3n-1)th, and (3n)th rows, where n is a natural number greater than or equal to 1.

[0176] In this embodiment of the present disclosure, the arrangement order of the second GOA unit, the third GOA unit and the fourth GOA unit in the column direction in Figures 19 and 20 can be set as needed. This disclosure does not limit this. By arranging the second GOA unit, the third GOA unit and the fourth GOA unit in one column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0177] For example, as shown in Figure 21, the pixel circuit of this embodiment is driven by six groups of GOA circuits. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, the second to fourth GOA circuits on the left and / or right sides are placed in one column, and the fifth to sixth GOA circuits on the left and / or right sides are placed in another column. Since the second to sixth GOA circuits are all driven by a one-to-three method, and the second to fourth GOA circuits and the fifth to sixth GOA circuits are placed in one column respectively, the arrangement space of the GOA circuits in both the column and row directions is increased, which can achieve the effect of narrow bezels.

[0178] In this embodiment, the connection method from the second GOA unit to the fourth GOA unit is as described in Figure 19 above, and will not be repeated here.

[0179] In this embodiment, the 2n-1th fifth GOA unit is located to the left of the sub-pixels in the 6n-5th row, the 6n-4th row, and the 6n-3rd row, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuits of the 6n-5th row, the 6n-3rd row, and the 6n-1st row. The 2nth second GOA unit is located to the right of the sub-pixels in the 6n-5th row, the 6n-4th row, and the 6n-3rd row, and is configured to provide a first light emission control signal to the first light emission control sub-circuit 1026 in the pixel circuits of the 6n-4th row, the 6n-2nd row, and the 6nth row.

[0180] The 2n-1th sixth GOA unit is located to the left of the sub-pixels in the 6n-2, 6n-1, and 6n rows, and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the pixel circuits of the 6n-5, 6n-3, and 6n-1 rows. The 2nth sixth GOA unit is located to the right of the sub-pixels in the 6n-2, 6n-1, and 6n rows, and is configured to provide a second light emission control signal to the second light emission control sub-circuit 1027 in the pixel circuits of the 6n-4, 6n-2, and 6n rows.

[0181] In this embodiment, the arrangement order of the fifth GOA unit and the sixth GOA unit in the column direction can be set as needed, and this disclosure does not limit this. By setting the second GOA unit, the third GOA unit and the fourth GOA unit in the same column, and setting the fifth GOA unit and the sixth GOA unit in the same column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0182] For example, as shown in Figure 22, the pixel circuit of this embodiment uses six groups of GOA circuits for driving. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, the second to fourth GOA circuits on the left and right sides are placed in one column, and the fifth to sixth GOA circuits on the left and right sides are placed in another column. Since the second to sixth GOA circuits are all driven in a one-to-three and bilateral manner, and the second to fourth GOA circuits and the fifth to sixth GOA circuits are placed in one column respectively, the arrangement space of the GOA circuits in the column direction and row direction is increased, which can achieve the effect of narrow bezel.

[0183] In this embodiment, the connection method from the second GOA unit to the fourth GOA unit is as described in Figure 20 above, and will not be repeated here.

[0184] In this embodiment, the nth fifth GOA unit and the nth sixth GOA unit are located on the left and right sides of the sub-pixels in the (3n-2)th, (3n-1)th, and (3n)th rows of sub-pixels, respectively. The nth fifth GOA unit and the nth sixth GOA unit on the left and right sides are arranged in a column. The nth fifth GOA unit is configured to provide a first light emission control signal to the first light emission control sub-circuit in the pixel circuit of the (3n-2)th, (3n-1)th, and (3n)th row of sub-pixels. The nth sixth GOA unit is configured to provide a second light emission control signal to the second light emission control sub-circuit in the pixel circuit of the (3n-2)th, (3n-1)th, and (3n)th row of sub-pixels.

[0185] In this embodiment, the arrangement order of the fifth GOA unit and the sixth GOA unit in the column direction can be set as needed, and this disclosure does not limit this. By setting the second GOA unit, the third GOA unit and the fourth GOA unit in the same column, and setting the fifth GOA unit and the sixth GOA unit in the same column, the arrangement space in the row direction can be saved, thereby achieving the effect of a narrow border.

[0186] In this embodiment of the disclosure, among the first to sixth GOA circuits, some GOA circuits can be driven by a one-to-one method, some GOA circuits can be driven by a one-to-two method, and some GOA circuits can be driven by a one-to-three method, thereby achieving the effect of a narrow bezel.

[0187] For example, as shown in Figure 23, the pixel circuit of this embodiment uses six groups of GOA circuits for driving. The correspondence between the six groups of GOA circuits and their respective connected scan control lines can be referred to the above description, and will not be repeated here. In this embodiment, among the six groups of GOA circuits, the first to sixth GOA circuits are each disposed on the left and right sides of the display area, and drive their respective connected scan control lines on both sides. The first GOA circuit is driven in a one-to-one manner, the second to fourth GOA circuits are driven in a one-to-two manner, and the fifth to sixth GOA circuits are driven in a one-to-three manner, which can also achieve the effect of narrow bezels.

[0188] In this embodiment, in addition to the first GOA circuit, other groups of GOA circuits can also be designed to be driven in a one-to-one manner, so as to simultaneously ensure the pixel display effect and achieve the effect of narrow bezel.

[0189] Figure 24 is a timing diagram of the signals corresponding to each scan control line when the pixel circuit of this embodiment is driven by any of the driving methods shown in Figures 18 to 22. As shown in Figure 24, for each row of pixel circuit, the start writing time of the first scan signal and the end writing time of the first reset control signal are different by three or more scan times of three pixel rows (e.g., a = 3H or a = 4H).

[0190] This disclosure also provides a display panel, including an array substrate as described in any embodiment of this disclosure.

[0191] This disclosure also provides a display device, including a display panel as described in any embodiment of this disclosure.

[0192] In an exemplary embodiment, the display device can be any product or component with display function, such as a wearable device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0193] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0194] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0195] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. An array substrate comprising a plurality of sub-pixels arranged in an array and a plurality of scan control lines, data signal lines, and initial signal lines, wherein each sub-pixel includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit, each scan control line is electrically connected to at least one row of pixel circuits, the scan control line including a first scan signal line and a first reset control line, the array substrate further comprising a GOA circuit group for driving the pixel circuits row by row, the GOA circuit group comprising: First GOA circuit and second GOA circuit, wherein: The pixel circuit includes a first node, a second node, a third node, a driving sub-circuit, and a coupling sub-circuit. The driving sub-circuit is electrically connected to the first node, the second node, and the third node, and is configured to provide a driving signal to the third node under the control of the signals from the first node and the second node. The coupling sub-circuit is connected to a first scan signal line, a first reset control line, a data signal line, a first initial signal line, and the third node, and is configured to couple the signal from the first initial signal line to the third node under the control of a first reset control signal provided by the first reset control line, and to couple the signal from the data signal line to the third node under the control of a first scan signal provided by the first scan signal line. The first GOA circuit includes a plurality of cascaded first GOA units, each of which is connected to a first scan signal line and is configured to provide a first scan signal to a coupling sub-circuit in a row pixel circuit; The second GOA circuit includes a plurality of cascaded second GOA units, which are disposed on one side of the display area and drive the first reset control line on one side. Alternatively, each second GOA unit is connected to two or more first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuit in two or more rows of pixel circuits.

2. The array substrate according to claim 1, wherein, For each row of pixel circuits, the start writing time of the first scan signal and the end writing time of the first reset control signal differ by at least three pixel rows of scan time.

3. The array substrate according to claim 2, wherein, For each row of pixel circuits, the start writing time of the first scan signal and the end writing time of the first reset control signal differ by four pixel rows of scan time.

4. The array substrate according to claim 1, wherein, The scan control line further includes a second reset control line, and the pixel circuit further includes a second reset sub-circuit. The second reset sub-circuit is electrically connected to the second reset control line, the second initial signal line, and the first node, and is configured to provide the signal of the second initial signal line to the first node under the control of the second reset control signal provided by the second reset control line. The first reset control line connected to the pixel circuit in the i-th row is the second reset control line connected to the pixel circuit in the (i-1)-th row, where i is a natural number greater than 1.

5. The array substrate according to claim 1, wherein, The scan control line further includes a second reset control line, and the pixel circuit further includes a second reset sub-circuit. The second reset sub-circuit is electrically connected to the second reset control line, the second initial signal line, and the first node, and is configured to provide the signal of the second initial signal line to the first node under the control of the second reset control signal provided by the second reset control line. The GOA circuit group further includes: a third GOA circuit, the third GOA circuit including a plurality of cascaded third GOA units, each of the third GOA units being connected to at least one second reset control line and configured to provide a second reset control signal to a second reset sub-circuit in at least one row of pixel circuits; The third GOA unit is located on the left and right sides of the display area and drives the second reset control line on both sides.

6. The array substrate according to claim 5, wherein, The scanning control line further includes a third reset control line, and the pixel circuit further includes a third reset sub-circuit. The third reset sub-circuit is electrically connected to the third reset control line, the third initial signal line, and the anode of the light-emitting device, respectively, and is configured to reset the anode of the light-emitting device using the signal of the third initial signal line under the control of the third reset control signal provided by the third reset control line. The GOA circuit group further includes: a fourth GOA circuit, which includes a plurality of cascaded fourth GOA units, each of which is connected to at least one third reset control line and is configured to provide a third reset control signal to a third reset sub-circuit in at least one row of pixel circuits; The fourth GOA unit is disposed on one side of the display area and drives the third reset control line on one side. Alternatively, each fourth GOA unit is connected to two or more third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuit in two or more pixel circuits.

7. The array substrate according to claim 6, wherein, Each of the second GOA units is connected to three of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuit in the three-row pixel circuitry; Each of the third GOA units is connected to three of the second reset control lines and is configured to provide the second reset control signal to the second reset sub-circuit in the three-row pixel circuit; Each of the fourth GOA units is connected to the three third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuit in the three-row pixel circuit.

8. The array substrate according to claim 7, wherein, The 2n-1th second GOA unit, the 2n-1th third GOA unit, and the 2n-1th fourth GOA unit are arranged in a column to the left of the sub-pixels in rows 6n-5 to 6n. The 2n-1th second GOA unit is configured to provide a first reset control signal to the coupling sub-circuits in the pixel circuits of rows 6n-5, 6n-3, and 6n-1. The 2n-1th third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuits of rows 6n-5, 6n-3, and 6n-1. The 2n-1th fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuits of rows 6n-5, 6n-3, and 6n-1. The 2nth second GOA unit, the 2nth third GOA unit, and the 2nth fourth GOA unit are arranged in a column to the right of the sub-pixels in rows 6n-5 to 6n. The 2nth second GOA unit is configured to provide a first reset control signal to the coupling sub-circuits in the pixel circuits of rows 6n-4, 6n-2, and 6n. The 2nth third GOA unit is configured to provide a second reset control signal to the second reset sub-circuits in the pixel circuits of rows 6n-4, 6n-2, and 6n. The 2nth fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuits in the pixel circuits of rows 6n-4, 6n-2, and 6n. Here, n is a natural number greater than or equal to 1.

9. The array substrate according to claim 7, wherein, The nth second GOA unit, the nth third GOA unit, and the nth fourth GOA unit are disposed on the left and right sides of the sub-pixels in rows 3n-2 to 3n. The nth second GOA unit, the nth third GOA unit, and the nth fourth GOA unit on the left and right sides are arranged in a column. The nth second GOA unit is configured to provide a first reset control signal to the coupling sub-circuit in the pixel circuit of the sub-pixels in rows 3n-2, 3n-1, and 3n. The nth third GOA unit is configured to provide a second reset control signal to the second reset sub-circuit in the pixel circuit of the sub-pixels in rows 3n-2, 3n-1, and 3n. The nth fourth GOA unit is configured to provide a third reset control signal to the third reset sub-circuit in the pixel circuit of the sub-pixels in rows 3n-2, 3n-1, and 3n.

10. The array substrate according to claim 6, wherein, Each of the second GOA units is connected to two of the first reset control lines and is configured to provide the first reset control signal to the coupling sub-circuit in the two rows of pixel circuits; Each of the third GOA units is connected to two second reset control lines and is configured to provide the second reset control signal to the second reset sub-circuit in the two rows of pixel circuits; Each of the fourth GOA units is connected to two of the third reset control lines and is configured to provide the third reset control signal to the third reset sub-circuit in the two rows of pixel circuits.

11. The array substrate according to claim 1, wherein, The scanning control line further includes a first light emission control line and a second light emission control line. The pixel circuit further includes a first light emission control sub-circuit and a second light emission control sub-circuit. The first light emission control sub-circuit is electrically connected to the first light emission control line, the first power line, and the second node, respectively, and is configured to provide a signal from the first power line to the second node under the control of the first light emission control signal provided by the first light emission control line. The second light emission control sub-circuit is electrically connected to the second light emission control line, the third node, and the anode of the light-emitting device, respectively, and is configured to conduct the third node and the anode of the light-emitting device under the control of the second light emission control signal provided by the second light emission control line. The GOA circuit group further includes a fifth GOA circuit and a sixth GOA circuit. The fifth GOA circuit includes a plurality of cascaded fifth GOA units. Each fifth GOA unit is connected to at least one first light emission control line and is configured to provide a first light emission control signal to a first light emission control sub-circuit in at least one row of pixel circuits. The sixth GOA circuit includes a plurality of cascaded sixth GOA units, each of which is connected to at least one second light emission control line and is configured to provide a second light emission control signal to a second light emission control sub-circuit in at least one row of pixel circuits. The fifth GOA unit is disposed on one side of the display area and drives the first light emission control line on one side. Alternatively, each fifth GOA unit is connected to two or more first light emission control lines and is configured to provide a first light emission control signal to the first light emission control sub-circuit in two or more pixel circuits. The sixth GOA unit is disposed on one side of the display area and drives the second light emission control line on one side. Alternatively, each sixth GOA unit is connected to two or more second light emission control lines and is configured to provide a second light emission control signal to the second light emission control sub-circuit in two or more rows of pixel circuits.

12. The array substrate according to claim 11, wherein, The 2n-1th fifth GOA unit and the 2n-1th sixth GOA unit are arranged in a column to the left of the sub-pixels in rows 6n-5 to 6n. The 2n-1th fifth GOA unit is configured to provide a first light emission control signal to the first light emission control sub-circuit in the pixel circuit of the sub-pixels in rows 6n-5, 6n-3, and 6n-1. The 2n-1th sixth GOA unit is configured to provide a second light emission control signal to the second light emission control sub-circuit in the pixel circuit of the sub-pixels in rows 6n-5, 6n-3, and 6n-1. The 2nth fifth GOA unit and the 2nth sixth GOA unit are arranged in a column to the left of the sub-pixels in rows 6n-5 to 6n. The 2nth fifth GOA unit is configured to provide a first light emission control signal to the first light emission control sub-circuit in the pixel circuits of the sub-pixels in rows 6n-4, 6n-2, and 6n. The 2nth sixth GOA unit is configured to provide a second light emission control signal to the second light emission control sub-circuit in the pixel circuits of the sub-pixels in rows 6n-4, 6n-2, and 6n. Here, n is a natural number greater than or equal to 1.

13. The array substrate according to claim 11, wherein, The nth fifth GOA unit and the nth sixth GOA unit are disposed on the left and right sides of the sub-pixels in rows 3n-2, 3n-1, and 3n respectively. The nth fifth GOA unit and the nth sixth GOA unit on the left and right sides are arranged in a column. The nth fifth GOA unit is configured to provide a first light emission control signal to the first light emission control sub-circuit in the pixel circuit of the sub-pixels in rows 3n-2, 3n-1, and 3n respectively. The nth sixth GOA unit is configured to provide a second light emission control signal to the second light emission control sub-circuit in the pixel circuit of the sub-pixels in rows 3n-2, 3n-1, and 3n respectively. Here, n is a natural number greater than or equal to 1.

14. A display panel comprising an array substrate as claimed in any one of claims 1 to 13.

15. A display device, comprising: The display panel as described in claim 14.

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