Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a display area and a bonding area disposed on one side of the display area, wherein the bonding area is provided with at least one second power supply signal line (2), at least one touch signal line group (4) and at least one touch connection line group (5), one end of the at least one second power supply signal line (2) is connected to a drive circuit layer of a touch area, the other end of the at least one second power supply signal line (2) is connected to a bonding pin area (2034), one end of the at least one touch signal line group (4) is connected to a touch structure layer of the touch area, the other end of the at least one touch signal line group (4) is connected to the bonding pin area (2034), one end of the at least one touch connection line group (5) is connected to the touch signal line group (4), and the other end of the at least one touch connection line group (5) is connected to a drive chip area (2033).

Description

A display panel, a display device

[0001] This application claims priority to Chinese Patent Application No. 202510104205.2, filed on January 22, 2025, entitled “A Display Panel, Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0003] With the rapid development of display technology, touch screens have gradually become ubiquitous in people's lives. Based on their structural composition, touch screens can be categorized into add-on mode, on-cell, and in-cell types. Based on their working principle, touch screens can be classified into capacitive, resistive, infrared, and surface acoustic wave types. Capacitive on-cell touch screens form the touch structure on the light-emitting surface of the display screen. Due to their advantages such as simple structure, thinness, and high transmittance, they have gradually become the mainstream technology. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display panel, including a touch area and a bonding area disposed on one side of the touch area: the touch area includes a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and a touch structure layer disposed on the side of the light-emitting structure layer away from the substrate; the bonding area includes a first flat area, a bent area and a second flat area disposed sequentially along a direction away from the touch area, the second flat area includes a driving chip area and a bonding pin area, the driving chip area being configured to provide touch and display driving circuits;

[0006] The bonding area is provided with at least one second power signal line, at least one touch signal line group, and at least one touch connection line group. One end of the at least one second power signal line is connected to the driving circuit layer of the touch area, and the other end of the at least one second power signal line is connected to the bonding pin area. One end of the at least one touch signal line group is connected to the touch structure layer of the touch area, and the other end of the at least one touch signal line group is connected to the bonding pin area. One end of the at least one touch connection line group is connected to the touch signal line group, and the other end of the at least one touch connection line group is connected to the driving chip area.

[0007] In an exemplary embodiment, the at least one touch connection line group is located in the second flat area.

[0008] In an exemplary embodiment, the bonding area further includes an anti-static area located in the second flat area, the anti-static area being located between the driver chip area and the bending area, the anti-static area being configured to provide an anti-static protection unit, the anti-static area being connected to the driver chip area via a touch transmission line group, one end of the at least one touch connection line group being connected to the at least one touch signal line group, and the other end of the at least one touch connection line group being connected to the anti-static area.

[0009] In an exemplary embodiment, the bonding region is provided with at least one constant voltage signal line group, one end of the at least one constant voltage signal line group is connected to the driving circuit layer, and the other end of the at least one constant voltage signal line group is connected to the bonding pin area. The constant voltage signal line group is connected to the anti-static area through a voltage connection line group. The constant voltage signal line group includes at least one of a gate high voltage line, a gate low voltage line, and an initial voltage line.

[0010] In an exemplary embodiment, the bonding area is provided with at least one data signal line group, one end of the at least one data signal line group is connected to the driving circuit layer of the touch area, and the other end of the at least one data signal line group is connected to the anti-static area. The anti-static area is connected to the driving chip area through the data transmission line group, and the at least one data transmission line group and the at least one touch connection line group are located in the same film layer.

[0011] In an exemplary embodiment, the driving circuit layer includes a first active layer disposed on the substrate, a first gate layer disposed on the side of the first active layer away from the substrate, a second gate layer disposed on the side of the first gate layer away from the substrate, a first source-drain layer disposed on the side of the second gate layer away from the substrate, and a second source-drain layer disposed on the side of the first source-drain layer away from the substrate. The at least one data transmission line group and the at least one touch connection line group are both located on the same film layer as the first gate layer or the second gate layer.

[0012] In an exemplary embodiment, at least a portion of the orthographic projection of the at least one touch connection line group on the substrate overlaps with the orthographic projection of the at least one second power signal line on the substrate; or, the orthographic projection of the at least one touch connection line group on the substrate does not overlap with the orthographic projection of the at least one second power signal line on the substrate.

[0013] In an exemplary embodiment, the at least one second power signal line includes a second power lead located in the first flat region and the bending region, and a second power input line located in the second flat region. One end of the second power lead is connected to the driving circuit layer, and the other end of the second power lead is connected to the second power input line. One end of the second power input line is connected to the second power lead, and the other end of the second power input line is connected to the bonding pin region. The at least one touch connection line group is located on the side of the second power input line closer to the substrate, or the at least one touch connection line group is located on the side of the second power input line away from the substrate.

[0014] In an exemplary embodiment, the driving circuit layer includes a first active layer disposed on the substrate, a first gate layer disposed on the side of the first active layer away from the substrate, a second gate layer disposed on the side of the first gate layer away from the substrate, a second active layer disposed on the side of the second gate layer away from the substrate, a third gate layer disposed on the side of the second active layer away from the substrate, a first source-drain layer disposed on the side of the third gate layer away from the substrate, and a second source-drain layer disposed on the side of the first source-drain layer away from the substrate; the touch structure layer includes a first touch conductive layer disposed on the side of the light-emitting structure layer away from the substrate, and a second touch conductive layer disposed on the side of the first touch conductive layer away from the substrate; the second power access line is located in the same film layer as at least one of the first source-drain layer and the second source-drain layer, and the at least one touch connection line group is located in the same film layer as the first gate layer; or, the second power access line is located in the same film layer as at least one of the first source-drain layer and the second source-drain layer, and the at least one touch connection line group is located in the same film layer as at least one of the first touch conductive layer and the second touch conductive layer.

[0015] In an exemplary embodiment, the at least one touch signal line group includes a touch lead-out line group located in the first flat area and the bending area, and a touch access line group located in the second flat area. One end of the touch lead-out line group is connected to the touch circuit layer, and the other end of the touch lead-out line group is connected to the touch access line group. One end of the touch access line group is connected to the touch lead-out line group, and the other end of the touch access line group is connected to the bonding pin area. The orthographic projection of the touch access line group on the substrate overlaps with at least a portion of the orthographic projection of the at least one second power signal line on the substrate.

[0016] In an exemplary embodiment, the second power lead includes two sub-wire groups spaced apart. One end of each of the two sub-wire groups is connected to the driving circuit layer, and the other end of each of the two sub-wire groups is connected to the same second power input line. The touch lead group is located between the two sub-wire groups.

[0017] In an exemplary embodiment, the touch lead group is located on one side of the second power lead near the center line of the bonding area.

[0018] In an exemplary embodiment, the bonding region is provided with at least one gate drive signal line group. One end of the at least one gate drive signal line group is connected to the drive circuit layer, and the other end of the at least one gate drive signal line group is connected to the drive chip region. The gate drive signal line group includes a gate drive lead-out line group located in the first flat region and the bending region, and a gate drive access line group and a gate drive connection line group located in the second flat region. One end of the gate drive lead-out line group is connected to the drive circuit layer, and the other end of the gate drive lead-out line group is connected to the gate drive access line group. The gate drive access line group is connected to the gate drive connection line group, and the gate drive connection line group is connected to the drive chip region. Both the gate drive lead-out line group and the gate drive access line group are located on the side of the second power signal line away from the center line of the bonding region. The orthographic projection of the gate drive connection line group on the substrate overlaps with at least a portion of the orthographic projection of the second power signal line on the substrate.

[0019] In an exemplary embodiment, the bonding area further includes an anti-static area located in the second flat area, the anti-static area being located between the driver chip area and the bending area, the bonding area being provided with at least one data signal line group, the data signal line group being located on the side of the second power signal line near the center line of the bonding area, and the data signal line group being connected to the driver circuit layer and the anti-static area respectively.

[0020] In an exemplary embodiment, the bonding area is provided with at least one first power signal line, the first power signal line being located on the side of the second power signal line near the center line of the bonding area, and the first power signal line being connected to the driving circuit layer and the bonding pin area respectively.

[0021] On the other hand, this disclosure also provides a display device, including the aforementioned display panel.

[0022] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0024] Figure 1 is a plan view of a display panel according to an exemplary embodiment of the present disclosure;

[0025] Figure 2 is a plan view of the bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0026] Figure 3 is a cross-sectional schematic diagram of the touch area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0027] Figure 4 is a plan view of the bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0028] Figure 5 is a plan view of a first power signal line, a second power signal line, and a constant voltage signal line group in the bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure.

[0029] Figure 6 is a plan view of a touch signal line group in the bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0030] Figure 7 is a plan view of the data signal line group and gate drive signal line group of the bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0031] Figure 8a is a plan view of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure;

[0032] Figure 8b is a plan view of a touch signal line group in the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure;

[0033] Figure 9a is a plan view of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure;

[0034] Figure 9b is a plan view of a touch signal line group in the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure;

[0035] Figure 9c is a plan view of a touch signal line group in the binding area of ​​another display panel of the present disclosure, in which the touch access line group is not shown;

[0036] Figure 10 is a circuit diagram of an anti-static protection unit for a display panel according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0037] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0038] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0039] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0040] This disclosure provides a display panel including a touch area and a bonding area disposed on one side of the touch area: the touch area includes a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and a touch structure layer disposed on the side of the light-emitting structure layer away from the substrate; the bonding area includes a first flat area, a bent area and a second flat area disposed sequentially along a direction away from the touch area, the second flat area including a driving chip area and a bonding pin area, the driving chip area being configured to provide touch and display driving circuits;

[0041] The bonding area is provided with at least one second power signal line, at least one touch signal line group, and at least one touch connection line group. One end of the at least one second power signal line is connected to the driving circuit layer of the touch area, and the other end of the at least one second power signal line is connected to the bonding pin area. One end of the at least one touch signal line group is connected to the touch structure layer of the touch area, and the other end of the at least one touch signal line group is connected to the bonding pin area. One end of the at least one touch connection line group is connected to the touch signal line group, and the other end of the at least one touch connection line group is connected to the driving chip area.

[0042] The display panel of this exemplary embodiment includes a touch area and a bonding area disposed on one side of the touch area. The touch area includes a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate, and a touch structure layer disposed on the side of the encapsulation structure layer away from the substrate. The light-emitting structure layer may include a light-emitting device, which may be a liquid crystal display (LCD) device, an organic light-emitting diode (OLED) device, a plasma display panel (PDP) device, or an electrophoretic display panel (EPD) device. In an exemplary embodiment, the light-emitting device may be an OLED light-emitting device. OLED light-emitting devices are active light-emitting display devices, which have advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, flexible display devices using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. This is in line with product requirements such as flexible folding and narrow bezels.

[0043] The OLED-based touch structure adopts a flexible multi-layer on-cell (FMLOC) structure, in which the light-emitting structure layer and the touch structure layer are all integrated on the substrate, and the touch structure layer is set on the encapsulation structure layer to form an on-cell structure. It has the advantages of being thin, light and foldable, and can meet the product requirements of flexible folding and narrow bezel.

[0044] Figure 1 is a plan view of a display panel according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 1, the touch structure layer of the touch area of ​​the display panel is disposed on the encapsulation structure layer to form an FMLOC structure. In a plane parallel to the display panel, the display panel includes an effective area (AA), a bonding area located on one side of the effective area, and edge areas located on other sides of the effective area. The effective area can be either the touch area or the display area of ​​the display panel; the touch area and display area mentioned below both refer to the effective area. In an exemplary embodiment, the touch area 100 includes at least a plurality of regularly arranged touch electrodes, the edge area 300 includes at least a plurality of touch leads, and the bonding area 200 includes at least a bonding pin area connecting the touch leads to the bonding area.

[0045] In an exemplary embodiment, the touch structure layer of the display panel can be a mutually compliant structure. The touch area 100 may include a plurality of first touch units 110 and a plurality of second touch units 120. The first touch units 110 have a linear shape extending along a first direction D1, and the plurality of first touch units 110 are arranged sequentially along a second direction D2. The second touch units 120 have a linear shape extending along the second direction D2, and the plurality of second touch units 120 are arranged sequentially along the first direction D1. The first direction D1 intersects the second direction D2; for example, the first direction D1 and the second direction D2 are perpendicular to each other.

[0046] In an exemplary embodiment, each first touch unit 110 includes a plurality of first touch electrodes 111 and a first connecting portion 112 arranged sequentially along a first direction D1. The first touch electrodes 111 and the first connecting portion 112 are alternately arranged and sequentially connected. Each second touch unit 120 includes a plurality of second touch electrodes 121 arranged sequentially along a second direction D2. The plurality of second touch electrodes 121 are spaced apart, and adjacent second touch electrodes 121 are connected to each other through second connecting portions 122. In an exemplary embodiment, the film layer where the second connecting portion 122 is located is different from the film layer where the first touch electrodes 111 and the second touch electrodes 121 are located. The first touch electrodes 111 and the second touch electrodes 121 are alternately arranged in a third direction D3, which intersects the first direction D1 and the second direction D2.

[0047] In an exemplary embodiment, a plurality of first touch electrodes 111, a plurality of second touch electrodes 121, and a plurality of first connection portions 112 can be disposed on the same layer of the touch layer and formed by the same patterning process. The first touch electrodes 111 and the first connection portions 112 can be an integral structure interconnected with each other. The second connection portions 122 can be disposed on a bridging layer, and adjacent second touch electrodes 121 are interconnected through vias. An insulating layer is disposed between the touch layer and the bridging layer. In some possible implementations, a plurality of first touch electrodes 111, a plurality of second touch electrodes 121, and a plurality of second connection portions 122 can be disposed on the same layer of the touch layer. The second touch electrodes 121 and the second connection portions 122 can be an integral structure interconnected with each other. The first connection portions 112 can be disposed on a bridging layer, and adjacent first touch electrodes 111 are interconnected through vias. In an exemplary embodiment, the first touch electrode can be a driving (Tx) electrode, and the second touch electrode can be a sensing (Rx) electrode. Alternatively, the first touch electrode can be a sensing (Rx) electrode, and the second touch electrode can be a driving (Tx) electrode.

[0048] In an exemplary embodiment, the first touch electrode 111 and the second touch electrode 121 may have a rhomboid shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In some possible implementations, the first touch electrode 111 and the second touch electrode 121 may have any one or more of the following shapes: triangle, square, trapezoid, parallelogram, pentagon, hexagon, and other polygons, which are not limited herein.

[0049] In one exemplary embodiment, the first touch electrode 111 and the second touch electrode 121 can be in the form of transparent conductive electrodes. In another exemplary embodiment, the first touch electrode 111 and the second touch electrode 121 can be in the form of a metal mesh, which is formed by multiple interwoven metal wires. The metal mesh includes multiple mesh patterns, and each mesh pattern is a polygon composed of multiple metal wires. The metal mesh-type first touch electrode 111 and the second touch electrode 121 have advantages such as low resistance, small thickness, and fast response speed.

[0050] Figure 2 is a plan view of a bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure; wherein, the bonding area shown in Figure 2 can be the bonding area of ​​the display panel shown in Figure 1. In an exemplary embodiment, as shown in Figure 2, the bonding area 200 is located on one side of the touch area 100 in the second direction D2. Along the direction away from the touch area 100 (second direction D2), the bonding area 200 may include a first flat area 201, a bent area 202, and a second flat area arranged sequentially. One end of the first flat area 201 is connected to the display area in the second direction D2, and the other end of the first flat area 201 is connected to the bent area 202 in the second direction D2. The first flat area 201 may be provided with a touch signal line group and a data signal line group. The touch signal line group includes multiple touch signal lines, and the data signal line group includes multiple data signal lines. The first flat area 201 may be referred to as the first fan-out area. The bending area 202 is connected to the first flat area 201 at one end in the second direction D2, and to the second flat area at the other end in the second direction D2. The bending area 202 is configured to bend the second flat area to the back of the touch area 100. The second flat area, along the direction away from the touch area 100 (second direction D2), may include a second fan-out area 2031, an anti-static area 2032, a driver chip area 2033, and a bonding pin area 2034 arranged sequentially. The second fan-out area 2031 may house touch signal line groups and data signal line groups. The anti-static area 2032 may house an anti-static protection unit configured to eliminate static electricity. The driver chip area 2033 may house touch and display driver circuits configured to connect to the data signal line groups and touch signal line groups. The bonding pin area 2034 can be configured to bond multiple pins to a flexible printed circuit board (FPC).

[0051] Figure 3 is a cross-sectional schematic diagram of a touch area of ​​a display panel according to an exemplary embodiment of the present disclosure; wherein, the touch area shown in Figure 3 can be the touch area of ​​the display panel shown in Figure 1. In an exemplary embodiment, as shown in Figure 3, on a plane perpendicular to the display panel, the touch area of ​​the display panel may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101, and a touch structure layer 105 disposed on the side of the encapsulation structure layer 104 away from the substrate 101. In some possible implementations, the display panel may include other film layers, such as spacers, etc., which are not limited herein.

[0052] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0053] In an exemplary embodiment, the driving circuit layer 102 may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. In some possible implementations, the driving circuit layer 102 of each sub-pixel may include: a light-shielding layer disposed on the substrate 101; a first insulating layer disposed on the side of the light-shielding layer away from the substrate; a first active layer disposed on the side of the first insulating layer away from the substrate; a second insulating layer covering the first active layer; a first gate layer disposed on the side of the second insulating layer away from the substrate, the first gate layer including at least a first gate, the orthographic projection of the first gate onto the substrate partially overlapping the orthographic projection of the first active layer onto the substrate; a third insulating layer disposed on the side of the first gate layer away from the substrate; a second gate layer disposed on the side of the third insulating layer away from the substrate, the second gate layer including at least a second gate, the orthographic projection of the second gate onto the substrate partially overlapping the orthographic projection of the subsequently formed second active layer onto the substrate; a fourth insulating layer and a fifth insulating layer disposed on the side of the second gate layer away from the substrate; a second active layer disposed on the side of the fifth insulating layer away from the substrate; a sixth insulating layer disposed on the side of the second active layer away from the substrate; a third gate layer disposed on the side of the sixth insulating layer away from the substrate, the third gate layer including at least a third gate, the orthographic projection of the third gate onto the substrate partially overlapping the orthographic projection of the second active layer onto the substrate. The shadow partially overlaps; a seventh insulating layer is disposed on the side of the third gate layer away from the substrate; a first source / drain electrode layer is disposed on the side of the seventh insulating layer away from the substrate, the first source / drain electrode layer includes at least a first connecting electrode, a second connecting electrode, a third connecting electrode, a fourth connecting electrode, and a fifth connecting electrode, the first connecting electrode is connected to the first end of the first active layer through a first via, the second connecting electrode is connected to the second end of the first active layer through a second via, the third connecting electrode is connected to the light-shielding layer through a third via, the fourth connecting electrode is connected to the first end of the second active layer through a fourth via, and the fifth connecting electrode is connected to the second end of the second active layer through a fifth via; a first organic dielectric layer is disposed on the side of the first source / drain electrode layer away from the substrate; a second source / drain electrode layer is disposed on the side of the first organic dielectric layer away from the substrate, the second source / drain electrode layer includes at least a sixth connecting electrode, a seventh connecting electrode, and an eighth connecting electrode, the sixth connecting electrode is connected to the first connecting electrode through a sixth via, the seventh connecting electrode is connected to the second connecting electrode through a seventh via, and the eighth connecting electrode is connected to the fourth connecting electrode through an eighth via; a second organic dielectric layer is disposed on the side of the second source / drain electrode layer away from the substrate. The first active layer and the first gate form the first transistor of the driving circuit layer 102, and the second gate, the second active layer and the third gate form the second transistor of the driving circuit layer 102. The second transistor has a dual-gate structure.

[0054] In an exemplary embodiment, the light-emitting structure layer 103 may include: a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode. The first electrode is disposed on the side of the second organic dielectric layer away from the substrate and is connected to the seventh connection electrode of the driving circuit layer 102 through a via formed in the second organic dielectric layer; the pixel definition layer is disposed on the first electrode and the second organic dielectric layer, and a pixel opening is provided on the pixel definition layer, the pixel opening exposing the first electrode; the organic light-emitting layer is at least partially disposed within the pixel opening and is connected to the first electrode; the second electrode is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer; the organic light-emitting layer emits light of a corresponding color under the drive of the first electrode and the second electrode.

[0055] In an exemplary embodiment, the encapsulation structure layer 104 may include a first encapsulation structure layer, a second encapsulation structure layer, and a third encapsulation structure layer stacked together. The first and third encapsulation structure layers may be made of inorganic materials, while the second encapsulation structure layer may be made of organic materials. The second encapsulation structure layer is disposed between the first and third encapsulation structure layers to ensure that external moisture cannot enter the light-emitting structure layer 103.

[0056] In an exemplary embodiment, the touch structure layer 105 may include a first metal mesh (TMA) layer 106 disposed on the side of the encapsulation structure layer 104 away from the substrate, a touch insulating layer disposed on the side of the first metal mesh layer 106 away from the substrate 101, a second metal mesh (TMB) layer 107 disposed on the side of the touch insulating layer away from the substrate 101, and a protective layer disposed on the side of the second metal mesh layer 107 away from the substrate 101.

[0057] In an exemplary embodiment, the first metal mesh layer 106 and the second metal mesh layer 107 may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals, and the protective layer may be made of organic materials.

[0058] In an exemplary embodiment, the first metal mesh layer 106 can be referred to as a bridging layer, and the second metal mesh layer 107 can be referred to as a touch layer. Multiple first touch electrodes, second touch electrodes, and first connecting portions can be disposed on the same layer of the touch layer, and the second connecting portions can be disposed on the bridging layer. Adjacent second touch electrodes are connected to each other through vias.

[0059] Figure 4 is a plan view of a bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure; wherein, the bonding area shown in Figure 4 can be the bonding area of ​​the display panel shown in Figure 1. In an exemplary embodiment, as shown in Figure 4, on a plane parallel to the display panel, the bonding area 200 includes a first flat area 201, a bending area 202, and a second flat area 203 arranged sequentially along a direction away from the touch area 100 (second direction D2). The first flat area 201 may be provided with at least one touch signal line group and at least one data signal line group, and the first flat area 201 may be referred to as the first fan-out area. The bending area 202 is configured to bend the second flat area to the back of the touch area 100. The second flat area 203 includes an anti-static area 2032, a detection unit area 2035, a driver chip area 2033, and a bonding pin area 2034 arranged sequentially along a direction away from the touch area 100 (second direction D2). At least one touch signal line group of the first flat area 201 is connected to the driver chip area 2033, at least one data signal line group of the first flat area 201 is connected to the anti-static area 2032, the anti-static area 2032 is connected to the detection unit area 2035, the detection unit area 2035 is connected to the driver chip area 2033 through the data transmission line group 9, and the driver chip area 2033 is connected to the bonding pin area 2034 through the driver chip lead-out line group 8.

[0060] In an exemplary embodiment, the anti-static area 2032, the detection unit area 2035, the driver chip area 2033, and the bonding pin area 2034 can be mirrored relative to the center line O, and the anti-static area 2032, the detection unit area 2035, the driver chip area 2033, and the bonding pin area 2034 are all adjacent to the center line O. The center line O can be a center line that extends along the first direction D1 and evenly divides the bonding area 100.

[0061] In an exemplary embodiment, the anti-static area 2032 is configured to house an anti-static protection unit for eliminating static electricity. The detection unit area 2035 is configured to house a detection unit, which can be at least one of a current transformer (CT) detection unit and a multiplexer (Mux) detection unit, used for electrical testing of the data lines in the touch area. The driver chip area 2033 is configured to house touch and display driver circuitry for connecting to the data lines and the first and second touch electrodes in the touch area. The bonding pin area 2034 is configured to bond with a flexible printed circuit board (FPC).

[0062] In an exemplary embodiment, the bonding region 200 is provided with at least one first power signal line 1, at least one second power signal line 2, at least one data signal line group 3, at least one touch signal line group 4, at least one touch connection line group 5, at least one constant voltage signal line group 6, at least one constant voltage connection line group, and at least one gate drive signal line group 7. The first power signal line 1 is configured to connect a first power line (VDD) in the touch region to a pin of the bonding pin region 2034. The second power signal line 2 is configured to connect a second power line (VSS) in the touch region to a pin of the bonding pin region 2034. The data signal line group 3 includes multiple data signal lines configured to connect data lines in the touch region to the anti-static protection unit of the anti-static region 2032. The touch signal line group 4 includes multiple touch signal lines configured to connect a first touch electrode and a second touch electrode in the touch region to a pin of the bonding pin region 2034. Touch connection line group 5 includes multiple touch connection lines configured to connect the touch signal lines in touch signal line group 4 to the touch and display driving circuits of driver chip area 2033. Constant voltage signal line group 6 includes multiple constant voltage signal lines configured to connect the constant voltage lines in the touch area to the pins of bonding pin area 2034. Constant voltage connection line group 6 includes multiple constant voltage connection lines configured to connect the constant voltage signal lines in constant voltage signal line group 6 to the anti-static protection unit of anti-static area 2032. Gate drive signal line group 7 includes multiple gate drive signal lines configured to connect the gate drive circuit in the touch area to the pins of bonding pin area 2034.

[0063] In an exemplary embodiment, the first power signal line 1, the second power signal line 2, the data signal line group 3, the touch signal line group 4, the touch connection line group 5, the constant voltage signal line group 6, the constant voltage connection line group, and the gate drive signal line group 7 in the binding area 100 can all be mirrored relative to the center line O.

[0064] In an exemplary embodiment, the multiple constant voltage signal lines in the constant voltage signal line group 6 may include at least one of the gate high voltage line (VGH), the gate low voltage line (VGL), and the initial voltage line.

[0065] Figure 10 is a circuit diagram of an anti-static protection unit for a display panel according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, as shown in Figure 10, the anti-static protection unit includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first terminal of the second transistor T2 is connected to the data signal line Date, and the second terminal of the second transistor T2 is connected to the first terminal of the first transistor T1. The second terminal of the first transistor T1 is connected to the gate low voltage line VGL. The first terminal of the third transistor T3 is connected to the data signal line Date, and the second terminal of the third transistor T3 is connected to the first terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 is connected to the gate high voltage line VGH.

[0066] The working principle of the anti-static protection unit of the display panel disclosed herein is as follows: When the data signal line Date is tested for illumination, the anti-static protection unit does not work; when the data signal line Date has a momentary high potential (e.g., 100V), the gate-source voltage Vgs of the third transistor T3 is less than the threshold voltage Vth, the third transistor T3 turns on, the gate-source voltage Vgs of the fourth transistor T4 is less than the threshold voltage Vth, the fourth transistor T4 turns on, and the high potential of the data signal line Date is output through the gate high voltage line VGH, reducing the potential of the data signal line Date; when the data signal line Date has a momentary low potential (e.g., -100V), the gate-source voltage Vgs of the second transistor T2 is less than the threshold voltage Vth, the second transistor T2 turns on, the gate-source voltage Vgs of the first transistor T1 is less than the threshold voltage Vth, the first transistor T1 turns on, and the high potential of the gate low voltage line VGL is input to the data signal line Date, increasing the potential of the data signal line Date.

[0067] Figure 5 is a plan view of a first power signal line, a second power signal line, and a constant voltage signal line group in a bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure; wherein, the first power signal line, the second power signal line, and the constant voltage signal line group in the bonding area shown in Figure 5 can be the first power signal line, the second power signal line, and the constant voltage signal line group in the bonding area shown in Figure 4. In an exemplary embodiment, as shown in Figures 4 and 5, on a plane parallel to the display panel, the first power signal line 1 includes a first power lead-out line located in the first flat area 201 and the bending area 202, and a first power input line 13 located in the second flat area 203. The first power lead includes a first sub-wire group 1-1 and a second sub-wire group 1-2 arranged at intervals along the first direction D1. Both the first sub-wire group 1-1 and the second sub-wire group 1-2 are straight lines or broken lines extending along the second direction D2. The first sub-wire group 1-1 is located in the middle of the bonding area 200 in the first direction D1, and the second sub-wire group 1-2 is located on the side of the first sub-wire group 1-1 away from the center line O. Both the first sub-wire group 1-1 and the second sub-wire group 1-2 include a first power fan-out wire 11 located in the first flat area 201 and a bend in the bending area 201. The first power bend line 12, the first power fan-out line 11, and the first power bend line 12 are all straight lines or broken lines extending along the second direction D2. One end of the first power fan-out line 11 in the second direction D2 is connected to the driving circuit layer of the touch area, and the other end of the first power fan-out line 11 is connected to the first power bend line 12 in the second direction D2. One end of the first power bend line 12 in the second direction D2 is connected to the first power fan-out line 11, and the other end of the first power bend line 12 in the second direction D2 is connected to the first power input line 13. The first power input line 13 is L-shaped and broken. One end of the first power input line 13 in the second direction D2 is connected to the first sub-line group 1-1 and the second sub-line group 1-2, and the other end of the first power input line 13 in the second direction D2 is connected to the pin of the bonding pin area 2034.

[0068] In an exemplary embodiment, on a plane perpendicular to the display panel, the first power fan-out line 11 can be located on the same film layer as the first source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The first power bend line 12 can be located on the same film layer as the second source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The first power input line 13 can be located on the same film layer as at least one of the first and second source / drain electrode layers of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. For example, the first power input line 13 can be located on the same film layer as the first and second source / drain electrode layers of the touch area, and can be fabricated using the same conductive material and the same manufacturing process, thereby reducing the impedance of the first power input line 13.

[0069] In an exemplary embodiment, the second power signal line 2 includes a second power lead-out line located in the first flat region 201 and the bending region 202, and a second power input line 23 located in the second flat region 203. The second power lead-out line includes a third sub-line group 2-1 and a fourth sub-line group 2-2 arranged at intervals along the first direction D1. Both the third sub-line group 2-1 and the fourth sub-line group 2-2 are straight lines or broken lines extending along the second direction D2. Both the third sub-line group 2-1 and the fourth sub-line group 2-2 are located on the side of the second sub-line group 1-2 of the first power lead-out line away from the center line O, and the fourth sub-line group 2-2 is located on the side of the third sub-line group 2-1 away from the center line O. Both the third sub-line group 2-1 and the fourth sub-line group 2-2 include a second power fan-out line 2 located in the first flat region 201. The second power supply bend line 22, located in the bend area 202, and the second power supply fan-out line 21 and the second power supply bend line 22 are both straight lines or broken lines extending along the second direction D2. One end of the second power supply fan-out line 21 is connected to the driving circuit layer of the touch area in the second direction D2, and the other end of the second power supply fan-out line 21 is connected to the second power supply bend line 22 in the second direction D2. One end of the second power supply bend line 22 is connected to the second power supply fan-out line 21 in the second direction D2, and the other end of the second power supply bend line 22 is connected to the second power supply access line 23 in the second direction D2. The second power supply access line 23 is broken line extending along the second direction D2. One end of the second power supply access line 23 is connected to the third sub-line group 2-1 and the fourth sub-line group 2-2, and the other end of the second power supply access line 23 is connected to the pin of the bonding pin area 2034.

[0070] In an exemplary embodiment, on a plane perpendicular to the display panel, the second power fan-out line 21 can be located on the same film layer as the first source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The second power bend line 22 can be located on the same film layer as the second source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The second power input line 23 can be located on the same film layer as at least one of the first and second source / drain electrode layers of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. For example, the second power input line 23 can be located on the same film layer as the first and second source / drain electrode layers of the touch area, and can be fabricated using the same conductive material and the same manufacturing process, thereby reducing the impedance of the second power input line 23.

[0071] In an exemplary embodiment, the constant voltage signal line group 6 includes a constant voltage lead-out line group located in the first flat region 201 and the bending region 202, and a constant voltage input line group 63 located in the second flat region 203. The constant voltage lead group is in the shape of a straight line or a broken line extending along the second direction D2. The constant voltage lead group is located on the side of the fourth sub-line group 2-2 of the second power lead away from the center line O. The constant voltage lead group includes a constant voltage fan-out line group 61 located in the first flat area 201 and a constant voltage bent line group 62 located in the bending area 202. Both the constant voltage fan-out line group 61 and the constant voltage bent line group 62 are in the shape of a straight line or a broken line extending along the second direction D2. One end of the constant voltage fan-out line group 61 in the second direction D2 is connected to the driving circuit layer of the touch area. The other end of the constant voltage fan-out line group 61 in the second direction D2 is connected to the constant voltage bent line group 62. One end of the constant voltage bent line group 62 in the second direction D2 is connected to the constant voltage fan-out line group 61. The other end of the constant voltage bent line group 62 in the second direction D2 is connected to the constant voltage input line group 63. The constant voltage access line group 63 is in the shape of a broken line extending along the second direction D2. One end of the constant voltage access line group 63 is connected to the constant voltage bent line group 62, and the other end of the constant voltage access line group 63 is connected to the pin of the bonding pin area 2034.

[0072] In an exemplary embodiment, on a plane perpendicular to the display panel, the constant voltage fan-out line group 61 can be located on the same film layer as at least one of the first gate layer and the second gate layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The constant voltage bending line group 62 can be located on the same film layer as the second source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The constant voltage access line group 63 can be located on the same film layer as at least one of the first gate layer, the second gate layer, and the first source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. For example, the constant voltage access line group 63 can be located on the same film layer as the first gate layer, the second gate layer, and the first source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process, thereby reducing the impedance of the constant voltage access line group 63.

[0073] In an exemplary embodiment, the constant voltage connection line group 64 is in the shape of a broken line extending along the first direction D1. One end of the constant voltage connection line group 64 is connected to the constant voltage access line group 63 in the first direction D1, and the other end of the constant voltage connection line group 64 is connected to the anti-static area 2032 in the first direction D1.

[0074] In an exemplary embodiment, the orthographic projection of the constant voltage connection line group 64 onto the substrate partially overlaps with the orthographic projections of the first power access line 13 and the second power access line 23 onto the substrate. The constant voltage connection line group 64 is located in the same film layer as at least one of the first gate layer and the second gate layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. For example, by having the constant voltage connection line group 64 and the first gate layer and the second gate layer of the touch area located in the same film layer, and fabricated using the same conductive material and the same manufacturing process, the impedance of the constant voltage connection line group 64 is reduced.

[0075] Figure 6 is a plan view of a touch signal line group in the bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure; wherein, the touch signal line group in the bonding area shown in Figure 6 can be the touch signal line group in the bonding area shown in Figure 4. In an exemplary embodiment, as shown in Figures 4 and 6, on a plane parallel to the display panel, the touch signal line group 4 includes a touch lead-out line group located in the first flat area 201 and the bending area 202 and a touch access line group 43 located in the second flat area 203. The touch lead-out line group is in the form of a straight line or a broken line extending along the second direction D2. The touch lead-out line group is located between the third sub-line group 2-1 and the fourth sub-line group 2-2. The orthographic projection of the touch lead-out line group on the substrate does not overlap with the orthographic projection of the third sub-line group 2-1 and the fourth sub-line group 2-2 on the substrate. The touch lead-out line group includes a touch fan-out line group 41 located in the first flat area 201 and a touch bent line group 42 located in the bending area 202. The touch fan-out line group 41 Both the touch bend line group 42 and the touch fan-out line group 41 are straight or bend line extending along the second direction D2. One end of the touch fan-out line group 41 is connected to the touch structure layer of the touch area in the second direction D2, and the other end of the touch fan-out line group 41 is connected to the touch bend line group 42 in the second direction D2. The touch bend line group 42 is connected to the touch fan-out line group 41 in the second direction D2, and the other end of the touch bend line group 42 is connected to the touch access line group 43 in the second direction D2. The touch access line group 43 is bend line extending along the second direction D2. One end of the touch access line group 43 is connected to the touch bend line group 42, and the other end of the touch access line group 43 is connected to the pin of the bonding pin area 2034. Thus, an electrical test signal can be input to the touch signal line 4 through the bonding pin area 2034 to perform electrical testing on the first touch electrode and the second touch electrode of the touch area 100.

[0076] In an exemplary embodiment, the orthographic projection of the touch access line group 43 on the substrate partially overlaps with the orthographic projection of the second power access line 23 on the substrate.

[0077] In an exemplary embodiment, on a plane perpendicular to the display panel, the touch fan-out line group 41 can be located in the same film layer as at least one of the first metal mesh layer and the second metal mesh layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The touch bending line group 42 can be located in the same film layer as the second source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The touch access line group 43 can be located in the same film layer as at least one of the first metal mesh layer and the second metal mesh layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. For example, the touch access line group 43 can be located in the same film layer as the first metal mesh layer and the second metal mesh layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process, thereby reducing the impedance of the touch access line group 43.

[0078] In an exemplary embodiment, the touch connection line group 5 is located in the second flat area 203. The touch connection line group 5 is an L-shaped zigzag line extending along the first direction D1. One end of the touch connection line group 5 is connected to the touch access line group 43 in the first direction D1, and the other end of the touch connection line group 5 is connected to the driver chip area 2033 in the first direction D1.

[0079] In an exemplary embodiment, the orthographic projection of the touch connection line group 5 on the substrate partially overlaps with the orthographic projections of the first power access line 13 and the second power access line 23 on the substrate.

[0080] In an exemplary embodiment, the touch connection line group 5 and the second power access line 23 are located on different film layers, and the touch connection line group 5 can be located on the side of the second power access line 23 closer to the substrate. For example, the second power access line 23 and at least one of the first and second source / drain electrode layers of the touch area are located on the same film layer, and can be fabricated using the same conductive material and the same fabrication process; the touch connection line group 5 and the first or second gate layer of the touch area are located on the same film layer, and can be fabricated using the same conductive material and the same fabrication process.

[0081] In this embodiment, the display panel is located on the same film layer as the first gate layer or the second gate layer of the touch area via the touch connection line group 5, and the second power access line 23 is located on the same film layer as at least one of the first source / drain electrode layers and the second source / drain electrode layers of the touch area. This increases the distance between the overlapping areas of the touch connection line group 5 and the second power access line 23 in the direction perpendicular to the display panel, thereby reducing the parasitic capacitance between the touch connection line group 5 and the second signal line group 2, and reducing the occurrence of adverse phenomena such as touch display ripples and abnormal touch reporting.

[0082] Figure 7 is a plan view of a data signal line group and a gate drive signal line group in a bonding area of ​​a display panel according to an exemplary embodiment of the present disclosure; wherein, the data signal line group and the gate drive signal line group in the bonding area shown in Figure 7 can be the data signal line group and the gate drive signal line group in the bonding area shown in Figure 4. In an exemplary embodiment, as shown in Figures 4 and 7, on a plane parallel to the display panel, the data signal line group 3 includes a data lead-out line group located in the first flat area 201 and the bending area 202 and a data access line group 33 located in the second flat area 203. The data lead-out line group includes a fifth line group 3-1 and a sixth line group 3-2 arranged at intervals along the first direction D1. Both the fifth line group 3-1 and the sixth line group 3-2 are straight lines or broken lines extending along the second direction D2. The fifth line group 3-1 is located between the first sub-line group 1-1 and the second sub-line group 1-2 of the first power signal line 1. The sixth line group 3-2 is located on the side of the fifth line group 3-1 away from the center line O. The sixth line group 3-2 is located between the second sub-line group 1-2 and the third sub-line group 2-1. Both the fifth line group 3-1 and the sixth line group 3-2 include a data fan-out line group 31 located in the first flat area 201 and a data bent line group 32 located in the bending area 202. Both the data fan-out line group 31 and the data bent line group 32 are straight lines or broken lines extending along the second direction D2. One end of the data fan-out line group 31 in the second direction D2 is connected to the driving circuit layer of the touch area, and the other end of the data fan-out line group 31 is connected to the data bent line group 32 in the second direction D2. One end of the data bent line group 32 in the second direction D2 is connected to the data fan-out line group 31, and the other end of the data bent line group 32 in the second direction D2 is connected to the data access line group 33. The data access line group 33 is broken line in shape, and one end of the data access line group 33 in the second direction D2 is connected to the data bent line group 32, while the other end of the data access line group 33 in the second direction D2 is connected to the anti-static area 2032.

[0083] In an exemplary embodiment, the data fan-out line group 31 may include a first fan-out line group and a second fan-out line group, which are alternately arranged along a first direction D1 and located in different film layers. The first fan-out line group and the first gate layer of the touch area are located in the same film layer and can be fabricated using the same conductive material and the same fabrication process. The second fan-out line group and the second gate layer of the touch area are located in the same film layer and can be fabricated using the same conductive material and the same fabrication process. The data bend line group 32 and the second source / drain electrode layer of the touch area are located in the same film layer and can be fabricated using the same conductive material and the same fabrication process. The data access line group 33 may include a first access line group and a second access line group, which are alternately arranged along a first direction D1 and located in different film layers. The first access line group and the first gate layer of the touch area are located on the same film layer and can be prepared using the same conductive material and the same manufacturing process. The second access line group and the second gate layer of the touch area are located on the same film layer and can be prepared using the same conductive material and the same manufacturing process.

[0084] In an exemplary embodiment, the bonding area 200 is further provided with a data transmission line group 9 located between the detection unit area 2035 and the driver chip area 2033. The data transmission line group 9 is in the form of a straight line or a broken line extending along the second direction D2. One end of the data transmission line group 9 is connected to the detection unit area 2035 in the second direction D2, and the other end of the data transmission line group 9 is connected to the driver chip area 2033 in the second direction D2. The signals of the touch and display driving circuits on the driver chip area 2033 are transmitted to the detection unit area 2035 through the data transmission line group 9, and then to the anti-static area 2032 through the detection unit area 2035. The anti-static area 2032 then transmits the signals to the data lines in the touch area 100 through the data signal line group 3.

[0085] In an exemplary embodiment, the data transmission line group 9 and the touch connection line group 5 are located on the same film layer and can be fabricated using the same conductive material and the same manufacturing process. For example, both the data transmission line group 9 and the touch connection line group 5 are located on the same film layer as the first gate layer of the touch area, or both the data transmission line group 9 and the touch connection line group 5 are located on the same film layer as the second gate layer of the touch area, thereby ensuring the flatness of the bonding area 200 and reducing the risk of breakage of the driver chip area 2033 during the bonding process.

[0086] In an exemplary embodiment, the bonding region 200 is provided with a driver chip lead group 8 located between the driver chip region 2033 and the bonding pin region 2034. The driver chip lead group 8 is in the form of a straight line or a broken line extending along the second direction D2. One end of the driver chip lead group 8 is connected to the driver chip region 2033 in the second direction D2, and the other end of the data transmission line group 9 is connected to the bonding pin region 2034 in the second direction D2.

[0087] In an exemplary embodiment, the gate drive signal line group 7 includes a gate drive lead group located in the first flat region 201 and the bending region 202, and a gate drive access line group 73 and a gate drive connection line group 74 located in the second flat region 203. The gate drive lead group is in the form of a straight line or a broken line extending along the second direction D2, and is located between the constant voltage lead group of the constant voltage signal line group 6 and the fourth sub-line group 2-2 of the second power signal line 2. The gate driver lead group includes a gate driver fan-out line group 71 located in the first flat region 201 and a gate driver bent line group 72 located in the bending region 202. Both the gate driver fan-out line group 71 and the gate driver bent line group 72 are straight lines or broken lines extending along the second direction D2. One end of the gate driver fan-out line group 71 is connected to the driving circuit layer of the touch area in the second direction D2, and the other end of the gate driver fan-out line group 71 is connected to the gate driver bent line group 72 in the second direction D2. One end of the gate driver bent line group 72 is connected to the gate driver fan-out line group 71 in the second direction D2, and the other end of the gate driver bent line group 72 is connected to the gate driver access line group 73 in the second direction D2. The gate driver access line group 73 is broken line extending along the second direction D2. One end of the gate driver access line group 73 is connected to the gate driver bent line group 72, and the other end of the gate driver access line group 73 is connected to the gate driver connection line group 74. The gate drive connection line group 74 is a zigzag line extending along the first direction D1. One end of the gate drive connection line group 74 is connected to the gate drive access line group 73, and the other end of the gate drive connection line group 74 is connected to the driver chip area 2033.

[0088] In an exemplary embodiment, the orthographic projection of the gate drive connection group 74 on the substrate overlaps with portions of the orthographic projections of the first power access line 13 and the second power access line 23 on the substrate.

[0089] In an exemplary embodiment, on a plane perpendicular to the display panel, the gate drive fan-out line group 71 can be located on the same film layer as at least one of the first gate layer and the second gate layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The gate drive bend line group 72 can be located on the same film layer as the second source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The gate drive access line group 73 can be located on the same film layer as at least one of the first gate layer, the second gate layer, and the first source / drain electrode layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process. The gate drive connection line group 74 can be located on the same film layer as at least one of the first gate layer and the second gate layer of the touch area, and can be fabricated using the same conductive material and the same manufacturing process.

[0090] In this embodiment of the present disclosure, the display panel is located on the same film layer as at least one of the first gate layer and the second gate layer of the touch area via the gate drive connection line group 74, so that the drive connection line group 74 is located on a different film layer from the first power access line 13 and the second power access line 23, thereby avoiding the intersection of the gate drive connection line group 74 with the first power access line 13 and the second power access line 23.

[0091] Figure 8a is a plan view of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure; Figure 8b is a plan view of the touch signal line group of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure. The touch signal line group shown in Figure 8b can be the same as the touch signal line group shown in Figure 8a. In the exemplary embodiment, as shown in Figures 8a and 8b, the structure of the bonding area of ​​the display panel in this embodiment is generally the same as the structure of the bonding area of ​​the display panel shown in Figure 4, except that the structure of the touch connection line group 5 in the bonding area of ​​the display panel in this embodiment is different.

[0092] In an exemplary embodiment, on a plane perpendicular to the display panel, the orthographic projection of the touch connection line group 5 on the substrate partially overlaps with the orthographic projections of the first power access line 13 and the second power access line 23 on the substrate.

[0093] In an exemplary embodiment, the touch connection line group 5 and the second power access line 23 are located in different film layers, and the touch connection line group 5 can be located on the side of the second power access line 23 away from the substrate. For example, the second power access line 23 and at least one of the first source / drain electrode layer and the second source / drain electrode layer of the touch area are located in the same film layer, and can be fabricated using the same conductive material and the same manufacturing process; the touch connection line group 5 and at least one of the first metal mesh layer and the second metal mesh layer of the touch area are located in the same film layer, and can be fabricated using the same conductive material and the same manufacturing process.

[0094] In an exemplary embodiment, the touch connection line group 5 and the first metal mesh layer and the second metal mesh layer of the touch area are located in the same film layer and can be prepared by the same conductive material and the same manufacturing process, thereby reducing the impedance of the touch connection line group 5.

[0095] In this embodiment, the display panel is located on the same film layer as at least one of the first metal mesh layer and the second metal mesh layer of the touch area via the touch connection line group 5, and the second power access line 23 is located on the same film layer as at least one of the first source drain electrode layer and the second source drain electrode layer of the touch area. This increases the distance between the overlapping areas of the touch connection line group 5 and the second power access line 23 in the direction perpendicular to the display panel, thereby reducing the parasitic capacitance between the touch connection line group 5 and the second signal line group 2, and reducing the occurrence of adverse phenomena such as touch display ripples and abnormal touch reporting.

[0096] Figure 9a is a plan view of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure; Figure 9b is a plan view of the touch signal line group of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure; Figure 9c is a plan view of the touch signal line group of the bonding area of ​​another display panel according to an exemplary embodiment of the present disclosure where the touch access line group is not shown. The touch signal line group shown in Figure 9b can be the same as the touch signal line group shown in Figure 9a; the touch signal line group shown in Figure 9c does not show the touch access line group. In the exemplary embodiment, as shown in Figures 9a, 9b, and 9c, the structure of the bonding area of ​​the display panel in this embodiment is generally the same as the structure of the bonding area of ​​the display panel shown in Figure 4, except that the structures of the touch signal line group 4, the touch connection line group 5, and the second power signal line 2 in the bonding area of ​​the display panel in this embodiment are different.

[0097] In an exemplary embodiment, the second power lead of the second power signal line 2 and the touch lead group of the touch signal line group 4 are both straight lines or broken lines extending along the second direction D2. The second power lead of the second power signal line 2 is located on the side of the touch lead group of the touch signal line group 4 away from the center line O. That is, the second power fan-out line 21 and the second power bend line 22 of the second power signal line 2 are both located on the side of the touch fan-out line group 41 and the touch bend line group 42 of the touch signal line group 4 away from the center line O.

[0098] In this embodiment of the present disclosure, the second power lead of the second power signal line 2 of the display panel is located on the side of the touch lead group of the touch signal line group 4 away from the center line O, so that the second power lead of the second power signal line 2 is a signal line, thereby reducing the impedance of the second power signal line 2 and increasing the signal strength of the second power signal line 2.

[0099] In an exemplary embodiment, the orthographic projection of the touch access line group 43 of the touch signal line group 4 onto the substrate partially overlaps with the orthographic projection of the second power access line 23 of the second power signal line 2 onto the substrate.

[0100] In an exemplary embodiment, the touch connection line group 5 is straight or zigzag-shaped. One end of the touch connection line group 5 is connected to the touch bend line group 42 of the touch signal line group 4, and the other end of the touch connection line group 5 is connected to the anti-static area 2032. A touch transmission line group 51 is provided on the bonding area 200. The touch transmission line group 51 is straight or zigzag-shaped extending along the second direction D2. One end of the touch transmission line group 51 is connected to the anti-static area 2032, and the other end of the touch transmission line group 51 is connected to the driver chip area 2033.

[0101] In this embodiment of the present disclosure, the touch signal line group 4 of the display panel is connected to the anti-static area 2032 through the touch connection line group 5, thereby improving the anti-static performance of the touch signal line group 4.

[0102] In an exemplary embodiment, the orthographic projection of the touch connection line group 5 on the substrate does not overlap with the orthographic projection of the second power signal line 2 on the substrate.

[0103] In this embodiment of the present disclosure, the display panel does not overlap with the orthographic projection of the touch connection line group 5 on the substrate and the orthographic projection of the second power signal line 2 on the substrate. This eliminates the parasitic capacitance between the touch connection line group 5 and the second signal line group 2, reduces the mutual interference between the second power signal line 2 and the touch connection line group 5, and reduces adverse phenomena such as touch display ripples and abnormal touch reporting.

[0104] In an exemplary embodiment, the touch connection line group 5 is located in the same film layer as at least one of the first gate layer and the second gate layer of the touch area, and can be prepared by the same conductive material and the same manufacturing process.

[0105] This disclosure also provides a display device, including the display panel described above. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0106] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0107] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0108] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0109] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0110] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0111] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0112] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0113] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, comprising a touch area and a bonding area disposed on one side of the touch area: the touch area includes a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, and a touch structure layer disposed on the side of the light-emitting structure layer away from the substrate; the bonding area includes a first flat area, a bent area, and a second flat area sequentially disposed along a direction away from the touch area, the second flat area including a driving chip area and a bonding pin area, the driving chip area being configured to provide touch and display driving circuits; The bonding area is provided with at least one second power signal line, at least one touch signal line group, and at least one touch connection line group. One end of the at least one second power signal line is connected to the driving circuit layer of the touch area, and the other end of the at least one second power signal line is connected to the bonding pin area. One end of the at least one touch signal line group is connected to the touch structure layer of the touch area, and the other end of the at least one touch signal line group is connected to the bonding pin area. One end of the at least one touch connection line group is connected to the touch signal line group, and the other end of the at least one touch connection line group is connected to the driving chip area.

2. The display panel according to claim 1, wherein, The at least one touch connection line group is located in the second flat area.

3. The display panel according to claim 1, wherein, The bonding area also includes an anti-static area located in the second flat area. The anti-static area is located between the driver chip area and the bending area. The anti-static area is configured to have an anti-static protection unit. The anti-static area is connected to the driver chip area through a touch transmission line group. One end of the at least one touch connection line group is connected to the at least one touch signal line group, and the other end of the at least one touch connection line group is connected to the anti-static area.

4. The display panel according to claim 3, wherein, The bonding area is provided with at least one constant voltage signal line group. One end of the at least one constant voltage signal line group is connected to the driving circuit layer, and the other end of the at least one constant voltage signal line group is connected to the bonding pin area. The constant voltage signal line group is connected to the anti-static area through a voltage connection line group. The constant voltage signal line group includes at least one of a gate high voltage line, a gate low voltage line, and an initial voltage line.

5. The display panel according to claim 3, wherein, The bonding area is provided with at least one data signal line group. One end of the at least one data signal line group is connected to the driving circuit layer of the touch area, and the other end of the at least one data signal line group is connected to the anti-static area. The anti-static area is connected to the driving chip area through the data transmission line group. The at least one data transmission line group and the at least one touch connection line group are located in the same film layer.

6. The display panel according to claim 5, wherein, The driving circuit layer includes a first active layer disposed on the substrate, a first gate layer disposed on the side of the first active layer away from the substrate, a second gate layer disposed on the side of the first gate layer away from the substrate, a first source-drain layer disposed on the side of the second gate layer away from the substrate, and a second source-drain layer disposed on the side of the first source-drain layer away from the substrate. The at least one data transmission line group and the at least one touch connection line group are both located on the same film layer as the first gate layer or the second gate layer.

7. The display panel according to any one of claims 1 to 6, wherein, The orthographic projection of the at least one touch connection line group on the substrate overlaps with at least a portion of the orthographic projection of the at least one second power signal line on the substrate; Alternatively, the orthographic projection of the at least one touch connection line group on the substrate does not overlap with the orthographic projection of the at least one second power signal line on the substrate.

8. The display panel according to any one of claims 1 to 6, wherein, The at least one second power signal line includes a second power lead located in the first flat region and the bending region, and a second power input line located in the second flat region. One end of the second power lead is connected to the driving circuit layer, and the other end of the second power lead is connected to the second power input line. One end of the second power input line is connected to the second power lead, and the other end of the second power input line is connected to the bonding pin region. The at least one touch connection line group is located on the side of the second power input line closer to the substrate, or the at least one touch connection line group is located on the side of the second power input line away from the substrate.

9. The display panel according to claim 8, wherein, The driving circuit layer includes a first active layer disposed on the substrate, a first gate layer disposed on the side of the first active layer away from the substrate, a second gate layer disposed on the side of the first gate layer away from the substrate, a first source-drain layer disposed on the side of the second gate layer away from the substrate, and a second source-drain layer disposed on the side of the first source-drain layer away from the substrate; the touch structure layer includes a first touch conductive layer disposed on the side of the light-emitting structure layer away from the substrate, and a second touch conductive layer disposed on the side of the first touch conductive layer away from the substrate; the second power access line is located in the same film layer as at least one of the first source-drain layer and the second source-drain layer, and the at least one touch connection line group is located in the same film layer as the first gate layer; or, the second power access line is located in the same film layer as at least one of the first source-drain layer and the second source-drain layer, and the at least one touch connection line group is located in the same film layer as at least one of the first touch conductive layer and the second touch conductive layer.

10. The display panel according to claim 8, wherein, The at least one touch signal line group includes a touch lead-out line group located in the first flat area and the bending area, and a touch access line group located in the second flat area. One end of the touch lead-out line group is connected to the touch circuit layer, and the other end of the touch lead-out line group is connected to the touch access line group. One end of the touch access line group is connected to the touch lead-out line group, and the other end of the touch access line group is connected to the bonding pin area. The orthographic projection of the touch access line group on the substrate overlaps with at least a portion of the orthographic projection of the at least one second power signal line on the substrate.

11. The display panel according to claim 10, wherein, The second power lead includes two sub-wire groups spaced apart. One end of each of the two sub-wire groups is connected to the driving circuit layer, and the other end of each of the two sub-wire groups is connected to the second power input line. The touch lead group is located between the two sub-wire groups.

12. The display panel according to claim 10, wherein, The touch lead group is located on one side of the second power lead near the center line of the bonding area.

13. The display panel according to any one of claims 1 to 6, wherein, The bonding area is provided with at least one gate drive signal line group. One end of the at least one gate drive signal line group is connected to the drive circuit layer, and the other end of the at least one gate drive signal line group is connected to the drive chip area. The gate drive signal line group includes a gate drive lead-out line group located in the first flat area and the bending area, and a gate drive access line group and a gate drive connection line group located in the second flat area. One end of the gate drive lead-out line group is connected to the drive circuit layer, and the other end of the gate drive lead-out line group is connected to the gate drive access line group. The gate drive access line group is connected to the gate drive connection line group, and the gate drive connection line group is connected to the drive chip area. Both the gate drive lead-out line group and the gate drive access line group are located on the side of the second power signal line away from the center line of the bonding area. The orthographic projection of the gate drive connection line group on the substrate overlaps with at least a portion of the orthographic projection of the second power signal line on the substrate.

14. The display panel according to any one of claims 1 to 6, wherein, The bonding area also includes an anti-static area located in the second flat area. The anti-static area is located between the driver chip area and the bending area. The bonding area is provided with at least one data signal line group. The data signal line group is located on the side of the second power signal line near the center line of the bonding area. The data signal line group is connected to the driver circuit layer and the anti-static area respectively.

15. The display panel according to any one of claims 1 to 6, wherein, The bonding area is provided with at least one first power signal line, which is located on the side of the second power signal line near the center line of the bonding area. The first power signal line is connected to the driving circuit layer and the bonding pin area respectively.

16. A display device comprising the display panel as described in any one of claims 1 to 15.

Images