Computing-in-memory apparatus, control method and apparatus, computing-in-memory system, and electronic device

Abstract

Disclosed are a computing-in-memory apparatus, a control method and apparatus, an computing-in-memory system, and an electronic device. The computing-in-memory apparatus comprises: an input conversion circuit and a memory circuit. The input conversion circuit comprises a conversion unit, which is used for receiving a first signal, and converting the first signal into a second signal and then outputting the second signal, wherein there is a first mapping relationship between the second signal and the first signal. The memory circuit is in signal connection with the input conversion circuit, and comprises a memory cell, which is used for receiving the second signal, and converting the second signal into a third signal on the basis of weight data stored in the memory cell and then outputting the third signal, wherein there is a second mapping relationship between the second signal and the third signal. The mapping curve of the first mapping relationship matches that of the second mapping relationship. The computing-in-memory apparatus can use the input conversion circuit to optimize a conversion relationship of the memory cell of the memory circuit, thereby improving the computing performance of the computing-in-memory apparatus.

Description

Storage devices, control methods and apparatus, storage systems and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510121073.4, filed on January 24, 2025, entitled "In-memory computing device, control method and apparatus, in-memory computing system and electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to a memory computing device, control method and apparatus, memory computing system and electronic device. Background Technology

[0003] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0004] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their computational performance still needs improvement. Summary of the Invention

[0005] This application provides a memory computing device, a control method and apparatus, a memory computing system, and an electronic device, with the aim of improving the computing performance of a memory computing architecture.

[0006] In a first aspect, a storage computing device is provided, comprising: an input conversion circuit for receiving a first signal and converting the first signal into a second signal for output, wherein the second signal and the first signal have a first mapping relationship; and a storage circuit connected to the input conversion circuit, the storage circuit including a storage unit for receiving the second signal and converting the second signal into a third signal for output based on weight data stored in the storage unit, wherein the second signal and the third signal have a second mapping relationship; wherein the mapping curves of the first mapping relationship and the second mapping relationship are matched.

[0007] Based on the above technical solution, by setting an input conversion circuit before the storage unit, an indirect conversion relationship can be established between the signal input to the input conversion circuit (which can be understood as the input signal of the in-memory computing device) and the signal output from the storage unit (which can be understood as the output signal of the in-memory computing device). Furthermore, by matching the first mapping relationship with the second mapping relationship, this indirect conversion relationship can be made to approach a linear relationship. Thus, an approximate linear relationship between the input and output signals of the in-memory computing device can be formed using indirect conversion. When performing calculations using this in-memory computing device with an approximate linear relationship, it can better support multi-valued inputs, helping to improve calculation accuracy. In addition, the storage unit operating in the non-linear region can have lower power consumption, which is beneficial for the low-power operation of the in-memory computing device.

[0008] In some implementations of the first aspect, the input conversion circuit is further configured to receive a reference signal and, based on the reference signal, convert the first signal into the second signal for output.

[0009] Based on the above technical solution, the working state of the conversion circuit can be adjusted by the reference signal, which helps to match the first mapping relationship and the second mapping relationship, thereby better realizing the approximate linear relationship between the input signal and the output signal of the memory computing device.

[0010] In some implementations of the first aspect, the storage cell includes: a first transistor including a first terminal, a second terminal, and a first driving terminal; a second transistor including a third terminal, a fourth terminal, and a second driving terminal, wherein the fourth terminal is connected to the first driving terminal, the charge at the first driving terminal is used for storing weight data of the storage cell, the second driving terminal is used to control the on or off state of the second transistor, and the weight data is written when the second transistor is on; the input conversion circuit includes a conversion unit, the conversion unit including a third transistor including a fifth terminal, a sixth terminal, and a third driving terminal, the third driving terminal being used to couple the reference signal, the fifth terminal being used to couple the first signal, and being connected to the first terminal.

[0011] Based on the above technical solution, the input and output states of the third transistor are opposite to those of the first transistor. Therefore, the mapping direction of the first mapping curve associated with the third transistor is opposite to that of the second mapping curve associated with the first transistor, thereby providing reverse compensation for the input and output characteristics of the first transistor, which helps to better present a linear relationship between the input and output signals of the memory computing device.

[0012] In some implementations of the first aspect, the reference signal is determined based on the voltage range of the first drive terminal, the weight distribution of the model used by the storage circuit for calculation, the distribution of the weight data stored in the storage circuit, or the weight data stored in the storage cell.

[0013] Based on the above technical solution, the difference between the reference signal and the voltage at the storage node can be averaged out for the entire storage circuit, thereby reducing the overall difference between the storage cell and the input conversion circuit and achieving a better linearization effect.

[0014] In some implementations of the first aspect, the first signal includes a current signal, the second signal includes a voltage signal, and the third signal includes a current signal.

[0015] In some implementations of the first aspect, the device parameters of the third transistor are matched with the device parameters of the first transistor.

[0016] Based on the above technical solution, the device parameters of the third transistor are related to the device parameters of the first transistor, making the input-output characteristics of the third transistor (i.e., the first mapping relationship) closer to the input-output characteristics of the first transistor (i.e., the second mapping relationship), thereby better performing signal compensation and making the linearization effect more superior.

[0017] In some implementations of the first aspect, the sixth terminal is grounded or connected to a constant voltage source.

[0018] In some implementations of the first aspect, the conversion unit includes a plurality of the third transistors, the fifth terminals of the plurality of the third transistors are connected in parallel and connected to the first terminal of the first transistor, and the sixth terminals of the plurality of the third transistors are respectively connected to a constant voltage source or ground.

[0019] Based on the above technical solution, by introducing multiple third transistors, the impact of process deviations can be averaged out, thereby reducing the impact of process deviations on device performance. Furthermore, multiple third transistors can improve the driving capability of the input conversion circuit to the memory cells of the memory circuit, increase the load capacity of the input conversion circuit output, and allow it to support more memory cells.

[0020] In some implementations of the first aspect, the input conversion circuit further includes a buffer circuit connected between the conversion unit and the storage unit.

[0021] Based on the above technical solution, the buffer circuit can provide a more stable signal input to the storage circuit.

[0022] In some implementations of the first aspect, the buffer circuit is also used to amplify the power of the output of the conversion unit.

[0023] Based on the above technical solutions, the power amplifier circuit can enhance the driving capability of the input conversion circuit, improve the load capacity of the output of the input conversion circuit, and load more storage units. At the same time, it can isolate the conversion circuit and the storage circuit, reduce the mutual influence between the circuits, and improve the security and anti-interference capability of the storage system.

[0024] In some implementations of the first aspect, the input conversion circuit includes multiple conversion sub-circuits; the storage circuit includes multiple storage cells, the second terminals of which are connected to the same output line; wherein the first terminals of the multiple storage cells are respectively connected to the multiple conversion sub-circuits via multiple input lines.

[0025] Based on the above technical solutions, the storage circuits can be better adapted to the storage cell array structure, reducing the number of input signals and wiring data, and achieving linear mapping optimization of the in-memory computing device with lower cost, simpler circuit structure, and smaller circuit area or size.

[0026] Secondly, a control method is provided for controlling a memory computing device, the memory computing device including an input conversion circuit and a storage circuit. The method includes: controlling the storage circuit to enter a first operating state; providing a first signal to the input conversion circuit, wherein the first signal is converted into a second signal output by the input conversion circuit, wherein the second signal and the first signal have a first mapping relationship; acquiring an output signal of the storage circuit, the output signal including a cumulative output of a third signal output by at least one storage unit of the storage circuit, wherein the third signal is converted and output by the corresponding storage unit based on stored weight data, wherein the second signal and the third signal have a second mapping relationship, and the mapping curves of the first mapping relationship and the second mapping relationship match.

[0027] In some implementations of the second aspect, the control method further includes: controlling the storage circuit to enter a second operating state; and in the second operating state, controlling the writing of weight data stored in the storage cells of the storage circuit.

[0028] Thirdly, a control device is provided, including an interface circuit and a processing circuit, wherein the interface circuit is signal-connected to a memory computing device, and the processing circuit is used to execute any of the control methods described in the second aspect.

[0029] Fourthly, a storage computing system is provided, comprising: any of the storage computing devices described in the first aspect; and a control device for controlling the operating state of the storage computing device.

[0030] Fifthly, an electronic device is provided, including any of the memory computing devices as described in the first aspect or the memory computing system as described in the fourth aspect. Attached Figure Description

[0031] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0032] Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0033] Figure 3 shows a schematic diagram of a storage device according to an exemplary embodiment of the present application.

[0034] Figure 4 shows a schematic diagram of another memory computing device according to an exemplary embodiment of this application.

[0035] Figure 5 shows a schematic diagram of a mapping relationship according to an exemplary embodiment of this application.

[0036] Figure 6 shows a schematic diagram of the circuit structure of a memory computing device according to an exemplary embodiment of this application.

[0037] Figure 7 shows a schematic diagram of another input conversion circuit according to an exemplary embodiment of this application.

[0038] Figure 8 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application.

[0039] Figure 9 shows a schematic diagram of a storage device according to an exemplary embodiment of the present application.

[0040] Figure 10 shows a schematic diagram of another memory computing device according to an exemplary embodiment of the present application.

[0041] Figure 11 shows a flowchart of a control method according to an exemplary embodiment of this application.

[0042] Figure 12 shows a flowchart of a control method according to an exemplary embodiment of this application.

[0043] Figure 13 shows a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0044] Figure 14 shows a schematic diagram of a control device according to an exemplary embodiment of the present application.

[0045] Figure 15 shows a schematic diagram of an electronic device according to an exemplary embodiment of this application. Detailed Implementation

[0046] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0047] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0048] The business scenarios described in the embodiments of this application are for illustrative purposes only and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0049] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0050] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0051] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit or control device); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0052] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.

[0053] As shown in Figure 1, the in-memory computing system 100 may include an in-memory computing device 110 and a control circuit (or control unit) 120. The in-memory computing device 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the in-memory computing device 110. The operating states of the in-memory computing device 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the in-memory computing device 110. In the calculation state, the in-memory computing device 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The in-memory computing device 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The in-memory computing device 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the in-memory computing device 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0054] Storage cells can utilize the conduction capabilities of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell can include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device. Alternatively, a storage cell can also utilize a capacitor to store weight data.

[0055] The in-memory computing device 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the in-memory computing device 110 receives an input signal. The conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group and outputting them can achieve an equivalent multiplication operation. The storage cell array includes one-dimensional arrays, two-dimensional arrays, or three-dimensional arrays, etc., and the storage cell group includes multiple storage cells located in the same row or column of the storage cell array, or multiple storage cells located in multiple rows or columns, etc. These multiple storage cells can output their output signals collinearly.

[0056] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the in-memory computing device 110; the in-memory computing device 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0057] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0058] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells Sij, where i∈[1,m], j∈[1,n], m is the number of rows in the memory cell array, and n is the number of columns in the memory cell array. Memory cell Sij can store weight data Wij. When the memory cell array 210 is in a programming state, the conduction capability of memory cell Sij can be controlled based on the weight data to achieve a target state, thereby achieving the storage of the weight data. When the memory cell array 210 is in a computing state, an input signal, such as an input voltage Vi, can be provided to memory cell Sij through its input terminal IN; memory cell Sij outputs its output signal, such as an output current, at its output terminal OUT. The output terminals of multiple memory cells (e.g., S1j-Smj) can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells accumulate, and the resulting output signal Ij satisfies the following formula:

[0059] In some possible embodiments, the input data includes digital input signals, while the input signal Vi of the memory cell array 210 may include analog signals. The input circuit 230 may, for example, include a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal of the memory cell array 210 may include a digital signal represented by its waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0060] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more of the following: signal type conversion, signal magnitude conversion, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For example, if the input signal includes a voltage signal and the output signal includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242. The second conversion may be implemented, for example, through a sampling circuit, and the signal converted by the first conversion circuit 241 can be further provided to the second conversion circuit 242 for the second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert the current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal and provide it to the subsequent circuit. For example, the output circuit may include a sense amplifier (SA), which can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Additionally, in the example of Figure 2, the in-memory computing system 200 may also include a control circuit 220, which can be used to control the operating state of the memory cell Sij in the memory cell array 210, such as the programming state and computing state described above.

[0061] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of the memory cells can be connected collinearly by columns, and the output terminals can be connected collinearly by rows. Furthermore, the input terminal of a memory cell can include the gate of a transistor memory device, or it can include the source or drain of a transistor memory device; this application does not limit the specific type of memory cell. This application also does not limit the type of memory cell; for example, the memory cell can include a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, a memory cell can include multiple transistors; for example, a memory cell can include a first transistor and a second transistor, where the gate of one transistor is connected to the source or drain of the other transistor, and the charge stored at the gate can be used to characterize weight data. Optionally, the gate can also be connected to a capacitor to increase the stability and duration of the stored charge.

[0062] When the storage circuit operates in computation mode, the storage cell can convert the received input signal into an output signal based on the stored weight data. There is a mapping relationship between the input and output signals. This mapping relationship can be linear or non-linear. The storage cell can utilize this linear relationship to perform computation. For example, when the storage cell operates in the linear region, it can support multi-valued inputs and has high computational accuracy, but the power consumption is relatively high. Alternatively, the storage cell can utilize non-linear relationships for computation. For example, when the storage cell operates in the subthreshold region, the power consumption is lower, but multi-valued inputs may face greater noise, leading to a decrease in computational accuracy. Or, when using 1-bit input, more storage cells are needed to achieve computational accuracy, resulting in an excessively large chip area. Therefore, the computational performance of in-memory computing architectures, such as power consumption or computational accuracy, still needs improvement.

[0063] In view of this, embodiments of this application provide a memory computing device, a memory computing system, and an electronic device. The memory computing device can incorporate an input conversion circuit. The signal conversion performed by this input conversion circuit can be matched with the signal conversion performed by the memory circuit of the memory computing device. Through two matched signal conversions, the nonlinear mapping relationship is optimized, making the nonlinear mapping relationship tend towards a linear mapping relationship. This helps the input signal and output signal of the memory computing device to present a more linear mapping relationship. When the memory cell of the memory circuit operates in the nonlinear region, higher precision calculation can be achieved with lower power consumption and / or lower chip area. For example, memory cells operating in the subthreshold region can support multi-value inputs for calculation, improving the calculation accuracy of the memory computing device. This circuit structure can also support the memory cell of the memory circuit operating in the linear region, thereby increasing the flexibility of the operating state of the memory circuit to adapt to the needs of different business scenarios.

[0064] As an example, FIG3 shows a schematic diagram of an in-memory computing device according to an exemplary embodiment of the present application. As shown in FIG3, the in-memory computing device 300 may include an input conversion circuit 310 and a storage circuit 320. The input conversion circuit 310 may receive a first signal S1 and convert the first signal S1 into a second signal S2 for output, wherein the second signal S2 and the first signal S1 have a first mapping relationship. The storage circuit 320 may be signal-connected to the input conversion circuit 310, and the storage circuit 320 may include a storage unit 321, which is used to receive the second signal S2 and convert the second signal S2 into a third signal S3 for output based on the weight data stored in the storage unit 321, wherein the second signal S2 and the third signal S3 have a second mapping relationship.

[0065] The mapping curves of the first mapping relationship and the second mapping relationship are matched. For example, matching the mapping curves of the first mapping relationship and the second mapping relationship can include: excluding the influence of device errors, the trends of the mapping curves are consistent and the mapping directions are opposite. Those skilled in the art will understand that consistent trends of the mapping curves mean that the trends are the same or nearly the same, and do not require that the two mapping curves be completely identical.

[0066] In the above scheme, by setting an input conversion circuit before the storage unit, an indirect conversion relationship can be established between the signal input to the input conversion circuit (which can be understood as the input signal of the in-memory computing device) and the signal output from the storage unit (which can be understood as the output signal of the in-memory computing device). Furthermore, by matching the first and second mapping relationships, this indirect conversion relationship can be made to approach a linear relationship. Thus, an approximate linear relationship between the input and output signals of the in-memory computing device can be formed using indirect conversion. When performing calculations using this in-memory computing device with an approximate linear relationship, it can better support multi-valued inputs, helping to improve calculation accuracy. In addition, the storage unit operating in the non-linear region can have lower power consumption, which is beneficial for the low-power operation of the in-memory computing device.

[0067] In this embodiment, the mapping relationship between object A and object B may include a mapping from object A to object B, or a mapping from object B to object A. This embodiment does not impose any limitations.

[0068] As one possible implementation, the mapping curves of the first and second mapping relationships are matched, which can be achieved by a conversion unit included in the input conversion circuit. The circuit structure of this conversion unit is similar to or identical to the circuit structure used for signal conversion in the storage unit; for example, they may share the same device type. This simplifies the circuit structure and allows for reuse of the same manufacturing process, reducing process complexity and cost. According to some embodiments, the parameters of the devices included in the conversion unit match the parameters of the devices included in the storage unit. For example, excluding the influence of process errors, the parameters of the devices included in the conversion unit are the same as those of the devices included in the storage unit.

[0069] As one possible implementation, FIG4 shows a schematic diagram of another memory computing device according to an exemplary embodiment of the present application. As shown in FIG4, the input conversion circuit 310 may also receive a reference signal Sr and convert the first signal S1 into a second signal S2 based on the reference signal Sr for output. For example, the input conversion circuit 310 includes a conversion unit 311 for receiving the first signal S1 and the reference signal Sr, converting the first signal S1 based on the reference signal Sr for output, and the output signal may include, for example, the second signal S2, or the output signal may be further converted to obtain the second signal S2 and provided to the storage unit 321.

[0070] According to some embodiments, the reference signal Sr may include a reference voltage. The reference signal Sr may be determined based on factors such as: the voltage range of the first driving terminal (or the storage node of the storage cell), the weight distribution of the neural network model (hereinafter referred to as the model) used by the storage circuit for calculation, the distribution of the weight data stored in the storage circuit, or the weight data stored in the storage cell, etc. In this way, from the perspective of the storage cells of the entire storage circuit, the difference between the reference signal Sr and the voltage at the storage node can be averaged, reducing the overall difference and achieving a better linearization effect.

[0071] For example, the reference signal Sr can be determined based on the voltage range of the first drive terminal. For instance, the reference signal Sr can be equal to or approximately equal to the average of the maximum and minimum voltage values ​​of the storage node of the storage cell. Alternatively, the reference signal Sr can be determined based on the weight distribution of the model used by the storage circuit for calculation. For instance, it can be determined based on a first weight of the model, which may include, for example, the average weight of the model, or any weight in the model whose weight distribution probability is greater than or equal to a probability threshold, or the average weight of multiple weights in the model whose weight distribution probability is greater than or equal to the probability threshold. The model weights can correspond to the weight data of the storage cell. The reference signal Sr can be determined based on the distribution of the weight data stored in the storage circuit. For instance, it can be determined based on the first weight data of the storage circuit, which may include, for example, the average weight data stored in the storage circuit, or any weight data in the weight data stored in the storage circuit whose distribution probability is greater than or equal to a probability threshold, or the average weight of multiple weight data in the weight data stored in the storage circuit whose distribution probability is greater than or equal to the probability threshold. For example, the reference signal Sr can be determined based on the weight data stored in the corresponding storage unit. The storage unit corresponding to the reference signal Sr includes the storage unit connected to the conversion unit that receives the reference signal Sr. This storage unit can include one or more units. When multiple storage units are included, the weight can be determined based on the weight data of one of the storage units, or based on the weight data of multiple storage units, for example, based on the average of the weight data of multiple storage units. The average value can include an arithmetic mean or a weighted average, and the weighting factor can be determined based on the probability distribution of the weights.

[0072] Optionally, the input conversion circuit 310 may further include a buffer circuit 312. The buffer circuit 312 may be connected between the conversion unit 311 and the storage unit 321. The buffer circuit 312 can buffer the signal output by the conversion unit 311, so that the signal can be provided to the subsequent circuit more stably. For example, the buffer circuit 312 may include a voltage buffer, a voltage follower, or an operational amplifier circuit with negative feedback. Optionally, the buffer circuit may also amplify the power of the output of the conversion unit 311 to improve the driving capability of the subsequent circuit. For example, the buffer circuit 312 can amplify the signal power by amplifying the current or voltage. When the storage circuit 320 is used for calculation, the buffer circuit 312 not only allows the storage circuit 320 to obtain a more stable signal input (i.e., the second signal S2), but also allows the signal input to drive multiple storage units simultaneously. These multiple storage units can share an input line to receive the second signal S2 and achieve parallel operation; this can reduce the wiring complexity within the storage device 300, increase the storage density of the storage circuit, and provide higher computing power per unit area.

[0073] According to the above embodiments, the buffer circuit can provide a more stable signal input to the storage circuit. Furthermore, the buffer circuit can enhance the driving capability of the input conversion circuit, increase the load capacity of the input conversion circuit output, and support more storage cells. Moreover, the buffer circuit can isolate the influence of the storage circuit on the preceding circuits, improving the stability and anti-interference capability of the memory computing system. As one possible implementation, the buffer circuit 312 may include a voltage follower circuit or a voltage stabilizing circuit. The voltage follower circuit or voltage stabilizing circuit can provide a more stable voltage input to the storage cells, which is beneficial for improving the accuracy of calculations. The embodiments of this application do not limit the implementation of the voltage follower circuit or voltage stabilizing circuit. For example, the voltage follower circuit or voltage stabilizing circuit may include, but is not limited to, a voltage follower composed of an operational amplifier, an emitter follower composed of a transistor, a voltage regulator composed of a Zener diode, or an integrated circuit or dedicated chip with similar voltage following or stabilizing functions, etc.

[0074] Optionally, the input conversion circuit 310 may omit the buffer circuit 312 and instead use multiple parallel conversion units 311 to improve the driving capability of subsequent circuits. Multiple parallel conversion units 311 can improve the reliability of the input conversion circuit 310. Thus, even if some of the parallel conversion units 311 malfunction, the remaining normally functioning conversion units 311 can still ensure the normal operation of the input conversion circuit 310. Alternatively, the input conversion circuit 310 may include both a buffer circuit 312 and multiple parallel conversion units 311. In this way, the multiple parallel conversion units 311 can ensure the stability of the voltage at the input terminal of the buffer circuit 312. This application embodiment does not limit the number of conversion units 311; it may include one or more, and can be configured according to the driving capability requirements of the subsequent circuits, or according to the yield and reliability requirements of the conversion units 311.

[0075] The following example illustrates the matching of the first and second mapping relationships, using the example of the first signal S1 including a current signal, the second signal S2 including a voltage signal, and the third signal S3 including a current signal.

[0076] For example, Figure 5 illustrates a schematic diagram of a mapping relationship according to an exemplary embodiment of this application. As shown in Figure 5, the first mapping relationship between the second signal S2 and the first signal S1 is characterized by a first characteristic curve F1, and the second mapping relationship between the second signal S2 and the third signal S3 is characterized by a second characteristic curve F2. The matching of the first and second mapping relationships can be represented by the interaction of the first characteristic curve F1 and the second characteristic curve F2, such that the mapping relationship between the first signal S1 and the third signal S3 approaches a linear mapping relationship, which can be characterized, for example, by a third curve F3.

[0077] According to some embodiments of this invention, both the conversion unit 311 and the storage unit 321 may include transistors, as described below with reference to the accompanying drawings.

[0078] As an example, FIG6 shows a schematic diagram of the circuit structure of a memory computing device according to an exemplary embodiment of the present application. As shown in FIG6, the memory cell 610 may include a first transistor T1 (also called a read transistor) and a second transistor T2 (also called a write transistor). For ease of description, the non-driving terminals of the first transistor T1 are described as the first terminal and the second terminal, and the non-driving terminals of the second transistor T2 are described as the third terminal and the fourth terminal; the driving terminal of the first transistor T1 is described as the first driving terminal, and the driving terminal of the second transistor T2 is described as the second driving terminal. The first transistor T1 includes the first terminal, the second terminal, and the first driving terminal; the second transistor T2 includes the third terminal, the fourth terminal, and the second driving terminal, and the fourth terminal is connected to the first driving terminal. The first driving terminal or any equipotential point connected to the first driving terminal can be understood as a memory node of the memory cell 610. The second driving terminal is used to control the on or off state of the second transistor T2. Weight data can be written when the second transistor T2 is in the on state. In the first working state (writing or programming), the storage circuit can control the second transistor T2 of the storage cell 610 to be in the conducting state through the control terminal Con1, and control the writing of data (e.g., weight data) through the control terminal Con2; in the second working state (reading or calculation), the storage circuit can control the second transistor T2 of the storage cell 610 to be in the cut-off state through the control terminal Con1, and the first transistor T1 receives the second signal S2 through the input terminal and outputs the third signal S3 at the output terminal.

[0079] According to some embodiments, the first driving terminal of the first transistor T1 includes a gate; the first terminal includes a source, and the second terminal includes a drain, or the first terminal includes a drain and the second terminal includes a source. The first transistor can operate in the subthreshold region or the linear region. For example, if the second terminal includes a drain, during reading or calculation, the second terminal can be clamped at a higher potential voltage, resulting in lower power consumption during reading or calculation. Alternatively, if the second terminal includes a source, during reading or calculation, the second terminal can be clamped at a lower potential voltage, resulting in a wider operating range, such as a wider range of weight data or input data, and higher calculation accuracy.

[0080] According to some embodiments, the second driving terminal includes a gate; the third terminal includes a source, and the fourth terminal includes a drain, or the third terminal includes a drain and the fourth terminal includes a source.

[0081] According to some embodiments, the first terminal of the first transistor T1 can serve as the input terminal of the storage cell for coupling to the second signal S2, and the second terminal can serve as the output terminal of the storage cell for outputting the third signal S3. The third signal S3 is determined based on the second signal S2 and the weight data stored in the storage cell 610. The storage cell 610 can convert the second signal S2 into the third signal S3 for output based on the stored weight data. For example, when the storage cell 610 is in a calculation state, the second signal S2 is applied to the first terminal of the first transistor T1, and there is a charge corresponding to the weight data at the first driving terminal. This charge acts on the first transistor T1, controlling the conduction capability of the first transistor T1. Under this conduction capability, the first transistor T1 outputs the third signal S3 at the second terminal.

[0082] According to some embodiments, the second driving terminal of the second transistor T2 is used to couple to a first control signal, and the third terminal is used to couple to a second control signal. The first and second control signals are used to control the writing of weight data.

[0083] As an example, the first control signal can be used to control whether the second transistor T2 is turned on, thereby enabling the programming state when it is turned on, allowing the writing of weight data, and de-enabling the programming state when it is turned off, maintaining the storage of weight data for reading or calculation. The second control signal can be used to control the writing of weight data, for example, by controlling the charge at the storage node. For example, when the storage cell 610 is in the programming state, the first control signal controls the second transistor T2 to turn on. At this time, the second control signal can accumulate charge at the connection between the third terminal and the fourth terminal and the first driving terminal, or write a voltage value to characterize the weight data. After the weight data is written, the first control signal controls the second transistor T2 to turn off.

[0084] Optionally, a parasitic capacitance is formed at the first driving terminal to store charge and improve the stability of weight data storage in the storage cell 610. The parasitic capacitance may include the parasitic capacitance of the equivalent capacitor corresponding to the parasitic parameters. For example, the parasitic capacitance may be formed between the first driving terminal and the ground point, or it may be formed between the first driving terminal and the channel of the first transistor T1.

[0085] Optionally, the storage unit 610 may further include a capacitor C, one end of which is connected to the first driving terminal and the third terminal, and the other end of which is coupled to a voltage Vc. The voltage Vc can be a positive voltage, a negative voltage, or a ground voltage; this application does not impose any limitations. When the other end of the capacitor C is grounded, the number of signals required for circuit connection can be simplified, circuit implementation can be simplified, and signal interference can be reduced. By setting the capacitor C coupled to the first driving terminal and the fourth terminal, the storage characteristics of the storage unit 500 can be improved, and the stability of the storage unit 610 for weighted data storage can be enhanced.

[0086] As shown by the Sachtang equation, when the gate voltage of a transistor is determined, the relationship between the source and drain signals may be non-linear. For example, the relationship between the source voltage and drain current may be non-linear, or vice versa. This can lead to a non-linear mapping relationship between the output signal and the input signal when the storage cell 610 converts the input signal into an output signal based on the stored weight data. The input conversion circuit 620 performs a mapping-matching conversion on the input signal (e.g., the first signal S1) to improve the overall non-linear relationship between the input signal and the output signal (e.g., the third signal S3).

[0087] As shown in Figure 6, the input conversion circuit 620 may include a third transistor T3. For ease of description, the non-driving terminals of the third transistor T3 are described as the fifth and sixth terminals, and the driving terminals of the third transistor T3 are described as the third driving terminal. The third transistor T3 may include a fifth terminal, a sixth terminal, and a third driving terminal. The third driving terminal includes a gate; the fifth terminal includes a source, and the sixth terminal includes a drain, or the fifth terminal includes a drain, and the sixth terminal includes a source. The third driving terminal may be coupled to a reference signal Sr, the fifth terminal may be used as a conversion node, and the sixth terminal may be coupled to a bias signal Vb, for example, grounded or connected to a constant voltage source. The constant voltage source may, for example, provide a voltage Vdd with a higher level, or may, for example, provide a voltage Vss with a lower level.

[0088] The first signal S1 can be converted into the second signal S2 at the fifth terminal. The second signal S2 can be output from the fifth terminal to the subsequent circuit. For example, the fifth terminal can be connected to the first terminal of the first transistor T1 of the memory cell 610. The first signal S1 can include a current signal, and the second signal S2 can include a voltage signal. The first mapping relationship between the second signal S2 and the first signal S1, and the second mapping relationship between the second signal S2 and the third signal S3, can both include the mapping relationship of transistor device signal conversion. Due to the similarity of the mapping relationships of devices of the same type, it is advantageous to achieve the matching of the first mapping relationship and the second mapping relationship with lower cost and complexity. The connection between the fifth terminal and the first terminal can be a direct connection or an indirect connection. For example, the fifth terminal and the first terminal can be directly connected by a trace, or other circuits can be included between the conversion unit and the memory cell, for example, the fifth terminal and the first terminal can be indirectly connected by a buffer circuit.

[0089] According to some embodiments, the device parameters of the third transistor T3 are matched with those of the first transistor T1. For example, the third transistor T3 is of the same type as the first transistor T1. The first transistor T1 and the third transistor T3 may include n-type transistors, or the first transistor T1 and the third transistor T3 may include p-type transistors. As another example, the third transistor T3 is nearly identical or the same as at least one of the following parameters of the first transistor T1: threshold voltage, transconductance, size parameters, thermal parameters, or noise parameters, etc. Differences in the device parameters of the third transistor T3 and the first transistor T1 may include differences within an acceptable range due to errors. The third transistor T3 and the first transistor T1 may be fabricated using the same or the same process. For example, the third transistor T3 and the first transistor T1 may be formed on the same substrate. Matching the device parameters of the two transistors can facilitate matching the first mapping relationship and the second mapping relationship.

[0090] According to some embodiments, the sixth terminal and the second terminal may include terminals of the same type. The sixth terminal and the second terminal may include drains, or they may include sources. The sixth terminal and the second terminal may have the same or similar voltages. The sixth terminal may be coupled to a higher voltage signal, such as a voltage signal Vdd; the second terminal may have a higher voltage, such as a voltage at the same or similar potential as the voltage signal Vdd. The sixth terminal may be coupled to a lower voltage signal, such as ground, or coupled to a voltage signal Vss at the same or similar potential as ground; the second terminal may have a lower voltage, such as ground voltage, or a voltage at the same or similar potential as the voltage signal Vss. The voltage of the second terminal can be used to establish read or calculation conditions for the memory cell / memory circuit.

[0091] According to some embodiments, the second terminal of the first transistor T1 can be connected to a clamping circuit that clamps the voltage at the second terminal to a target voltage, which can be used to establish read or calculation conditions for the memory cell / memory circuit. The target voltage can be determined based on the type of the first transistor T1 and the type of the second terminal. For example, the first transistor T1 may include an n-type transistor, the second terminal may include a drain, and the target voltage may include a voltage with a higher potential, such as voltage Vdd. Alternatively, the first transistor T1 may include an n-type transistor, the second terminal may include a source, and the target voltage may include a voltage with a lower potential, such as ground voltage, voltage Vss, etc. The target voltage may be the same as or close to the voltage of the voltage signal coupled to the sixth terminal.

[0092] According to some embodiments, current can flow into the third transistor T3 from the fifth terminal and out from the sixth terminal, or current can flow into the third transistor T3 from the sixth terminal and out from the fifth terminal. The currents in the first transistor T1 and the third transistor T3 can have a corresponding flow direction relationship. For example, current flows into the third transistor T3 from the fifth terminal, and current flows into the first transistor T1 from the first terminal. For example, current flows into the third transistor T3 from the sixth terminal, and current flows into the first transistor T1 from the second terminal.

[0093] As an example, Figure 7 shows a schematic diagram of another input conversion circuit according to an exemplary embodiment of this application. As shown in Figure 7, according to some embodiments, the input conversion circuit 720 may include a plurality of third transistors T3, the fifth terminals of which are connected in parallel. The fifth terminals of the plurality of third transistors T3 may be connected to the first terminal of the first transistor T1, for example, directly or indirectly. The sixth terminals of the plurality of third transistors T3 may be respectively coupled to a bias signal Vb. For example, the sixth terminals of the plurality of third transistors T3 may be respectively connected to a constant voltage source or ground.

[0094] By introducing multiple third transistors T3, the impact of process variations can be averaged out, thereby reducing the influence of process variations on device performance. Multiple third transistors T3 can improve the driving capability of the input conversion circuit to the memory cells of the memory circuit, increase the load capacity of the input conversion circuit output, and allow it to support more memory cells.

[0095] The above input conversion circuit may include one or more conversion sub-circuits, which may include conversion units or a combination of conversion units and buffer circuits. One conversion sub-circuit may correspond to multiple memory cells, providing the second signal S2 to multiple memory cells. This allows for better adaptation to memory cell array structures, reducing the number of input signals and wiring data, resulting in a lower cost and a simpler circuit structure. Smaller circuit area or size enables optimized linear mapping of the in-memory computing device.

[0096] As an example, FIG8 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of the present application. As shown in FIG8, the in-memory computing system 800 may include an in-memory computing device 810 and a control circuit 820. Optionally, the in-memory computing system 800 may further include an input circuit 830 and an output circuit 840. The in-memory computing device 810 may include an input conversion circuit 811 and a storage circuit 812. The storage circuit 812 includes a plurality of storage cells, which may be arranged in an array, such as a one-dimensional, two-dimensional, or three-dimensional array. For example, taking the plurality of storage cells S11 to Smn arranged in an array along a first direction and a second direction as an example, wherein the first direction and the second direction intersect.

[0097] For example, the first direction may include a column direction, and the second direction may include a row direction; or, the first direction may include a row direction, and the second direction may include a column direction. The input conversion circuit 811 may include multiple conversion units 811-1 to 811-m. Conversion units 811-1 to 811-m may be arranged along the first direction, and the input terminals of storage units S11 to Sm1 arranged along the first direction are connected to conversion units 811-1 to 811-m via different input lines, while their output terminals are connected to the same output line. Conversion unit 811-i can convert the first signal S1-i into a second signal S2-i and input it to storage units Si1 to Sin. Storage unit Sij can convert the second signal S2-i into a third signal S3-i based on the stored weight data. Multiple storage units S1j to Smj can output the third signals S3-1 to S3-m on the same output line. The output signals are accumulated on the same output line, enabling multiplication operations, such as vector multiplication. Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Figure 8 shows an example with j=1, and the other columns are similar. In some other embodiments, the conversion units can be arranged along the second direction and provide a second signal to the storage cells arranged along the first direction. For example, conversion unit 811-j can convert the first signal S1-j into the second signal S2-j and input it to the storage cells S1j to Smj.

[0098] Furthermore, other relevant descriptions of the in-memory computing system 800 are as described above for the in-memory computing system 200, and will not be repeated here. According to some embodiments, the input circuit 830 may include a digital-to-analog converter (DAC), which may optionally include a voltage-type DAC or a current-type DAC; wherein the current-type DAC causes the input circuit 830 to output a current signal, which is converted into a voltage signal by the input conversion circuit 811 and output.

[0099] The following example uses an input conversion circuit that includes a conversion unit and a buffer circuit, wherein the conversion unit includes a third transistor and the buffer circuit includes an operational amplifier circuit with negative feedback connection, to describe the working process of the memory computing device under different working states.

[0100] For example, FIG9 shows a schematic diagram of an in-memory computing device according to an exemplary embodiment of the present application. FIG10 shows a schematic diagram of another in-memory computing device according to an exemplary embodiment of the present application.

[0101] As shown in Figure 9 or Figure 10, the input conversion circuit 910 may include a conversion sub-circuit 911, which includes a conversion unit 9111 and a buffer circuit 9112. The conversion unit 9111 may include a third transistor T3, the fifth terminal of which may be coupled to a first signal S1. The conversion unit 9111 can convert the first signal S1 into a second signal S2. The buffer circuit 9112 may include an operational amplifier, which may include a non-inverting input, an inverting input, and an output. The non-inverting input of the operational amplifier may be connected to the output of the conversion unit 9111, for example, to the fifth terminal of the third transistor T3, to receive the signal output by the conversion unit 9111. The inverting input of the operational amplifier may be connected to its output, which may be connected to the first terminal of the first transistor T1 to provide the second signal S2 to the first terminal of the first transistor T1. The input conversion circuit 910 may include multiple conversion sub-circuits 911 arranged along a first direction.

[0102] As shown in Figure 9 or Figure 10, the storage circuit 920 may include a storage cell array. The storage cell array may include multiple storage cells arranged in an array along a first direction and a second direction. The first direction may include a column direction, and the second direction may include a row direction; alternatively, the first direction may include a row direction, and the second direction may include a column direction. Although Figure 9 shows a portion of the rows and columns of the storage cell array, it is for illustrative purposes only, and the embodiments of this application are not limited thereto. The storage cell array may include more or fewer rows, and / or more or fewer columns. Furthermore, this application does not limit whether the number of rows and columns are equal. Taking the first direction including the column direction and the second direction including the row direction as an example, the number of rows m and the number of columns n of the storage cell array may be the same or different.

[0103] Taking the first direction as the column direction and the second direction as the row direction as an example: In the memory cell array: the first terminal of the first transistor T1 in the memory cell located in the same row is connected to the same input line among multiple input lines IN1-INm, and the first terminal of the first transistor T1 in memory cells located in different rows is connected to different input lines among multiple input lines IN1-INm. The second terminal of the first transistor T1 in the memory cell located in the same column is connected to the same output line among multiple output lines OUT1-OUTn. Additionally, as shown in Figure 9 or Figure 10, the second drive terminal of the second transistor T2 in the memory cell located in the same row is connected to the same control line among multiple control lines C1-Cm, and the third terminal of the second transistor T2 in the memory cell located in the same column is connected to the same write line (or programming line) among multiple write lines (or programming lines) W1-Wn; or, unlike what is shown in Figure 9 or Figure 10, the second drive terminal of the second transistor T2 in the memory cell located in the same column is connected to the same control line among multiple control lines, and the third terminal of the second transistor T2 in the memory cell located in the same row is connected to the same write line among multiple write lines.

[0104] Taking the first direction as the row direction and the second direction as the column direction as an example. In the memory cell array: the first terminal of the first transistor T1 in the memory cell located in the same column is connected to the same input line among multiple input lines, and the first terminal of the first transistor T1 in the memory cell located in different columns is connected to different input lines among multiple input lines. The second terminal of the first transistor T1 in the memory cell located in the same row is connected to the same output line among multiple output lines. In addition, as shown in FIG9 or FIG10, the second driving terminal of the second transistor T2 in the memory cell located in the same column is connected to the same control line among multiple control lines, and the third terminal of the second transistor T2 in the memory cell located in the same row is connected to the same write line among multiple write lines; or, different from that shown in FIG9 or FIG10, the second driving terminal of the second transistor T2 in the memory cell located in the same row is connected to the same control line among multiple control lines, and the third terminal of the second transistor T2 in the memory cell located in the same column is connected to the same write line among multiple write lines.

[0105] The conversion sub-circuit 911 can be connected to the input line. The conversion sub-circuit 911 can couple to a first signal S1, converting it into a second signal S2, and transmitting the second signal S2 to the first terminal of the first transistor T1 in the storage unit via the corresponding input line. The first signal S1 may include a current signal. The first signal S1 can be input to the conversion sub-circuit 911 via a pre-amplifier circuit. The pre-amplifier circuit may include a DAC, such as a current-mode DAC. The conversion unit 9111 can convert the first signal S1 and provide it to a buffer circuit 9112, which then stably outputs the second signal S2 to the corresponding input line of the conversion sub-circuit 911. The first transistor T1 in the storage unit can convert the second signal S2 into a third signal S3 based on stored weight data and output it. The second signal may include a voltage signal, and the third signal S3 may include a current signal.

[0106] During reading or calculation, the second transistor T2 of the storage cell in the storage circuit 920 is turned off. For example, the second drive terminal of the second transistor T2 of the storage cell can be coupled (e.g., coupled via a control line) to a cutoff voltage. The storage cell participating in the reading or calculation can be coupled to a read drive signal or a calculation input signal via a corresponding conversion sub-circuit 911. The read drive signal or calculation input signal may include a first signal S1, which is converted by the conversion sub-circuit 911 to obtain a second signal S2. The read drive signal can drive the corresponding storage cell to read the stored data, or the calculation input signal can drive the corresponding storage cell to output a corresponding output signal based on the weight data. The output signals of multiple storage cells are accumulated to obtain the calculation result.

[0107] Optionally, the memory computing device 900 can read data stored in one or more memory cells at once, for example, read data stored in multiple memory cells connected to the same input line at once. The memory computing device 900 can receive multiple first signals S1 through multiple conversion sub-circuits, convert the multiple first signals S1 into multiple second signals S2, and provide the multiple second signals S2 to the memory cell array through multiple input lines. The multiple input lines can transmit the second signals S2 to the first terminal of the first transistor T1 of the memory cell to which they are connected. The multiple first signals S1 can be all the same, partially the same, or all different. The multiple second signals S2 can be all the same, partially the same, or all different. The first transistor T1 of the memory cell converts the second signals S2 into a third signal S3 based on the stored weight data and outputs it. The third signals S3 output by the memory cells connected to the same output line can be accumulated on that output line to perform multiplication operations, such as vector multiplication.

[0108] For example, as shown in FIG9, the first terminal of the first transistor T1 may include a drain, and the second terminal may include a source; the fifth terminal of the third transistor T3 may include a drain, and the sixth terminal may include a source. The sixth terminal may be grounded or coupled to a low-potential voltage signal Vss. In the read state or the calculation state, a first signal S1 may be provided to the conversion sub-circuit connected to the target memory cell involved in the read or calculation. The first signal S1 is converted to obtain a second signal S2, which is provided to the drain of the target memory cell, so that the drain has a drain voltage. The first transistor T1 generates a current under the action of the drain voltage and the gate voltage. This current flows from the drain of the first transistor to the source, is collected or accumulated on the output line, enters the output circuit, and is output after being converted by the output circuit. The voltage on the output line can be clamped to a lower potential voltage, for example, the same as or similar to the voltage signal coupled to the sixth terminal. In addition, other related descriptions of the output circuit refer to the relevant content of the output circuit 240 above, and will not be repeated here.

[0109] For example, as shown in FIG10, the first terminal of the first transistor T1 may include the source and the second terminal may include the drain; the fifth terminal of the third transistor T3 may include the source and the sixth terminal may include the drain. The sixth terminal may be coupled to a high-potential voltage signal Vdd. In the read state or the calculation state, a first signal S1 may be provided to the conversion sub-circuit connected to the target memory cell involved in the read or calculation. The first signal S1 is converted to obtain a second signal S2, which is provided to the source of the target memory cell, so that the source has a source voltage. The first transistor T1 generates current under the action of the source voltage and the gate voltage. This current flows from the drain of the first transistor to the source. After being collected or accumulated on the output line, it enters the output circuit and is output after being converted by the output circuit. The voltage on the output line can be clamped to a higher potential voltage. For example, this voltage may be the same as or similar to the voltage signal coupled to the sixth terminal. In addition, other related descriptions of the output circuit refer to the relevant content of the output circuit 240 above, and will not be repeated here.

[0110] Figure 11 shows a flowchart of a control method according to an exemplary embodiment of this application. The control method can be used to control the operating state of a memory computing device, which may include an input conversion circuit and a storage circuit. Control method 1100 may include:

[0111] S1110: Controls the storage circuit to enter the first working state.

[0112] S1120: Provide a first signal S1 to the input conversion circuit, wherein the first signal S1 is converted into a second signal S2 and output by the input conversion circuit, wherein the second signal S2 and the first signal S1 have a first mapping relationship.

[0113] S1130: Obtain the output signal of the storage circuit. The output signal includes the cumulative output of the third signal S3 output by at least one storage cell of the storage circuit. The third signal S3 is converted and output by the corresponding storage cell based on the stored weight data of the second signal S2. There is a second mapping relationship between the second signal S2 and the third signal S3, and the mapping curves of the first mapping relationship and the second mapping relationship match.

[0114] For example, the first operating state may include a read state or a calculation state. In the read state, the in-memory computing device can be controlled to output a third signal S3, which represents the data stored in the storage unit. In the calculation state, the in-memory computing device can be controlled to output an accumulated signal of the third signal S3, which represents the calculation result of a set of storage units.

[0115] Figure 12 shows a flowchart of a control method according to an exemplary embodiment of this application. According to some embodiments, the control method 1200 includes the control method 1100 described above, and further includes:

[0116] S1210: Controls the storage circuit to enter the second working state;

[0117] S1220: In the second working state, the writing of weight data stored in the storage cell of the control storage circuit is performed.

[0118] The writing of weight data can be referred to the description in the above embodiments, and will not be repeated here.

[0119] This application embodiment may also provide a control device, which may include units or means for implementing any of the above control methods. For example, FIG13 shows a schematic diagram of a control device according to an exemplary embodiment of this application. As shown in FIG13, the control device 1300 may include a processing unit 1310 and an interface unit 1320. The processing unit 1310 is used to control the operating state of the storage circuit, and the interface unit 1320 is used to signal connect with the storage circuit. For example, the processing unit 1310 is used to control the storage circuit to enter a first operating state or a second operating state. Furthermore, in the first operating state, the processing unit 1310 is used to provide a first signal to the input conversion circuit through the interface unit 1320 to obtain an output signal from the storage circuit. Also, in the second operating state, the processing unit 1310 is used to control the writing of weight data stored in the storage cells of the storage circuit, etc.

[0120] It should be understood that the above division of units is only a logical functional division. In actual implementation, all or part of them can be integrated into a single physical entity, or they can be physically separated. Furthermore, the above units can be implemented in the form of a processor calling software; for example, a control device may include a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above control methods. The memory can be internal to the control device or external to it. Alternatively, the above units can be implemented in the form of hardware circuits. The functions of some or all units can be achieved through the design of the hardware circuits, which can be understood as one or more processing circuits. For example, in some embodiments, the hardware circuit may include an application-specific integrated circuit (ASIC), which implements the functions of some or all of the above units through the design of the logical relationships between the devices within the circuit. Furthermore, in some embodiments, the hardware circuit can be implemented using a programmable logic device (PLD) circuit, which may include a large number of logic devices. The logical relationships between the logic devices are configured through a configuration file, thereby achieving the functions of some or all of the above units. The above control devices can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0121] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, including, for example, a central processing unit (CPU), a microcontroller unit (MCU), a graphics processing unit (GPU), or a digital signal processor (DSP). Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0122] In some possible embodiments, the units in the above control device may be integrated in whole or in part, or may be implemented independently. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC).

[0123] This application also provides a control device, which may be located within or include the above-described control circuit. The control device may be located within the control circuit 120 / 220 shown in FIG. 1 or FIG. 2, or may be independent of the control circuit 120 / 220. This control device can be used to execute any of the above-described control methods.

[0124] This application also provides a control device, as shown in FIG14. FIG14 shows a schematic diagram of a control device according to an exemplary embodiment of this application. As shown in FIG14, the control device 1400 includes: at least one processing circuit 1410 and an interface circuit 1420, the interface circuit 1420 being used for signal connection with a memory computing device, and at least one processing circuit 1410 being used for executing any of the control methods provided in the above embodiments.

[0125] This application also provides a memory computing system, which may include any of the above-mentioned memory computing devices and a control device. The control device is used to control the operating state of the memory computing device.

[0126] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0127] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause any of the control methods described in the above embodiments to be executed.

[0128] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0129] This application also provides an electronic device, as shown in FIG15. FIG15 illustrates a schematic diagram of an electronic device according to an exemplary embodiment of this application. As shown in FIG15, the electronic device 1500 may include any of the above-described in-memory computing systems 1510 for processing data of the electronic device. The electronic device may also include an input / output device 1520 for receiving user input or outputting processing results. This application does not limit the input type and output type. For example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 1530, which may process data provided to the in-memory computing system 1510 or process output data of the in-memory computing system 1510. The output of the input / output device 1520 may be based on the output of the processor 1530 or the output of the in-memory computing system 1510.

[0130] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0131] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A storage computing device, characterized in that, include: An input conversion circuit is used to receive a first signal and convert the first signal into a second signal for output, wherein the second signal and the first signal have a first mapping relationship. A storage circuit is connected to the input conversion circuit. The storage circuit includes a storage unit for receiving the second signal and converting the second signal into a third signal based on the weight data stored in the storage unit. The second signal and the third signal have a second mapping relationship. The mapping curves of the first mapping relationship and the second mapping relationship match.

2. The storage and computing device according to claim 1, characterized in that, The input conversion circuit is also used to receive a reference signal and convert the first signal into the second signal based on the reference signal for output.

3. The storage and computing device according to claim 2, characterized in that, The storage unit includes: The first transistor includes a first terminal, a second terminal, and a first driving terminal; The second transistor includes a third terminal, a fourth terminal, and a second driving terminal, wherein the fourth terminal is connected to the first driving terminal, the charge at the first driving terminal is used for storing the weight data of the storage cell, and the second driving terminal is used to control the on or off state of the second transistor, and when the second transistor is on, the weight data is written. The input conversion circuit includes a conversion unit, which includes a third transistor, a fifth terminal, a sixth terminal, and a third driving terminal. The third driving terminal is used to couple the reference signal, and the fifth terminal is used to couple the first signal and is connected to the first terminal.

4. The storage and computing device according to claim 3, characterized in that, The reference signal is determined based on the following factors: the voltage range of the first driving terminal, the weight distribution of the model used by the storage circuit for calculation, the distribution of the weight data stored in the storage circuit, or the weight data stored in the storage unit.

5. The storage device according to claim 3 or 4, characterized in that, The first signal includes a current signal, the second signal includes a voltage signal, and the third signal includes a current signal.

6. The storage device according to any one of claims 3 to 5, characterized in that, The device parameters of the third transistor are matched with those of the first transistor.

7. The storage device according to any one of claims 3 to 6, characterized in that, The sixth terminal is grounded or connected to a constant voltage source.

8. The storage device according to any one of claims 3 to 7, characterized in that, The conversion unit includes a plurality of third transistors, the fifth terminals of the plurality of third transistors are connected in parallel and connected to the first terminal of the first transistor, and the sixth terminals of the plurality of third transistors are respectively connected to a constant voltage source or ground.

9. The storage device according to any one of claims 3 to 8, characterized in that, The input conversion circuit includes: A buffer circuit is connected between the conversion unit and the storage unit.

10. The memory computing device according to claim 9, characterized in that, The buffer circuit is also used to amplify the power of the output of the conversion unit.

11. The storage device according to any one of claims 1 to 10, characterized in that, The input conversion circuit includes multiple conversion sub-circuits; The storage circuit includes multiple storage cells, and the second terminals of the multiple storage cells are connected to the same output line; The first terminals of the plurality of storage units are connected to the plurality of conversion sub-circuits respectively through multiple input lines.

12. A control method, characterized in that, The method for controlling a memory computing device, the memory computing device including an input conversion circuit and a storage circuit, includes: The storage circuit is controlled to enter the first working state; A first signal is provided to the input conversion circuit, wherein the first signal is converted into a second signal output by the input conversion circuit, and wherein the second signal and the first signal have a first mapping relationship; The output signal of the storage circuit is obtained. The output signal includes the cumulative output of a third signal output by at least one storage cell of the storage circuit. The third signal is converted and output by the corresponding storage cell based on the stored weight data of the second signal. There is a second mapping relationship between the second signal and the third signal, and the mapping curves of the first mapping relationship and the second mapping relationship match.

13. The control method according to claim 12, characterized in that, Also includes: The storage circuit is controlled to enter the second operating state; In the second operating state, the writing of weight data stored in the storage unit of the storage circuit is controlled.

14. A control device, characterized in that, It includes an interface circuit and a processing circuit, wherein the interface circuit is signal-connected to the in-memory computing device, and the processing circuit is used to execute the control method as described in claim 12 or 13.

15. An in-memory computing system, characterized in that, include: The storage device according to any one of claims 1-11; A control device is used to control the operating state of the in-memory computing device.

16. An electronic device, characterized in that, Includes the storage device according to any one of claims 1-11 or the storage system according to claim 15.

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