Display panel and display device
By reducing the density of isolation pillars between the display area and the common electrode overlap ring in the OLED display panel, and setting an isolation pillar ring around the display area, the problem of uneven touch traces caused by excessive isolation pillar density is solved, thereby improving the yield and performance of the display panel.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-07-30
AI Technical Summary
In the manufacturing process of existing OLED display panels, excessively high density of isolation pillars leads to uneven touch traces in the touch functional layer, affecting the yield and performance of the display panel.
By reducing the density of isolation pillars between the display area and the common electrode overlap ring, and by setting the distance between the first isolation pillar and the common electrode overlap ring to be smaller than the distance of the display area, an isolation pillar ring is formed around the display area. This reduces the impact of the isolation pillars on the organic encapsulation layer, ensures the surface flatness of the thin film encapsulation layer, and thus improves the uniformity of the touch traces.
It improves the yield and performance of display panels, reduces process costs, minimizes the adverse effects on touch traces, and enhances the reliability and image quality of display panels.
Smart Images
Figure CN2026071967_30072026_PF_FP_ABST
Abstract
Description
Display panel and display device
[0001] Cross-references
[0002] This disclosure claims priority to Chinese Patent Application No. 202510115035.8, filed on January 23, 2025, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field
[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology
[0004] As consumers increasingly demand better viewing angles and spend more time on electronic products, the requirements for image quality, reliability, and durability of OLED panels are becoming more stringent. Photo spacers (PS) are crucial structures that support the precision metal photomask during the fabrication of OLED display panels.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device that improves the uniformity of touch traces in the touch function layer by reducing the density of isolation pillars outside the display area, thereby improving the yield of the display panel.
[0007] According to one aspect of this disclosure, a display panel is provided, including a display area and a peripheral area; the display panel has isolation pillars.
[0008] The peripheral area has a common electrode overlap ring surrounding the display area, and the density of the isolation pillars between the common electrode overlap ring and the display area is less than the density of the isolation pillars in the display area.
[0009] In one exemplary embodiment of this disclosure, the isolation post is not provided between the common electrode overlap ring and the display area.
[0010] In one exemplary embodiment of this disclosure, the isolation post includes a first isolation post located between the common electrode overlap ring and the display area;
[0011] The distance between the first isolation post and the common electrode overlap ring is less than the distance between the first isolation post and the display area.
[0012] In one exemplary embodiment of this disclosure, the distance between the first isolation post and the common electrode overlap ring does not exceed 0.1 times the distance between the first isolation post and the display area.
[0013] In one exemplary embodiment of this disclosure, the distance between the first isolation post and the common electrode overlap ring is between 1 and 10 micrometers.
[0014] In one exemplary embodiment of this disclosure, the first isolation pillars are arranged in an isolation pillar ring surrounding the display area; the distance between each of the first isolation pillars and the common electrode overlap ring is equal.
[0015] In one exemplary embodiment of this disclosure, the display area has a straight edge and a rounded edge located between two adjacent straight edges, and the center-to-center distance between two adjacent first isolation pillars near the straight edge is equal to the center-to-center distance between two adjacent first isolation pillars near the rounded edge.
[0016] In one exemplary embodiment of this disclosure, the display area has a straight edge and a rounded edge located between two adjacent straight edges, and the center-to-center distance between two adjacent first isolation pillars near the straight edge is not equal to the center-to-center distance between two adjacent first isolation pillars near the rounded edge.
[0017] In one exemplary embodiment of this disclosure, the isolation pillar further includes a second isolation pillar, which is at least partially located within the display area;
[0018] The area of the top of the first isolation post is smaller than the area of the top of the second isolation post, and the distance between adjacent first isolation posts is smaller than the distance between adjacent second isolation posts.
[0019] In one exemplary embodiment of this disclosure, the isolation pillar further includes a second isolation pillar, which is at least partially located within the display area;
[0020] The area of the top of the first isolation post is greater than the area of the top of the second isolation post, and the distance between adjacent first isolation posts is greater than the distance between adjacent second isolation posts.
[0021] In one exemplary embodiment of this disclosure, the display area includes multiple sub-pixel rows, and any one sub-pixel row includes multiple sub-pixels arranged sequentially along the row direction;
[0022] Wherein, at least one sub-pixel row includes multiple sub-pixel groups arranged sequentially in the same row, and the sub-pixel group includes one red sub-pixel, two green sub-pixels and one blue sub-pixel;
[0023] The display panel is provided with a second isolation pillar between the red and blue subpixels of at least a portion of the subpixel groups.
[0024] In one exemplary embodiment of this disclosure, the display panel includes a substrate, a driving layer, a pixel layer, a thin film encapsulation layer, and a touch function layer stacked sequentially.
[0025] The pixel layer includes a pixel electrode layer, a pixel definition layer, and an isolation pillar layer stacked sequentially on the driving layer, wherein the isolation pillar layer is provided with the isolation pillars.
[0026] In one exemplary embodiment of this disclosure, the thin-film encapsulation layer has an organic encapsulation layer, and the touch functional layer has touch wiring;
[0027] The isolation pillar includes a first isolation pillar, which is located between the common electrode overlap ring and the display area;
[0028] The organic encapsulation layer covers the first isolation pillar; at least a portion of the touch traces overlap with the first isolation pillar.
[0029] In one exemplary embodiment of this disclosure, the first isolation pillar has the same shape when projected onto the substrate.
[0030] In one exemplary embodiment of this disclosure, at least two of the first isolation pillars have different shapes in their orthographic projections onto the substrate.
[0031] In one exemplary embodiment of this disclosure, the isolation pillar further includes a second isolation pillar, which is at least partially located within the display area;
[0032] The second isolation pillar has the same shape when projected onto the substrate.
[0033] In one exemplary embodiment of this disclosure, the isolation pillar further includes a second isolation pillar, which is at least partially located within the display area;
[0034] In the orthographic projection of the second isolation pillar onto the substrate, at least two of the second isolation pillars have different shapes.
[0035] In one exemplary embodiment of this disclosure, the orthographic projection of the first isolation pillar on the substrate is a circle, an ellipse, a square, a rectangle, a square with rounded corners, a rectangle with rounded corners, a hexagon, and / or an octagon.
[0036] The orthographic projection of the second isolation pillar onto the substrate is a circle, ellipse, square, rectangle, rounded square, rounded rectangle, hexagon, and / or octagon.
[0037] In one exemplary embodiment of this disclosure, the common electrode overlap ring is provided with an exhaust hole;
[0038] The isolation column layer is provided with auxiliary isolation columns, which are arranged around the exhaust holes.
[0039] According to another aspect of this disclosure, a display device is also provided, including the aforementioned display panel.
[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0042] Figure 1 is a top view of the display panel in one embodiment of this disclosure.
[0043] Figure 2 is a cross-sectional schematic diagram of the display panel in one embodiment of this disclosure.
[0044] Figure 3 is a schematic diagram of the arrangement of isolation columns in a display panel in related technologies.
[0045] Figure 4 is a schematic diagram of the arrangement of isolation columns in a display panel according to one embodiment of the present disclosure.
[0046] Figure 5-1 is a magnified view of a portion of region 100 in Figure 4.
[0047] Figure 5-2 is a schematic diagram of the auxiliary isolation column on the common electrode overlap ring in one embodiment of this disclosure.
[0048] Figure 6 is a schematic diagram of the shape of the first isolation column or the second isolation column in one embodiment of this disclosure.
[0049] Figure 7 is a schematic diagram of a four-point rectangular array of the second isolation column in one embodiment of this disclosure.
[0050] Figure 8 is a schematic diagram of an eight-point square array of the second isolation column in one embodiment of this disclosure.
[0051] Figure 9 is a schematic diagram of the rotating rhomboid array of the second isolation column in one embodiment of this disclosure.
[0052] Figure 10 is a schematic diagram of a rotating square array of second isolation columns in one embodiment of this disclosure.
[0053] Figure 11 is a schematic diagram of the isolation column layout of the display panel in one embodiment of the present disclosure.
[0054] Figure 12 is a schematic diagram of the arrangement of isolation columns in a display panel according to one embodiment of the present disclosure.
[0055] The reference numerals in the attached figures are as follows: AA, Display area; BB, Peripheral area; BUF, Inorganic buffer layer; CFL, Color filter layer; COML, Common electrode layer; CVD1, First inorganic encapsulation layer; CVD2, Second inorganic encapsulation layer; DBP, Driving backplane; DRL, Driving layer; EFL, Emitting light layer; FMM, Fine metal mask; GI, Gate insulating layer; GT, Gate layer; IJP, Organic encapsulation layer; ILD, Interlayer dielectric layer; L1, First pitch; L2, Second pitch; LD, Light-emitting element; PDL, Pixel definition layer; PEL, Pixel electrode layer; PIXL, Pixel layer; PLN, Planarization layer. PNL, Display Panel; PS, Isolation Pillar; PS1, First Isolation Pillar; PS2, Second Isolation Pillar; PS21, Display Area Isolation Pillar; PS22, Display Area Boundary Isolation Pillar; PS3, Auxiliary Isolation Pillar; PSL, Isolation Pillar Layer; RR, Common Electrode Overlap Ring; SBT, Substrate; SCL, Semiconductor Layer; SD, Source / Drain Metal Layer; TFE, Thin Film Encapsulation Layer; TFT, Thin Film Transistor; TSL, Touch Functional Layer; VH, Exhaust Hole; RPIX, Red Subpixel; GPIX, Green Subpixel; BPIX, Blue Subpixel; 300, Subpixel Group; DH, Row Direction. Detailed Implementation
[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0057] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” etc. are used only as markers and are not a limitation on the number of objects.
[0058] In this disclosure, when describing the overlapping arrangement of structure A and structure B, it means that structure A and structure B are disposed on different film layers, and the orthographic projection of structure A on the substrate overlaps with the orthographic projection of structure B on the substrate.
[0059] In this disclosure, the overlapping portion of structure C and structure D refers to a specific portion C1 in structure C; the orthographic projection of this specific portion C1 on the substrate is the overlapping portion of the orthographic projection of structure C on the substrate and the orthographic projection of structure D on the substrate.
[0060] In this disclosure, structural layer E is located on the side of structural layer F away from the substrate. This can be understood as structural layer E being formed on the side of structural layer F away from the substrate. When structural layer F is a patterned structure, some structures of structural layer E may also be located at the same physical height as structural layer E or below the physical height of structural layer E, wherein the substrate serves as the height reference.
[0061] This disclosure provides a display panel PNL, as shown in FIG1. The display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with sub-pixels for display; in the peripheral area BB, the display panel PNL may not be provided with sub-pixels for display, or the provided sub-pixels may not be used for displaying images.
[0062] In this embodiment of the disclosure, the sub-pixels in the display panel PNL are thin-film self-emissive light-emitting elements (LDs), such as OLED, PLED, QLED, etc. Furthermore, the light-emitting elements (LDs) located in the display area AA include various light-emitting elements (LDs) of different colors. For example, the light-emitting elements (LDs) include red light-emitting elements for emitting red light, blue light-emitting elements for emitting blue light, and green light-emitting elements for emitting green light. It is understood that in other embodiments of this disclosure, the light-emitting elements (LDs) in the display area AA may also be of only one color, or may include light-emitting elements (LDs) of other colors (e.g., yellow light-emitting elements for emitting yellow light, cyan light-emitting elements for emitting cyan light, white light-emitting elements for emitting white light, etc.).
[0063] In one embodiment of this disclosure, referring to FIG2, the display panel PNL may include a driving backplane DBP and a pixel layer PIXL stacked sequentially. The pixel layer PIXL contains light-emitting elements (LDs), and the driving backplane DBP drives the light-emitting elements LDs in the pixel layer PIXL. The driving backplane DBP may drive each light-emitting element LD using either an active driving method or a passive driving method.
[0064] In one embodiment of this disclosure, referring to FIG2, the driving backplane DBP includes a substrate SBT and a driving layer DRL disposed on one side of the substrate SBT; the pixel layer PIXL is disposed on the side of the driving layer DRL away from the substrate SBT. The driving layer DRL is provided with a pixel driving circuit for driving light-emitting elements LD; each light-emitting element LD can emit light under the drive of the pixel driving circuit to display an image. Furthermore, the display panel PNL also includes a thin film encapsulation layer TFE located on the side of the pixel layer PIXL away from the driving backplane DBP, and the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.
[0065] Optionally, the substrate SBT can be an inorganic material substrate or an organic material substrate; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrates. For example, in some embodiments of this disclosure, the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass. In other embodiments of this disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof. In other embodiments of this disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT may include polyimide.
[0066] Optionally, in the driving layer DRL, any pixel driving circuit may include a thin-film transistor (TFT) and a storage capacitor. Further, the TFT can be selected from top-gate, bottom-gate, or dual-gate TFTs; the active layer of the TFT can be made of amorphous silicon, low-temperature polycrystalline silicon, metal-oxide-semiconductor, organic semiconductor, carbon nanotube, or other types of semiconductor materials; the TFT can be an N-type or P-type TFT.
[0067] It is understood that any two transistors in a pixel driving circuit can be of the same or different types. Exemplarily, in some embodiments, some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors. Further exemplarily, in other embodiments, in a pixel driving circuit, the active layer material of some transistors can be low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer material of some transistors can be metal-oxide-semiconductor (MODS) semiconductor material. In some embodiments of this disclosure, the thin-film transistor is a LPS transistor. In other embodiments of this disclosure, some thin-film transistors are LPS transistors, and some thin-film transistors are MODS transistors.
[0068] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN, stacked between the substrate SBT and the pixel layer PIXL. Each thin-film transistor and storage capacitor can be formed from the semiconductor layer SCL, gate insulating layer GI, gate layer GT, interlayer dielectric layer ILD, and source / drain metal layer SD. The positional relationship of each layer can be determined based on the thin-film transistor's layer structure. Further, the semiconductor layer SCL can be used to form the channel region of the transistor, and can also be used to form partial traces or conductive structures if necessary. The gate layer can be used to form one or more gate layer traces such as scan traces, reset control traces, and light emission control traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer can be used to form data traces, drive power supply voltage traces, or other source / drain metal layer traces, or it can be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of this disclosure, the driving layer DRL may also include other film layers as needed, such as a light-shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any one of the above-mentioned semiconductor layer SCL, gate layer GT, source / drain metal layer SD may be multiple layers. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Correspondingly, the insulating film layers in the driving layer DRL (such as gate insulating layer GI, interlayer dielectric layer ILD, planarization layer PLN, etc.) may be increased or decreased adaptively, or new insulating film layers may be added as needed.
[0069] Optionally, the driving layer DRL may also include a passivation layer, which may be disposed on the surface of the source / drain metal layer SD away from the substrate SBT, in order to protect the source / drain metal layer SD.
[0070] As an example, referring to Figure 2, the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked sequentially, thus forming a top-gate thin-film transistor.
[0071] It is understood that the above examples of the driving backplane DBP are merely one possible embodiment of the driving backplane DBP in this disclosure. In other embodiments of this disclosure, the driving backplane DBP may also have other structures, such as a passive driving glass substrate, a silicon-based driving substrate, etc.
[0072] In this example, referring to Figure 2, the pixel layer PIXL can be disposed on the side of the driving layer DRL away from the substrate SBT. It can include a pixel electrode layer PEL, a pixel definition layer PDL, an isolation pillar layer PSL, a light-emitting functional layer EFL, and a common electrode layer COML stacked sequentially. The pixel electrode layer PEL has multiple pixel electrodes in the display area of the display panel PDL. The pixel definition layer PDL has multiple through-holes in the display area, each corresponding to one of the pixel electrodes, with each pixel opening exposing at least a portion of the corresponding pixel electrode. The isolation pillar layer PSL includes multiple isolation pillars PS, located on the surface of the pixel definition layer PDL away from the substrate SBT, to support a fine metal mask (FMM) during the evaporation process. The light-emitting functional layer EFL at least covers the pixel electrodes exposed by the pixel definition layer PDL. The light-emitting functional layer EFL can include an organic electroluminescent material layer, and can include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer. The individual layers of the light-emitting functional layer (EFL) can be fabricated using a vapor deposition process, and a fine metal mask or an open mask can be used to define the pattern of each layer during vapor deposition. A common electrode layer (COML) can cover the EFL in the display area. Thus, the pixel electrode, the common electrode layer (COML), and the EFL located between the pixel electrode and the common electrode layer (COML) form an organic light-emitting diode (OLED), and any one of these OLEDs can serve as a sub-pixel of the display panel. One of the pixel electrode and the common electrode layer (COML) serves as the anode of the light-emitting element (LD), and the other serves as the cathode of the LD.
[0073] In one example, the pixel electrode serves as the anode of the light-emitting element LD, and the common electrode layer COML serves as the cathode of the light-emitting element LD.
[0074] Optionally, referring to Figure 2, the thin-film encapsulation layer TFE can be disposed on the surface of the pixel layer PIXL away from the substrate SBT, and it can include alternately stacked inorganic encapsulation layers and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing material aging in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer can be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT.
[0075] In some embodiments of this disclosure, referring to FIG2, the display panel PNL may further include a touch function layer TSL, which may be disposed on the side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel PNL has touch function.
[0076] In some embodiments of this disclosure, referring to FIG2, the display panel PNL may further include a color filter layer CFL, which may be disposed on the side of the thin film encapsulation layer TFE away from the driving backplane DBP to reduce reflection of ambient light and improve display quality.
[0077] As shown in Figure 3, in the related technology, the density of isolation pillars PS in the area between the display area AA and the common electrode overlap ring RR is comparable to the density of isolation pillars PS within the display area AA. The orthographic projections of the touch functional layer TSL, the isolation pillars PS, and the common electrode overlap ring RR onto the substrate SBT are all within the orthographic projection range of the thin-film encapsulation layer TFE onto the substrate SBT. Between the display area AA and the common electrode overlap ring RR, the touch functional layer TSL is used to form touch traces. The presence of numerous isolation pillars PS between the display area AA and the common electrode overlap ring RR causes the overlapping portion of the thin-film encapsulation layer TFE and the isolation pillars to bulge during the leveling of the organic encapsulation layer IJP that forms the thin-film encapsulation layer TFE. This results in an uneven surface on the side of the thin-film encapsulation layer TFE away from the substrate SBT. When the touch functional layer TSL is formed on the side of the thin-film encapsulation layer TFE away from the substrate SBT, the metal layer used to form the touch traces (before patterning) is also uneven. When patterning the metal layer that forms the touch traces, the thickness of the photoresist applied is inconsistent, which causes the thickness and width of the exposed pattern to be inconsistent with the preset, resulting in inconsistent width of the touch traces after etching, or even open circuits.
[0078] To address the aforementioned issues, this disclosure provides a display panel PNL. Referring to FIG4, the display panel PNL has isolation pillars PS for supporting a fine metal mask FMM; the peripheral area BB has a common electrode overlap ring RR surrounding the display area AA, and the density of the isolation pillars PS between the common electrode overlap ring RR and the display area AA is less than the density of the isolation pillars PS in the display area AA.
[0079] In this embodiment, the density of isolation pillars (PS) in the display area AA is high, while the density of isolation pillars (PS) outside the display area AA (the area between the display area AA and the common electrode overlap ring RR) is low. By reducing the density of isolation pillars (PS) outside the display area AA while ensuring support for the fine metal mask (FMM), the impact of the isolation pillars (PS) on the leveling of the organic encapsulation layer (IJP) is reduced. This allows the thin-film encapsulation layer (TFE) to form a relatively flat surface on the side away from the pixel layer (PIXL), providing a good planar foundation for the touch traces in the touch functional layer (TSL). Thus, a large flat surface area for the touch traces in the touch functional layer (TSL) can be provided without the need for an additional planarization layer (PLN), reducing the impact on the patterning of the touch traces and improving the yield and performance of the display panel (PNL). Simultaneously, it also reduces the number of photomasks, lowering the process cost.
[0080] In one embodiment of this disclosure, the isolation pillar PS includes a first isolation pillar PS1, which is located between the common electrode overlap ring RR and the display area AA; the thin-film encapsulation layer TFE has an organic encapsulation layer IJP, and the touch functional layer TSL has touch traces; the organic encapsulation layer IJP covers the first isolation pillar PS1; at least a portion of the touch traces overlap with the first isolation pillar PS1. In this embodiment, by covering the first isolation pillar PS1 with the organic encapsulation layer IJP, the surface flatness of the thin-film encapsulation layer TFE on the side away from the substrate SBT is further improved, avoiding inconsistencies in thickness or width during the fabrication of the touch traces, which could adversely affect the touch function.
[0081] In one embodiment of this disclosure, as shown in FIG5-1, which is an enlarged schematic diagram of region 100 indicated in FIG4, the distance between the first isolation pillar PS1 and the common electrode overlap ring RR is less than the distance between the first isolation pillar PS1 and the display area AA. That is, the orthographic projection of the first isolation pillar PS1 on the substrate SBT is located between the orthographic projection of the common electrode overlap ring RR on the substrate SBT and the orthographic projection of the display area AA on the substrate SBT. The distance from the orthographic projection of the first isolation pillar PS1 on the substrate SBT to the orthographic projection of the common electrode overlap ring RR on the substrate SBT is a first spacing L1, and the distance from the orthographic projection of the first isolation pillar PS1 on the substrate SBT to the orthographic projection of the display area AA on the substrate SBT is a second spacing L2, satisfying that the second spacing L2 is greater than the first spacing L1.
[0082] In one embodiment of this disclosure, the distance between the first isolation pillar PS1 and the common electrode overlap ring RR does not exceed 0.1 times the distance between the first isolation pillar PS1 and the display area AA. That is, as shown in Figure 5-1, the second spacing L2 is greater than or equal to 10*L1 (the first spacing). During the leveling process of the organic encapsulation layer IJP, the leveling proceeds from the display area AA to the peripheral area BB; without setting the first isolation pillar PS1 within a range of not less than 10*L1 (the first spacing) from the display area AA, the influence of the ink of the organic encapsulation layer IJP on the first isolation pillar PS1 during the leveling process can be further reduced, thereby reducing the impact on the patterning of the touch traces.
[0083] In one example, the distance between the first isolation pillar PS1 and the common electrode overlap ring RR is between 1 and 10 micrometers. Thus, by positioning the first isolation pillar PS1 as far away from the display area AA as possible and avoiding overlap with the common electrode overlap ring RR, the impact on other structures (such as organic encapsulation layers and touch traces) can be minimized while providing support for the precision metal mask. Positioning the first isolation pillar PS1 close to the common electrode overlap ring RR significantly reduces the risk of the precision metal mask scraping against the common electrode overlap ring RR.
[0084] Optionally, the common electrode overlap ring RR is provided with a vent hole VH. In this way, the gas generated by the planarization layer PLN can be discharged through the vent hole VH, avoiding defects caused by gas accumulation in the planarization layer PLN.
[0085] Optionally, as shown in Figure 5-2, the isolation column layer PSL is also provided with an auxiliary isolation column PS3 surrounding the exhaust port VH. The auxiliary isolation column PS3 is arranged around the exhaust port VH, which can, on the one hand, avoid blocking the exhaust port VH and ensure the effective discharge of the gas generated by the organic layer; on the other hand, it can reduce the obstruction of the common electrode lap ring RR, so that more area of the common electrode lap ring RR is exposed, increasing the contact area between the common electrode lap ring RR and the common electrode, and reducing the contact resistance between the common electrode lap ring RR and the common electrode.
[0086] In one embodiment of this disclosure, the shape of the first isolation post PS1 can be circular (Fig. 6A), elliptical (Fig. 6B), square (Fig. 6C), rectangular (Fig. 6D), a square with rounded corners (Fig. 6E), a rectangle with rounded corners (Fig. 6F), hexagonal (Fig. 6G), or octagonal (Fig. 6H). It is understood that the first isolation post PS1 at different locations can have the same shape or different shapes.
[0087] In one embodiment of this disclosure, as shown in FIG4, the first isolation pillars PS1 are arranged in an isolation pillar ring surrounding the display area AA; the distance between each of the first isolation pillars PS1 and the common electrode overlap ring RR is equal. That is, each of the first isolation pillars PS1 forms an isolation pillar ring surrounding the display area AA, and the spacing between each of the first isolation pillars PS1 in the isolation pillar ring and the common electrode overlap ring RR is equal on the orthogonal projection of the substrate SBT. In this way, uniform support for the fine metal mask FMM can be achieved. At the same time, by retaining only one isolation pillar ring, the density of the first isolation pillars PS1 between the display area AA and the common electrode overlap ring RR is reduced, further reducing the impact of the first isolation pillars PS1 on the touch traces of the touch functional layer TSL, and improving the yield of the display panel PNL.
[0088] In one example, the display area AA has straight edges and rounded edges located between two adjacent straight edges. The center-to-center distance between two adjacent first isolation pillars PS1 near the straight edges is equal to the center-to-center distance between two adjacent first isolation pillars PS1 near the rounded edges.
[0089] In another example, the display area AA has straight edges and rounded edges between two adjacent straight edges. The center-to-center distance between two adjacent first isolation pillars PS1 near the straight edges is not equal to the center-to-center distance between two adjacent first isolation pillars PS1 near the rounded edges. The spacing of the first isolation pillars PS1 can be adaptively adjusted according to the actual situation.
[0090] In one embodiment of this disclosure, the isolation pillar PS further includes a second isolation pillar PS2, which is at least partially located within the display area AA. For example, referring to Figures 7-10, the second isolation pillar PS2 includes a display area isolation pillar PS21 and a display area boundary isolation pillar PS22. The display area isolation pillar PS21 is located within the display area AA, and a portion of the display area boundary isolation pillar PS22 is located within the display area AA, while another portion is located on the boundary of the display area AA. Since the display area boundary isolation pillar PS22 is located on the boundary of the display area AA, the distance between the first isolation pillar PS1 and the display area AA can be the distance between the first isolation pillar PS1 and the adjacent display area boundary isolation pillar PS22.
[0091] In one embodiment of this disclosure, the shape of the second isolation post PS2 can also be circular (Fig. 6A), elliptical (Fig. 6B), square (Fig. 6C), rectangular (Fig. 6D), a square with rounded corners (Fig. 6E), a rectangle with rounded corners (Fig. 6F), hexagonal (Fig. 6G), or octagonal (Fig. 6H). It is understood that the second isolation posts PS2 at different locations can have the same shape or different shapes.
[0092] In some embodiments, the second isolation pillars PS2 located in the display area AA are arranged in an array. Exemplary examples include an eight-point square array or an eight-point rectangular array (as shown in Figure 8, a square array composed of 8 second isolation pillars PS2), a four-point square array or a four-point rectangular array (as shown in Figure 7, a rectangular array composed of 4 second isolation pillars PS2), a rotated square array or rectangular array (as shown in Figure 10, a square array composed of 4 second isolation pillars PS2, where the side length of the rectangle or square formed is not parallel to the boundary of the display area AA), a rotated rhombus (as shown in Figure 9, a rhombus array composed of 4 second isolation pillars PS2), or a rotated parallelogram. Figure 7 is a partial enlarged view of region 200 in Figure 4, and the dashed lines in Figures 7-10 represent the boundary of the display area AA.
[0093] In one embodiment of this disclosure, as shown in FIG11, the AA includes multiple sub-pixel rows, and any sub-pixel row includes multiple sub-pixels arranged sequentially along the row direction DH. At least one sub-pixel row includes multiple sub-pixel groups 300 arranged sequentially in the same row. Each sub-pixel group 300 includes one red sub-pixel RPIX, two green sub-pixels GPIX, and one blue sub-pixel BPIX. Between at least a portion of the red sub-pixel RPIX and the blue sub-pixel BPIX of the sub-pixel group 300, the display panel PNL is provided with a second isolation pillar PS2. In other embodiments, the second isolation pillar PS2 may also be provided within the display area AA according to the support requirements of the display area AA and the arrangement of the pixel electrodes.
[0094] It is worth noting that the subpixels in a pixel row can be arranged in a straight line along the row direction DH, or they can be arranged alternately along the row direction DH. For example, in Figure 11, the subpixels in a pixel row are arranged alternately along the row direction DH. The red subpixel RPIX and the blue subpixel BPIX are arranged to form a sub-subpixel row, and the green subpixel GPIX forms another sub-subpixel row. The extension lines of the two sub-subpixel rows are parallel and do not overlap; a green subpixel GPIX is positioned between the red subpixel RPIX and the blue subpixel BPIX. Furthermore, the pixel driving circuits of each subpixel in the pixel row are arranged in a straight line. In one example, the area of the top of the first isolation pillar PS1 is smaller than the area of the top of the second isolation pillar PS2, and the spacing between adjacent first isolation pillars PS1 is smaller than the spacing between adjacent second isolation pillars PS2. The top of the first isolation pillar PS1 is the end of the first isolation pillar PS1 that is away from the substrate, and the top of the second isolation pillar PS2 is the end of the second isolation pillar PS2 that is away from the substrate. It is understandable that the top area of the second isolation pillar PS2 is relatively large, allowing for a larger spacing between adjacent second isolation pillars PS2, thus achieving good support. It is worth noting that in this embodiment, a portion of the area between the display area AA and the common electrode overlap ring RR does not have isolation pillars PS. Therefore, even with a large spacing between adjacent second isolation pillars PS2, the overall density of second isolation pillars PS2 in the display area AA is still greater than the overall density of first isolation pillars PS1 between the display area AA and the common electrode overlap ring RR. For example, as shown in Figures 4 and 5-1, only one ring of first isolation pillars PS1 is provided between the display area AA and the common electrode overlap ring RR. Thus, even if the spacing between two adjacent second isolation pillars PS2 in the display area AA is increased, making the spacing between two adjacent second isolation pillars PS2 greater than the spacing between two adjacent first isolation pillars PS1, the density of second isolation pillars PS2 is still greater than the density of first isolation pillars PS1.
[0095] In another example, the area of the top of the first isolation pillar PS1 is larger than the area of the top of the second isolation pillar PS2, and the spacing between adjacent first isolation pillars PS1 is larger than the spacing between adjacent second isolation pillars PS2. The top of the first isolation pillar PS1 is the end of the first isolation pillar PS1 that is furthest from the substrate, and the top of the second isolation pillar PS2 is the end of the second isolation pillar PS2 that is furthest from the substrate. That is, the area of the top of the first isolation pillar PS1 is larger than that of the second isolation pillar PS2, and a larger spacing can be set between adjacent first isolation pillars PS1. In this way, fewer first isolation pillars PS1 can be used to achieve support for the fine metal mask (FMM), further reducing the impact of the first isolation pillars PS1 on the touch performance of the display panel.
[0096] In one embodiment of this disclosure, as shown in FIG12, the isolation pillar PS is not provided between the common electrode overlap ring RR and the display area AA. That is, the second isolation pillar PS2 is only provided within the display area AA, and the first isolation pillar PS1 is not provided outside the boundary of the display area AA. In this way, the influence of the isolation pillar PS on the organic encapsulation layer IJP of the thin film encapsulation layer TFE can be avoided, thereby providing a flat surface for the formation of the metal layer (used to form touch traces) formed on the side away from the thin film encapsulation layer TFE, improving the signal stability and durability of the touch traces formed by the patterning of the metal layer, and enhancing the touch experience of the display panel PNL.
[0097] This disclosure also provides a display device including the aforementioned display panel. Thus, the display device also possesses the aforementioned beneficial effects, which will not be elaborated further here.
[0098] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A display panel, characterized in that, It includes a display area and a peripheral area; the display panel has isolation pillars; The peripheral area has a common electrode overlap ring surrounding the display area, and the density of the isolation pillars between the common electrode overlap ring and the display area is less than the density of the isolation pillars in the display area.
2. The display panel according to claim 1, characterized in that, The isolation column is not provided between the common electrode overlap ring and the display area.
3. The display panel according to claim 1, characterized in that, The isolation pillar includes a first isolation pillar, which is located between the common electrode overlap ring and the display area; The distance between the first isolation post and the common electrode overlap ring is less than the distance between the first isolation post and the display area.
4. The display panel according to claim 3, characterized in that, The distance between the first isolation post and the common electrode overlap ring shall not exceed 0.1 times the distance between the first isolation post and the display area.
5. The display panel according to claim 3, characterized in that, The distance between the first isolation column and the common electrode overlap ring is between 1 and 10 micrometers.
6. The display panel according to claim 3, characterized in that, The first isolation pillars are arranged in an isolation pillar ring surrounding the display area; the distance between each of the first isolation pillars and the common electrode overlap ring is equal.
7. The display panel according to any one of claims 1-6, characterized in that, The display area has straight edges and rounded edges located between two adjacent straight edges. The center-to-center distance between two adjacent first isolation pillars near the straight edges is equal to the center-to-center distance between two adjacent first isolation pillars near the rounded edges.
8. The display panel according to any one of claims 1-6, characterized in that, The display area has straight edges and rounded edges located between two adjacent straight edges. The center-to-center distance between two adjacent first isolation pillars near the straight edges is not equal to the center-to-center distance between two adjacent first isolation pillars near the rounded edges.
9. The display panel according to claim 3, characterized in that, The isolation pillar also includes a second isolation pillar, which is at least partially located within the display area; The area of the top of the first isolation post is smaller than the area of the top of the second isolation post, and the distance between adjacent first isolation posts is smaller than the distance between adjacent second isolation posts.
10. The display panel according to claim 3, characterized in that, The isolation pillar also includes a second isolation pillar, which is at least partially located within the display area; The area of the top of the first isolation post is greater than the area of the top of the second isolation post, and the distance between adjacent first isolation posts is greater than the distance between adjacent second isolation posts.
11. The display panel according to claim 9 or 10, characterized in that, The display area includes multiple sub-pixel rows, and any one sub-pixel row includes multiple sub-pixels arranged sequentially along the row direction; Wherein, at least one sub-pixel row includes multiple sub-pixel groups arranged sequentially in the same row, and the sub-pixel group includes one red sub-pixel, two green sub-pixels and one blue sub-pixel; The display panel is provided with a second isolation pillar between the red and blue subpixels of at least a portion of the subpixel groups.
12. The display panel according to claim 1, characterized in that, The display panel includes a substrate, a driving layer, a pixel layer, a thin film encapsulation layer, and a touch function layer stacked in sequence. The pixel layer includes a pixel electrode layer, a pixel definition layer, and an isolation pillar layer stacked sequentially on the driving layer, wherein the isolation pillar layer is provided with the isolation pillars.
13. The display panel according to claim 12, characterized in that, The thin-film encapsulation layer has an organic encapsulation layer, and the touch function layer has touch wiring; The isolation pillar includes a first isolation pillar, which is located between the common electrode overlap ring and the display area; The organic encapsulation layer covers the first isolation pillar; at least a portion of the touch traces overlap with the first isolation pillar.
14. The display panel according to claim 13, characterized in that, The first isolation pillar has the same shape when projected onto the substrate.
15. The display panel according to claim 13, characterized in that, In the orthographic projection of the first isolation pillar onto the substrate, at least two of the first isolation pillars have different shapes.
16. The display panel according to claim 13, characterized in that, The isolation pillar also includes a second isolation pillar, which is at least partially located within the display area; The second isolation pillar has the same shape when projected onto the substrate.
17. The display panel according to claim 13, characterized in that, The isolation pillar also includes a second isolation pillar, which is at least partially located within the display area; In the orthographic projection of the second isolation pillar onto the substrate, at least two of the second isolation pillars have different shapes.
18. The display panel according to claim 16 or 17, characterized in that, The orthographic projection of the first isolation pillar on the substrate is a circle, an ellipse, a square, a rectangle, a square with rounded corners, a rectangle with rounded corners, a hexagon, and / or an octagon; The orthographic projection of the second isolation pillar onto the substrate is a circle, ellipse, square, rectangle, rounded square, rounded rectangle, hexagon, and / or octagon.
19. The display panel according to claim 12, characterized in that, The common electrode overlap ring is provided with an exhaust hole; The isolation column layer is provided with auxiliary isolation columns, which are arranged around the exhaust holes.
20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.