Display substrate and display device

Abstract

A display substrate and a display device, relating to the technical field of display. The display substrate comprises: a substrate, and a first conductive layer, a semiconductor layer, a first insulating layer, and a second conductive layer which are stacked on one side of the substrate, the first conductive layer being arranged close to the substrate. The first conductive layer comprises a data line and multiple first conductive structures. The semiconductor layer comprises a source connection region, a first conductive region, a channel region, a second conductive region, and a drain connection region which are successively arranged in a first direction. The second conductive layer comprises multiple gates, and a first transfer pattern and a second transfer pattern which are arranged on two sides of each gate. The first insulating layer is provided with a first via hole and a second via hole. The data line and the source connection region are respectively connected to the first transfer pattern through the first via hole, and the first conductive structures and the drain connection region are respectively connected to the second transfer pattern through the second via hole. The first transfer pattern does not overlap the first conductive region, and the second transfer pattern does not overlap the second conductive region.

Description

[Amended according to Rule 91, February 25, 2026] Display substrate and display device

[0001] Cross-reference of related applications

[0002] [Amended according to Rule 91 25.02.2026] This disclosure claims priority to Chinese Patent Application No. 202510104491.2, filed on January 22, 2025, entitled “Display Substrate and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0004] Electronic paper primarily uses electrophoresis display (EPD) technology as its display panel. Electronic paper displays not only offer advantages similar to paper, such as comfortable reading, ultra-thin and lightweight design, and flexibility, but also allow for content refresh and consume less power than LCD displays.

[0005] Overview

[0006] This disclosure provides a display substrate including a plurality of sub-pixels located in a display area, the display substrate comprising:

[0007] A substrate, and a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer is disposed close to the substrate;

[0008] The first conductive layer includes data lines and multiple first conductive structures located in different sub-pixels. The semiconductor layer includes multiple semiconductor patterns located in different sub-pixels. Each semiconductor pattern includes a source connection region, a first conductive region, a channel region, a second conductive region, and a drain connection region arranged sequentially along a first direction. The second conductive layer includes multiple gates located in different sub-pixels, and a first transition pattern and a second transition pattern disposed opposite to each other on both sides of the gates along the first direction.

[0009] The first insulating layer has a first via and a second via. The first via exposes a portion of the data line, the source connection region, and the first conductor region. The second via exposes a portion of the first conductive structure, the drain connection region, and the second conductor region. The data line and the source connection region are respectively connected to the first transition pattern through the first via. The first conductive structure and the drain connection region are respectively connected to the second transition pattern through the second via. In the orthographic projection on the substrate, the first transition pattern does not overlap with the first conductor region, and the second transition pattern does not overlap with the second conductor region.

[0010] In some embodiments, the semiconductor pattern further includes:

[0011] A third conductive region is connected between the first conductive region and the channel region, wherein the thickness of the first conductive region is different from the thickness of the third conductive region; and

[0012] A fourth conductive region is connected between the second conductive region and the channel region, and the thickness of the second conductive region is different from the thickness of the fourth conductive region.

[0013] In some embodiments, the thickness of the first conductive region is less than the thickness of the third conductive region, the thickness of the first conductive region is less than or equal to the thickness of the source connection region, and the thickness of the third conductive region is less than or equal to the thickness of the channel region; and

[0014] The thickness of the second conductive region is less than the thickness of the fourth conductive region, the thickness of the second conductive region is less than or equal to the thickness of the drain connection region, and the thickness of the fourth conductive region is less than or equal to the thickness of the channel region.

[0015] In some embodiments, the display substrate further includes:

[0016] A second insulating layer is disposed on the side of the second conductive layer opposite to the substrate; and

[0017] A transparent conductive layer is disposed on the side of the second insulating layer away from the substrate. The transparent conductive layer includes a plurality of second conductive structures located in different sub-pixels. The second conductive structures and the second transition pattern overlap through a third via disposed on the second insulating layer. The second conductive structures do not overlap with the orthographic projection of the gate on the substrate.

[0018] In some embodiments, the second conductive structure includes a first sub-electrode, a second sub-electrode, and a third sub-electrode. The second sub-electrode and the third sub-electrode are located on the same side of the first sub-electrode and are respectively connected to the first sub-electrode. In a projection onto the substrate, the second sub-electrode and the third sub-electrode are disposed opposite to each other on both sides of the gate along the first direction.

[0019] The gap width between the second sub-electrode and the third sub-electrode is approximately equal to the gap width between two adjacent second conductive structures.

[0020] In some embodiments, the display substrate further includes:

[0021] A third conductive layer is disposed between the second insulating layer and the transparent conductive layer. The third conductive layer includes a plurality of third conductive structures located in different sub-pixels. The surface of the third conductive structure facing away from the substrate is in direct contact with the surface of the second conductive structure close to the substrate. In the orthographic projection on the substrate, the second conductive structure covers the third conductive structure, and the third conductive structure covers the third via and the second transition pattern.

[0022] In some embodiments, in the orthographic projection on the substrate, the second conductive structure and the third conductive structure have different shapes, the second conductive structure covers the first transition pattern, and the third conductive structure does not overlap with the first transition pattern.

[0023] In some embodiments, the third conductive layer further includes a first shielding pattern, which is spaced apart from the third conductive structure, and the orthographic projection of the first shielding pattern on the substrate covers the orthographic projection of the channel region on the substrate.

[0024] The transparent conductive layer further includes a protective pattern, which is spaced apart from the second conductive structure, and the orthogonal projection of the protective pattern on the substrate covers the orthogonal projection of the first shielding pattern on the substrate.

[0025] In some embodiments, in the orthographic projection on the substrate, the gap width between two adjacent second conductive structures is greater than or equal to 5 micrometers and less than or equal to 15 micrometers.

[0026] In some implementations, the sub-pixel further includes:

[0027] A fourth conductive structure is located in the second conductive layer and / or semiconductor layer. The fourth conductive structure overlaps with the orthographic projection of the first conductive structure on the substrate. The fourth conductive structures of a plurality of sub-pixels arranged along the first direction and / or the second direction are interconnected. The second direction is the extension direction of the data line.

[0028] In some embodiments, the first conductive structure includes:

[0029] The fourth and fifth sub-electrodes are interconnected. In the orthographic projection on the substrate, the fifth sub-electrode is located on the side of the fourth sub-electrode closer to the gate. The width of the fifth sub-electrode along the first direction is smaller than the width of the fourth sub-electrode along the first direction. The fifth sub-electrode overlaps with the second transition pattern. The fourth conductive structure covers a portion of the fifth sub-electrode and the fourth sub-electrode.

[0030] In some embodiments, the fourth conductive structure disposed on the same layer includes:

[0031] The sixth and seventh sub-electrodes are interconnected. In the orthographic projection on the substrate, the seventh sub-electrode is located on the side of the sixth sub-electrode closer to the gate, and the seventh sub-electrode is located on the side of the second transition electrode away from the gate. The width of the seventh sub-electrode along the first direction is smaller than the width of the sixth sub-electrode along the first direction. The sixth sub-electrode completely covers the fourth sub-electrode, and the seventh sub-electrode covers a portion of the fifth sub-electrode.

[0032] In some embodiments, the fourth conductive structure includes:

[0033] A fifth conductive structure is located in the second conductive layer. The fifth conductive structure overlaps with the orthographic projection of the first conductive structure on the substrate. The fifth conductive structures of multiple sub-pixels arranged along the first direction are interconnected. A scan line is provided between two adjacent fifth conductive structures of sub-pixels arranged along the second direction. The scan line is located in the second conductive layer and connected to the gate.

[0034] In some embodiments, in the orthographic projection on the substrate, the fifth conductive structure and the data line have an overlapping region, and the width of the overlapping region along the second direction is less than or equal to the width of the non-overlapping region along the second direction.

[0035] In some embodiments, the fourth conductive structure further includes:

[0036] A sixth conductive structure is located in the semiconductor layer. The orthographic projection of the sixth conductive structure onto the substrate overlaps with that of the first conductive structure. The sixth conductive structure is connected to the fifth conductive structure via a fourth via disposed on the first insulating layer. In the orthographic projection onto the substrate, the edge of the sixth conductive structure is located outside the edge of the fourth via.

[0037] The data line is provided between the sixth conductive structures of two adjacent sub-pixels arranged along the first direction, and the scan line is provided between the sixth conductive structures of two adjacent sub-pixels arranged along the second direction.

[0038] In some embodiments, in the orthographic projection on the substrate, the distance between the edge of the sixth conductive structure and the edge of the fourth via is greater than or equal to half the width of the data line along the first direction, and less than or equal to twice the width of the data line along the first direction.

[0039] In some embodiments, in the orthographic projection on the substrate, the diameter of the fourth via along the first direction is larger than the diameters of the first via and the second via along the first direction, and the diameter of the fourth via along the second direction is larger than the diameters of the first via and the second via along the second direction.

[0040] In some embodiments, in an orthographic projection onto the substrate, the second conductive layer completely covers the first insulating layer, and a portion of the edge of the first insulating layer is substantially aligned with the edge of the second conductive layer.

[0041] This disclosure provides a display device, including: a counter substrate, an electrophoretic solution, and a display substrate as described in any embodiment, wherein the electrophoretic solution is located between the counter substrate and the display substrate, and a second conductive layer is located on the side of the substrate close to the electrophoretic solution.

[0042] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below.

[0043] Brief description of the attached diagram

[0044] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0045] Figure 1 shows a schematic diagram of the structure after the first conductive layer is fabricated in the first display substrate example;

[0046] Figure 2 shows a schematic diagram of the structure after the semiconductor layer fabrication is completed in the first display substrate example;

[0047] Figure 3 shows a schematic diagram of the structure after the first insulating layer is fabricated in the first display substrate example;

[0048] Figure 4 shows a schematic diagram of the structure after the fabrication of the second conductive layer in the first display substrate example;

[0049] Figure 5 shows a schematic diagram of the structure after the fabrication of the second insulating layer in the first display substrate example;

[0050] Figure 6 shows a schematic diagram of the structure after the fabrication of the third conductive layer in the first display substrate example;

[0051] Figure 7 shows a schematic diagram of the structure after the transparent conductive layer is fabricated in the first display substrate example;

[0052] Figure 8 shows a schematic diagram of the structure after the first conductive layer is fabricated in the second display substrate example;

[0053] Figure 9 shows a schematic diagram of the structure after the semiconductor layer fabrication is completed in the second display substrate example;

[0054] Figure 10 shows a schematic diagram of the structure after the first insulating layer is fabricated in the second display substrate example;

[0055] Figure 11 shows a schematic diagram of the structure after the fabrication of the second conductive layer in the second display substrate example;

[0056] Figure 12 shows a schematic diagram of the structure after the fabrication of the second insulating layer in the second display substrate example;

[0057] Figure 13 shows a schematic diagram of the structure after the transparent conductive layer is fabricated in the second display substrate example;

[0058] Figure 14 shows a schematic diagram of the structure after the first conductive layer is fabricated in the third display substrate example;

[0059] Figure 15 shows a schematic diagram of the structure after the semiconductor layer fabrication is completed in the third display substrate example;

[0060] Figure 16 shows a schematic diagram of the structure after the first insulating layer is fabricated in the third display substrate example;

[0061] Figure 17 shows a schematic diagram of the structure after the fabrication of the second conductive layer in the third display substrate example;

[0062] Figure 18 shows a schematic diagram of the structure after the second insulating layer is fabricated in the third display substrate example;

[0063] Figure 19 shows a schematic diagram of the structure after the transparent conductive layer is fabricated in the third display substrate example;

[0064] Figure 20 shows a bar chart illustrating the variation of the electric field strength in the channel region with the doping concentration in the first conductor region;

[0065] Figure 21 shows a schematic cross-sectional view of a display device;

[0066] Figure 22 illustrates a schematic diagram of the connection structure of a display device.

[0067] Detailed description

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0069] In related technologies, electronic paper mainly uses the following two methods to achieve full-color display: The first is color printing electronic paper technology, which uses electronic paper with color filters and the principle of color mixing to convert black and white electronic paper into full-color electronic paper; the second is color electronic paper technology, which is composed of ink particles of four colors (such as yellow, cyan, magenta and white). By applying an electric field and using the principle of attraction between positive and negative, the ink particles of the corresponding colors are pushed to the display side. After the particles of different colors are mixed, a variety of colors are presented.

[0070] To drive electronic paper for full-color display, higher driving voltages are required, such as VGH ≥ 28V and VGL ≤ -28V. However, the highest operating voltage of display substrates in related technologies cannot meet the driving requirements of color electronic paper. Therefore, there is an urgent need to develop display substrates with high voltage resistance.

[0071] This disclosure provides a display substrate, as shown in FIG22, which includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a plurality of sub-pixels PX, and the sub-pixels PX include thin film transistors.

[0072] In Figures 1 to 19, Figure a exemplarily shows a planar structural schematic of a sub-pixel PX in a display substrate, and Figure b exemplarily shows a cross-sectional structural schematic along position AA' in Figure a. In Figures 1 to 13, Figure c exemplarily shows a planar structural schematic of two sub-pixels PX in a display substrate.

[0073] As shown in Figure 7, Figure 13 or Figure 19, the display substrate includes: a substrate 10, and a first conductive layer M1, a semiconductor layer ACT, a first insulating layer GI and a second conductive layer M2 sequentially stacked on one side of the substrate 10, wherein the first conductive layer M1 is disposed close to the substrate 10.

[0074] The first conductive layer M1 includes a data line DL and multiple first conductive structures EP1 located in different sub-pixels PX. The semiconductor layer ACT includes multiple semiconductor patterns located in different sub-pixels PX. The semiconductor patterns include a source connection region S, a first conductor region DT1, a channel region CH, a second conductor region DT2 and a drain connection region D arranged sequentially along the first direction f1. The second conductive layer M2 includes multiple gates G located in different sub-pixels PX, and a first transition pattern ZJ1 and a second transition pattern ZJ2 disposed opposite to each other on both sides of the gates G along the first direction f1.

[0075] The first insulating layer GI has a first via H1 and a second via H2. The first via H1 exposes a portion of the data line DL, the source connection region S, and the first conductor region DT1. The second via H2 exposes a portion of the first conductive structure EP1, the drain connection region D, and the second conductor region DT2. The data line DL and the source connection region S are respectively connected to the first transition pattern ZJ1 through the first via H1. The first conductive structure EP1 and the drain connection region D are respectively connected to the second transition pattern ZJ2 through the second via H2. In the orthographic projection on the substrate 10, the first transition pattern ZJ1 and the first conductor region DT1 do not overlap, and the second transition pattern ZJ2 and the second conductor region DT2 do not overlap.

[0076] As shown in Figures 7, 13, or 19, the first conductive region DT1 is exposed at the location of the first via H1, and the first transition pattern ZJ1 does not cover the first conductive region DT1. That is, the first transition pattern ZJ1 achieves the connection between the data line DL and the source connection region S by partially covering the first via H1. The second conductive region DT2 is exposed at the location of the second via H2, and the second transition pattern ZJ2 does not cover the second conductive region DT2. That is, the second transition pattern ZJ2 achieves the connection between the first conductive structure EP1 and the drain connection region D by partially covering the second via H2.

[0077] The display substrate provided in this disclosure can adjust the resistance of the first via H1 and the second via H2 by adjusting the doping concentration of the first conductive region DT1 exposed at the first via H1 position and the second conductive region DT2 exposed at the second via H2 position, thereby adjusting the voltage division magnitude of the first via H1 and the second via H2, which is beneficial to improving the voltage withstand capability of the thin film transistor.

[0078] Figure 20 shows a bar graph illustrating the change in the electric field strength of the channel region CH as a function of the doping concentration of the first conductive region DT1. As shown in Figure 20, the electric field strength of the channel region CH decreases as the doping concentration of the first conductive region DT1 decreases. This is because as the doping concentration of the first conductive region DT1 decreases, the resistance and voltage division of the first via H1 increase, thus reducing the electric field strength of the channel region CH, which in turn improves the breakdown voltage capability of the thin-film transistor.

[0079] In this disclosure, a thin-film transistor (TFT) refers to a device comprising at least three terminals: a gate (G), a drain (G), and a source (D). A TFT has a channel region CH between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel region CH, and the source. In this disclosure, the channel region CH refers to the region through which current primarily flows, the source is connected to the source connection region S, and the drain is connected to the drain connection region D.

[0080] In this disclosure, the functions of the "source" and "drain" are sometimes interchanged when using thin-film transistors with opposite polarities or when the current direction changes during circuit operation. Therefore, in this disclosure, the "source" and "drain" can be interchanged.

[0081] For example, the material of the semiconductor layer ACT includes oxide semiconductor materials such as IGZO, and may also include materials such as amorphous silicon or low-temperature polycrystalline silicon, which are not limited in this disclosure.

[0082] In some embodiments, the channel region CH of the thin-film transistor comprises a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents oxygen, and N represents nitrogen. That is, the semiconductor material is a metal oxide material or a metal oxide-nitrogen material. Suitable metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth element-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel CH can be amorphous, partially crystalline, single crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0083] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the channel region CH includes indium gallium zinc oxide (IGZO).

[0084] For example, as shown in FIG7, FIG13 or FIG19, in the orthographic projection on the substrate 10, the first transition pattern ZJ1 overlaps with the data line DL and the source connection region S, respectively, and the second transition pattern ZJ2 overlaps with the first conductive structure EP1 and the drain connection region D, respectively.

[0085] For example, as shown in Figures 7, 13, or 19, a buffer layer BF is further provided between the first conductive layer M1 and the semiconductor layer ACT to insulate the first conductive layer M1 from the semiconductor layer ACT. During the etching process to form the first via H1 and the second via H2, the buffer layer BF at the corresponding positions is also etched away, thereby exposing a portion of the data line DL through the first via H1 and a portion of the first conductive structure EP1 through the second via H2.

[0086] For example, as shown in Figures 1, 8, or 14, the data line DL includes a first segment XD1 extending along a second direction f2 and a second segment XD2 extending along a first direction f1. The second segment XD2 is connected to the side of the first segment XD1 near the channel region CH, and is exposed at a first via H1. The first transition pattern ZJ1 connects the second segment XD2 to the source connection region S by partially overlapping the first via H1. The second segment XD2 is located near the intersection of the first segment XD1 and the scan line GL.

[0087] For example, the first direction f1 and the second direction f2 are perpendicular to each other.

[0088] For example, the second conductive layer M2 also includes a scan line GL extending along the first direction f1, and the scan line GL is connected to the gate G.

[0089] Because the etching process of forming the first via H1 and the second via H2 will cause over-etching of the source connection region S, the first conductive region DT1, the drain connection region D, and the second conductive region DT2, as shown in Figures 7, 13, or 19, the thickness of the source connection region S, the first conductive region DT1, the drain connection region D, and the second conductive region DT2 is all less than the thickness of the channel region CH.

[0090] For example, the first via H1 and the second via H2 can be formed simultaneously using the same process. In this case, the thickness of the drain connection region D is approximately equal to the thickness of the source connection region S, and the thickness of the first conductor region DT1 is approximately equal to the thickness of the second conductor region DT2.

[0091] In some embodiments, as shown in FIG7, FIG13 or FIG19, the semiconductor pattern further includes: a third conductor region DT3 connected between the first conductor region DT1 and the channel region CH; and a fourth conductor region DT4 connected between the second conductor region DT2 and the channel region CH.

[0092] For example, the thickness of the first conductive region DT1 is different from the thickness of the third conductive region DT3, and the thickness of the second conductive region DT2 is different from the thickness of the fourth conductive region DT4.

[0093] For example, after forming the second conductive layer M2, the first insulating layer GI can be etched a second time using the second conductive layer M2 as a mask. Then, using the second conductive layer M2 as a mask again, a self-aligned process is used to conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4). This conductor formation process can, for example, use a dry etching device or an ion implantation device to implant plasma (such as plasma containing at least one element selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or it can use an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductor formation. Among these methods, the conductor formation of the semiconductor material using a dry etching device can be performed simultaneously with the second etching process of the first insulating layer GI, thereby simplifying the process.

[0094] When the first insulating layer GI is etched twice, as shown in Figures 7, 13, or 19, the third conductive region DT3 and the first insulating layer GI do not overlap in their orthographic projections on the substrate 10, and the fourth conductive region DT4 and the first insulating layer GI do not overlap in their orthographic projections on the substrate 10. Furthermore, since the first conductive region DT1 and the second conductive region DT2 have undergone two over-etchings, and the source connection region S, the drain connection region D, the third conductive region DT3, and the fourth conductive region DT4 have all undergone one over-etching, while the channel region CH has not undergone over-etching, the thickness of the first conductive region DT1 is less than the thickness of the source connection region S and the third conductive region DT3, the thickness of the second conductive region DT2 is less than the thickness of the drain connection region D and the fourth conductive region DT4, the thickness of the source connection region S and the third conductive region DT3 is less than the thickness of the channel region CH, and the thickness of the drain connection region D and the fourth conductive region DT4 is less than the thickness of the channel region CH.

[0095] For example, after forming the second conductive layer M2, the first insulating layer GI may not be etched a second time. Instead, the second conductive layer M2 can be used as a mask to directly conduct the semiconductor material in the exposed areas (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4) of the semiconductor layer ACT using a self-aligned process. This conductor formation process can, for example, use a dry etching device or an ion implantation device to implant plasma (such as plasma containing at least one element selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material. Alternatively, an ion doping process can be used to dope any one or more of the above elements into the semiconductor material to achieve conductor formation.

[0096] For example, without performing a second etching on the first insulating layer GI, the first insulating layer GI covers the surface of the third conductive region DT3 and the fourth conductive region DT4 away from the substrate 10. Since the source connection region S, the drain connection region D, the first conductive region DT1 and the second conductive region DT2 have all been over-etched once, while the third conductive region DT3, the fourth conductive region DT4 and the channel region CH have not been over-etched, the thickness of the first conductive region DT1 is approximately equal to the thickness of the source connection region S, the thickness of the second conductive region DT2 is approximately equal to the thickness of the drain connection region DS, the thickness of the source connection region S and the first conductive region DT1 is less than the thickness of the third conductive region DT3, the thickness of the drain connection region DS and the second conductive region DT2 is less than the thickness of the fourth conductive region DT4, and the thickness of the third conductive region DT3 and the fourth conductive region DT4 is approximately equal to the thickness of the channel region CH.

[0097] For example, the thickness difference between the channel region CH and the source connection region S is greater than or equal to 5 nm and less than or equal to 15 nm. The thickness difference between the channel region CH and the drain connection region D is greater than or equal to 5 nm and less than or equal to 15 nm. The thickness difference between the channel region CH and the first conductive region DT1 is greater than or equal to 10 nm and less than or equal to 30 nm. The thickness difference between the channel region CH and the second conductive region DT2 is greater than or equal to 10 nm and less than or equal to 30 nm. The thickness difference between the channel region CH and the third conductive region DT3 is greater than or equal to 2 nm and less than or equal to 10 nm. The thickness difference between the channel region CH and the fourth conductive region DT4 is greater than or equal to 2 nm and less than or equal to 10 nm. For example, the first conductive structures EP1 of different sub-pixels PX are separated from each other. For example, in the orthographic projection on the substrate 10, a data line DL is provided between two adjacent first conductive structures EP1 along the first direction f1, and a scan line GL is provided between two adjacent first conductive structures EP1 along the second direction f2, and the first conductive structures EP1 do not overlap with the data line DL and the scan line GL.

[0098] For example, as shown in FIG1, FIG8, or FIG14, the first conductive structure EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 interconnected. As shown in FIG7, FIG13, or FIG19, in the orthographic projection on the substrate 10, the fifth sub-electrode 115 is located on the side of the fourth sub-electrode 114 near the gate G, and the fifth sub-electrode 115 is located on the side of the gate G away from the first transition pattern ZJ1. The width of the fifth sub-electrode 115 along the first direction f1 is smaller than the width of the fourth sub-electrode 114 along the first direction f1. The fifth sub-electrode 115 overlaps with the second transition pattern ZJ2. The edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 on the side away from the channel region CH are approximately aligned.

[0099] In this process, a portion of the fifth sub-electrode 115 is exposed at the second via H2, and the second transition pattern ZJ2 connects the fifth sub-electrode 115 to the drain connection region D by partially overlapping the second via H2.

[0100] In some embodiments, as shown in Figures 7, 13, or 19, the display substrate further includes: a second insulating layer PVX disposed on the side of the second conductive layer M2 facing away from the substrate 10; and a transparent conductive layer TD disposed on the side of the second insulating layer PVX facing away from the substrate 10. The transparent conductive layer TD includes a plurality of second conductive structures EP2 located at different sub-pixels PX. The second conductive structures EP2 and the second transition pattern ZJ2 are connected through a third via H3 disposed on the second insulating layer PVX. The second conductive structures EP2 completely cover the third via H3. The second conductive structures EP2 and the first conductive structure EP1 are connected through the second transition pattern ZJ2.

[0101] For example, the second conductive structures EP2 of different sub-pixels PX are arranged separately from each other. For instance, in the orthographic projection on the substrate 10, a data line DL is arranged between two adjacent second conductive structures EP2 along the first direction f1, and a scan line GL is arranged between two adjacent second conductive structures EP2 along the second direction f2. The second conductive structures EP2 and the scan line GL do not overlap, and the second conductive structures EP2 and the data line DL do not overlap or partially overlap.

[0102] For example, the second conductive structure EP2 is used to drive the movement of the target particles. The target particles can be electrophoretic particles, such as two-color, three-color, or four-color particles; or they can be liquid crystal molecules. The movement of the target particles can refer to their vertical movement (e.g., movement perpendicular to the substrate 10) or horizontal movement (e.g., movement parallel to the substrate 10) between the two substrates or electrodes, or it can refer to the target particles deflecting vertically, horizontally, or forward and backward between the two substrates or electrodes.

[0103] To avoid signal interference between the second conductive structure EP2 and the gate G, for example, the orthogonal projections of the second conductive structure EP2 and the gate G on the substrate 10 do not overlap. This reduces the coupling capacitance formed between the second conductive structure EP2 and the gate G, thereby reducing signal interference.

[0104] For example, as shown in FIG7, FIG13 or FIG19, the second conductive structure EP2 includes a first sub-electrode 111, a second sub-electrode 112 and a third sub-electrode 113. The second sub-electrode 112 and the third sub-electrode 113 are located on the same side of the first sub-electrode 111 and are respectively connected to the first sub-electrode 111. In the orthographic projection on the substrate 10, the second sub-electrode 112 and the third sub-electrode 113 are disposed opposite to each other on both sides of the gate G along the first direction f1.

[0105] For example, the gap width between the second sub-electrode 112 and the third sub-electrode 113 is approximately equal to the gap width between two adjacent second conductive structures EP2 (as shown in Figure 7 or Figure 13c, w1).

[0106] To ensure that the orthogonal projection of the second conductive structure EP2 and the gate G on the substrate 10 does not overlap, the gap width between the second sub-electrode 112 and the third sub-electrode 113 is greater than or equal to the width of the gate G along the first direction f1.

[0107] For example, in the orthographic projection on the substrate 10, the second sub-electrode 112 covers the first transition pattern ZJ1, and the third sub-electrode 113 covers the second transition pattern ZJ2. The width of the second sub-electrode 112 along the first direction f1 is smaller than the width of the first sub-electrode 111 along the first direction f1, and the width of the third sub-electrode 113 along the first direction f1 is smaller than the width of the first sub-electrode 111 along the first direction f1. The width of the second sub-electrode 112 along the first direction f1 can be less than or equal to the width of the third sub-electrode 113 along the first direction f1.

[0108] For example, in the orthographic projection on the substrate 10, the edges of the first sub-electrode 111 and the second sub-electrode 112 away from the third sub-electrode 113 are generally aligned, the edges of the first sub-electrode 111 and the third sub-electrode 113 away from the second sub-electrode 112 are generally aligned, and the edges of the second sub-electrode 112 and the third sub-electrode 113 away from the first sub-electrode 111 are generally aligned.

[0109] In some embodiments, as shown in FIG7, the display substrate further includes a third conductive layer M3 disposed between the second insulating layer PVX and the transparent conductive layer TD. The third conductive layer M3 includes a plurality of third conductive structures EP3 located in different sub-pixels PX. The surface of the third conductive structure EP3 facing away from the substrate 10 is in direct contact with the surface of the second conductive structure EP2 close to the substrate 10. In the orthographic projection on the substrate 10, the second conductive structure EP2 covers the third conductive structure EP3, and the third conductive structure EP3 covers the third via H3 and the second transition pattern ZJ2.

[0110] For example, the third conductive structures EP3 of different sub-pixels PX are arranged separately from each other. For instance, in the orthographic projection on the substrate 10, a data line DL is arranged between two adjacent third conductive structures EP3 along the first direction f1, and a scan line GL is arranged between two adjacent third conductive structures EP3 along the second direction f2. The third conductive structures EP3 and the scan line GL do not overlap, and the third conductive structures EP3 and the data line DL do not overlap or partially overlap.

[0111] As shown in Figure 7, the transparent conductive layer TD and the third conductive layer M3 are two adjacent films disposed in the normal direction of the substrate 10. By providing the third conductive structure EP3, which is in direct contact with the second conductive structure EP2, and given that the conductivity of the third conductive layer M3 is greater than that of the transparent conductive layer TD, the impedance and contact resistance of the pixel electrodes can be reduced, which is beneficial for improving display uniformity. In addition, by providing the transparent conductive layer TD to cover the third conductive layer M3, the transparent conductive layer TD can protect the third conductive layer M3, thereby improving the stability of the display substrate.

[0112] It should be noted that the third conductive layer M3 is not necessary. Without the third conductive layer M3, one masking process can be eliminated, thereby simplifying the process.

[0113] For example, as shown in FIG7, in the orthographic projection on the substrate 10, the second conductive structure EP2 and the third conductive structure EP3 have different shapes. The second conductive structure EP2 covers the first transition pattern ZJ1, and the third conductive structure EP3 does not overlap with the first transition pattern ZJ1.

[0114] As shown in Figure 7, the orthogonal projection shape of the second conductive structure EP2 on the substrate 10 is a U-shape with the notch facing the scan line GL, wherein the notch of the U-shape is centered in the first direction f1 or near the data line DL (as shown in Figure 7). The orthogonal projection shape of the third conductive structure EP3 on the substrate 10 is an L-shape with the opening facing the channel region CH.

[0115] For example, as shown in Figures 6 and 7, the third conductive structure EP3 includes an eighth sub-electrode 118 and a ninth sub-electrode 119 interconnected. In the orthographic projection on the substrate 10, the ninth sub-electrode 119 is located on the side of the eighth sub-electrode 118 closer to the gate G, and on the side of the gate G away from the first transition pattern ZJ1. The width of the ninth sub-electrode 119 along the first direction f1 is smaller than the width of the eighth sub-electrode 118 along the first direction f1. The ninth sub-electrode 119 overlaps with the second transition pattern ZJ2. The edges of the eighth sub-electrode 118 and the ninth sub-electrode 119 on the side away from the channel region CH are approximately aligned.

[0116] In a specific implementation, in the orthographic projection on the substrate 10, the second conductive structure EP2 and the third conductive structure EP3 can have the same shape. The third conductive structure EP3 is roughly centered in the area of ​​the second conductive structure EP2, and the second conductive structure EP2 completely covers the third conductive structure EP3.

[0117] In some embodiments, as shown in FIG6, the third conductive layer M3 further includes a first shielding pattern ZD1, the first shielding pattern ZD1 being spaced apart from the third conductive structure EP3, and the orthogonal projection of the first shielding pattern ZD1 on the substrate 10 covering the orthogonal projection of the channel region CH on the substrate 10.

[0118] By setting a first shielding pattern ZD1 on the side of the channel region CH away from the substrate 10, the characteristics of the thin film transistor can be prevented from being affected by light, thus improving the stability of the display substrate.

[0119] To protect the first shielding pattern ZD1, for example, as shown in FIG7, the transparent conductive layer TD further includes a protective pattern PT, which is spaced apart from the second conductive structure EP2, and the orthogonal projection of the protective pattern PT on the substrate 10 covers the orthogonal projection of the first shielding pattern ZD1 on the substrate 10.

[0120] As shown in Figure 7, the protective pattern PT is located between the second sub-electrode 112 and the third sub-electrode 113. The gap width between the protective pattern PT and the second sub-electrode 112 is, for example, 3 micrometers, and the gap width between the protective pattern PT and the third sub-electrode 113 is, for example, 3 micrometers.

[0121] For example, as shown in Figure 7 or Figure 13, the gap width w1 between two adjacent second conductive structures EP2 is greater than or equal to 5 micrometers and less than or equal to 15 micrometers, for example, 10 micrometers. Such a gap width ensures that two adjacent second conductive structures EP2 will not short-circuit, and also maximizes the area of ​​the second conductive structure EP2, which is beneficial to improving display uniformity.

[0122] In some embodiments, as shown in FIG7, FIG13 or FIG19, the sub-pixel PX further includes: a fourth conductive structure EC, located in the second conductive layer M2 and / or semiconductor layer ACT, the fourth conductive structure EC overlaps with the orthographic projection of the first conductive structure EP1 on the substrate 10, and the fourth conductive structures EC of the multiple sub-pixels PX arranged along the first direction f1 and / or the second direction f2 are interconnected, the second direction f2 is the extension direction of the data line DL.

[0123] For example, the fourth conductive structure EC also overlaps with the orthographic projection of the second conductive structure EP2 on the substrate 10.

[0124] Among them, the fourth conductive structure EC and the first conductive structure EP1 constitute the two plates of the first storage capacitor Cst1, and the fourth conductive structure EC and the second conductive structure EP2 constitute the two plates of the second storage capacitor Cst2.

[0125] By setting a fourth conductive structure EC between the first conductive structure EP1 and the second conductive structure EP2, a sandwich-structure pixel capacitor is formed. This reduces the number of vias in the display area AA, allowing for a larger area of ​​the pixel electrode facing the fourth conductive structure EC, thereby increasing the storage capacitance. This improves pixel density and allows for more flexible adjustment of the storage capacitance size according to actual needs. Furthermore, the reduced number of vias reduces the number of photomasks, simplifying the process and lowering costs.

[0126] In some embodiments, as shown in FIG7, FIG13 or FIG19, the fourth conductive structure EC covers a portion of the fifth sub-electrode 115 and the fourth sub-electrode 114.

[0127] In some embodiments, as shown in Figures 2, 4, 9, 11, 15, or 17, the fourth conductive structure EC disposed in the same layer includes a sixth sub-electrode 116 and a seventh sub-electrode 117 connected to each other. In the orthographic projection on the substrate 10, the seventh sub-electrode 117 is located on the side of the sixth sub-electrode 116 closer to the gate G, and the seventh sub-electrode 117 is located on the side of the second transfer electrode away from the gate G. The width of the seventh sub-electrode 117 along the first direction f1 is smaller than the width of the sixth sub-electrode 116 along the first direction f1.

[0128] For example, the sixth sub-electrode 116 completely covers the fourth sub-electrode 114, and the seventh sub-electrode 117 covers a portion of the fifth sub-electrode 115.

[0129] It should be noted that the fourth conductive structure EC set in the same layer can be the fifth conductive structure EC1 located in the second conductive layer M2, or the sixth conductive structure EC2 located in the semiconductor layer ACT.

[0130] For example, the fourth conductive structure EC may include at least one of the following: a fifth conductive structure EC1 located in the second conductive layer M2, and a sixth conductive structure EC2 located in the semiconductor layer ACT.

[0131] In some embodiments, as shown in FIG7, FIG13 or FIG19, the fourth conductive structure EC includes: a fifth conductive structure EC1 located in the second conductive layer M2, the fifth conductive structure EC1 and the first conductive structure EP1 having an orthographic projection on the substrate 10, the fifth conductive structures EC1 of a plurality of sub-pixels PX arranged along the first direction f1 being interconnected, and a scan line GL being provided between the fifth conductive structures EC1 of two adjacent sub-pixels PX arranged along the second direction f2.

[0132] In this embodiment, the fourth conductive structure EC disposed in the same layer is the fifth conductive structure EC1 located in the second conductive layer M2, as shown in FIG4. The fifth conductive structure EC1 includes a sixth sub-electrode 116 and a seventh sub-electrode 117 located in the second conductive layer M2 and interconnected with each other.

[0133] For example, in the orthographic projection on the substrate 10, the fifth conductive structure EC1, the first transition pattern ZJ1 and the second transition pattern ZJ2 are roughly aligned near the edge of the scan line GL.

[0134] For example, in the orthographic projection on the substrate 10, the fifth conductive structure EC1 and the data line DL have an overlapping region, and the width of the overlapping region along the second direction f2 is less than or equal to the width of the non-overlapping region along the second direction f2 (as shown in Figures 7, 13 and 19).

[0135] By reducing the width of the overlapping area between the fifth conductive structure EC1 and the data line DL along the second direction f2, making the width of the overlapping area along the second direction f2 smaller than the width of the non-overlapping area along the second direction f2, the parasitic capacitance between the fifth conductive structure EC1 and the data line DL can be reduced, thereby improving signal stability.

[0136] In some embodiments, as shown in FIG7 or FIG13, the fourth conductive structure EC further includes: a sixth conductive structure EC2 located in the semiconductor layer ACT, the sixth conductive structure EC2 and the first conductive structure EP1 having an orthographic projection on the substrate 10 overlapping, and the sixth conductive structure EC2 and the fifth conductive structure EC1 being connected by a fourth via H4 disposed on the first insulating layer GI.

[0137] For example, the semiconductor layer ACT also includes a fifth conductive region DT5, which is separated from the semiconductor pattern. The fifth conductive region DT5 constitutes a sixth conductive structure EC2, that is, the sixth conductive structure EC2 is a conductive semiconductor material.

[0138] In this embodiment, by setting a sixth conductive structure EC2 in the semiconductor layer ACT, the distance between the first conductive structure EP1 and the fourth conductive structure EC can be reduced, which is beneficial to increasing the capacitance of the first storage capacitor Cst1 or reducing the area of ​​the first conductive structure EP1 and the fourth conductive structure EC, thereby improving the pixel density.

[0139] In this embodiment, the fourth conductive structure EC disposed in the same layer is the sixth conductive structure EC2 located in the semiconductor layer ACT, as shown in FIG2. The sixth conductive structure EC2 includes a sixth sub-electrode 116 and a seventh sub-electrode 117 located in the semiconductor layer ACT and interconnected. In the orthographic projection on the substrate 10, the edges of the sixth sub-electrode 116 and the seventh sub-electrode 117 located in the semiconductor layer ACT are roughly aligned away from the gate G.

[0140] For example, as shown in FIG7 or FIG13, in the orthographic projection on the substrate 10, the edge of the sixth conductive structure EC2 is located outside the edge of the fourth via H4 to ensure that the first insulating layer GI covers the edge of the sixth conductive structure EC2, which helps to avoid a short circuit between the fifth conductive structure EC1 and the first conductive structure EP1.

[0141] For example, as shown in FIG7 or FIG13, in the orthographic projection on the substrate 10, the distance between the edge of the sixth conductive structure EC2 and the edge of the fourth via H4 is greater than or equal to half the width of the data line DL along the first direction f1, and less than or equal to twice the width of the data line DL along the first direction f1.

[0142] For example, as shown in FIG7 or FIG13, a data line DL is provided between the sixth conductive structures EC2 of two adjacent sub-pixels PX arranged along the first direction f1, and a scan line GL is provided between the sixth conductive structures EC2 of two adjacent sub-pixels PX arranged along the second direction f2. In the orthographic projection on the substrate 10, the sixth conductive structure EC2 does not overlap with the scan line GL and the data line DL.

[0143] For example, as shown in Figure 3 or Figure 10, in the orthographic projection on the substrate 10, the diameter of the fourth via H4 along the first direction f1 is larger than the diameters of the first via H1 and the second via H2 along the first direction f1, and the diameter of the fourth via H4 along the second direction f2 is larger than the diameters of the first via H1 and the second via H2 along the second direction f2. In this way, the fifth conductive structure EC1 and the sixth conductive structure EC2 are connected through a larger via, which helps to reduce contact resistance.

[0144] For example, as shown in FIG7, FIG13 or FIG19, in the orthographic projection on the substrate 10, the second conductive layer M2 completely covers the first insulating layer GI, and a portion of the edge of the first insulating layer GI is approximately aligned with the edge of the second conductive layer M2.

[0145] For example, during the secondary etching of the first insulating layer GI, the first insulating layer GI is etched using the second conductive layer M2 as a mask. The first insulating material not covered by the second conductive layer M2 will be etched away, thereby making part of the edge of the first insulating layer GI roughly aligned with the edge of the second conductive layer M2.

[0146] For example, any one of the first conductive structure EP1, the second conductive structure EP2, the third conductive structure EP3, the fourth conductive structure EC, the fifth conductive structure EC1, and the sixth conductive structure EC2 can be a pixel electrode or a common electrode.

[0147] In some embodiments, the first conductive structure EP1, the second conductive structure EP2, and the third conductive structure EP3 are pixel electrodes, and the fourth conductive structure EC, the fifth conductive structure EC1, and the sixth conductive structure EC2 are common electrodes. This disclosure is illustrated by way of example.

[0148] For example, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 are all metal layers.

[0149] For example, the first conductive layer M1, the second conductive layer M2 and the third conductive layer M3 can each be independently made of any one or more of the following metal materials: copper, molybdenum, aluminum, titanium, silver, nickel, niobium, etc., and the structure of each conductive layer can be a single layer or a stack.

[0150] In some embodiments, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may each independently include at least one of copper or copper alloy, molybdenum-niobium alloy, molybdenum-nickel alloy, and molybdenum-nickel-titanium alloy, for example, copper / molybdenum-niobium, molybdenum-niobium / copper, copper / molybdenum-nickel-titanium, molybdenum-nickel-titanium / copper, molybdenum-nickel / copper, copper / molybdenum-nickel, molybdenum-niobium / copper / molybdenum-niobium ...nickel / copper / molybdenum-nickel-titanium, etc.

[0151] For example, the transparent conductive layer TD can be made of transparent conductive materials, such as metal oxides like ITO, IZO, IGZO, IGO, and ZTO. Using metal oxides can improve the oxidation resistance of the transparent conductive layer TD.

[0152] To meet the driving requirements of color electronic paper, for example, the storage capacitance of each sub-pixel PX is greater than or equal to 1.0pF and less than or equal to 2.0pF, such as 1.2pF. The storage capacitance is the sum of the capacitance values ​​of the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0153] For example, as shown in Figure 7 or Figure 13, the data line DL extends along the column direction (i.e., the second direction f2), and the scan line GL extends along the row direction (i.e., the first direction f1). Two adjacent sub-pixels PX located in the same column are connected to the same scan line GL. Two data lines DL located in the same column are connected to two data lines DL. These two data lines DL are located on both sides of the sub-pixel PX in that column. Two adjacent sub-pixels PX located in the same column are connected to different data lines DL.

[0154] The technical solutions provided in this disclosure are illustrated below with reference to Figures 1 to 19.

[0155] In the first exemplary embodiment, as shown in FIG7, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX, a third conductive layer M3 and a transparent conductive layer TD sequentially stacked on one side of the substrate 10, wherein the first conductive layer M1 is disposed close to the substrate 10.

[0156] As shown in Figure 7, the first conductive layer M1 includes a data line DL and a first conductive structure EP1. The semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2. The semiconductor pattern includes a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D, arranged and connected sequentially along the first direction f1. The sixth conductive structure EC2 is the fifth conductive region DT5. A first via H1, a second via H2, and a fourth via H4 are provided on the first insulating layer GI. The aperture of the fourth via H4 is larger than that of the first via H1 and the second via H2. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. A third via H3 is provided on the second insulating layer PVX. The third conductive layer M3 includes a third conductive structure EP3 and a first blocking pattern ZD1 for blocking the channel region CH. The transparent conductive layer TD includes a second conductive structure EP2 and a protective pattern PT for protecting the first shielding pattern ZD1.

[0157] As shown in Figure 7, the first transition pattern ZJ1 connects the data line DL and the source connection region S through a partially covered first via H1. The second transition pattern ZJ2 connects the first conductive structure EP1 and the drain connection region D through a partially covered second via H2. The second conductive structure EP2 and the third conductive structure EP3 are directly connected in contact, and the second conductive structure EP2 and the third conductive structure EP3 are connected to the second transition pattern ZJ2 through the third via H3, thereby connecting the second conductive structure EP2, the third conductive structure EP3, and the first conductive structure EP1. The fifth conductive structure EC1 and the sixth conductive structure EC2 are connected through the fourth via H4.

[0158] The storage capacitors include a first storage capacitor Cst1 and a second storage capacitor Cst2 connected in parallel. One plate of the first storage capacitor Cst1 is a first conductive structure EP1, and the other plate is a fifth conductive structure EC1 and a sixth conductive structure EC2; the dielectric layer is a buffer layer BF. One plate of the second storage capacitor Cst2 is a second conductive structure EP2 and a third conductive structure EP3, and the other plate is a fifth conductive structure EC1 and a sixth conductive structure EC2; the dielectric layer is a second insulating layer PVX.

[0159] Referring to Figures 1 to 7, the display substrate provided in this embodiment can be prepared by the following steps:

[0160] Step 11: Form a patterned first conductive layer M1 on the substrate 10, as shown in Figure 1. The first conductive layer M1 includes a data line DL and a first conductive structure EP1, and may also include a second shielding pattern (not shown in the figure). The orthographic projection of the second shielding pattern on the substrate 10 covers the channel region CH.

[0161] Step 12: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in Figure 2. The semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2. The semiconductor pattern includes a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D arranged and connected sequentially along the first direction f1. The sixth conductive structure EC2 is the fifth conductive region DT5.

[0162] Step 13: A patterned first insulating layer GI is formed on the side of the semiconductor layer ACT facing away from the substrate 10, as shown in Figure 3. A first via H1, a second via H2, and a fourth via H4 are provided on the first insulating layer GI. The aperture of the fourth via H4 is larger than that of the first via H1 and the second via H2. In the orthographic projection on the substrate 10, the first via H1 and the second via H2 are located on opposite sides of the channel region CH. The first via H1 exposes a portion of the data line DL, the source connection region S, and the first conductive region DT1. The second via H2 exposes a portion of the first conductive structure EP1, the drain connection region D, and the second conductive region DT2. The fourth via H4 is located within the region of the sixth conductive structure EC2.

[0163] Step 14: A patterned second conductive layer M2 is formed on the side of the first insulating layer GI facing away from the substrate 10, as shown in Figure 4. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1, which is connected to the data line DL and the source connection region S, respectively. The second transition pattern ZJ2 partially covers the second via H2, which is connected to the drain connection region D and the first conductive structure EP1, respectively. The fifth conductive structure EC1 fully covers the fourth via H4, which is connected to the sixth conductive structure EC2.

[0164] As shown in Figure 4, after the second conductive layer M2 is formed, the first insulating layer GI is etched a second time using the second conductive layer M2 as a mask. Then, the semiconductor material in the exposed areas (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3 and the fourth conductor region DT4) in the semiconductor layer ACT is conductord using a self-aligned process.

[0165] Step 15: A patterned second insulating layer PVX is formed on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 5. A third via H3 is provided on the second insulating layer PVX.

[0166] Step 16: A patterned third conductive layer M3 is formed on the side of the second insulating layer PVX away from the substrate 10, as shown in Figure 6. The third conductive layer M3 includes a third conductive structure EP3 and a first shielding pattern ZD1 for shielding the channel region CH. The third conductive structure EP3 fully covers the third via H3 and is connected to the second transition pattern ZJ2.

[0167] Step 17: A patterned transparent conductive layer TD is formed on the side of the third conductive layer M3 away from the substrate 10, as shown in Figure 7. The transparent conductive layer TD includes a second conductive structure EP2 and a protective pattern PT for protecting the first shielding pattern ZD1. The second conductive structure EP2 completely covers the third conductive structure EP3, and the protective pattern PT completely covers the first shielding pattern ZD1.

[0168] In a second exemplary embodiment, as shown in FIG13, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX, and a transparent conductive layer TD sequentially stacked on one side of the substrate 10, wherein the first conductive layer M1 is disposed close to the substrate 10.

[0169] As shown in Figure 13, the first conductive layer M1 includes a data line DL and a first conductive structure EP1. The semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2. The semiconductor pattern includes a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D, arranged and connected sequentially along the first direction f1. The sixth conductive structure EC2 is the fifth conductive region DT5. A first via H1, a second via H2, and a fourth via H4 are provided on the first insulating layer GI. The aperture of the fourth via H4 is larger than that of the first via H1 and the second via H2. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. A third via H3 is provided on the second insulating layer PVX. The transparent conductive layer TD includes a second conductive structure EP2.

[0170] As shown in Figure 13, the first transition pattern ZJ1 connects the data line DL and the source connection region S through a partially covered first via H1. The second transition pattern ZJ2 connects the first conductive structure EP1 and the drain connection region D through a partially covered second via H2. The second conductive structure EP2 is connected to the second transition pattern ZJ2 through a third via H3, thereby connecting the second conductive structure EP2 and the first conductive structure EP1. The fifth conductive structure EC1 and the sixth conductive structure EC2 are connected through a fourth via H4.

[0171] The storage capacitors include a first storage capacitor Cst1 and a second storage capacitor Cst2 connected in parallel. One plate of the first storage capacitor Cst1 is a first conductive structure EP1, and the other plate is a fifth conductive structure EC1 and a sixth conductive structure EC2; the dielectric layer is a buffer layer BF. One plate of the second storage capacitor Cst2 is a second conductive structure EP2, and the other plate is a fifth conductive structure EC1 and a sixth conductive structure EC2; the dielectric layer is a second insulating layer PVX.

[0172] Referring to Figures 8 to 13, the display substrate provided in this embodiment can be prepared by the following steps:

[0173] Step 21: Form a patterned first conductive layer M1 on the substrate 10, as shown in FIG8. The first conductive layer M1 includes a data line DL and a first conductive structure EP1, and may also include a second shielding pattern (not shown in the figure). The orthographic projection of the second shielding pattern on the substrate 10 covers the channel region CH.

[0174] Step 22: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in Figure 9. The semiconductor layer ACT includes a semiconductor pattern and a sixth conductive structure EC2. The semiconductor pattern includes a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D arranged and connected sequentially along the first direction f1. The sixth conductive structure EC2 is the fifth conductive region DT5.

[0175] Step 23: A patterned first insulating layer GI is formed on the side of the semiconductor layer ACT facing away from the substrate 10, as shown in Figure 10. The first insulating layer GI has a first via H1, a second via H2, and a fourth via H4. The diameter of the fourth via H4 is larger than the diameters of the first via H1 and the second via H2. In the orthographic projection onto the substrate 10, the first via H1 and the second via H2 are located on opposite sides of the channel region CH. The first via H1 exposes a portion of the data line DL, the source connection region S, and the first conductive region DT1. The second via H2 exposes a portion of the first conductive structure EP1, the drain connection region D, and the second conductive region DT2. The fourth via H4 is located within the region of the sixth conductive structure EC2.

[0176] Step 24: A patterned second conductive layer M2 is formed on the side of the first insulating layer GI facing away from the substrate 10, as shown in Figure 11. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1, which is connected to the data line DL and the source connection region S, respectively. The second transition pattern ZJ2 partially covers the second via H2, which is connected to the drain connection region D and the first conductive structure EP1, respectively. The fifth conductive structure EC1 fully covers the fourth via H4, which is connected to the sixth conductive structure EC2.

[0177] As shown in Figure 11, after the second conductive layer M2 is formed, the first insulating layer GI is etched a second time using the second conductive layer M2 as a mask. Then, the semiconductor material in the exposed areas (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4) of the semiconductor layer ACT is conductord using a self-aligned process.

[0178] Step 25: A patterned second insulating layer PVX is formed on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 12. A third via H3 is provided on the second insulating layer PVX.

[0179] Step 26: A patterned transparent conductive layer TD is formed on the side of the second insulating layer PVX away from the substrate 10, as shown in Figure 13. The transparent conductive layer TD includes a second conductive structure EP2, which fully covers the third via H3 and is connected to the second transition pattern ZJ2.

[0180] In a third exemplary embodiment, as shown in FIG19, the display substrate includes: a substrate 10, and a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX, and a transparent conductive layer TD sequentially stacked on one side of the substrate 10, wherein the first conductive layer M1 is disposed close to the substrate 10.

[0181] As shown in Figure 19, the first conductive layer M1 includes a data line DL and a first conductive structure EP1. The semiconductor layer ACT includes a semiconductor pattern comprising a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D, arranged and connected sequentially along a first direction f1. A first via H1 and a second via H2 are disposed on the first insulating layer GI. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. A third via H3 is disposed on the second insulating layer PVX. The transparent conductive layer TD includes a second conductive structure EP2.

[0182] As shown in Figure 19, the first transition pattern ZJ1 connects the data line DL and the source connection region S by partially covering the first via H1. The second transition pattern ZJ2 connects the first conductive structure EP1 and the drain connection region D by partially covering the second via H2. The second conductive structure EP2 is connected to the second transition pattern ZJ2 through the third via H3, thereby connecting the second conductive structure EP2 and the first conductive structure EP1.

[0183] The storage capacitors include a first storage capacitor Cst1 and a second storage capacitor Cst2 connected in parallel. One plate of the first storage capacitor Cst1 is a first conductive structure EP1, and the other plate is a fifth conductive structure EC1. The dielectric layer includes a buffer layer BF and a first insulating layer GI. One plate of the second storage capacitor Cst2 is a second conductive structure EP2, and the other plate is a fifth conductive structure EC1. The dielectric layer is a second insulating layer PVX.

[0184] Referring to Figures 14 to 19, the display substrate provided in this embodiment can be prepared by the following steps:

[0185] Step 31: Form a patterned first conductive layer M1 on the substrate 10, as shown in FIG14. The first conductive layer M1 includes a data line DL and a first conductive structure EP1, and may also include a second shielding pattern (not shown in the figure). The orthographic projection of the second shielding pattern on the substrate 10 covers the channel region CH.

[0186] Step 32: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in Figure 15. The semiconductor layer ACT includes a semiconductor pattern, which includes a source connection region S, a first conductive region DT1, a third conductive region DT3, a channel region CH, a fourth conductive region DT4, a second conductive region DT2, and a drain connection region D arranged and connected sequentially along the first direction f1.

[0187] Step 33: A patterned first insulating layer GI is formed on the side of the semiconductor layer ACT facing away from the substrate 10, as shown in Figure 16. A first via H1 and a second via H2 are provided on the first insulating layer GI. In the orthographic projection on the substrate 10, the first via H1 and the second via H2 are located on both sides of the channel region CH. The first via H1 exposes a portion of the data line DL, the source connection region S, and the first conductor region DT1. The second via H2 exposes a portion of the first conductive structure EP1, the drain connection region D, and the second conductor region DT2.

[0188] Step 34: A patterned second conductive layer M2 is formed on the side of the first insulating layer GI facing away from the substrate 10, as shown in Figure 17. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a fifth conductive structure EC1. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1, which is connected to the data line DL and the source connection region S, respectively. The second transition pattern ZJ2 partially covers the second via H2, which is connected to the drain connection region D and the first conductive structure EP1, respectively.

[0189] As shown in Figure 17, after the second conductive layer M2 is formed, the first insulating layer GI is etched a second time using the second conductive layer M2 as a mask. Then, the semiconductor material in the exposed areas (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4) of the semiconductor layer ACT is conductord using a self-aligned process.

[0190] Step 35: A patterned second insulating layer PVX is formed on the side of the second conductive layer M2 away from the substrate 10, as shown in Figure 18. A third via H3 is provided on the second insulating layer PVX.

[0191] Step 36: A patterned transparent conductive layer TD is formed on the side of the second insulating layer PVX away from the substrate 10, as shown in Figure 19. The transparent conductive layer TD includes a second conductive structure EP2, which fully covers the third via H3 and is connected to the second transition pattern ZJ2.

[0192] In the first to third exemplary embodiments, each step corresponds to a mask process. The display substrate in the first exemplary embodiment is prepared by seven mask processes. In the second and third exemplary embodiments, since the third conductive layer M3 is not provided, the display substrate in the second and third exemplary embodiments is prepared by six mask processes, reducing one mask process.

[0193] This disclosure provides a display device, as shown in FIG21. The display device includes a counter substrate 171, an electrophoretic solution 172, and a display substrate 173 as provided in any embodiment. The electrophoretic solution 172 is located between the counter substrate 171 and the display substrate 173, and a second conductive layer M2 is located on the side of the substrate 10 near the electrophoretic solution.

[0194] The electrophoresis solution 172 includes target particles LZ. These target particles can be electrophoretic particles, such as two-color, three-color, or four-color particles; they can also be liquid crystal molecules.

[0195] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the display substrate 173 described above.

[0196] The display devices disclosed herein can be: electronic paper, electronic price tags, electronic name tags, display modules, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, in-vehicle display devices, smartwatches, fitness wristbands, personal digital assistants, and any other products or components with display functions.

[0197] For example, the counter substrate 171 includes: a counter substrate 1711, and a counter electrode 1712 disposed on the side of the counter substrate 1711 near the electrophoretic solution 172. The counter electrode 1712 and the pixel electrode EP2 together form an electric field that drives the target particle LZ to move.

[0198] For example, the electrophoresis solution 172 can be an electronic paper membrane.

[0199] For example, as shown in FIG22, the display device may further include a driver chip IC bonded to the non-display area NA of the display substrate 173, and the driver chip IC is connected to the driver circuit board 182 via the flexible circuit board 181.

[0200] During the display process, the driver chip IC can be activated through the driver circuit board 182. The driver chip IC inputs the scan signal to the scan line GL and the data signal to the data line DL, turns on the thin film transistor, and the pixel electrode EP2 of the sub-pixel PX obtains the voltage required for the image. It forms a voltage difference with the upper counter electrode 1712, thereby separating the white particles and black particles in the electrophoresis solution 172, and thus forming different display grayscale states.

[0201] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0202] In this disclosure, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0203] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0204] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0205] The use of “for” or “configured to” in this disclosure implies an open and inclusive language that does not preclude applicability to or configuration to devices for performing additional tasks or steps.

[0206] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0207] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 10° or 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between the flushes being less than or equal to 5% of either one's dimension.

[0208] It should be understood that when a layer or element is referred to as being disposed on one side of another layer or substrate, it may be that the layer or element is directly disposed on the other layer or substrate, or it may be that there is an intermediate layer between the layer or element and the other layer or substrate.

[0209] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown in this disclosure, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0210] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate comprising a plurality of sub-pixels located in a display area, the display substrate comprising: A substrate, and a first conductive layer, a semiconductor layer, a first insulating layer and a second conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer is disposed close to the substrate; The first conductive layer includes data lines and multiple first conductive structures located in different sub-pixels. The semiconductor layer includes multiple semiconductor patterns located in different sub-pixels. Each semiconductor pattern includes a source connection region, a first conductive region, a channel region, a second conductive region, and a drain connection region arranged sequentially along a first direction. The second conductive layer includes multiple gates located in different sub-pixels, and a first transition pattern and a second transition pattern disposed opposite to each other on both sides of the gates along the first direction. The first insulating layer has a first via and a second via. The first via exposes a portion of the data line, the source connection region, and the first conductor region. The second via exposes a portion of the first conductive structure, the drain connection region, and the second conductor region. The data line and the source connection region are respectively connected to the first transition pattern through the first via. The first conductive structure and the drain connection region are respectively connected to the second transition pattern through the second via. In the orthographic projection on the substrate, the first transition pattern does not overlap with the first conductor region, and the second transition pattern does not overlap with the second conductor region.

2. The display substrate according to claim 1, wherein, The semiconductor pattern also includes: A third conductive region is connected between the first conductive region and the channel region, wherein the thickness of the first conductive region is different from the thickness of the third conductive region; and A fourth conductive region is connected between the second conductive region and the channel region, and the thickness of the second conductive region is different from the thickness of the fourth conductive region.

3. The display substrate according to claim 2, wherein, The thickness of the first conductive region is less than the thickness of the third conductive region, and the thickness of the first conductive region is less than or equal to the thickness of the source connection region; and the thickness of the third conductive region is less than or equal to the thickness of the channel region; and The thickness of the second conductive region is less than the thickness of the fourth conductive region, the thickness of the second conductive region is less than or equal to the thickness of the drain connection region, and the thickness of the fourth conductive region is less than or equal to the thickness of the channel region.

4. The display substrate according to claim 1, wherein, The display substrate further includes: A second insulating layer is disposed on the side of the second conductive layer opposite to the substrate; and A transparent conductive layer is disposed on the side of the second insulating layer away from the substrate. The transparent conductive layer includes a plurality of second conductive structures located in different sub-pixels. The second conductive structures and the second transition pattern overlap through a third via disposed on the second insulating layer. The second conductive structures do not overlap with the orthographic projection of the gate on the substrate.

5. The display substrate according to claim 4, wherein, The second conductive structure includes a first sub-electrode, a second sub-electrode, and a third sub-electrode. The second sub-electrode and the third sub-electrode are located on the same side of the first sub-electrode and are respectively connected to the first sub-electrode. In the orthographic projection on the substrate, the second sub-electrode and the third sub-electrode are disposed opposite to each other on both sides of the gate along the first direction; and The gap width between the second sub-electrode and the third sub-electrode is approximately equal to the gap width between two adjacent second conductive structures.

6. The display substrate according to claim 4, wherein, The display substrate further includes: A third conductive layer is disposed between the second insulating layer and the transparent conductive layer. The third conductive layer includes a plurality of third conductive structures located in different sub-pixels. The surface of the third conductive structure facing away from the substrate is in direct contact with the surface of the second conductive structure close to the substrate. In the orthographic projection on the substrate, the second conductive structure covers the third conductive structure, and the third conductive structure covers the third via and the second transition pattern.

7. The display substrate according to claim 6, wherein, In the orthographic projection on the substrate, the second conductive structure and the third conductive structure have different shapes, the second conductive structure covers the first transition pattern, and the third conductive structure does not overlap with the first transition pattern.

8. The display substrate according to claim 6, wherein, The third conductive layer further includes a first shielding pattern, which is spaced apart from the third conductive structure, and the orthographic projection of the first shielding pattern on the substrate covers the orthographic projection of the channel region on the substrate. The transparent conductive layer further includes a protective pattern, which is spaced apart from the second conductive structure, and the orthogonal projection of the protective pattern on the substrate covers the orthogonal projection of the first shielding pattern on the substrate.

9. The display substrate according to claim 4, wherein, In the orthographic projection on the substrate, the gap width between two adjacent second conductive structures is greater than or equal to 5 micrometers and less than or equal to 15 micrometers.

10. The display substrate according to any one of claims 1 to 9, wherein, The sub-pixel also includes: A fourth conductive structure is located in the second conductive layer and / or semiconductor layer. The fourth conductive structure overlaps with the orthographic projection of the first conductive structure on the substrate. The fourth conductive structures of a plurality of sub-pixels arranged along the first direction and / or the second direction are interconnected. The second direction is the extension direction of the data line.

11. The display substrate according to claim 10, wherein, The first conductive structure includes: The fourth and fifth sub-electrodes are interconnected. In the orthographic projection on the substrate, the fifth sub-electrode is located on the side of the fourth sub-electrode closer to the gate. The width of the fifth sub-electrode along the first direction is smaller than the width of the fourth sub-electrode along the first direction. The fifth sub-electrode overlaps with the second transition pattern. The fourth conductive structure covers a portion of the fifth sub-electrode and the fourth sub-electrode.

12. The display substrate according to claim 11, wherein, The fourth conductive structure arranged in the same layer includes: The sixth and seventh sub-electrodes are interconnected. In the orthographic projection on the substrate, the seventh sub-electrode is located on the side of the sixth sub-electrode closer to the gate, and the seventh sub-electrode is located on the side of the second transition electrode away from the gate. The width of the seventh sub-electrode along the first direction is smaller than the width of the sixth sub-electrode along the first direction. The sixth sub-electrode completely covers the fourth sub-electrode, and the seventh sub-electrode covers a portion of the fifth sub-electrode.

13. The display substrate according to claim 10, wherein, The fourth conductive structure includes: A fifth conductive structure is located in the second conductive layer. The fifth conductive structure overlaps with the orthographic projection of the first conductive structure on the substrate. The fifth conductive structures of multiple sub-pixels arranged along the first direction are interconnected. A scan line is provided between two adjacent fifth conductive structures of sub-pixels arranged along the second direction. The scan line is located in the second conductive layer and connected to the gate.

14. The display substrate according to claim 13, wherein, In the orthographic projection on the substrate, the fifth conductive structure and the data line have an overlapping area, and the width of the overlapping area along the second direction is less than or equal to the width of the non-overlapping area along the second direction.

15. The display substrate according to claim 13, wherein, The fourth conductive structure further includes: A sixth conductive structure is located in the semiconductor layer. The orthographic projection of the sixth conductive structure onto the substrate overlaps with that of the first conductive structure. The sixth conductive structure is connected to the fifth conductive structure via a fourth via disposed on the first insulating layer. In the orthographic projection onto the substrate, the edge of the sixth conductive structure is located outside the edge of the fourth via. The data line is provided between the sixth conductive structures of two adjacent sub-pixels arranged along the first direction, and the scan line is provided between the sixth conductive structures of two adjacent sub-pixels arranged along the second direction.

16. The display substrate according to claim 15, wherein, In the orthographic projection on the substrate, the distance between the edge of the sixth conductive structure and the edge of the fourth via is greater than or equal to half the width of the data line along the first direction, and less than or equal to twice the width of the data line along the first direction.

17. The display substrate according to claim 15, wherein, In the orthographic projection on the substrate, the diameter of the fourth via along the first direction is greater than the diameters of the first via and the second via along the first direction, and the diameter of the fourth via along the second direction is greater than the diameters of the first via and the second via along the second direction.

18. The display substrate according to any one of claims 1 to 9, wherein, In an orthographic projection onto the substrate, the second conductive layer completely covers the first insulating layer, and a portion of the edge of the first insulating layer is approximately aligned with the edge of the second conductive layer.

19. A display device, comprising: The substrate includes a counter substrate, an electrophoretic solution, and a display substrate as described in any one of claims 1 to 18, wherein the electrophoretic solution is located between the counter substrate and the display substrate, and the second conductive layer is located on the side of the substrate closer to the electrophoretic solution.

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