Information processing method and apparatus

Abstract

An information processing method and apparatus. A first LDPC base matrix used for encoding or decoding can be divided into a plurality of G×G submatrices each having a row weight not greater than 1 and a column weight not greater than 1, enabling low hardware implementation complexity, supporting a long code length under the same hardware. In addition, the number of elements in an intersection of a first column set and a second column set is limited to be less than or equal to a first threshold, wherein the first column set is a set of columns in which non-zero elements of an i-th row of the first LDPC base matrix in a first region are located, the second column set is a set of columns in which non-zero elements of an i'-th row of the first LDPC base matrix in the first region are located, the i-th row and the i'-th row of the first LDPC base matrix can be any two rows in a first row set, and the first row set is a set of rows in which non-zero elements of each of the last x columns in a second region are located, thereby increasing the speed of information exchange, reducing decoding delay, and improving decoding performance.

Description

An information processing method and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202510129420.8, filed on January 27, 2025, entitled "An Information Processing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more specifically, to an information processing method and apparatus. Background Technology

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used coding schemes. LDPC codes are a channel coding scheme very close to Shannon lines, featuring good performance and low complexity. LDPC codes have been adopted by the 3rd Generation Partnership Project (3GPP) as a data channel coding scheme.

[0004] The current LDPC code has poor performance. Summary of the Invention

[0005] Embodiments of this application provide an information processing method and apparatus to improve the performance of LDPC codes.

[0006] In a first aspect, embodiments of this application provide an information processing method that can be applied to a first communication device, which is an encoding-side device. The first communication device can be an encoding device, a module within the encoding device (e.g., a circuit, a chip, or a chip system (such as a modem chip, also known as a baseband chip, or a system-on-a-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip), or a logical node, logical module, or software capable of implementing all or part of the encoding device. The encoding device can be a terminal or a network device.

[0007] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to a first LDPC base matrix, and outputting a codeword sequence; wherein, the first LDPC base matrix includes multiple G×G submatrices, the row weight of each row of the submatrices is less than or equal to 1 and the column weight of each column is less than or equal to 1, and G is an integer greater than 1; the first LDPC base matrix includes a first region and a second region, the first region includes the X1 row and Y1 column of the first LDPC base matrix, the X1 row belongs to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column includes the punched information column of the first LDPC base matrix, and i1 is an integer greater than 1; the second region includes the X2 row and G column of the first LDPC base matrix, the X2 ... the Y1 column includes the punched information column of the first LDPC base matrix, the Y1 column includes the punched information column of the first LDPC base matrix, and the Y1 column includes the punched information column of the first LDPC base matrix, the Y1 column includes the punched information column of the first LDPC base matrix, and the Y1 column includes the punched information column of the first LDPC base matrix, the Y1 column includes the punched information The first LDPC basis matrix consists of rows 1 to G×i1, where X2 is the row containing the non-zero elements of column G. Column G is a check column of the first LDPC basis matrix and belongs to the same submatrix. The column containing the non-zero elements of row i in the first region of the first LDPC basis matrix forms a first column set, and the column containing the non-zero elements of row i' in the first region of the first LDPC basis matrix forms a second column set. The number of elements in the intersection of the first column set and the second column set is less than or equal to a first threshold. Row i and row i' are any two rows in the first row set. The first row set is the set of rows containing the non-zero elements of each column from the last column to the last x column of the second region, where x is a positive integer less than G.

[0008] Based on the above method, the first LDPC basis matrix can be divided into multiple G×G submatrices with row weights no greater than 1 and column weights no greater than 1. This reduces hardware implementation complexity and allows for longer code lengths with the same hardware. Furthermore, restricting the number of elements in the intersection of the first and second column sets to be less than or equal to a first threshold speeds up information exchange, reduces decoding latency, and improves decoding performance. In addition, this method also exhibits good decoding performance in high-throughput scenarios.

[0009] In conjunction with the first aspect, in some implementations, the first threshold is 0, 1, or 2.

[0010] A smaller first threshold value results in a larger convergence amplitude. A larger first threshold value allows for a larger design space, which helps to improve the decoding threshold. Therefore, by selecting different first threshold values, a trade-off can be achieved between the convergence amplitude and the decoding threshold.

[0011] In conjunction with the first aspect or any of its implementations, in some other implementations, in the first row pairs obtained by combining rows of the first row set in pairs, the number of first row pairs that satisfy the first condition is less than the second threshold; wherein, the first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

[0012] Based on the above implementation method, the speed of information exchange can be further accelerated, the decoding latency can be reduced, and the decoding performance can be improved.

[0013] In conjunction with the first aspect or any of its implementations, in some other implementations, the second threshold is 0 or 1.

[0014] A smaller second threshold value results in a larger convergence amplitude. A larger second threshold value allows for a larger design space, which helps to improve the decoding threshold. Therefore, by selecting different second threshold values, a balance can be achieved between the convergence amplitude and the decoding threshold.

[0015] In conjunction with the first aspect or any of its implementations, in some other implementations, the column containing the non-zero elements of the i”th row of the first LDPC basis matrix in the first region constitutes a third column set, wherein the i”th row is any row in the second row set, and the rows in the second row set belong to the first row to the G×i1th row of the first LDPC basis matrix but do not belong to the first row set; the number of elements in the intersection of the first column set and the third column set is less than or equal to a third threshold.

[0016] Based on the above implementation method, the speed of information exchange can be further accelerated, and it can be applied to a wider range of bit rates, with gains not only at peak bit rates but also at higher bit rates.

[0017] In conjunction with the first aspect or any of its implementations, in some other implementations, the third threshold is 0, 1, or 2.

[0018] A smaller third threshold value results in a larger convergence amplitude. A larger third threshold value allows for a larger design space, which helps to improve the decoding threshold. Therefore, by selecting different third threshold values, a balance can be achieved between the convergence amplitude and the decoding threshold.

[0019] In conjunction with the first aspect or any of its implementations, in some other implementations, in the second row pairs obtained by combining rows from the first row set and rows from the second row set in pairs, the number of second row pairs that satisfy the first condition is less than the fourth threshold; wherein, the first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

[0020] Based on the above implementation method, the speed of information exchange can be further accelerated, and it can be applied to a wider range of bit rates, with gains not only at peak bit rates but also at higher bit rates.

[0021] In conjunction with the first aspect or any of its implementations, in some other implementations, the fourth threshold is 0 or 1.

[0022] A smaller fourth threshold value results in a larger convergence amplitude. A larger fourth threshold value allows for a larger design space, which helps to improve the decoding threshold. Therefore, by selecting different fourth threshold values, a balance can be achieved between the convergence amplitude and the decoding threshold.

[0023] In conjunction with the first aspect or any of its implementations, in some other implementations, the first LDPC basis matrix is ​​obtained by boosting a second LDPC basis matrix; wherein, the zero elements in the second LDPC basis matrix are boosted to obtain a first-type G×G submatrix in the first LDPC basis matrix, and the non-zero elements in the second LDPC basis matrix are boosted to obtain a second-type G×G submatrix in the first LDPC basis matrix, the elements of the first-type G×G submatrix are all 0, and the row weight of each row of the second-type G×G submatrix is ​​1 and the column weight of each column is 1. Compared to encoding using a second LDPC basis matrix, this implementation can obtain a larger first LDPC basis matrix. Encoding based on a larger-scale first LDPC basis matrix helps improve the performance of LDPC codes with low iteration counts.

[0024] In conjunction with the first aspect or any of its implementations, in some other implementations, the X1 row is the first row to the G×i1 row of the first LDPC basis matrix, the first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix, the fourth region comprising one row, and the translation value of the third region satisfies: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1

[0025] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

[0026] In conjunction with the first aspect or any of its implementations, in some other implementations, the X1 row is the first row to the G×i1 row of the first LDPC basis matrix, the first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix, the fourth region includes one row, and the number of rows and columns satisfying the second condition in the third region is less than a fifth threshold, wherein the second condition is: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)=0

[0027] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

[0028] In conjunction with the first aspect or any of its implementations, in some other implementations, the first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region comprises multiple rows, and the row set of the fourth region is the same as the row set of the third region. The translation values ​​of the third region and the fourth region satisfy: mod(SV) p,q -SV p',q +SV p',q' -SVp,q' ,G)≥1

[0029] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

[0030] In conjunction with the first aspect or any of its implementations, in some other implementations, the first region of the first LDPC base matrix corresponds to the third region of the second LDPC base matrix, and the second region of the first LDPC base matrix corresponds to the fourth region of the second LDPC base matrix. The fourth region comprises multiple rows, and the row set of the fourth region is the same as the row set of the third region. The number of rows and columns satisfying the second condition in the third and fourth regions is less than a sixth threshold, wherein the second condition is: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)=0

[0031] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

[0032] In conjunction with the first aspect or any of its implementations, in some other implementations, X2 is a multiple of G by w, where w is an integer; when w equals 1, the X1 row is the row from the 1st row to the G×i1th row; and / or, when w is greater than 1, the X1 row is the same as the X2 row.

[0033] In conjunction with the first aspect or any of its implementations, in some other implementations, the first column of the second region is the Gth-th core check column from the end of the first LDPC base matrix, the first extended check column of the first LDPC base matrix, or the 2Gth-th-th core check column from the end of the first LDPC base matrix.

[0034] In conjunction with the first aspect or any of its implementations, in some other implementations, the columns of the second region are punch verification columns.

[0035] In conjunction with the first aspect or any of its implementations, in some other implementations, rows 1 to G×i1 are the core rows of the first LDPC base matrix; or, rows 1 to G×i1 include the core rows of the first LDPC base matrix and G extended rows.

[0036] In conjunction with the first aspect or any of its implementations, in some other implementations, i1 is 4, 5, or 6.

[0037] In some implementations, G is 2 or 3, in conjunction with the first aspect or any of its implementations.

[0038] Secondly, embodiments of this application provide an information processing method that can be applied to a second communication device, which is a decoding-side device. The second communication device can be a decoding device, a module within the decoding device (e.g., a circuit, a chip, or a chip system (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core), or a logical node, logical module, or software capable of implementing all or part of the decoding device. The decoding device can be a network device or a terminal. This second aspect is a decoding-side method corresponding to the first aspect. Descriptions of the same terms can refer to the first aspect or its implementation. The beneficial effects of the second aspect or its implementation can refer to the beneficial effects of the first aspect or its corresponding implementation, and will not be repeated here.

[0039] The method includes: acquiring information to be decoded; decoding the information according to a first LDPC base matrix to obtain a decoded bit sequence; wherein, the first LDPC base matrix includes multiple G×G sub-matrices, the row weight of each row of the sub-matrices is less than or equal to 1 and the column weight of each column is less than or equal to 1, and G is an integer greater than 1; the first LDPC base matrix includes a first region and a second region, the first region includes the X1 row and Y1 column of the first LDPC base matrix, the X1 row belongs to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column includes the punch information column of the first LDPC base matrix, i1 is an integer greater than 1, the second region includes the X2 row and G column of the first LDPC base matrix, the X2 row belongs to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column includes the punch information column of the first LDPC base matrix, i1 is an integer greater than 1, and the second region includes the X2 row and G column of the first LDPC base matrix, the X2 row belongs to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column includes the punch information column of the first LDPC base matrix, and i1 is an integer greater than 1; the second region includes the X2 row and G column of the first LDPC base matrix, the X2 row belongs to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column includes the punch information column of the first LDPC base matrix, and the Y1 column includes the punch information column of the first LDPC base matrix, ... The first LDPC basis matrix consists of rows 1 to G×i1, where X2 is the row containing the non-zero elements of column G. Column G is a check column of the first LDPC basis matrix and belongs to the same submatrix. The column containing the non-zero elements of row i in the first region of the first LDPC basis matrix forms a first column set, and the column containing the non-zero elements of row i' in the first region of the first LDPC basis matrix forms a second column set. The number of elements in the intersection of the first column set and the second column set is less than or equal to a first threshold. Row i and row i' are any two rows in the first row set. The first row set is the set of rows containing the non-zero elements of each column from the last column to the last x column of the second region, where x is a positive integer less than G.

[0040] In conjunction with the second aspect, in some implementations, the first threshold is 0, 1, or 2.

[0041] In conjunction with the second aspect or any of its implementations, in some other implementations, in the first row pairs obtained by combining rows of the first row set in pairs, the number of first row pairs that satisfy the first condition is less than the second threshold; wherein, the first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

[0042] In conjunction with the second aspect or any of its implementations, in some other implementations, the second threshold is 0 or 1.

[0043] In conjunction with the second aspect or any of its implementations, in some other implementations, the column containing the non-zero elements of the i”th row of the first LDPC basis matrix in the first region constitutes a third column set, wherein the i”th row is any row in the second row set, and the rows in the second row set belong to the first row to the G×i1th row of the first LDPC basis matrix but do not belong to the first row set; the number of elements in the intersection of the first column set and the third column set is less than or equal to a third threshold.

[0044] In conjunction with the second aspect or any of its implementations, in some other implementations, the third threshold is 0, 1, or 2.

[0045] In conjunction with the second aspect or any of its implementations, in some other implementations, in the second row pairs obtained by combining rows from the first row set and rows from the second row set in pairs, the number of second row pairs that satisfy the first condition is less than the fourth threshold; wherein, the first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

[0046] In conjunction with the second aspect or any of its implementations, in some other implementations, the fourth threshold is 0 or 1.

[0047] In conjunction with the second aspect or any of its implementations, in some other implementations, the first LDPC basis matrix is ​​obtained by promoting the second LDPC basis matrix; wherein, the zero elements in the second LDPC basis matrix are promoted to obtain a first-type G×G submatrix in the first LDPC basis matrix, the non-zero elements in the second LDPC basis matrix are promoted to obtain a second-type G×G submatrix in the first LDPC basis matrix, the elements of the first-type G×G submatrix are all 0, and the row weight of each row of the second-type G×G submatrix is ​​1 and the column weight of each column is 1.

[0048] In conjunction with the second aspect or any of its implementations, in some other implementations, the X1 row is the first row to the G×i1 row of the first LDPC basis matrix, the first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix, the fourth region comprising one row, and the translation value of the third region satisfies: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1

[0049] Where mod() represents the remainder, SVp,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

[0050] In conjunction with the second aspect or any of its implementations, in some other implementations, the X1 row is the first row to the G×i1 row of the first LDPC base matrix, the first region of the first LDPC base matrix corresponds to the third region of the second LDPC base matrix, the second region of the first LDPC base matrix corresponds to the fourth region of the second LDPC base matrix, the fourth region includes one row, and the number of rows and columns satisfying the second condition in the third region is less than a fifth threshold, wherein the second condition is: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)=0

[0051] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

[0052] In conjunction with the second aspect or any of its implementations, in some other implementations, the first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region comprises multiple rows, and the row set of the fourth region is the same as the row set of the third region. The translation values ​​of the third region and the fourth region satisfy: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1

[0053] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

[0054] In conjunction with the second aspect or any of its implementations, in some other implementations, the first region of the first LDPC base matrix corresponds to the third region of the second LDPC base matrix, and the second region of the first LDPC base matrix corresponds to the fourth region of the second LDPC base matrix. The fourth region comprises multiple rows, and the row set of the fourth region is the same as the row set of the third region. The number of rows and columns satisfying the second condition in the third and fourth regions is less than a sixth threshold, wherein the second condition is: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)=0

[0055] Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

[0056] In conjunction with the second aspect or any of its implementations, in some other implementations, X2 is a multiple of G by w, where w is an integer; when w equals 1, the X1 row is the row from the 1st row to the G×i1th row; and / or, when w is greater than 1, the X1 row is the same as the X2 row.

[0057] In conjunction with the second aspect or any of its implementations, in some other implementations, the first column of the second region is the Gth-th core check column from the end of the first LDPC base matrix, the first extended check column of the first LDPC base matrix, or the 2Gth-th-th core check column from the end of the first LDPC base matrix.

[0058] In conjunction with the second aspect or any of its implementations, in some other implementations, the columns of the second region are punch verification columns.

[0059] In conjunction with the second aspect or any of its implementations, in some other implementations, the first row to the G×i1th row are the core rows of the first LDPC base matrix; or, the first row to the G×i1th row include the core rows of the first LDPC base matrix and G extended rows.

[0060] In conjunction with the second aspect or any of its implementations, in some other implementations, i1 is 4, 5, or 6.

[0061] In combination with the second aspect or any of its implementations, in some other implementations, G is 2 or 3.

[0062] Thirdly, embodiments of this application provide a communication device that has the function of implementing the first aspect or any of its implementations. For example, the communication device includes modules, units, or means corresponding to the operations involved in the first aspect or any of its implementations. These modules, units, or means can be implemented in software, hardware, or a combination of software and hardware. This communication device can be the first communication device in the first aspect described above.

[0063] Fourthly, embodiments of this application provide a communication device that has the function of implementing the second aspect or any of its implementations. For example, the communication device includes modules, units, or means corresponding to the operations involved in the second aspect or any of its implementations. These modules, units, or means can be implemented in software, hardware, or a combination of software and hardware. This communication device can be the second communication device described in the second aspect.

[0064] Fifthly, embodiments of this application provide a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions involved in the first aspect or any of its implementations. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in the first aspect or any of its implementations when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0065] In one possible implementation, the processor is used to communicate with other devices or components through the interface circuit.

[0066] In one possible implementation, the communication device may also include the memory. Optionally, the memory and processor are integrated together.

[0067] The aforementioned communication device may be a terminal, or a communication module in a terminal, or a chip in a terminal that is responsible for communication functions, such as a modem chip or a SoC or SIP chip containing a modem module.

[0068] The aforementioned communication device may also be a network device, a module (e.g., a circuit, chip, or chip system) within a network device, or a logical node, logical module, or software that can implement all or part of a network device.

[0069] Sixthly, embodiments of this application provide a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions involved in the second aspect or any of its implementations. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in the second aspect or any of its implementations when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0070] In one possible implementation, the processor is used to communicate with other devices or components through the interface circuit.

[0071] In one possible implementation, the communication device may also include the memory. Optionally, the memory and processor are integrated together.

[0072] The aforementioned communication device may be a terminal, or a communication module in a terminal, or a chip in a terminal that is responsible for communication functions, such as a modem chip or a SoC or SIP chip containing a modem module.

[0073] The aforementioned communication device may also be a network device, a module (e.g., a circuit, chip, or chip system) within a network device, or a logical node, logical module, or software that can implement all or part of a network device.

[0074] In a seventh aspect, embodiments of this application provide a communication system including at least one of the first communication device or the second communication device described above.

[0075] Eighthly, embodiments of this application provide a computer-readable storage medium storing computer-readable instructions that, when read and executed by a computer, cause the computer to perform any of the above aspects or any implementation thereof.

[0076] Ninthly, embodiments of this application provide a computer program product that, when read and executed by a computer, causes the computer to perform the method in any of the above aspects or any of its implementations.

[0077] In a tenth aspect, embodiments of this application provide a computer program that, when run on a computer, causes the methods provided in any of the foregoing aspects or their possible implementations to be executed. Attached Figure Description

[0078] Figure 1 is a schematic diagram of a network architecture applicable to embodiments of this application.

[0079] Figure 2 is a schematic diagram of the information transmission process applicable to an embodiment of this application.

[0080] Figure 3 is the Tanner plot of the parity-check matrix H.

[0081] Figure 4 shows the fifth generation (5) th A schematic diagram of the matrix structure of the base graph of the LDPC code (generation, 5G).

[0082] Figure 5 is a schematic diagram of 5G LDPC code.

[0083] Figure 6 is a schematic flowchart of the information processing method 600 provided in this application.

[0084] Figure 7 is an example of rows from row 1 to row G×i1 associated with column G.

[0085] Figure 8 is an example of the correspondence between row X1 of the first region and row X2 of the second region.

[0086] Figure 9 is another example of the correspondence between row X1 of the first region and row X2 of the second region.

[0087] Figure 10 is an example of the first column set and the second column set.

[0088] Figure 11 is another example of the first column set and the second column set.

[0089] Figure 12 is an example of the first and third column sets.

[0090] Figure 13 is another example of the first and third column sets.

[0091] Figure 14 is an example of obtaining the first LDPC basis matrix by lifting the second LDPC basis matrix.

[0092] Figure 15 shows an example of the third and fourth regions.

[0093] Figure 16 shows another example of the third and fourth regions.

[0094] Figure 17 shows a performance comparison between the new radio (NR) LDPC code and the LDPC code of this application at different code lengths.

[0095] Figure 18 shows a performance comparison between existing multi-stage boosted LDPC codes and the LDPC codes of this application at different code lengths.

[0096] Figure 19 is a schematic diagram of a device provided in an embodiment of this application.

[0097] Figure 20 is another structural schematic diagram of the device provided in an embodiment of this application.

[0098] Figure 21 is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0099] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0100] The terms "system" and "network" are used interchangeably. "For indicating" or "indication" can include both direct and indirect indication, or in other words, "for indicating" or "indication" can be explicit and / or implicit. Various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the NR protocol, and related protocols applied to future communication systems; this application does not limit this. Words such as "exemplary," "for example," "exemplarily," and "as (another) example" are used to indicate that something is an example, illustration, or description. Any embodiment or design scheme described as an "example" in this application should not be construed as being better or more advantageous than other embodiments or design schemes. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, R and / or U can mean: R alone, R and U simultaneously, or U alone, where R and U can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element S sending messages, information, or data to network element T, and network element T receiving messages, information, or data from network element S, aim to specify which network element the message, information, or data is to be sent to, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, and do not require the device to perform a judgment action during implementation, nor do they imply any other limitations. "Greater than or equal to" and "greater than" are interchangeable, as are "less than or equal to" and "less than."

[0101] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0102] The following describes a communication system to which embodiments of this application can be applied.

[0103] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems or NR systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, long term evolution-vehicle (LTE-V) communication, long term evolution-machine (LTE-M) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. The embodiments of this application can also be applied to satellite communication systems, high altitude platform station (HAPS) communications, unmanned aerial vehicles (UAVs), and other non-terrestrial network (NTN) systems, such as integrated communication and navigation (ICAN) systems, global navigation satellite systems (GNSS), and ultra-dense low-Earth orbit (LEO) satellite communication systems. Furthermore, it can be extended to similar wireless communication systems, such as wireless local area networks (WLANs), wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and other communication systems related to the 3rd generation partnership project (3GPP).

[0104] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminals. Optionally, both the transmitting device and the receiving device may be network devices.

[0105] In this application, the transmitting device can be understood as a data or information transmitting device, or an encoding device. The receiving device can be understood as a data or information receiving device, or a decoding device.

[0106] For example, Figure 1 shows a schematic diagram of a network architecture to which embodiments of this application may be applied.

[0107] Figure 1 illustrates a possible, non-limiting system diagram. As shown in Figure 1, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal (120a-120j in Figure 1, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wired connected to core network 200. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0108] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0109] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0110] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. The RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node's functions.

[0111] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0112] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0113] In the embodiments of this application, the access network device may also be simply referred to as a network device.

[0114] A terminal is a device or module that connects to the aforementioned communication system and possesses corresponding communication functions. Terminals can also be called terminal equipment, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, and smart cities. The terminal can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, wearable device, vehicle device (such as a complete vehicle device, vehicle module, vehicle chip, on-board unit (OBU) or telematics box (T-BOX)), flight equipment (e.g., drone, helicopter, airplane, hot air balloon), ship, robot, robotic arm, smart home device, transportation vehicle with wireless communication capabilities, communication module, smart point of sale (POS) machine, customer-premises equipment (CPE), light user equipment (light UE), reduced capability user equipment (REDCAP UE), vehicle-mounted equipment (e.g., car, bicycle, electric vehicle, airplane, ship, train, high-speed rail, etc.), satellite terminal, etc. The embodiments of this application do not limit the device form of the terminal. The terminal typically contains a communication module, circuit, or chip that performs the corresponding communication function. The terminal can also be configured with program instructions for performing the corresponding communication function.

[0115] Unless otherwise specified, the means for implementing the functions of a terminal or network device in this application can refer to the terminal or network device itself, or it can refer to a means that enables the terminal or network device to implement the function, such as a system-on-a-chip (SoC) or a chip, specifically a SoC or a modem. This means can be installed in the terminal or network device. In the embodiments of this application, the SoC can be composed of chips, or it can include chips and other discrete devices.

[0116] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0117] Figure 2 is a schematic diagram of the information transmission process according to an embodiment of this application. As shown in Figure 2, information is sent from a source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery, and other processing, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 2 (including source coding, channel coding, and modulation) is performed on the coding side, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed on the decoding side.

[0118] The embodiments of this application can be implemented in hardware, such as through a dedicated chip or a programmable chip, or by a processor executing software instructions, and mainly involve channel coding and channel decoding as shown in Figure 2. It should be noted that the embodiments of this application can be used for the channel decoding part, and the decoding method of the embodiments of this application is a general decoding means, effective for any coding scheme; therefore, the embodiments of this application do not limit the channel coding scheme.

[0119] Furthermore, the embodiments of this application can be applied to one or more specific application scenarios, or they can be general methods applicable to various application scenarios. Application scenarios may include peak rate scenarios, high throughput scenarios, high reliability scenarios, low latency scenarios, high reliability low latency scenarios, or low power consumption scenarios, etc. High-throughput scenarios include enhanced mobile broadband (eMBB), eMBB+, extended-reality (XR), cloud gaming (CG), and augmented reality (AR). High-reliability and low-latency scenarios include ultra-reliable low-latency communication (URLLC) and hyper-reliable low-latency communication (HRLLC). Low-power scenarios include M2M, MTC, massive MTC (mMTC), IoT, narrowband Internet of Things (NB-IoT), advanced Internet of Things (A-IoT), and low-power wide-area (LPWA).

[0120] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application will be briefly explained.

[0121] The concepts and terms described below are based on those specified in the agreement, but do not imply that the embodiments of this application can only be applied to existing systems. The concepts and terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms related to functional descriptions) may be adjusted as future systems develop.

[0122] 1. LDPC code

[0123] LDPC codes are linear block codes with sparse parity-check matrices. The proportion of non-zero elements in the parity-check matrix of an LDPC code is extremely small; in other words, the row and column weights of the parity-check matrix are very small compared to the code length of the LDPC. For an LDPC code with K information bits and a code length of N, the dimension of its parity-check matrix H is (NK) × N, and the corresponding codeword c can be defined by the parity-check matrix H as: c = {c | Hc} T=0, c∈{0,1} N}

[0124] .

[0125] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and the NK parity-check equations correspond to the NK parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. In the check matrix, the number of non-zero elements in each row represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree; the corresponding LDPC code is a regular code. Otherwise, it is an irregular code. For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0126] Where v0, v1, ..., v9 represent variable nodes, and c0, c1, ..., c4 represent check nodes.

[0127] LDPC codes can be represented using graphical models, such as Tanner graphs, factor graphs, and tree graphs, with Tanner graphs offering the most concise and intuitive representation. The Tanner graph of the parity-check matrix H is shown in Figure 3. The degree in Figure 3 corresponds to the definition of degree in the parity-check matrix H, where the degree of a node is defined as the number of edges connected to it. In a Tanner graph, a cycle is defined as a structure that starts from a vertex, follows non-repeating edges, passes through non-repeating vertices, and eventually returns to the starting point. Since a Tanner graph is bipartite, the length of its cycles can only be an even number greater than 2, such as 4, 6, or 8. Short cycles are detrimental to LDPC codes, primarily in two ways: short cycles form trap sets, significantly impacting the code distance; and short cycles introduce correlations into the confidence propagation decoding algorithm, leading to inaccurate mutual information estimation. Therefore, short cycles should be avoided as much as possible in the design of LDPC codes.

[0128] 2. Quasi-cyclic low-density parity check (QC-LDPC) code

[0129] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes.

[0130] QC-LDPC codes are represented using BG (Browser Group). Elements in BG are either 0 or 1, and a 1 in BG can be extended to Z. C ×Z C The cyclic displacement matrix BG, where 0 can be extended to Z C ×Z C The zero matrix is ​​expanded to obtain the parity matrix. Where Z... C Z is the lifting size. C It can also be referred to as boost size, expansion factor, boost value, expansion coefficient, or boost dimension, etc. Z C It can also be denoted as Z. The BG model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, and F represents the edge relationships. The boosted value is Z. C After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, E is the edge relationship between the variable node and the check node, the corresponding number of columns in the check matrix N = |V| = Zc|X|, the number of rows in the check matrix M = |C| = Zc|Y|, and the number of non-zero elements in the check matrix is ​​|E| = Zc|F|.

[0131] BG can also be expressed in matrix form, denoted as H. BG Based on the basis matrix H BG And the boost value Zc, which can transform the basis matrix H BG It is expanded into a complete parity-check matrix for encoding or decoding. The lifting process involves... BG The element in the middle is promoted to a Z. C ×Z C A square matrix, where 0 is promoted to Z. C ×Z C The 0 matrix is ​​transformed into an identity matrix by a rightward circular shift of matrix Pi,j, where Pi,j is the shifting value (SV) corresponding to the i-th row and j-th column. Let Z... C The results of a cyclic shift of 4, 0, 1, 2, 3 are shown below:

[0132] 3. Base map of 5G LDPC code

[0133] The base map of 5G LDPC code includes BG1 and BG2, which share a common matrix structure.

[0134] Figure 4 is a schematic diagram of the matrix structure of the 5G LDPC code base map. The 5G LDPC code base map can be divided into five regions: A, B, C, D, and E. Region A is the high-rate region, corresponding to the high-rate information columns. Region B is the core check region, corresponding to the high-rate. Region C is an all-zero region, a zero matrix. Region D is the incremental redundancy region, corresponding to the low-rate. Region E is a diagonal region (e.g., a raptor-like region), possessing an identity matrix structure.

[0135] The elements of the base graph take values ​​of 0 or 1, where a value of 0 represents an empty element or a zero element, and a value of 1 represents an edge present at that position in the base graph or an association between the corresponding check node and the variable node.

[0136] 5G LDPC codes include fixed punched columns, as shown in the dashed box in Figure 4. For example, the first two columns of BG1 and BG2 are fixed punched columns. In terms of matrix characteristics, the column weight (i.e., the number of all 1s contained in the column) of a punched column is very large. In terms of transmission characteristics, the bits corresponding to the punched positions are not transmitted, and the receiver has no received information about this part. The receiver sets its log-likelihood ratio to 0 and recovers the information of the punched positions through decoding.

[0137] In 5G LDPC codes, the protocol specifies storing the largest possible base map. In practical applications, different matrix regions are selected based on the code rate. Specifically, rows 1 to M0 and columns 1 to N0 are selected. As the code rate decreases, M0 and N0 gradually increase, and the area of ​​the matrix used also gradually expands. For example, the dashed boxes in Figure 5 that contain high code rate regions correspond to different code rates.

[0138] The base map of 5G LDPC code has a nested characteristic, meaning that low code rate regions contain high code rate regions.

[0139] 4. Information column and validation column

[0140] The columns of the LDPC base matrix consist of information columns and check columns.

[0141] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to area A.

[0142] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check column is the column corresponding to region B, and the extended check column is the column corresponding to region C or region E. Extended check columns can also be called raptor-like columns.

[0143] 5. Core rows, extended rows, core columns, and extended columns

[0144] Core rows: The core rows of the LDPC base matrix are the rows corresponding to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or regions A, B, or C.

[0145] Extended rows: Rows corresponding to area D or area E.

[0146] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate regions, or the columns corresponding to regions A and B.

[0147] Extended columns: Columns corresponding to range C or range E.

[0148] 6. Drilling column

[0149] In LDPC codes, punching a column means not sending the information bits corresponding to that column; the column that is punched is called the punched column.

[0150] Punch columns can include information columns and / or check columns. The information column that is punched can be called the punch information column. The check column that is punched can be called the punch check column. The punch information column can be a fixed punch column, as shown in the columns within the dashed box in Figure 4, such as the first two columns of BG1 and BG2. The punch check column can refer to the check column that may be punched due to rate matching.

[0151] It should be noted that, in the embodiments of this application, the base matrix can refer to a matrix with elements of 0 or 1, wherein elements represented as 0 can be replaced by a Z*Z all-zero matrix, and elements represented as 1 can be replaced by a Z*Z cyclic permutation matrix.

[0152] It should also be noted that the embodiments of this application are described based on code length, information length, and code rate, and these terms are explained here. Information length refers to the number of information bits to be transmitted. These information bits may or may not include cyclic redundancy check (CRC) bits, and are not limited thereto. Code length refers to the length of the (to be) transmitted bits, which can be the number of transmitted bits corresponding to the modulated symbol. Code rate refers to the ratio of the number of information bits to the number of transmitted bits. Code length, information length, and code rate can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, and can also be directly obtained and calculated by the transceiver. More specifically, code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits; code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS) table.

[0153] It should also be noted that the row and / or column numbers of the basis matrix can start from 1, for example, the row number of the first row of the basis matrix is ​​1, and the column number of the second column of the basis matrix is ​​2. Alternatively, the row and / or column numbers of the basis matrix can start from 0, for example, the row number of the first row of the basis matrix is ​​0, and the column number of the second column of the basis matrix is ​​1. The following description uses the example of starting the row and column numbers of the basis matrix from 1.

[0154] The relevant terms used in the embodiments of this application have been described above, and will not be explained further below.

[0155] Currently, the maximum boost value Z of 5G LDPC codes is... max =384, the maximum supported information length is 22*384, and the hardware of LDPC code is based on the maximum boost value Z. max The design process is underway. Future demands for information length may be even greater, in which case:

[0156] One possible solution is for: Z max Expand. Expand Z max The proposed solution would result in a heavy hardware burden and would not be able to reuse existing hardware. Furthermore, the existing LDPC code shift values ​​are complex to design, and in order to support longer information lengths, the shift values ​​need to be changed, because reusing the current shift values ​​would result in a significant performance loss.

[0157] Another possible solution is to perform a second lifting operation on the current base graph. This second lifting operation could involve performing two lifting operations on the base graph to obtain the parity check matrix. The first lifting operation expands the 1s in the base graph (BG) to a G×G matrix with both row and column weights of 1, and expands the 0s in the base matrix to a G×G matrix of 0s, resulting in BG0. The second lifting operation expands the 1s in BG0 to Z... C ×Z C The cyclic shift matrix, and the expansion of 0 in BG0 to Z C ×Z C The zero matrix, and the description of the second boost, can be found in the relevant description in QC-LDPC codes. However, the performance of the second boost scheme is not stable.

[0158] To address the aforementioned problems, this application provides an information processing method and a communication device to improve the performance of LDPC codes.

[0159] The method embodiments of this application are described below with reference to the accompanying drawings.

[0160] Figure 6 is a schematic flowchart of the information processing method 600 provided in this application.

[0161] Method 600 can be executed by a first communication device and a second communication device. The first communication device is an encoding-side device; for example, it can be an encoding device, a module within an encoding device, or a logic node, logic module, or software capable of implementing all or part of the functions of the encoding device. The second communication device is a decoding-side device; for example, it can be a decoding device, a module within a decoding device, or a logic node, logic module, or software capable of implementing all or part of the functions of the decoding device. The modules in the encoding or decoding device can be, for example, circuits, chips, or chip systems (such as modem chips, or SoC chips or SIP chips containing modem cores, etc.). Exemplarily, the encoding device can be a terminal or a network device. Exemplarily, the decoding device can be a network device or a terminal.

[0162] Method 600 may include at least a portion of the following.

[0163] Step 601: The first communication device acquires the information bit sequence.

[0164] In other words, if the first communication device needs to communicate with the second communication device, that is, if the first communication device needs to send a signal to the second communication device, the first communication device needs to first obtain the information bit sequence corresponding to the signal to be sent to the second communication device.

[0165] The phrase "the first communication device acquires the information bit sequence" can refer to: the first communication device performing source encoding on source symbols to generate the information bit sequence. Alternatively, it can refer to: the first communication device receiving the information bit sequence from other communication devices.

[0166] Step 602: The first communication device encodes the information bit sequence according to the first LDPC base matrix and outputs the codeword sequence.

[0167] In one implementation, the first communication device selects a first LDPC base matrix and a boost value based on at least one of the target code length, target code rate, or application scenario. Then, it determines the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix based on the first LDPC base matrix and the boost value. Next, based on the boost value and the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix, it expands the first LDPC base matrix into a parity-check matrix. Finally, it uses the expanded parity-check matrix to encode the information bit sequence to obtain a codeword sequence. One implementation of the first communication device selecting the first LDPC base matrix based on information such as the target code length, target code rate, and application scenario is as follows: the first communication device selects a portion or all of the matrix region from the largest stored base matrix based on at least one of the target code length, target code rate, and application scenario.

[0168] In step 603, the first communication device sends a symbol sequence to the second communication device based on the codeword sequence. Correspondingly, the second communication device receives the symbol sequence from the first communication device.

[0169] The symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the first communication device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0170] Understandably, since the symbol sequence may introduce channel noise signals during transmission, the symbol sequence sent by the first communication device and the symbol sequence received by the second communication device may be different.

[0171] Step 604: The second communication device decodes the information to be decoded according to the first LDPC basis matrix to obtain the information bit sequence.

[0172] For example, the information to be decoded can be a sequence of symbols.

[0173] For example, the information to be decoded can also be based on information obtained from a symbol sequence. In other words, the second communication device can process the received symbol sequence to obtain the information to be decoded. For instance, the information to be decoded can be information obtained after demodulation of the symbol sequence. As another example, the information to be decoded can be information obtained after demodulation and distribution matching processing.

[0174] In some implementations, the second communication device can select a first LDPC base matrix and a boost value based on at least one of the target code length, target code rate, or application scenario. Then, it determines the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix based on the first LDPC base matrix and the boost value. Next, based on the boost value and the shift values ​​corresponding to the non-zero elements of the first LDPC base matrix, it expands the first LDPC base matrix into a parity check matrix. Finally, it uses the expanded parity check matrix to decode the information to be decoded, obtaining the information bit sequence. One implementation where the second communication device selects the first LDPC base matrix based on information such as the target code length, target code rate, and application scenario is as follows: the second communication device selects a portion or all of the matrix region from the largest stored base matrix based on at least one of the target code length, target code rate, and application scenario.

[0175] The first LDPC basis matrix of the embodiments of this application will be described in detail below.

[0176] The first LDPC basis matrix in embodiments of this application may include multiple G×G submatrices, where G is an integer greater than or equal to 2, such as G = 2 or 3. The first LDPC basis matrix may consist of multiple G×G submatrices, meaning the number of rows and columns of the first LDPC basis matrix are both integer multiples of G; the first LDPC basis matrix may also further include areas beyond the multiple G×G submatrices, without limitation. It should be understood that the first LDPC basis matrix may include multiple G×G submatrices, or it can be described as: part or all of the region of the first LDPC basis matrix can be divided into multiple G×G submatrices.

[0177] In some implementations, multiple G×G submatrices can include first-type submatrices and second-type submatrices. The first-type submatrices are G×G zero matrices. The second-type submatrices have a row weight of 1 and a column weight of 1, and can have multiple element arrangements. This multiple element arrangement of the second-type submatrices can also be described as: the elements of the second-type submatrices have multiple permutations.

[0178] Taking G=2 as an example, the first type of submatrix is: The second type of submatrix includes two element arrangement methods. Specifically, the second type of submatrix includes... and

[0179] Taking G as 3 as an example, the first type of submatrix is: The second type of submatrix includes six possible element arrangements. Specifically, the second type of submatrix includes... or

[0180] The first LDPC basis matrix may include a first region and a second region. The embodiments of this application do not limit the division of the first and second regions.

[0181] In some implementations, the first region includes the X1 row and Y1 column of the first LDPC base matrix, and the second region includes the X2 row and G column of the first LDPC base matrix. The first region including the X1 row and Y1 column of the first LDPC base matrix can be understood as: the first region includes the region formed by the X1 row and Y1 column of the first LDPC base matrix. The second region including the X2 row and G column of the first LDPC base matrix can be understood as: the second region includes the region formed by the X2 row and G column of the first LDPC base matrix. The X1 row, Y1 column, X2 row, or G column can be continuous or discontinuous, and is not limited. It should be understood that in the embodiments of this application, the X1 row, X2 row, Y1 column, or G column can refer to: X1 rows, X2 rows, Y1 columns, or G columns. Thus, the X1 row, X2 row, Y1 column, and G column can also be replaced with: X1 rows, X2 rows, Y1 columns, and G columns.

[0182] In this matrix, rows X1 belong to rows 1 through G×i1 of the first LDPC base matrix, where i1 is an integer greater than 1. As an example, rows 1 through G×i1 of the first LDPC base matrix can be the core rows of the first LDPC base matrix; a description of the core rows can be found in the terminology explanation section. As another example, rows 1 through G×i1 of the first LDPC base matrix can include the core rows and G extension rows. For example, if G = 2, the number of core rows is 8, and rows 1 through G×i1 of the first LDPC base matrix can be rows 1 through 10. As yet another example, i1 = 4, 5, or 6.

[0183] Column Y1 is an information column belonging to the first LDPC base matrix. As an example, column Y1 is the Y1 column with the largest column weight in the first LDPC base matrix. As another example, column Y1 is a fixed punch information column in the first LDPC base matrix. As yet another example, column Y1 is the Y1 column with the largest fixed punch weight in the first LDPC base matrix. As yet another example, column Y1 is the leftmost Y1 column in the first LDPC base matrix. For example, when G=2, the value of Y1 can be 2, 4, or 6, etc. For example, when G=3, the value of Y1 can be 3, 6, or 9, etc.

[0184] Row X2 belongs to rows 1 through G×i1 of the first LDPC basis matrix, and rows X2 are the rows containing the non-zero elements of column G in the second region. In other words, rows X2 are all the rows in column G that are associated with rows 1 through G×i1 of the first LDPC basis matrix. For example, as shown in Figure 7, assuming G = 2 and columns G are columns 3 and 4, rows X2 are rows 3, 4, 5, 6, 7, and 8.

[0185] Column G is a check column of the first LDPC base matrix, and column G belongs to the same G×G submatrix. As an example, column G is a core check column of the first LDPC base matrix. For instance, the first column of column G (or the first column of the second region) is the Gth-th core check column from the end of the first LDPC base matrix. If we assume G is 2, the first LDPC base matrix has 44 information columns and 8 core check columns, then column G is columns 51 to 52 of the first LDPC base matrix. Another example is that the first column of column G is the Gth-th-from-the-end core check column of the first LDPC base matrix. For instance, if G is 2, the first LDPC base matrix has 44 information columns and 8 core check columns, then column G is columns 49 to 50 of the first LDPC base matrix. As yet another example, column G is an extended check column of the first LDPC base matrix. For example, the first column of column G is the first extended check column of the first LDPC base matrix. Assuming G is 2, the first LDPC base matrix has 44 information columns and 8 core check columns, then column G is the 53rd to 54th columns of the first LDPC base matrix. As another example, column G corresponds to the rows of the first region. For example, column G is the G×(i1-1)+kb1+1 to G×i1+kb1 columns of the first LDPC base matrix, where kb1 is the number of information columns in the first LDPC base matrix. Another example: column G is the G×i1+kb1+1 to G×(i1+1)+kb1 columns of the first LDPC base matrix, where kb1 is the number of information columns in the first LDPC base matrix. Yet another example: column G is the G×(i1-2)+kb1+1 to G×(i1-1)+kb1 columns of the first LDPC base matrix, where kb1 is the number of information columns in the first LDPC base matrix.

[0186] In some implementations, column G can be a punched check column of the first LDPC basis matrix. Here, punching can refer to: due to the rate matching pair check column corresponding to column Z... C Punch at least one of the bits.

[0187] In some implementations, there is a correspondence between row X1 of the first region and row X2 of the second region.

[0188] As an example, when X2 is G, the X1 row is the first row to the G×i1 row of the first LDPC basis matrix. As shown in Figure 8, taking G=2 and i1=4 as an example, the X2 row of the second region is the 7th and 8th rows, X2=G, and the X1 row of the first region is the first row to the 8th row of the first LDPC basis matrix.

[0189] As another example, X2 can be a multiple of G, where w is an integer greater than 1. In this case, rows X1 and X2 are the same. As shown in Figure 9, taking G=2 and i1=4 as an example, rows X2 of the second region are rows 5 to 8, and X2 is twice G. In this case, rows X1 of the first region are rows 5 to 8 of the first LDPC basis matrix.

[0190] In the embodiments of this application, the element distribution in the first region and the element distribution in the second region satisfy at least one of conditions 1 to 4. Conditions 1 to 4 are as follows.

[0191] Condition 1: The number of elements in the intersection of the first column set and the second column set is less than or equal to the first threshold.

[0192] The first column set consists of the set of columns (or column numbers) containing the non-zero elements of the i-th row of the first LDPC basis matrix in the first region. The second column set consists of the set of columns (or column numbers) containing the non-zero elements of the i'-th row of the first LDPC basis matrix in the first region. The i-th and i'-th rows of the first LDPC basis matrix can be any two rows from the first row set. The first row set consists of the set of rows (or row numbers) containing the non-zero elements of each column in the x-th column of the second region. Here, x is a positive integer less than G. For example, x = G / 2 or G / 3. For example, x = 1, 2, or 3. The embodiments of this application do not limit the specific value of the first threshold; for example, the value of the first threshold can be 0, 1, 2, or 3, etc.

[0193] Figure 10 is an example of the first and second column sets. Figure 10 uses G=2, x=1, and the first threshold as an example. As shown in Figure 10, the first region is rows 4 to 8 and columns 1 to 4 of the first LDPC basis matrix, and the second region is rows 4 to 8 and columns 51 to 52 of the first LDPC basis matrix. The last column of the second region is column 52. The rows where the non-zero element (i.e., 1) of column 52 is located in the second region are rows 6 and 8, that is, the first row set is {6, 8}. Taking row i as row 8 and row i' as row 6 as an example, the columns containing the non-zero elements in the first region of row 8 of the first LDPC basis matrix are columns 2 and 4, i.e., the first column set is {2, 4}. The columns containing the non-zero elements in the first region of row 6 of the first LDPC basis matrix are columns 2 and 3, i.e., the second column set is {2, 3}. The intersection of the first and second column sets is {2}, and the number of elements in this intersection is 1, which is equal to the first threshold. In this example, the element distribution in the first region and the distribution in the second region satisfy condition 1.

[0194] Figure 11 is another example of the first and second column sets. Figure 11 uses G=2, x=1, and the first threshold as an example. As shown in Figure 11, the first region is rows 4 to 8 and columns 1 to 4 of the first LDPC basis matrix, and the second region is rows 4 to 8 and columns 51 to 52 of the first LDPC basis matrix. The last column of the second region is column 52. The rows where the non-zero element (i.e., 1) of column 52 is located in the second region are rows 6 and 8, that is, the first row set is {6, 8}. Taking row i as row 8 and row i' as row 6 as an example, the columns containing the non-zero elements in the first region of row 8 of the first LDPC basis matrix are columns 2 and 3, i.e., the first column set is {2, 3}. The columns containing the non-zero elements in the first region of row 6 of the first LDPC basis matrix are columns 2 and 3, i.e., the second column set is {2, 3}. The intersection of the first and second column sets is {2, 3}, and the number of elements in this intersection is 2, which is equal to the first threshold. In this example, the element distribution in the first region and the distribution in the second region satisfy condition 1.

[0195] The formula for condition 1 is given below.

[0196] Define the row set of the first region as rowset and the column set of the first region as colset.

[0197] For any column j in the xth column from the end of column G in the second region, define a set row1 = {N(j) ∩ rowset}, where N(j) represents the set of rows containing the non-zero elements of column j.

[0198] For all rows i∈row1, define the set coli={N(i)∩colset}.

[0199] Condition 1 can be expressed as: For any i, i'∈row1, i≠i', there exists a threshold t0 such that |col i ∩col i' |≤t0. Where row1 is the first row set, coli is the first column set, coli' is the second column set, and t0 is the first threshold.

[0200] Condition 2: In the first row pairs obtained by combining rows of the first row set in pairs, the number of first row pairs that satisfy the first condition is less than the second threshold. The first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of the other row in the first region is greater than or equal to 2.

[0201] The first set is the set of rows (or row numbers) containing the non-zero elements of each column in the second region's x-th column. Here, x is a positive integer less than G. For example, x = G / 2 or G / 3. For example, x = 1, 2, or 3. The embodiments of this application do not limit the specific value of the second threshold; for example, the value of the second threshold can be 0 or 1, etc.

[0202] Taking a second threshold of 1 as an example, referring to Figure 10 above, the first row set is {6, 8}. The first row pair obtained by combining each row of the first row set is (6, 8). The columns containing the non-zero elements of the 8th row of the first LDPC basis matrix in the first region are columns 2 and 4, i.e., the first column set is {2, 4}. The columns containing the non-zero elements of the 6th row of the first LDPC basis matrix in the first region are columns 2 and 3, i.e., the second column set is {2, 3}. The intersection of the first and second column sets is {2}. The number of elements in this intersection is 1, which is less than 2, thus not satisfying the first condition. Therefore, the number of first row pairs that satisfy the first condition is 0 and less than the second threshold. In this example, the element distribution in the first region and the distribution in the second region satisfy condition 2.

[0203] Taking a second threshold of 1 as an example, referring to Figure 11 above, the first row set is {6, 8}. The first row pair obtained by combining each row of the first row set is (6, 8). The columns containing the non-zero elements of the 8th row of the first LDPC basis matrix in the first region are the 2nd and 3rd columns, i.e., the first column set is {2, 4}. The columns containing the non-zero elements of the 6th row of the first LDPC basis matrix in the first region are the 2nd and 3rd columns, i.e., the second column set is {2, 3}. The intersection of the first and second column sets is {2, 3}, and the number of elements in this intersection is 2. This number equals 2, satisfying the first condition. Thus, the number of first row pairs satisfying the first condition is 1 and equal to the second threshold. In this example, the element distribution in the first region and the distribution in the second region satisfy condition 2.

[0204] The formula for condition 2 is given below.

[0205] Define the row set of the first region as rowset and the column set of the first region as colset.

[0206] For any column j in the xth column from the end of column G in the second region, define a set row1 = {N(j) ∩ rowset}, where N(j) represents the set of rows containing the non-zero elements of column j.

[0207] For all rows i∈row1, define the set coli={N(i)∩colset}.

[0208] Condition 2 can be expressed as: for all i, i'∈row1, i≠i', satisfying |col i ∩col i' The number of i and i' with ≥2 is less than the threshold t1. Where row1 is the first row set, coli is the first column set, coli' is the second column set, and t1 is the second threshold.

[0209] It should be noted that when the number of rows X2 in the second region is G, if G is greater than 2, then the first set of rows will also have multiple rows. However, these multiple rows are orthogonal to each other in the first region, so they will definitely satisfy conditions 1 and 2.

[0210] Condition 3: The number of elements in the intersection of the first column set and the third column set is less than or equal to the third threshold.

[0211] The first column set is the set of columns (or column numbers) containing the non-zero elements of the i-th row of the first LDPC basis matrix in the first region. The third column set is the set of columns (or column numbers) containing the non-zero elements of the i”-th row of the first LDPC basis matrix in the first region. The i-th row of the first LDPC basis matrix can be any row in the first row set. The first row set is the set of rows (or row numbers) containing the non-zero elements of each column in the x-th column of the second region. The i”-th row of the first LDPC basis matrix can be any row in the second row set. The second row set is the set of rows from the 1st row to the G×i1-th row of the first LDPC basis matrix that do not belong to the first row set. Here, x is a positive integer less than G. For example, x = G / 2 or G / 3. For example, x = 1, 2, or 3. The embodiments of this application do not limit the specific value of the first threshold; for example, the value of the third threshold can be 0, 1, 2, or 3, etc.

[0212] Figure 12 is an example of the first and third column sets. Figure 12 uses G=2, x=1, and the third threshold as an example. For clarity, Figure 12 only shows a portion of the first and second regions in the first LDPC basis matrix. As shown in Figure 12, the first region is rows 1 to 8 and columns 1 to 4 of the first LDPC basis matrix, the second region is rows 7 to 8 and column 52 of the first LDPC basis matrix, the last column of the second region is column 52, and the row containing the non-zero element (i.e., 1) of column 52 in the second region is row 8. That is, the first row set is {8}, and the second row set is {1, 2, 3, 4, 5, 6, 7}. Taking row i as row 8 and row i” as row 6 as an example, the columns containing the non-zero elements of row 8 in the first LDPC basis matrix are columns 2 and 4 in the first region, i.e., the first column set is {2, 4}. The columns containing the non-zero elements of row 6 in the first LDPC basis matrix are columns 2 and 3 in the first region, i.e., the third column set is {2, 3}. The intersection of the first and third column sets is {2}, and the number of elements in this intersection is 1, which is equal to the third threshold. For i = 8, i” = 1, 2, 3, 4, 5, or 7, the same condition applies: the number of elements in the intersection is less than or equal to 1. In this example, the element distribution in the first region and the distribution in the second region satisfy condition 3.

[0213] Figure 13 is another example of the first and third column sets. Figure 13 uses G=2, x=1, and the third threshold as an example. For clarity, Figure 13 also only shows a portion of the first and second regions in the first LDPC basis matrix. As shown in Figure 13, the first region is rows 1 to 8 and columns 1 to 4 of the first LDPC basis matrix, the second region is rows 7 to 8 and column 52 of the first LDPC basis matrix, the last column of the second region is column 52, and the row containing the non-zero element (i.e., 1) of column 52 in the second region is row 8. That is, the first row set is {8}, and the second row set is {1, 2, 3, 4, 5, 6, 7}. Taking row i as row 8 and row i” as row 6 as an example, the columns containing the non-zero elements of row 8 in the first LDPC basis matrix are columns 2 and 3 in the first region, i.e., the first column set is {2, 3}. The columns containing the non-zero elements of row 6 in the first LDPC basis matrix are columns 2 and 3 in the first region, i.e., the third column set is {2, 3}. The intersection of the first and third column sets is {2, 3}, and the number of elements in this intersection is 2, which is equal to the third threshold. For i = 8, i” = 1, 2, 3, 4, 5, or 7, the same condition applies: the number of elements in the intersection is less than or equal to 2. In this example, the element distribution in the first region and the distribution in the second region satisfy condition 3.

[0214] The formula for condition 3 is given below.

[0215] Define the row set of the first region as rowset and the column set of the first region as colset.

[0216] For any column j in the xth column from the end of column G in the second region, define a set row1 = {N(j) ∩ rowset}, where N(j) represents the set of rows containing the non-zero elements of column j.

[0217] For all rows i∈row1, define the set coli={N(i)∩colset}.

[0218] For all rows i”∈row set \row1, define the set col i "={N(i”)∩col set}

[0219] Condition 3 can be expressed as: for any i∈row1, i”∈row set For row1, there exists a threshold t2 such that |col i ∩col i "|≤t2. Where row1 is the first row set, rowset\row1 is the second row set, coli is the first column set, coli" is the third column set, and t2 is the third threshold.

[0220] Condition 4: In the second row pairs obtained by combining rows from the first row set and rows from the second row set, the number of second row pairs that satisfy the first condition is less than the fourth threshold; wherein, the first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of the other row in the first region is greater than or equal to 2.

[0221] The first row set is the set of rows (or row numbers) containing the non-zero elements of each column in the x-th column of the second region. Here, x is a positive integer less than G. For example, x = G / 2 or G / 3. For example, x = 1, 2, or 3. The embodiments of this application do not limit the specific value of the fourth threshold; for example, the value of the fourth threshold can be 0 or 1. The second row set is the set of rows from the 1st row to the G×i1th row of the first LDPC basis matrix that do not belong to the first row set.

[0222] Taking a fourth threshold of 1 as an example, referring to Figure 12 above, the first row set is {8}, and the second row set is {1, 2, 3, 4, 5, 6, 7}. The second row pairs obtained by combining rows from the first row set are (1, 8), (2, 8), (3, 8), (4, 8), (5, 8), (6, 8), and (7, 8). The number of elements in the intersection corresponding to the second row pairs (1, 8), (3, 8), (5, 8), and (7, 8) is 0, and the number of elements in the intersection corresponding to the second row pairs (2, 8), (4, 8), and (6, 8) is 1. The number of elements in the intersection corresponding to these second row pairs is less than 2, meaning the number of second row pairs satisfying the first condition is 0, which equals the fourth threshold. Therefore, in this example, the element distribution in the first region and the distribution in the second region satisfy condition 4.

[0223] Taking a fourth threshold of 1 as an example, referring to Figure 13 above, the first row set is {8}, and the second row set is {1, 2, 3, 4, 5, 6, 7}. The second row pairs obtained by combining rows from the first row set are (1, 8), (2, 8), (3, 8), (4, 8), (5, 8), (6, 8), and (7, 8). The number of elements in the intersection corresponding to the second row pairs (1, 8), (3, 8), (5, 8), and (7, 8) is 0. The number of elements in the intersection corresponding to the second row pair (2, 8) is 1. The number of elements in the intersection corresponding to the second row pairs (4, 8) and (6, 8) is 2. The number of elements in the intersection corresponding to any two of these second row pairs is equal to 2, which equals the fourth threshold. Therefore, in this example, the element distribution in the first region and the distribution in the second region do not satisfy condition 4.

[0224] The formula for condition 4 is given below.

[0225] Define the row set of the first region as rowset and the column set of the first region as colset.

[0226] For any column j in the xth column from the end of column G in the second region, define a set row1 = {N(j) ∩ rowset}, where N(j) represents the set of rows containing the non-zero elements of column j.

[0227] For all rows i∈row1, define the set coli={N(i)∩colset}.

[0228] For all rows i”∈row set \row1, define the set col i "={N(i”)∩col set}

[0229] Condition 4 can be expressed as: for all i∈row1, i”∈row set \row1, satisfying |col i ∩col i The number of "|≥t2. i and i" is less than the threshold t3. Where row1 is the first row set, rowset\row1 is the second row set, coli is the first column set, coli" is the third column set, and t2 is the fourth threshold.

[0230] For example, when the number of rows X2 in the second region is G, the element distribution in the first region and the distribution in the second region satisfy conditions 3 and 4.

[0231] For example, when the number of rows X2 in the second region is G, the element distribution in the first region and the distribution in the second region satisfy conditions 2 and 3.

[0232] For example, when the number of rows X2 in the second region is w times G and w is an integer greater than 1, the element distribution in the first region and the distribution in the second region satisfy conditions 1 and 2.

[0233] For example, when the number of rows X2 in the second region is w times G and w is an integer greater than 1, the element distribution in the first region and the distribution in the second region satisfy conditions 1, 2, 3 and 4.

[0234] Steps 602 and 604 above describe one method for obtaining the first LDPC base matrix: selecting a portion or all of the matrix region from the largest stored base matrix based on at least one of the target code length, target code rate, and application scenario. In another implementation, the first LDPC base matrix can also be obtained by extending or improving the second LDPC base matrix. It should be noted that the steps or operations after obtaining the first LDPC base matrix are described in steps 602 and 604 and will not be detailed further. It should also be noted that in this implementation, the largest stored LDPC base matrix can be extended first, and then the extended LDPC base matrix can be selected or truncated to obtain the first LDPC base matrix, where the second LDPC base matrix is ​​a portion or all of the largest LDPC base matrix, and the first LDPC base matrix corresponds to the second LDPC base matrix; alternatively, the second LDPC base matrix can be selected or truncated from the largest stored LDPC base matrix, and then the second LDPC base matrix can be extended to obtain the first LDPC base matrix, without limitation.

[0235] In some implementations, the second LDPC basis matrix can be the NR LDPC basis matrix. It should be understood that the NR LDPC basis matrix is ​​an NR-related LDPC basis matrix, which can be the LDPC basis matrix in the NR protocol, or the LDPC basis matrix mentioned in the discussion of the NR protocol. The NR protocol can be any version of the protocol, without restriction.

[0236] When the first LDPC basis matrix is ​​obtained by extending the second LDPC basis matrix, G can be the lifting value used when extending the first LDPC basis matrix from the second LDPC basis matrix, and G can also be denoted as Zc1. In other words, one position of the second LDPC basis matrix corresponds to G×G positions of the first LDPC basis matrix.

[0237] The embodiments of this application are not limited to the implementation of extending the second LDPC base matrix into the first LDPC base matrix.

[0238] In some implementations, the first type of submatrix in the first LDPC basis matrix is ​​obtained by expanding the zero elements in the second LDPC basis matrix, and the second type of submatrix in the first LDPC basis matrix is ​​obtained by expanding the non-zero elements in the second LDPC basis matrix. In other words, the zero elements in the second LDPC basis matrix are expanded to obtain the first type of submatrix in the first LDPC basis matrix, and the non-zero elements in the second LDPC basis matrix are expanded to obtain the second type of submatrix in the first LDPC basis matrix.

[0239] Taking G=2 as an example, the first LDPC basis matrix is ​​denoted as BG0, and the second LDPC basis matrix is ​​denoted as BG. Elements in BG are either 0 or 1. The 1s in BG are expanded into a 2×2 matrix. In a 2×2 matrix, the elements on the diagonal are either 0 or the elements on the anti-diagonal are 0. That is, the 1s in BG are expanded to... or Expand the zeros in BG into a 2×2 zero matrix, i.e. After expansion, we get BG0.

[0240] Taking G as 3 as an example, the first LDPC basis matrix is ​​denoted as BG0, and the second LDPC basis matrix is ​​denoted as BG. Elements in BG are either 0 or 1. The 1s in BG are then extended to... or Expand the zeros in BG into a 3x3 zero matrix, that is After expansion, the matrix BG0 is obtained.

[0241] Figure 14 is an example of obtaining the first LDPC basis matrix by lifting the second LDPC basis matrix. Figure 14 uses G=2 as an example.

[0242] The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. Specifically, row X1 of the first region corresponds to row X1 / G of the third region, column Y1 of the first region corresponds to column Y1 / G of the third region, row X2 of the second region corresponds to row X2 / G of the fourth region, and column G of the second region corresponds to column 1 of the fourth region (denoted as column a).

[0243] The characteristics of the first and second regions are also reflected in the third and fourth regions.

[0244] Specifically, rows X1 / G of the third region belong to rows 1 through i1 of the second LDPC basis matrix. When rows 1 through G×i1 of the first LDPC basis matrix are the core rows of the first LDPC basis matrix, rows 1 through i1 of the second LDPC basis matrix are also core rows of the second LDPC basis matrix. When rows 1 through G×i1 of the first LDPC basis matrix include the core rows and G extended rows, rows 1 through i1 of the second LDPC basis matrix include the core rows and one extended row of the second LDPC basis matrix.

[0245] The Y1 / G column of the third region belongs to the information column of the second LDPC base matrix. When the Y1 column of the first region is the Y1 column with the largest column weight in the first LDPC base matrix, the Y1 / G column of the third region is also the Y1 / G column with the largest column weight in the second LDPC base matrix. When the Y1 column of the first region is a fixed punched information column in the first LDPC base matrix, the Y1 / G column of the third region is also a fixed punched information column in the second LDPC base matrix. When the Y1 column of the first region is the Y1 column with the largest fixed punched column weight in the first LDPC base matrix, the Y1 / G column of the third region is also a fixed punched column with the largest column weight in the second LDPC base matrix. When the Y1 column of the first region is the leftmost Y1 column in the first LDPC base matrix, the Y1 / G column of the third region is also the leftmost Y1 / G column in the second LDPC base matrix.

[0246] The X2 / G column of the fourth region belongs to rows 1 to i1 of the second LDPC basis matrix, and the X2 / G row is the row containing the non-zero elements of column a. In other words, the X2 / G row is all the rows associated with column a and rows 1 to i1 of the second LDPC basis matrix.

[0247] Column 'a' is a check column of the second LDPC base matrix. When column G of the second region is a core check column of the first LDPC base matrix, column 'a' is also a core check column of the second LDPC base matrix. For example, column 'a' might be the last core check column of the second LDPC base matrix, or the second-to-last core check column. When column G of the second region is an extended check column of the first LDPC base matrix, column 'a' is also an extended check column of the second LDPC base matrix. For example, column 'a' might be the first extended check column of the second LDPC base matrix. When column G of the second region corresponds to a row of the first region, column 'a' of the fourth region also corresponds to a row of the third region. For example, column 'a' might be the i1+kb2th, i1+kb2+1th, or i1+kb2-1th column of the second LDPC base matrix, where kb2 is the information column number of the second LDPC base matrix.

[0248] There is also a correspondence between X1 / G rows in the third region and X2 / G rows in the fourth region.

[0249] Figure 15 shows an example of the third and fourth regions. The second LDPC basis matrix shown in Figure 15 corresponds to the first LDPC basis matrix shown in Figure 8, or in other words, the third region shown in Figure 15 corresponds to the first region shown in Figure 8, and the fourth region shown in Figure 15 corresponds to the second region shown in Figure 8. As shown in Figure 15, when the number of rows in the fourth region is equal to 1, the rows in the third region are rows 1 to 4 of the second LDPC basis matrix.

[0250] Figure 16 shows another example of the third and fourth regions. The second LDPC basis matrix shown in Figure 16 corresponds to the first LDPC basis matrix shown in Figure 9, or in other words, the third region shown in Figure 16 corresponds to the first region shown in Figure 9, and the fourth region shown in Figure 16 corresponds to the second region shown in Figure 9. As shown in Figure 16, when the number of rows in the fourth region is greater than 1, the row set of the third region is the same as the row set of the fourth region, which is rows 3 to 4.

[0251] In the embodiments of this application, the translation values ​​corresponding to the non-zero elements of the third and fourth regions satisfy at least one of conditions 5 to 8. Conditions 5 to 8 are as follows.

[0252] Condition 5: The translation values ​​corresponding to the non-zero elements in the third region satisfy: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)≥t4

[0253] Where mod() represents the remainder, SV p,q SV represents the shift value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV represents the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' t4 is the shift value of the p-th row and q'-th column of the second LDPC basis matrix, the set of rows belonging to the third region for the p-th and p'-th rows, the set of columns belonging to the third region for the q-th and q'-th columns, and the seventh threshold.

[0254] For example, the seventh threshold can be 1.

[0255] Condition 6: The number of rows and columns satisfying the second condition in the third region is less than the fifth threshold, where the second condition is: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)=0

[0256] Where mod() represents the remainder, SV p,q SV represents the shift value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV represents the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q'Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, p be the set of rows belonging to the third region, and q be the set of columns belonging to the third region.

[0257] The embodiments of this application do not limit the value of the fifth threshold. For example, the fifth threshold can be 0, 1, or 2, etc.

[0258] Condition 7: The translation values ​​corresponding to the non-zero elements in the third and fourth regions satisfy: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)≥t5

[0259] Where mod() represents the remainder, SV p,q SV represents the shift value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV represents the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' t5 is the shift value of the p-th row and q'-th column of the second LDPC basis matrix, the p-th row and the p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, the q'-th column belongs to the column set of the fourth region, and t5 is the eighth threshold.

[0260] For example, the eighth threshold can be 1.

[0261] Condition 8: The number of rows and columns satisfying the second condition in the third and fourth regions is less than the sixth threshold, where the second condition is: mod(SV) p,q -SV p',q +SV p',q' -SV p,q' ,G)=0

[0262] Where mod() represents the remainder, SV p,q SV represents the shift value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV represents the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, p and p' be the set of columns belonging to the third region, q be the set of columns belonging to the third region, and q' be the set of columns belonging to the fourth region.

[0263] The embodiments of this application do not limit the value of the sixth threshold. For example, the sixth threshold can be 0, 1, or 2, etc.

[0264] For example, when the number of rows X2 in the second region is G, that is, when the fourth region is one row, the translation value of the third region satisfies condition 5 or condition 6.

[0265] For example, when the number of rows X2 in the second region is a multiple of G and w is an integer greater than 1, that is, when the fourth region has multiple rows, the translation values ​​of the third and fourth regions satisfy condition 7 or condition 8.

[0266] It should be noted that, in the embodiments of this application, the translation value of the position P of the basis matrix can also be replaced by: the translation value corresponding to the position P of the basis matrix, or the translation value corresponding to the non-zero element of the position P of the basis matrix, without limitation.

[0267] It should also be noted that the first threshold, second threshold, third threshold, fourth threshold, fifth threshold, sixth threshold, seventh threshold and eighth threshold mentioned above can be the same or different from each other, without restriction.

[0268] The performance of the LDPC code provided in the embodiments of this application is described below based on simulation results.

[0269] Figure 17 shows a performance comparison between the NR LDPC code and the LDPC code of this application at different code lengths.

[0270] Figure 17 shows the information length on the horizontal axis and the signal-to-noise ratio (SNR) reaching 1e⁻² on the vertical axis. The curves shown in Figure 17 represent the simulation results at a code rate of 0.9362 and a decoding iteration count of 5. As shown in Figure 17, compared with NR LDPC codes, the LDPC codes of this application perform better at all code lengths.

[0271] Figure 18 shows a performance comparison between existing multi-stage boosted LDPC codes and the LDPC codes of this application at different code lengths.

[0272] Figure 18 shows the information length on the horizontal axis and the SNR reaching 1e-2 on the vertical axis. The curves shown in Figure 18 are simulation results with a code rate of 0.9362 and a decoding iteration number of 5. As shown in Figure 18, compared with existing multi-stage boosting LDPC codes, the LDPC code of this application performs better at all code lengths.

[0273] It should be understood that in this application, if the third LDPC basis matrix or the translation value matrix corresponding to the third LDPC basis matrix can be obtained by performing a first transformation on the first LDPC basis matrix or the translation value matrix corresponding to the first LDPC basis matrix provided in the embodiments of this application, then the third LDPC basis matrix or the translation value matrix corresponding to the third LDPC basis matrix is ​​considered to be included within the protection scope of this application. The first transformation includes at least one of the following operations: row permutation, column permutation, or translation value transformation. Row permutation may include permuting one or more rows. Column permutation may include permuting one or more columns. Translation value transformation may include simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more rows, and / or simultaneously adding or subtracting non-negative integers to the translation values ​​corresponding to the non-zero elements of one or more columns.

[0274] In other words, the third LDPC basis matrix can be obtained from the first LDPC basis matrix through a first transformation, the shift matrix corresponding to the third LDPC basis matrix can be obtained from the shift matrix corresponding to the first LDPC basis matrix through a first transformation, and the third LDPC parity check matrix can be obtained from the first LDPC parity check matrix through a first transformation. Therefore, "encode the information bit sequence according to the first LDPC basis matrix and output a codeword sequence" can be replaced with "encode the information bit sequence according to the third LDPC basis matrix and output a codeword sequence," and / or, "decode the information to be decoded according to the first LDPC basis matrix to obtain an information bit sequence" can be replaced with "decode the information to be decoded according to the third LDPC basis matrix to obtain an information bit sequence."

[0275] Row permutations of the LDPC base matrix, its corresponding shifted value matrix, and its corresponding parity check matrix are equivalent to swapping the order of the parity check equations, without changing the required parity check relations. Column permutations or shifted value transformations of the LDPC base matrix, its corresponding shifted value matrix, and its corresponding parity check matrix are equivalent to swapping the order of the encoded bits, which can be considered as reordering the encoded result. During decoding, restoring the order first yields the same effect as the matrix before the column transformation. Therefore, the third LDPC base matrix obtained by the first transformation can be considered equivalent to the first LDPC base matrix provided in the embodiments of this application, the third shifted value matrix obtained by the first transformation can be considered equivalent to the shifted value matrix corresponding to the first LDPC base matrix provided in the embodiments of this application, and the parity check matrix obtained by the first transformation can be considered equivalent to the parity check matrix corresponding to the first LDPC base matrix provided in the embodiments of this application.

[0276] In other words, the first LDPC base matrix or the translation value matrix corresponding to the first LDPC base matrix can be modified to its equivalent or equivalent form. The equivalent or equivalent translation value matrix to the first LDPC base matrix or the translation value matrix corresponding to the first LDPC base matrix differs from the LDPC base matrix or LDPC translation value matrix provided in the embodiments of this application in that the row order is different, and / or the column order is different, and / or the translation values ​​of one or more rows are shifted, and / or the translation values ​​of one or more columns are shifted.

[0277] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 18. The apparatus embodiments of this application will be described below with reference to Figures 19 to 21.

[0278] It is understood that, in order to achieve the functions in the above embodiments, the apparatuses in Figures 19 to 21 include hardware structures and / or software modules corresponding to each function. These apparatuses can be used to implement the functions of the encoding or decoding devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software.

[0279] Figure 19 is a schematic diagram of a device provided in an embodiment of this application.

[0280] This application embodiment can divide the encoding or decoding device into functional units according to the above method examples. For example, each function can be divided into different functional units, or two or more functions can be integrated into one unit. Each function can be implemented in hardware or as a software functional module. It should be noted that the division shown in Figure 19 is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0281] As shown in Figure 19, the device 10 includes a transceiver unit 11 and a processing unit 12.

[0282] When device 10 is used to implement the function of the encoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the encoding device, such as step 603, and processing unit 12 is used to execute the processing steps 601 and 602 of the encoding device. When device 10 is used to implement the function of the decoding device in the above method embodiments, transceiver unit 11 is used to execute the transceiver steps of the decoding device, such as step 603, and processing unit 12 is used to execute the processing steps of the decoding device, such as step 604.

[0283] Optionally, the device 10 also includes a storage unit 13 for storing instructions and / or data.

[0284] For a more detailed description of the transceiver unit 11 and the processing unit 12, please refer to the relevant descriptions in the above method embodiments, which will not be repeated here.

[0285] Figure 20 is another structural schematic diagram of the device provided in an embodiment of this application.

[0286] The device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, which stores instructions. When the device 20 is used to implement the method described above, the processing circuit 21 executes the instructions in the memory 23 to implement the function of the processing unit 12 described above.

[0287] Optionally, the device 20 further includes a memory 23 for implementing the functions of the aforementioned storage unit 13.

[0288] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit can be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 can be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 executes instructions to implement the function of the processing unit 12, and the transceiver circuit 22 implements the function of the transceiver unit 11.

[0289] Optionally, device 20 can be an encoding device or a decoding device, and correspondingly, the transceiver circuit can be a transceiver.

[0290] Optionally, the device 20 can be a chip used in encoding or decoding equipment, and correspondingly, the transceiver circuit can be an input / output interface.

[0291] For example, when device 20 is a chip applied to an encoding or decoding device, the chip implements the functions of the encoding or decoding device in the above method embodiments. The chip receives information from other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to the encoding or decoding device by other devices; or, the chip sends information to other modules (such as radio frequency modules or antennas) in the encoding or decoding device, which is sent to other devices by the encoding or decoding device.

[0292] Figure 21 is a schematic diagram of a chip system provided in an embodiment of this application. The chip system 30 (or may also be called a processing system) includes logic circuitry 31 and an input / output interface 32.

[0293] The logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to a memory unit, calling instructions from the memory unit, enabling the chip system 30 to implement the methods and functions of the embodiments of this application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting processed information from the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0294] As an alternative, the chip system 30 may also include a memory unit.

[0295] As one approach, the chip system 30 is used to implement the operations performed by the encoding or decoding device in the various method embodiments described above.

[0296] For example, logic circuit 31 is used to implement processing-related operations performed by the encoding or decoding device in the above method embodiments; input / output interface 32 is used to implement sending and / or receiving-related operations performed by the encoding or decoding device in the above method embodiments.

[0297] This application also provides a communication device including a processing circuit coupled to a memory for storing computer programs or instructions and / or data. The processing circuit is used to execute the computer programs or instructions stored in the memory, or to read the data stored in the memory, to perform the methods in the above-described method embodiments. Optionally, the processing circuit may be one or more. Optionally, the communication device includes a memory. Optionally, the memory may be one or more. Optionally, the memory may be integrated with the processing circuit, or may be separately disposed.

[0298] This application also provides a chip including a processing circuit coupled to a memory. The memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods executed by the encoding or decoding device in the above-described method embodiments. The memory may be located within the chip or independently of the chip, located outside the chip; this is not limited thereto.

[0299] This application also provides a computer-readable storage medium having stored thereon computer instructions for implementing the methods executed by an encoding device or a decoding device in the above-described method embodiments.

[0300] This application also provides a computer program product comprising instructions that, when executed by a computer, implement the methods performed by an encoding or decoding device in the above-described method embodiments.

[0301] This application also provides a computer program that, when executed by a computer, implements the methods performed by the encoding or decoding device in the above-described method embodiments.

[0302] This application also provides a communication system that includes at least one of the encoding or decoding devices described in the above embodiments.

[0303] The explanations and beneficial effects of the relevant contents in any of the devices provided above can be found in the corresponding method embodiments provided above, and will not be repeated here.

[0304] It is understood that the processing circuit in the embodiments of this application may be a processor or a circuit in a processor for performing processing operations. The processor may include one or more of the following: a central processing unit (CPU), a digital signal processor (DSP), a microprocessor unit (MPU), a microcontroller unit (MCU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an artificial intelligence processor (AI processor), or a neural processing unit (NPU).

[0305] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored in non-volatile memory, such as the aforementioned memory 23 or at least a portion of the storage cells (e.g., one or more of ROM, flash memory, EPROM, or hard disk).

[0306] The method steps in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). Furthermore, the ASIC can reside in an encoding or decoding device. Alternatively, the processor and storage medium can exist as discrete components in the encoding or decoding device.

[0307] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive.

[0308] In the various embodiments of this application, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of different embodiments are consistent and can be referenced by each other. The technical features of different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0309] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the scope of this application. It should be understood that the above are illustrative examples, and the examples above are merely to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of the application to the specific numerical values ​​or specific scenarios exemplified. Those skilled in the art can obviously make various equivalent modifications or variations based on the examples given above, and such modifications and variations also fall within the scope of the embodiments of this application.

Claims

1. An information processing method characterized by comprising: The method includes: Obtain the information bit sequence; The information bit sequence is encoded according to the first LDPC basis matrix to output a codeword sequence; The first LDPC base matrix comprises multiple G×G submatrices, wherein the row weight of each row of the submatrices is less than or equal to 1 and the column weight of each column is less than or equal to 1, and G is an integer greater than 1; the first LDPC base matrix comprises a first region and a second region, wherein the first region comprises an X1 row and a Y1 column of the first LDPC base matrix, the X1 row belonging to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column comprising the punch information column of the first LDPC base matrix, and i1 is an integer greater than 1; the second region comprises an X2 row and a G column of the first LDPC base matrix, the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the Y1 column comprising the punch information column of the first LDPC base matrix, and i1 is an integer greater than 1; the second region comprises an X2 row and a G column of the first LDPC base matrix, the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the Y1 column comprising the punch information column ... Row 2 is the row containing the non-zero elements of column G, column G is a check column of the first LDPC base matrix and belongs to the same submatrix; the column containing the non-zero elements of the i-th row of the first LDPC base matrix in the first region constitutes the first column set, the column containing the non-zero elements of the i'-th row of the first LDPC base matrix in the first region constitutes the second column set, the number of elements in the intersection of the first column set and the second column set is less than or equal to a first threshold, the i-th row and the i'-th row are any two rows in the first row set, the first row set is the set consisting of the rows containing the non-zero elements of each column from the 1st to the xth column from the end of the second region, where x is a positive integer less than G.

2. The method of claim 1, wherein, The first threshold is 0, 1, or 2.

3. The method according to claim 1 or 2, characterized in that, In the first row pairs obtained by combining rows of the first row set in pairs, the number of first row pairs that satisfy the first condition is less than the second threshold. The first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

4. The method of claim 3, wherein, The second threshold is 0 or 1.

5. The method according to any one of claims 1 to 4, characterized in that, The columns containing the non-zero elements of the i”th row of the first LDPC basis matrix in the first region constitute the third column set. The i”th row is any row in the second row set. The rows in the second row set belong to the first row to the G×i1th row of the first LDPC basis matrix and do not belong to the first row set. The number of elements in the intersection of the first column set and the third column set is less than or equal to the third threshold.

6. The method of claim 5, wherein, The third threshold is 0, 1, or 2.

7. The method according to claim 5 or 6, characterized in that, In the second row pairs obtained by combining rows from the first row set and rows from the second row set in pairs, the number of second row pairs that satisfy the first condition is less than the fourth threshold. The first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

8. The method of claim 7, wherein, The fourth threshold is 0 or 1.

9. The method according to any one of claims 1 to 8, characterized in that, The first LDPC basis matrix is ​​obtained by lifting the second LDPC basis matrix; In this process, zero elements in the second LDPC basis matrix are promoted to obtain a first-class G×G submatrix in the first LDPC basis matrix, and non-zero elements in the second LDPC basis matrix are promoted to obtain a second-class G×G submatrix in the first LDPC basis matrix. All elements of the first-class G×G submatrix are 0, and each row of the second-class G×G submatrix has a row weight of 1 and each column has a column weight of 1.

10. The method according to claim 9, characterized in that, The X1 row represents rows 1 to G×i1 of the first LDPC base matrix. The first region of the first LDPC base matrix corresponds to the third region of the second LDPC base matrix, and the second region of the first LDPC base matrix corresponds to the fourth region of the second LDPC base matrix. The fourth region includes one row. The number of rows and columns satisfying the second condition in the third region is less than a fifth threshold. The second condition is: against(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)=0 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

11. The method according to claim 9 or 10, characterized in that, The X1 row represents rows 1 to G×i1 of the first LDPC basis matrix. The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix. The second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region comprises one row. The translation value of the third region satisfies: against(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

12. The method according to claim 9, characterized in that, The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region includes multiple rows, and the row set of the fourth region is the same as the row set of the third region. The number of rows and columns satisfying the second condition in the third region and the fourth region is less than a sixth threshold, wherein the second condition is: against(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)=0 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

13. The method according to claim 9 or 10, characterized in that, The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region includes multiple rows, and the row set of the fourth region is the same as the row set of the third region. The translation values ​​of the third region and the fourth region satisfy: against(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

14. The method according to any one of claims 1 to 13, characterized in that, X2 is w times G, where w is an integer; When w equals 1, the X1 row is the first row to the G×i1th row; and / or, When w is greater than 1, row X1 is the same as row X2.

15. The method according to any one of claims 1 to 14, characterized in that, The first column of the second region is the Gth core check column from the end of the first LDPC base matrix, the first extended check column of the first LDPC base matrix, or the 2Gth core check column from the end of the first LDPC base matrix.

16. The method according to claim 15, characterized in that, The columns in the second area are punch verification columns.

17. The method according to any one of claims 1 to 16, characterized in that, Rows 1 to G×i1 are the core rows of the first LDPC basis matrix; or... The first row to the G×i1th row includes the core row and G extended rows of the first LDPC basis matrix.

18. The method of any one of claims 1 to 17, wherein, i1 is 4, 5, or 6.

19. The method of any one of claims 1 to 18, wherein, G is 2 or 3.

20. An information processing method characterized by comprising: The method includes: Obtain the information to be decoded; The information is decoded based on the first LDPC basis matrix to obtain the decoded bit sequence; The first LDPC base matrix comprises multiple G×G submatrices, wherein the row weight of each row of the submatrices is less than or equal to 1 and the column weight of each column is less than or equal to 1, and G is an integer greater than 1; the first LDPC base matrix comprises a first region and a second region, wherein the first region comprises an X1 row and a Y1 column of the first LDPC base matrix, the X1 row belonging to the first row to the G×i1 row of the first LDPC base matrix, the Y1 column comprising the punch information column of the first LDPC base matrix, and i1 is an integer greater than 1; the second region comprises an X2 row and a G column of the first LDPC base matrix, the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the Y1 column comprising the punch information column of the first LDPC base matrix, and i1 is an integer greater than 1; the second region comprises an X2 row and a G column of the first LDPC base matrix, the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the X2 row belonging to the first row to the G×i1 row of the first LDPC base matrix, and the Y1 column comprising the punch information column ... Row 2 is the row containing the non-zero elements of column G, column G is a check column of the first LDPC base matrix and belongs to the same submatrix; the column containing the non-zero elements of the i-th row of the first LDPC base matrix in the first region constitutes the first column set, the column containing the non-zero elements of the i'-th row of the first LDPC base matrix in the first region constitutes the second column set, the number of elements in the intersection of the first column set and the second column set is less than or equal to a first threshold, the i-th row and the i'-th row are any two rows in the first row set, the first row set is the set consisting of the rows containing the non-zero elements of each column from the 1st to the xth column from the end of the second region, where x is a positive integer less than G.

21. The method of claim 20, wherein, The first threshold is 0, 1, or 2.

22. The method according to claim 20 or 21, characterized in that, In the first row pairs obtained by combining rows of the first row set in pairs, the number of first row pairs that satisfy the first condition is less than the second threshold. The first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

23. The method of claim 22, wherein, The second threshold is 0 or 1.

24. The method according to any one of claims 20 to 23, characterized in that, The columns containing the non-zero elements of the i”th row of the first LDPC basis matrix in the first region constitute the third column set. The i”th row is any row in the second row set. The rows in the second row set belong to the first row to the G×i1th row of the first LDPC basis matrix and do not belong to the first row set. The number of elements in the intersection of the first column set and the third column set is less than or equal to the third threshold.

25. The method of claim 24, wherein, The third threshold is 0, 1, or 2.

26. The method according to claim 24 or 25, characterized in that, In the second row pairs obtained by combining rows from the first row set and rows from the second row set in pairs, the number of second row pairs that satisfy the first condition is less than the fourth threshold. The first condition is: in a row pair, the number of elements in the intersection of the column set consisting of the columns containing the non-zero elements of one row in the first region and the column set consisting of the columns containing the non-zero elements of another row in the first region is greater than or equal to 2.

27. The method of claim 26, wherein, The fourth threshold is 0 or 1.

28. The method according to any one of claims 20 to 27, characterized in that, The first LDPC basis matrix is ​​obtained by lifting the second LDPC basis matrix; In this process, zero elements in the second LDPC basis matrix are promoted to obtain a first-class G×G submatrix in the first LDPC basis matrix, and non-zero elements in the second LDPC basis matrix are promoted to obtain a second-class G×G submatrix in the first LDPC basis matrix. All elements of the first-class G×G submatrix are 0, and each row of the second-class G×G submatrix has a row weight of 1 and each column has a column weight of 1.

29. The method according to claim 28, characterized in that, The X1 row represents rows 1 to G×i1 of the first LDPC base matrix. The first region of the first LDPC base matrix corresponds to the third region of the second LDPC base matrix, and the second region of the first LDPC base matrix corresponds to the fourth region of the second LDPC base matrix. The fourth region includes one row. The number of rows and columns satisfying the second condition in the third region is less than a fifth threshold. The second condition is: against(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)=0 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

30. The method according to claim 28 or 29, characterized in that, The X1 row represents rows 1 to G×i1 of the first LDPC basis matrix. The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix. The second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region comprises one row. The translation value of the third region satisfies: mod(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' Let p be the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the row set of the third region, and the q-th column and q'-th column belong to the column set of the third region.

31. The method according to claim 28, characterized in that, The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region includes multiple rows, and the row set of the fourth region is the same as the row set of the third region. The number of rows and columns satisfying the second condition in the third region and the fourth region is less than a sixth threshold, wherein the second condition is: mod(SV p,q -SV p',q +SV p',q' -SV p,q' ,G) = 0 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

32. The method according to claim 28 or 29, characterized in that, The first region of the first LDPC basis matrix corresponds to the third region of the second LDPC basis matrix, and the second region of the first LDPC basis matrix corresponds to the fourth region of the second LDPC basis matrix. The fourth region includes multiple rows, and the row set of the fourth region is the same as the row set of the third region. The translation values ​​of the third region and the fourth region satisfy: against(SV p,q -SV p',q +SV p',q' -SV p,q' ,G)≥1 Where mod() represents the remainder, SV p,q SV is the translation value of the p-th row and q-th column of the second LDPC basis matrix. p',q SV is the translation value of the p'-th row and q-th column of the second LDPC basis matrix. p',q' SV is the shift value of the p'-th row and q'-th column of the second LDPC basis matrix. p,q' is the translation value of the p-th row and q'-th column of the second LDPC basis matrix, where the p-th row and p'-th row belong to the column set of the third region, the q-th column belongs to the column set of the third region, and the q'-th column belongs to the column set of the fourth region.

33. The method according to any one of claims 20 to 32, characterized in that, X2 is w times G, where w is an integer; When w equals 1, the X1 row is the first row to the G×i1th row; and / or, When w is greater than 1, row X1 is the same as row X2.

34. The method according to any one of claims 20 to 33, characterized in that, The first column of the second region is the Gth core check column from the end of the first LDPC base matrix, the first extended check column of the first LDPC base matrix, or the 2Gth core check column from the end of the first LDPC base matrix.

35. The method according to claim 34, characterized in that, The columns in the second area are punch verification columns.

36. The method according to any one of claims 20 to 35, characterized in that, Rows 1 to G×i1 are the core rows of the first LDPC basis matrix; or... The first row to the G×i1th row includes the core row and G extended rows of the first LDPC basis matrix.

37. The method according to any one of claims 20 to 36, characterized in that, i1 is 4, 5, or 6.

38. The method of any one of claims 20-37, wherein, G is 2 or 3.

39. A communication device, characterized in that, The device includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, and the processor is used to implement the method as described in any one of claims 1 to 38 through logic circuits or execution code instructions.

40. The communication apparatus of claim 39, wherein, The communication device is a chip or chip system.

41. A computer-readable storage medium, comprising: The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method as described in any one of claims 1 to 38.

42. A computer program product, characterised in that, Includes a computer program that, when run, implements the method as described in any one of claims 1 to 38.

43. A communication system, characterized by include: An encoding device for performing the method as described in any one of claims 1 to 19, and a decoding device for performing the method as described in any one of claims 20 to 38.

44. A communications device, characterized by comprise means or units for performing the method as claimed in any one of claims 1 to 38.

Images