Encoding method and apparatus, and decoding method and apparatus

Abstract

Provided in the present application are an encoding method and method, and a decoding method and apparatus. The encoding method comprises: on the basis of a first LDPC matrix, encoding information bits, so as to obtain encoded bits, wherein the first LDPC matrix is obtained by means of performing row interleaving on a first region of a second LDPC matrix on the basis of a code rate and / or the number of rows of the second LDPC matrix; and outputting the encoded bits. Row interleaving is performed on a first region of a second LDPC matrix, such that a reduction in the correlation between rows of the second LDPC matrix is facilitated, and thus the orthogonality of the second LDPC matrix is improved, thereby improving the performance of an LDPC code, such as reducing the decoding complexity. In addition, the improvement in the orthogonality also facilitates a reduction in the decoding latency, an increase in the throughput, etc. Furthermore, the improvement in the orthogonality also facilitates a reduction in the bit error rate.

Description

Compilation and Decoding Methods and Apparatus

[0001] This application claims priority to Chinese patent application filed on January 24, 2025, with application number 202510121411.4 and entitled "Encoding and Decoding Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and particularly to encoding and decoding methods and apparatus in the field of communications. Background Technology

[0003] Low-density parity-check (LDPC) codes are a type of forward error correction coding technique. They are typically implemented using a parity-check matrix, which is usually constructed from a base matrix.

[0004] Currently, the orthogonality of adjacent rows in the basis matrix is ​​poor, which may affect the overall efficiency of the system, such as increased latency and reduced throughput. Summary of the Invention

[0005] This application provides a coding and decoding method and apparatus to improve the orthogonality of adjacent rows of a basis matrix, thereby improving the overall efficiency of the system, such as reducing latency and increasing throughput.

[0006] Firstly, this application provides an encoding method that can be executed by a first communication device. For example, it can be executed by the first communication device itself, or by a component configured in the first communication device (such as a processor, chip, chip system, etc.), or by a logic module or software capable of implementing all or part of the functions of the first communication device; this application does not limit the scope of the method.

[0007] For example, the method includes: encoding information bits based on a first LDPC matrix to obtain encoded bits, wherein the first LDPC matrix is ​​obtained by row interleaving a first region of a second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix; and outputting the encoded bits.

[0008] Secondly, this application provides a decoding method that can be executed by a second communication device. For example, it can be executed by the second communication device itself, or by a component configured in the second communication device (such as a processor, chip, chip system, etc.), or by a logic module or software capable of implementing all or part of the functions of the second communication device. This application does not limit the scope of the method.

[0009] For example, the method includes: inputting bits to be decoded; decoding the bits to be decoded based on a first LDPC matrix to obtain information bits, wherein the first LDPC matrix is ​​obtained by row interleaving a first region of a second LDPC matrix according to the code rate and / or the number of rows of a second LDPC matrix.

[0010] Optionally, the aforementioned second LDPC matrix / first LDPC matrix can be a base matrix or an exponential matrix, and this application does not limit it in this regard.

[0011] Optionally, the first region mentioned above can be the region corresponding to the core column of the second LDPC matrix.

[0012] In the schemes provided in the first and second aspects above, row interleaving of the first region of the second LDPC matrix helps reduce the correlation between rows in the second LDPC matrix, thereby improving the orthogonality of the second LDPC matrix and thus improving the performance of the LDPC code, such as reducing decoding complexity. Furthermore, improving orthogonality also helps reduce decoding latency and increase throughput. Moreover, improving orthogonality also helps reduce the bit error rate. In addition, by considering the code rate and / or the number of rows in the second LDPC matrix, row interleaving of the first region of the second LDPC matrix helps adapt to different communication environments and communication requirements.

[0013] In conjunction with the first and second aspects, in some possible implementations, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: when the code rate is greater than or equal to a first threshold, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix; and / or, when the number of rows of the second LDPC matrix is ​​less than or equal to a second threshold, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix.

[0014] At higher code rates, data transmission redundancy is typically lower, and the system's error tolerance is also lower. Therefore, performing row interleaving on the first region of the second LDPC matrix at higher code rates can improve the orthogonality of rows within the second LDPC matrix, thereby reducing the bit error rate and ensuring a lower bit error rate even at higher code rates. Furthermore, higher code rates generally result in higher decoding complexity. Therefore, performing row interleaving on the first region of the second LDPC matrix at higher code rates can improve the orthogonality of rows within the second LDPC matrix, thereby improving decoding performance and reducing decoding complexity, thus achieving lower decoding complexity even at higher code rates.

[0015] The number of rows in the second LDPC matrix is ​​related to the code rate. For example, the more rows in the second LDPC matrix, the lower the code rate. Therefore, when the number of rows in the second LDPC matrix is ​​small, performing row interleaving on the first region of the second LDPC matrix can improve the orthogonality between rows in the second LDPC matrix, thereby achieving a lower bit error rate and lower decoding complexity when the code rate is large.

[0016] In conjunction with the first and second aspects, in some possible implementations, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix based on an interleaving sequence, the interleaving sequence is determined according to the code rate and / or the number of rows of the second LDPC matrix, each element in the interleaving sequence is used to indicate the row of the first region of the second LDPC matrix corresponding to each row of the first region of the first LDPC matrix, one code rate interval corresponds to one interleaving sequence, and / or, one row number interval of the second LDPC matrix corresponds to one interleaving sequence.

[0017] In the above scheme, one code rate interval / row interval of a second LDPC matrix corresponds to one interleaving sequence to improve flexibility. For example, it allows for flexible adjustment of the interleaving sequence under different code rate intervals / row intervals, that is, flexible adjustment of the structure of the interleaved matrix to adapt to different communication environments and communication requirements. In addition, different code rate intervals / row intervals may require matrices with different structures to achieve better performance of LDPC codes. Therefore, assigning interleaving sequences to each code rate interval / row interval is beneficial to improving the performance of LDPC codes, such as reducing the bit error rate and decoding delay.

[0018] Combining the first and second aspects, in some possible implementations, the i-th row and j-th row of the first region in the second LDPC matrix are intertwined if one or more of the following conditions are met: a first quantity is less than or equal to a second quantity (denoted as Rule 1); the first quantity is the number of columns in the same column of the first region where the element in the j-th row has a first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has a second value; the second quantity is the number of columns in the same column of the first region where the element in the i-th row has a first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has a second value; wherein, when i = 1, the (i-1)-th row of the first region is located above the first row of the first region in the first LDPC matrix; or, the difference between the number of elements in the i-th row of the first region that have a third value and the number of elements in the j-th row that have a third value is within a first range (denoted as Rule 2).

[0019] In the above scheme, rule one helps to reduce decoding latency after interleaving the i-th row and j-th row of the first region (e.g., the decoding latency corresponding to the i-th row of the first region after interleaving is lower). Rule two ensures that the number of values ​​taking the third value in the i-th and j-th rows of the first region is relatively small, which helps to reduce the impact on decoding performance. For example, the number of 1s in the basis matrix affects decoding performance. Rule two, by limiting the difference in the number of 1s in the i-th and j-th rows of the first region, helps to reduce the impact on decoding performance. For example, a larger number of 1s may lead to higher decoding complexity. By limiting the difference in the number of 1s in the i-th and j-th rows of the first region, the impact on decoding complexity is reduced. In summary, the above scheme reduces decoding latency while ensuring that decoding performance is not significantly affected.

[0020] Combining the first and second aspects, in some possible implementations, the difference between the number of elements in the i-th row of the aforementioned first region that take the third value and the number of elements in the j-th row that take the third value is within a first range includes: the first region is composed of k sub-blocks, each of the k sub-blocks corresponds to a first range, the i-th row of the first region belongs to the first sub-block among the aforementioned k sub-blocks, the difference between the number of elements in the i-th row that take the third value and the number of elements in the j-th row that take the third value is within the first range corresponding to the first sub-block, and k is an integer greater than 0.

[0021] In the above scheme, using a sub-block to correspond to a first range helps to improve the flexibility of the above rule two.

[0022] Combining the first and second aspects, in some possible implementations, the number of elements in the i-th row that take the third value is the same as the number of elements in the j-th row that take the third value.

[0023] By restricting the number of third values ​​in the i-th and j-th rows of the first region to be the same, it helps to ensure that there is basically no impact on decoding performance. For example, if the number of 1s in the i-th and j-th rows of the first region is the same, it helps to ensure that the decoding complexity will not increase after interleaving.

[0024] Combining the first and second aspects, in some possible implementations, the columns in the first sub-block are the punched columns in the first region.

[0025] In the above possible implementations, rules one and two apply to the first region of the LDPC matrix. If the i-th and j-th rows of the first region satisfy rules one and / or rules two, the i-th and j-th rows of the first region are interleaved. In another possible implementation, by considering the LDPC matrix, taking the x-th and y-th rows as an example, if the x-th and y-th rows satisfy rules three and / or rules four, the elements belonging to the first region in the x-th and y-th rows of the LDPC matrix are row-interleaved. For example, the x-th and y-th rows of the core column of the LDPC matrix are row-interleaved.

[0026] Combining the first and second aspects, in some possible implementations, if the x-th and y-th rows of the second LDPC matrix satisfy one or more of the following, the elements belonging to the first region in the x-th and y-th rows of the second LDPC matrix are row-interleaved: the third quantity is less than or equal to the third threshold (denoted as rule three), the third quantity is the sum of the number of columns in the same column where the elements in the y-th row have the first value, but the corresponding elements in the (x-1)-th row of the first LDPC matrix have the second value, and the number of columns in the same column where the elements in the 1-th row of the first LDPC matrix have the first value, but the elements in the y-th row of the second LDPC matrix have the second value; or, the difference between the number of elements in the x-th row having the third value and the number of elements in the y-th row having the third value is within the second range (denoted as rule four).

[0027] In the above scheme, rule three is beneficial to reducing decoding latency (such as reducing the decoding latency of the xth row after interleaving), and rule four is beneficial to reducing the impact on decoding performance.

[0028] Combining the first and second aspects, in some possible implementations, the difference between the number of elements in row x that take the third value and the number of elements in row y that take the third value is within a second range, including: the second LDPC matrix is ​​composed of p sub-blocks, each of the p sub-blocks corresponds to a second range, the elements in row x belong to the second sub-block among the p sub-blocks, the difference between the number of elements in row x that take the third value and the number of elements in row y that take the third value is within the second range corresponding to the second sub-block, and k is an integer greater than 0.

[0029] In the above scheme, using a sub-block to correspond to a second range helps to improve the flexibility of rule four.

[0030] Combining the first and second aspects, in some possible implementations, the number of elements in row x that take the third value is the same as the number of elements in row y that take the third value.

[0031] By limiting the number of third values ​​in rows x and y to be the same, it is beneficial to ensure that there is basically no impact on decoding performance. For example, if the number of 1s in rows x and y is the same, it is beneficial to ensure that the decoding complexity will not increase after interleaving.

[0032] Combining the first and second aspects, in some possible implementations, the columns in the second sub-block are the punched columns in the second LDPC matrix.

[0033] Thirdly, this application provides a communication device that enables the method described in the first aspect and any possible implementation thereof to be implemented, or enables the method described in the second aspect and any possible implementation thereof to be implemented. The device includes corresponding modules for performing the above-described methods. The modules included in the device can be implemented in software and / or hardware.

[0034] Fourthly, this application provides a communication device including a processor. The processor can be used to execute a computer program stored in memory, causing the methods described in the first aspect and any possible implementation thereof to be implemented, or causing the methods described in the second aspect and any possible implementation thereof to be implemented.

[0035] Optionally, the device further includes a communication interface, to which the processor is coupled. The communication interface is used to receive signals from other communication devices besides the aforementioned device and transmit them to the processor, or to send signals from the processor to other communication devices besides the aforementioned device. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0036] Optionally, the device also includes a memory, to which the processor is coupled. The memory is used to store program instructions and data.

[0037] Fifthly, this application provides a computer-readable storage medium storing a computer program or instructions that, when executed by a computer, cause the methods in the first aspect and any possible implementation thereof to be executed, or cause the methods in the second aspect and any possible implementation thereof to be executed.

[0038] Sixthly, this application provides a computer program product comprising: a computer program (also referred to as code or instructions) that, when executed, causes the method in the first aspect and any possible implementation thereof to be executed, or causes the method in the second aspect and any possible implementation thereof to be executed.

[0039] In a seventh aspect, this application provides a chip system including at least one processor for supporting the implementation of the functions involved in the first aspect and any possible implementation of the first aspect, or for supporting the implementation of the functions involved in the second aspect and any possible implementation of the second aspect, such as receiving or processing data involved in the above methods.

[0040] In one possible design, the chip system described above also includes a memory for storing program instructions and data, which may be located inside or outside the processor.

[0041] The chip system can consist of chips or include chips and other discrete components.

[0042] Eighthly, this application provides a communication system, which includes a first communication device and a second communication device, wherein the first communication device is used to implement the method in the first aspect and any possible implementation of the first aspect, and the second communication device is used to implement the method in the second aspect and any possible implementation of the second aspect.

[0043] It should be understood that the third to eighth aspects of this application correspond to the technical solutions of the first and second aspects of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0044] Figure 1 is a schematic diagram of the information transmission process provided in an embodiment of this application;

[0045] Figure 2 is a schematic diagram of the structure of an existing basis matrix;

[0046] Figure 3 is a schematic diagram of the verification matrix provided in an embodiment of this application;

[0047] Figure 4 is a schematic diagram of the basis matrix provided in an embodiment of this application;

[0048] Figure 5 is a schematic diagram of the architecture of a communication system applicable to the method provided in this application;

[0049] Figure 6 is a schematic flowchart of the encoding and decoding method provided in the embodiments of this application;

[0050] Figure 7 is a schematic diagram of the first region provided in an embodiment of this application;

[0051] Figure 8 is a schematic diagram comparing decoding delays provided in an embodiment of this application;

[0052] Figure 9 is a schematic block diagram of a communication device provided in an embodiment of this application;

[0053] Figure 10 is another schematic block diagram of the communication device provided in the embodiments of this application. Detailed Implementation

[0054] Before describing the technical solutions in this application, the following points should be noted.

[0055] First, to facilitate a clear description of the technical solutions provided in this application, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. For example, "first communication device" and "second communication device" are used only to distinguish different communication devices and do not limit their order of execution. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0056] Second, in this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the preceding and following related objects, but it does not exclude the possibility of indicating an "and" relationship; the specific meaning can be understood in context. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c; a and b; a and c; b and c; or a and b and c. Here, a, b, and c can be single or multiple.

[0057] Third, in this application, “when…”, “if,” “under…” and “if” all refer to the device making a corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the device to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0058] Fourth, in this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to the second communication device" can be understood as the destination of the information being the second communication device, which may include direct transmission via the air interface or indirect transmission via the air interface from other units or modules. "Receive information from the first communication device" can be understood as the source of the information being the first communication device, which may include direct reception from the first communication device via the air interface or indirect reception from the first communication device via the air interface from other units or modules. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface.

[0059] In other words, sending and receiving can be performed between communication devices, such as between a second communication device and a first communication device; or they can be performed within a communication device, such as between components, modules, chips, software modules, or hardware modules within the communication device via a bus, wiring, or interface.

[0060] It is understandable that information may undergo necessary processing, such as encoding and modulation, before being sent from the source to the destination. Similarly, the destination, upon receiving information from the source, can also perform corresponding processing, such as decoding and demodulation, to interpret the valid information from the source. The following will describe the information transmission and reception process in detail with reference to Figure 1.

[0061] Figure 1 is a schematic diagram of the information transmission process provided in an embodiment of this application.

[0062] As shown in Figure 1, the information source is the origin of information and information sequences. The information source outputs an information sequence, which is converted into a binary (or multi-level) information sequence through source coding. Then, channel coding is performed on this information sequence to obtain the encoded information sequence, thereby improving the reliability of message transmission. Further, the encoded information sequence can be modulated and then transmitted through the channel. Correspondingly, after receiving the modulated information sequence, the receiving end demodulates it and then performs channel decoding using decoding techniques corresponding to channel coding. Further source decoding is then performed to obtain the original information sequence. Here, the information sink is the object (or destination) of information transmission. The method provided in this application mainly involves channel coding and channel decoding.

[0063] This application primarily relates to improvements in encoding information sequences at the transmitting end and decoding received information at the receiving end. For example, the methods described below may employ LDPC coding techniques. Therefore, before introducing the methods provided in this application, the relevant technical terms of LDPC will be explained in detail below.

[0064] LDPC codes are a forward error correction technique where the encoder uses a parity-check matrix (PCM) for encoding. The PCM is a sparse matrix used to define the parity-check equations for LDPC codes. Each row of the PCM represents a parity-check equation, and each column corresponds to a codeword bit. In other words, the number of rows in the PCM equals the number of parity-check equations, and the number of columns equals the length of the codeword.

[0065] The parity-check matrix can be constructed from the basis matrix. The elements in the basis matrix are typically 0 or 1. The basis matrix can also be represented by a base graph (BG). Each column of the basis matrix can be denoted as a variable node, and each row as a parity node. In the base graph, variable nodes and parity nodes are connected by edges based on the non-zero elements in the parity-check matrix. Each edge connects a variable node and a parity node. A parity node can be connected to one or more variable nodes, and these variable nodes participate in the parity-check equation corresponding to the parity node.

[0066] Currently, the LDPC code base diagrams are BG1 and BG2. BG1 and BG2 share a common matrix structure, which will be described in detail below with reference to Figure 2.

[0067] Figure 2 is a schematic diagram of the structure of an existing basis matrix.

[0068] As shown in Figure 2, the base matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include regions A and B as shown in Figure 2. Region A corresponds to information bits (or information segments, system bits, etc.), and region B is a square matrix corresponding to core parity bits (or core parity digits). The core parity digit can be the parity corresponding to the highest bit rate, or a parity digit with a degree greater than or equal to 2, or a parity node corresponding to the row set with the highest row weight (row weight significantly higher than other rows). The all-zero region can correspond to region C as shown in Figure 2 and is an all-zero matrix. The incremental redundancy region can correspond to region D as shown in Figure 2. The raptor-like region can correspond to region E as shown in Figure 2 and can be an identity matrix, corresponding to the parity bits of the low-rate extension. In this context, regions B and E are both verification parts. Region B is defined as the core verification region, and its features can be non-lower triangular encoded parts (i.e., values ​​above the diagonal are not all 0) or encoded parts with column weights greater than 1. Region E is defined as the extended verification region, and its features can be lower triangular encoded parts (i.e., values ​​above the diagonal are all 0) or diagonal matrices.

[0069] The columns of the LDPC base matrix consist of information columns and check columns.

[0070] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to area A.

[0071] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to regions B and C, and can include core check columns and extended check columns. The core check column is the column corresponding to region B, and the extended check columns are the columns corresponding to regions C or E. Extended check columns can also be called raptor-like columns. Alternatively, the core check column is the check column in region B where the column weight is greater than 1 (there are 1 elements both above and below the diagonal of region B), and the extended check columns are the remaining check columns excluding the core check column.

[0072] Core rows: The core rows of the LDPC basis matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or regions A, B, or C.

[0073] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to area A + area B.

[0074] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or a portion composed of regions A and B.

[0075] The bold box indicates the punched column. The first two columns of the basis matrix corresponding to BG1 and BG2 are punched columns. In terms of matrix characteristics, these two columns have a large column weight, which refers to the number of elements with a value of 1 in the column. In terms of transmission characteristics, the bits (or codewords) corresponding to the punched column are not transmitted. The receiving end recovers these bits by decoding.

[0076] The matrix formed by the values ​​of each element with a value of 1 (also called a non-zero element) in the base matrix (which can be called shift values, translation values, etc.) and the values ​​of each element with a value of 0 (also called a zero element) (this value is, for example, -1) can be called an exponential matrix. The positions with a value of -1 can be expanded into a matrix of Zc rows (Zc being the lift value) and Zc columns, all containing zeros. The positions with a value other than -1 can be expanded into a cyclic shift matrix of Zc rows and Zc columns. From the explanation of exponential and base matrices, it can be seen that the number of rows in the exponential matrix is ​​the same as the number of rows in the base matrix, and the number of columns in the exponential matrix is ​​the same as the number of columns in the base matrix.

[0077] Based on the lifting factor and the base / exponential matrix, the base / exponential matrix can be extended into a parity-check matrix, which can be used for encoding and / or decoding. The lifting factor can also be called the expansion factor, lifting value, expansion value, lifting size, or expansion coefficient, etc., and this application does not specifically limit its name.

[0078] For example, the boost value is denoted as Zc. Each element in the base matrix can be boosted into a matrix with Zc rows and Zc columns. These matrices are combined to form the entire parity check matrix. For instance, the positions of elements 0 in the base matrix can be expanded into a matrix of all zeros with Zc rows and Zc columns, and the positions of elements 1 can be expanded into a cyclic shift matrix with Zc rows and Zc columns. This cyclic shift matrix can be a column-wise cyclic shift P of an identity matrix with Zc rows and Zc columns. i,j The matrix obtained after this step, where P i,j This is the shift value corresponding to the element in the i-th row and j-th column of the base matrix, where the element in the i-th row and j-th column has a value of 1. The shift value can also be called a translation value or a cyclic shift value, etc. It should be understood that the above method of expanding the base matrix into a parity check matrix is ​​merely an example and should not constitute any limitation on this application. The cyclic shift will be explained in detail below.

[0079] In this application, circular shift can be understood as follows: during the shift, the bits in the original range are not lost, but are instead used as fill bits at the other end. For example, circular right shift by x bits means: each bit is shifted right by x bits, and the original low x bits become high x bits; circular left shift by x bits means: each bit is shifted left by x bits, and the original high x bits become low x bits. Where x is a natural number.

[0080] In this application, cyclic shifting of columns or rows in a matrix can also be understood as performing column or row transformations on the matrix. For example, consider an identity matrix with 4 rows and 4 columns. The identity matrix is ​​obtained by cyclically shifting it one position to the right. After the identity matrix is ​​cyclically shifted to the right twice, the resulting matrix is: The identity matrix is ​​cyclically shifted three times to the right, resulting in the following matrix: It is understandable that the matrix obtained by cyclically shifting the identity matrix to the right 0 times is still the identity matrix.

[0081] The base matrix, after being expanded by the lifting value (Zc), yields the parity-check matrix. Correspondingly, the base graph, after being expanded by the lifting value, yields a bipartite graph (tanner). That is, the parity-check matrix can also be represented by a bipartite graph. Assuming the number of variable nodes in the base graph is X, the number of parity-check nodes is Y, and the number of edges is F, then the number of columns in the parity-check matrix (the number of variable nodes in the bipartite graph) is Zc×X, the number of rows in the parity-check matrix (the number of parity-check nodes) is Zc×Y, and the number of non-zero elements in the parity-check matrix is ​​Zc×F.

[0082] Figure 3 is a schematic diagram of the verification matrix provided in an embodiment of this application.

[0083] As shown in Figure 3, the parity-check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a Laptler-like region. A detailed explanation of each region can be found in Figure 2, and will not be repeated here. The parity-check matrix of the LDPC code shown in Figure 3 adopts a "raptor-like" structure, which can be gradually extended to low-rate regions from a high-rate core matrix. In practical use, as shown in Figure 3, the first X rows and first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the region using the matrix also gradually expands.

[0084] Currently, the orthogonality of adjacent rows in the basis matrix is ​​poor, which may affect the performance of LDPC codes. Figure 4 shows a portion of the basis matrix, and its orthogonality will be analyzed below in conjunction with Figure 4. In the embodiments described below, the orthogonality between two adjacent rows can be measured by the number of columns with different values.

[0085] As shown in Figure 4, rows A, B, and C have adjacent rows containing only 1s, indicating poor orthogonality. Poor orthogonality can lead to increased interference between different codewords, which may affect decoder performance and complicate the decoding process. Furthermore, the decoder may require additional computation to handle interference, potentially reducing overall system efficiency, such as increased latency and lower throughput. Poor orthogonality can also increase the bit error rate because the decoder may struggle to accurately distinguish and recover the original information.

[0086] To address this, this application provides an encoding / decoding method based on an interleaved LDPC matrix (such as an interleaved base matrix / interleaved exponent matrix). The interleaving of the LDPC matrix considers the code rate and / or the number of rows in the LDPC matrix. By performing row interleaving on the first region of the LDPC matrix, the correlation between rows in the LDPC matrix is ​​reduced, thereby improving the orthogonality of the LDPC matrix and thus improving the performance of the LDPC code, such as reducing decoding complexity. This, in turn, improves the overall efficiency of the system, such as reducing decoding latency and increasing throughput. Furthermore, improving orthogonality also helps to reduce the bit error rate.

[0087] It should be understood that this application uses row interleaving of the first region of the LDPC matrix as an example, but this should not constitute any limitation on this application. For example, in practical applications, column interleaving or row / column interleaving of the LDPC matrix can also be performed on the first region of the LDPC matrix, and this application does not limit this. When column interleaving is performed, the rules that the columns satisfy are similar to the rules that the rows satisfy, as described below.

[0088] Before detailing the encoding and decoding methods described above, the architecture of the communication system to which this application applies will be explained in detail below.

[0089] The solution provided in this application can be applied to various communication systems, such as: non-terrestrial networks (NTN) communication systems, Internet of Things (IoT) systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, machine-to-machine (M2M) communication systems, machine-type communication (MTC) systems, LTE systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, universal mobile telecommunications systems (UMTS), 5G mobile communication systems, new radio (NR) systems, or future communication systems, etc.

[0090] Figure 5 illustrates a possible, non-limiting system diagram. As shown in Figure 5, the communication system 10 includes a RAN 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (110a and 110b in Figure 5, collectively referred to as 110) and at least one terminal (120a-120j in Figure 5, collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment (not shown in Figure 5). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is connected to core network 200 wirelessly or via wired connection. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and wireless access network logical functions.

[0091] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud RAN (CRAN), a virtualized RAN (vRAN), an artificial intelligence RAN (AI RAN), or a wireless fidelity (Wi-Fi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0092] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in this communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 5 can be a helicopter or drone, which can be configured as a mobile base station. For terminals 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes both referred to as communication devices. For example, network elements 110a and 110b in Figure 5 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal functions.

[0093] In one possible scenario, the RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a Wi-Fi system. The RAN node can be a macro base station (as shown in Figure 5, 110a), a micro base station or indoor station (as shown in Figure 5, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions, as well as corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the access node's functions, or a circuit or chip (such as a GPU, AI processor, or ASIC) responsible for computational functions within the access node.

[0094] In another possible scenario, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes implementing some of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs). CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). Furthermore, RAN nodes can also be computing units, providing computational power for tasks such as model inference and / or model training, and can also be used to implement one or more of the following: task partitioning, scheduling, and orchestration. The functionality of a computing unit can be implemented by a separate module independent of other units (e.g., CU, DU, RU), or by one or more other units (e.g., one or more of CU, DU, RU).

[0095] In different systems, CU (or CU-CP and CU-UP), DU, computing unit, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, computing unit, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, computing unit, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0096] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. Terminals typically contain communication modules, circuits, or chips that perform corresponding communication functions, and may further contain modules, circuits, or chips that perform corresponding computing functions. The terminal can also be configured with program instructions for performing corresponding communication and / or computing functions.

[0097] The encoding and decoding method provided in this application will be described in detail below with reference to the accompanying drawings. The method is described using the interaction between a first communication device and a second communication device as an example, and should not be construed as limiting this application in any way. The first communication device may also be replaced by a component configured in the first communication device (such as a chip, chip system, processor, etc.), or a logic module or software capable of implementing all or part of the functions of the first communication device. The second communication device may be replaced by a component configured in the second communication device (such as a chip, chip system, processor, etc.), or a logic module or software capable of implementing all or part of the functions of the second communication device. The first communication device can be an access network device (as shown in Figure 5, access network device 110), and the second communication device can be a terminal (as shown in Figure 5, terminal 120); or, the first communication device can be a terminal (as shown in Figure 5, terminal 120), and the second communication device can be an access network device (as shown in Figure 5, access network device 110); or, the first communication device can be a terminal (as shown in Figure 5, terminal 120), and the second communication device can also be a terminal (as shown in Figure 5, terminal 120); or, the first communication device can be an access network device (as shown in Figure 5, access network device 110), and the second communication device can also be an access network device (as shown in Figure 5, access network device 110), etc., which will not be listed here.

[0098] Figure 6 is a schematic flowchart of a coding / decoding method 600 provided in an embodiment of this application. The method 600 shown in Figure 6 includes steps 610 to 630. The various steps in method 600 are described in detail below.

[0099] In step 610, the first communication device encodes information bits based on the first LDPC matrix to obtain encoded bits. The first LDPC matrix is ​​obtained by row interleaving the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix.

[0100] In step 620, the first communication device outputs the aforementioned encoded bits.

[0101] The encoded bits can also undergo one or more of the following processes: rate matching, interleaving, or modulation, to obtain a bit sequence to be transmitted, which the first communication device then transmits. Correspondingly, the second communication device receives the bit sequence from the first communication device.

[0102] In step 630, the second communication device decodes the bits to be decoded based on the first LDPC matrix to obtain information bits.

[0103] The second communication device can obtain the bits to be decoded by performing one or more of the following on the received bit sequence: demodulation, deinterleaving, or rate matching, etc., and then the second communication device can decode the bits to be decoded based on the first LDPC matrix to obtain the information bits.

[0104] The first communication device can encode information bits based on the first LDPC matrix, and the second communication device can decode bits to be decoded based on the first LDPC matrix. The following will take the first communication device as an example to introduce in detail the improvement of the first LDPC matrix in this application.

[0105] It should be understood that in the embodiment shown in Figure 6, the example is to perform row interleaving on the first region of the second LDPC matrix to obtain the first LDPC matrix, and then encode based on the first LDPC matrix. However, this should not constitute any limitation on this application. For example, the first communication device can also encode information bits based on the second LDPC matrix to obtain coded bits, and then interleave the coded bits based on the interleaving sequence. The rules satisfied by the interleaving sequence are the same as those of rules one to four described below, as detailed below. Correspondingly, the second communication device can deinterleave based on the interleaving sequence and decode the deinterleaved sequence based on the second LDPC matrix.

[0106] The first LDPC matrix described above can be considered as the interleaved LDPC matrix, and the second LDPC matrix can be considered as the uninterleaved LDPC matrix. Optionally, in this application, the LDPC matrix can be a base matrix or an exponential matrix, and this application does not limit this. For example, the second LDPC matrix described above is a base matrix (such as the base matrix corresponding to BG1 / BG2 mentioned above), and the first LDPC matrix is ​​obtained by row interleaving the first region of the base matrix. As another example, the second LDPC matrix described above is an exponential matrix, and the first LDPC matrix is ​​obtained by row interleaving the first region of the exponential matrix. Optionally, the first region can be the region corresponding to the core columns; for example, row interleaving is performed on the rows corresponding to the core columns of the base matrix, and as another example, row interleaving is performed on the rows corresponding to the core columns of the exponential matrix.

[0107] For example, the first communication device performs row interleaving on a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix to obtain a first LDPC matrix, and encodes information bits according to the first LDPC matrix to obtain and output encoded bits. The first communication device may also perform one or more of the following on the encoded bits: rate matching, interleaving or modulation, etc., to obtain a bit sequence to be transmitted, thereby the first communication device transmits the bit sequence to be transmitted.

[0108] Correspondingly, the second communication device receives a bit sequence from the first communication device. Further, the second communication device can perform one or more of the following on the received bit sequence to obtain and input the bits to be decoded: demodulation, deinterleaving, or rate matching, etc., and then the second communication device can decode the bits to be decoded based on the first LDPC matrix to obtain the information bits. Alternatively, similar to the first communication device, the second communication device can perform row interleaving on the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix to obtain the aforementioned first LDPC matrix.

[0109] The first LDPC matrix mentioned above is obtained by row interleaving the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix. It can be implemented based on any of the following implementation methods A and B:

[0110] Implementation Method A: The first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the bit rate and / or the number of rows of the second LDPC matrix, including: when the bit rate is greater than or equal to a first threshold, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix; and / or, when the number of rows of the second LDPC matrix is ​​less than or equal to a second threshold, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix.

[0111] As one possible design, when the code rate is greater than or equal to a first threshold, the first communication device / second communication device can perform row interleaving on the first region of the second LDPC matrix to obtain the first LDPC matrix; when the code rate is less than the first threshold, the first communication device may not perform row interleaving on the first region of the second LDPC matrix, that is, the first communication device can encode the information bits based on the second LDPC matrix. Correspondingly, the second communication device may also not perform row interleaving on the first region of the second LDPC matrix, that is, the second communication device can decode the bits to be decoded based on the second LDPC matrix. This application does not limit the size of the first threshold; for example, the first threshold can be 1 / 2, the first threshold can be 1 / 3, etc., and will not be listed here.

[0112] At higher code rates, data transmission redundancy is typically lower, and the system's error tolerance is also lower. Therefore, in the above design, row interleaving of the second LDPC matrix at higher code rates improves the orthogonality of rows within the second LDPC matrix, thereby reducing the bit error rate and ensuring a lower bit error rate even at higher code rates. Furthermore, higher code rates generally result in higher decoding complexity. Therefore, in the above design, row interleaving of the second LDPC matrix at higher code rates improves the orthogonality of rows within the second LDPC matrix, thereby improving decoding performance and reducing decoding complexity, thus achieving lower decoding complexity even at higher code rates.

[0113] As another possible design, when the number of rows in the second LDPC matrix is ​​less than or equal to the second threshold, the first communication device / second communication device can perform row interleaving on the first region of the second LDPC matrix to obtain the first LDPC matrix; when the number of rows in the second LDPC matrix is ​​greater than the second threshold, the first communication device may not perform row interleaving on the first region of the second LDPC matrix, that is, the first communication device can encode information bits based on the second LDPC matrix. Correspondingly, the second communication device may also not perform row interleaving on the first region of the second LDPC matrix, that is, the second communication device can decode the bits to be decoded based on the second LDPC matrix. This application does not limit the size of the second threshold; for example, the second threshold can be 12, the second threshold can be 22, etc., and will not be listed here.

[0114] The number of rows in the second LDPC matrix is ​​related to the code rate. For example, the more rows in the second LDPC matrix, the lower the code rate. Therefore, when the number of rows in the second LDPC matrix is ​​small, the code rate is relatively high. Performing row interleaving in the first region of the second LDPC matrix can improve the orthogonality of the rows, thereby achieving a lower bit error rate even at a higher code rate. Furthermore, when the number of rows in the second LDPC matrix is ​​small, the code rate is relatively high. Performing row interleaving in the first region of the second LDPC matrix can improve the orthogonality of the rows, thereby improving decoding performance and reducing decoding complexity, achieving lower decoding complexity even at a higher code rate.

[0115] In one possible implementation, the first communication device / second communication device can perform row interleaving on the first region of the second LDPC matrix based on an interleaving sequence. Each element in the interleaving sequence indicates which row of the first region in the first LDPC matrix corresponds to a row of the first region in the second LDPC matrix; or, in other words, indicates which row of the first region in the interleaved LDPC matrix corresponds to a row of the first region in the LDPC matrix before interleaving. The number of elements in the interleaving sequence can be equal to the number of rows in the first region of the LDPC matrix.

[0116] For example, when the code rate is greater than or equal to a first threshold, or when the number of rows in the second LDPC matrix is ​​less than or equal to a second threshold, the first communication device / second communication device can perform row interleaving on the first region of the second LDPC matrix based on the interleaving sequence to obtain the first LDPC matrix. Here, the elements in the interleaving sequence correspond one-to-one with the rows of the first region of the first LDPC matrix, indicating the row of the first region of the second LDPC matrix corresponding to each row of the first region of the first LDPC matrix. For instance, the first element in the interleaving sequence corresponds to the first row of the first region of the first LDPC matrix, indicating which row of the first region of the second LDPC matrix corresponds to the first row of the first region of the first LDPC matrix. In the embodiments below, the interleaving sequence can be represented by U, where U(i) = j represents the value of the i-th element in the interleaving sequence. This value indicates that the i-th row of the first region of the first LDPC matrix is ​​the j-th row of the first region of the second LDPC matrix, or in other words, that the i-th row of the first region of the interleaved LDPC matrix is ​​the j-th row of the first region of the LDPC matrix before interleaving.

[0117] For example, the interleaving sequence is {1, 2, 4, 3, 5, 6, 10, 7, 14, 8, 9, 12, 13, 11, 17, 19, 15, 24, 18, 20, 21, 22, 25, 16, 29, 35, 31, 28, 36, 37, 27, 39, 40, 41, 33, 23, 26, 34, 42, 30, 38, 32}, where the first region is, for example, the region corresponding to the core column, such as region A + region B + region D, and the third element corresponds to the interleaved LDPC matrix. In the third row of the first region, the third element in the aforementioned interleaving sequence has a value of 4, indicating that the third row of the first region of the interleaved LDPC matrix is ​​the fourth row of the first region of the uninterleaved LDPC matrix. Similarly, the fourth element in the aforementioned interleaving sequence has a value of 3, indicating that the fourth row of the first region of the interleaved LDPC matrix is ​​the third row of the first region of the uninterleaved LDPC matrix. In other words, the third and fourth rows of the first region of the LDPC matrix are interleaved / exchanged. The above example uses the third and fourth elements as examples; for simplicity, other elements will not be explained here.

[0118] Implementation Method B: The first LDPC matrix is ​​obtained by row interleaving the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: the first LDPC matrix is ​​obtained by row interleaving the first region of the second LDPC matrix based on the interleaving sequence, the interleaving sequence is determined according to the code rate and / or the number of rows of the second LDPC matrix, each element in the interleaving sequence is used to indicate the row of the first region of the second LDPC matrix corresponding to each row of the first region of the first LDPC matrix, one code rate interval corresponds to one interleaving sequence, and / or, one row number interval of the second LDPC matrix corresponds to one interleaving sequence.

[0119] As one possible design, a code rate interval corresponds to an interleaving sequence. The first communication device / second communication device can determine the corresponding interleaving sequence based on the code rate interval to which the code rate belongs, and perform row interleaving on the first region in the second LDPC matrix according to the interleaving sequence to obtain the first LDPC matrix. In other words, the first LDPC matrix is ​​obtained by performing row interleaving on the first region in the second LDPC matrix based on the interleaving sequence corresponding to the code rate interval to which the code rate belongs. The correspondence between one code rate interval and one interleaving sequence can also be replaced by one code rate corresponding to one interleaving sequence. The above correspondence between code rate intervals and interleaving sequences can be predefined / configured / pre-configured, and this application does not limit this.

[0120] For example, as shown in Table 1, the code rate interval 1 corresponds to interleaving sequence 1, the code rate interval 2 corresponds to interleaving sequence 2, ..., the code rate interval n corresponds to interleaving sequence n. Assuming that the current code rate belongs to code rate interval 1, the first communication device / second communication device can perform row interleaving on the first region in the second LDPC matrix according to the interleaving sequence corresponding to code rate interval 1 to obtain the first LDPC matrix.

[0121] Table 1

[0122] As another possible design, one row interval corresponds to one interleaving sequence. The first communication device / second communication device can determine the corresponding interleaving sequence based on the row interval to which the row number of the second LDPC matrix belongs, and perform row interleaving on the first region of the second LDPC matrix according to the interleaving sequence to obtain the first LDPC matrix. In other words, the first LDPC matrix is ​​obtained by performing row interleaving on the first region of the second LDPC matrix based on the interleaving sequence corresponding to the row interval to which the row number belongs. One row interval corresponding to one interleaving sequence can also be replaced by one row number corresponding to one interleaving sequence. The correspondence between the row intervals and the interleaving sequences can be predefined / configured / pre-configured, and this application does not limit this.

[0123] For example, as shown in Table 2, row number interval 1 corresponds to interleaving sequence 1, row number interval 2 corresponds to interleaving sequence 2, ..., row number interval m corresponds to interleaving sequence m. Assuming that the row number of the second LDPC matrix belongs to row number interval 1, the first communication device / second communication device can perform row interleaving on the first region in the second LDPC matrix according to the interleaving sequence corresponding to row number interval 1 to obtain the first LDPC matrix.

[0124] Table 2

[0125] It should be understood that the correspondences shown in the above tables (Table 1, Table 2) can be configured or predefined. The values ​​of the information in each table are merely examples and can be configured to other values; this application is not limiting. When configuring the correspondence between information and parameters, it is not necessarily required to configure all the correspondences shown in each table. For example, the correspondences shown in some rows of the tables in this application may not be configured. Furthermore, appropriate modifications and adjustments can be made based on the above tables, such as splitting, merging, etc. The names of the parameters shown in the headings of the above tables can also use other names that the communication device can understand, and the values ​​or representations of the parameters can also be other values ​​or representations that the communication device can understand. In the implementation of the above tables, other data structures can also be used, such as arrays, queues, containers, stacks, linear lists, pointers, linked lists, trees, graphs, structures, classes, heaps, hash tables, or hash tables, etc.

[0126] In implementation B described above, one code rate interval / row interval of a second LDPC matrix corresponds to one interleaving sequence to improve flexibility. For example, it allows for flexible adjustment of the interleaving sequence under different code rate intervals / row intervals, that is, flexible adjustment of the structure of the interleaved matrix to adapt to different communication environments and requirements. Furthermore, different code rate intervals / row intervals may require matrices with different structures to achieve better performance of the LDPC code. Therefore, assigning interleaving sequences to each code rate interval / row interval is beneficial to improving the performance of the LDPC code, such as reducing the bit error rate and decoding latency.

[0127] Optionally, the row interleaving of the first region in the second LDPC matrix includes interleaving the rows of the core columns in the second LDPC matrix. That is, the first region is the region corresponding to the core columns, where the core columns can be, for example, all columns corresponding to regions A and B as shown in Figure 2. By interleaving only the rows of the core columns in the second LDPC matrix, the complexity of the interleaving can be reduced.

[0128] The rules that the interleaving sequences must satisfy will be described in detail below. That is, if two rows in the second LDPC matrix satisfy the rules, these two rows can be interleaved (interleaving only applies to these two rows in the core column). In the rules described below, rules one and two are based on the first region in the LDPC matrix (denoted as implementation method one), while rules three and four are based on the LDPC matrix itself (denoted as implementation method two).

[0129] Implementation Method 1: The i-th and j-th rows of the first region in the second LDPC matrix are intertwined if one or more of the following conditions are met: the first quantity is less than or equal to the second quantity (referred to as Rule 1); the first quantity is the number of columns in the same column of the first region where the element in the j-th row has the first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has the second value; the second quantity is the number of columns in the same column of the first region where the element in the i-th row has the first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has the second value; where, when i=1, the (i-1)-th row of the first region is located above the first row of the first region in the first LDPC matrix; or, the difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value is within the first range (referred to as Rule 2).

[0130] The first region mentioned above can be the region corresponding to the core column. For example, the first region could be region A + region B + region C, or region D, region B, or region A, or region A + B, etc. This application does not limit the specific region. The row numbers of the i-th and j-th rows are numbered with the first region as the granularity. The i-th row in the first region could be the x-th row in the LDPC matrix, and the j-th row in the first region could be the y-th row in the LDPC matrix.

[0131] Figure 7 is a schematic diagram of the first region provided in an embodiment of this application. Figure 7 shows an example of the first region in the base matrix and should not be construed as limiting the present application. In addition, Figure 7 only shows a portion of the base matrix, and the values ​​of the elements in Figure 7 should not be construed as limiting the present application.

[0132] As shown in Figure 7, the first region is indicated by the dashed box. The third row in the first region is the seventh row in the basis matrix, and the eleventh row in the first region is the fifteenth row in the basis matrix. When the third and eleventh rows in the first region satisfy Rule 1 and / or Rule 2, these two rows in the first region intertwine. That is, the seventh row of the first region of the basis matrix and the fifteenth row of the basis matrix intertwine.

[0133] The following will explain Rule 1 and Rule 2 in detail.

[0134] Explanation of Rule 1: The first quantity mentioned above refers to the number of columns in the first region where the element in the j-th row has the first value, but the element in the (i-1)-th row of the first region in the first LDPC matrix has the second value. The second quantity mentioned above refers to the number of columns in the first region where the element in the i-th row has the first value, but the element in the (i-1)-th row of the first region in the first LDPC matrix has the second value.

[0135] Wherein, the above-mentioned (i-1)th row is the (i-1)th row of the first region of the first LDPC matrix, that is, the above-mentioned (i-1)th row is the (i-1)th row of the first region of the interleaved LDPC matrix. The above-mentioned (i-1)th row of the first region may be interleaved with other rows or may not be interleaved. This application does not limit this.

[0136] When i = 1, the (i-1)th row of the first region is located above the first row of the first region in the first LDPC matrix. For example, as shown in Figure 7, when i = 1, the (i-1)th row is located above the first row of the first region, as indicated by the arrow in Figure 7. In this case, only the columns that are the same as those in the first region are considered in the row above the first row of the first region, as shown by columns 1 to 14 in Figure 7.

[0137] In one possible design, the LDPC matrix is ​​the base matrix. The first quantity mentioned above can be understood as the number of columns in the first region where the element in the j-th row is 1, but the corresponding element in the (i-1)-th row is 0; the second quantity mentioned above can be understood as the number of columns in the first region where the element in the i-th row is 1, but the corresponding element in the (i-1)-th row is 0, where 1 is an example of the first value and 0 is an example of the second value. Alternatively, the first quantity mentioned above can be understood as the number of columns in the first region where the element in the j-th row is 0, but the corresponding element in the (i-1)-th row is 1; the second quantity mentioned above can be understood as the number of columns in the first region where the element in the i-th row is 0, but the corresponding element in the (i-1)-th row is 1, where 0 is an example of the first value and 1 is an example of the second value.

[0138] For example, as shown in Figure 7, i = 3, j = 11, the element in the 11th row and 1st column of the first region has a value of 0, the element in the 2nd row and 1st column of the first region has a value of 1, the element in the 11th row and 6th column of the first region has a value of 0, the element in the 2nd row and 6th column of the first region has a value of 1, the element in the 11th row and 8th column of the first region has a value of 0, and the element in the 2nd row and 8th column of the first region has a value of 1. Therefore, the first quantity is 3. Similarly, the element in the 3rd row and 2nd column of the first region has a value of 0, and the element in the 2nd row and 2nd column of the first region has a value of 1. Therefore, the second quantity is 1. In the above example, the 2nd row of the first region can be the 2nd row of the first region of the interleaved base matrix, that is, the 2nd row of the first region may be obtained after interleaving with other rows of the base matrix, or the 2nd row of the first region may be uninterleaved, that is, the 2nd row of the first region may not be interleaved with other rows of the base matrix.

[0139] In another possible design, the LDPC matrix is ​​an exponential matrix. The first quantity mentioned above can be understood as the number of columns in the first region where the element in the j-th row has a value of -1, but the corresponding element in the (i-1)-th row has a value other than -1. The second quantity mentioned above can be understood as the number of columns in the first region where the element in the i-th row has a value of -1, but the corresponding element in the (i-1)-th row has a value other than -1. -1 is an example of the first value, and non--1 is an example of the second value. Alternatively, the first quantity mentioned above can be understood as the number of columns in the first region where the element in the j-th row has a value other than -1, but the corresponding element in the (i-1)-th row has a value of -1. The second quantity mentioned above can be understood as the number of columns in the first region where the element in the i-th row has a value other than -1, but the corresponding element in the (i-1)-th row has a value of -1. Non--1 is an example of the first value, and -1 is an example of the second value.

[0140] In the above implementation method one, rule one is beneficial to ensure that after the i-th row of the first region is interleaved with the j-th row of the first region, the latency corresponding to the i-th row of the first region is reduced.

[0141] Explanation of Rule 2: The difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value is within a first range, where the first range can be [a, b]. That is, the difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value can be greater than or equal to a and less than or equal to b, where a and b can be opposite numbers or two real numbers. This application does not limit this.

[0142] In one possible design, the LDPC matrix is ​​the base matrix. For example, the third value can be 1, and rule two can be that the difference between the number of elements with a value of 1 in the i-th row and the number of elements with a value of 1 in the j-th row of the first region is within a certain range. Alternatively, the third value can be 0, and rule two can be that the difference between the number of elements with a value of 0 in the i-th row and the number of elements with a value of 0 in the j-th row of the first region is within a certain range.

[0143] For example, as shown in Figure 7, i = 3, j = 11, assuming the third value is 1, the number of 1s in the 11th row of the first region is 4, the number of 1s in the 3rd row of the first region is 5, assuming the first range is [-1, 1], the difference between the number of 1s in the 11th row of the first region and the number of 1s in the 3rd row of the first region is within the first range.

[0144] In another possible design, the LDPC matrix is ​​an exponential matrix. For example, the third value can be non--1, and rule two can be that the difference between the number of non--1 elements in the i-th row and the number of non--1 elements in the j-th row of the first region is within a certain range. Alternatively, the third value can be -1, and rule two can be that the difference between the number of -1 elements in the i-th row and the number of -1 elements in the j-th row of the first region is within a certain range.

[0145] In the first implementation described above, rule two stipulates that the number of values ​​taking the third value in the i-th and j-th rows of the first region should be relatively close. This helps to reduce the impact on decoding performance. For example, the number of 1s in the basis matrix affects decoding performance. Rule two, by limiting the number of 1s in the i-th and j-th rows of the first region to be relatively close, helps to reduce the impact on decoding performance. For instance, a higher number of 1s may lead to higher decoding complexity. By limiting the number of 1s in the i-th and j-th rows of the first region to be relatively close, the impact on decoding complexity is reduced.

[0146] Optionally, one possible scenario for Rule 2 above is that the number of elements in the i-th row of the first region that take the third value is the same as the number of elements in the j-th row that take the third value. In other words, the first range is 0.

[0147] In one possible design, the LDPC matrix is ​​the base matrix. For example, the third value can be 1, and rule two can be that the number of 1s in the i-th row of the first region is the same as the number of 1s in the j-th row. Alternatively, the third value can be 0, and rule two can be that the number of 0s in the i-th row of the first region is the same as the number of 0s in the j-th row.

[0148] For example, as shown in Figure 7, i = 3, j = 11, assuming the third value is 1, the number of 1s in the 11th row of the first region is 4, and the number of 1s in the 3rd row of the first region is 5. The number of 1s in these two rows is different, so the 11th row of the first region and the 3rd row of the first region do not intertwine.

[0149] In another possible design, the LDPC matrix is ​​an exponential matrix. For example, the third value can be non--1, and rule two can be that the number of non--1 elements in the i-th row of the first region is the same as the number of non--1 elements in the j-th row. Alternatively, the third value can be -1, and rule two can be that the number of -1 elements in the i-th row of the first region is the same as the number of -1 elements in the j-th row.

[0150] By restricting the number of third values ​​in the i-th and j-th rows of the first region to be the same, it helps to ensure that there is basically no impact on decoding performance. For example, if the number of 1s in the i-th and j-th rows of the first region is the same, it helps to ensure that the decoding complexity will not increase after interleaving.

[0151] Optionally, the difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value is within a first range, including: the first region is composed of k sub-blocks, each of the k sub-blocks corresponds to a first range, the i-th row of the first region belongs to the first sub-block among the k sub-blocks, the difference between the number of elements in the i-th row that have the third value and the number of elements in the j-th row that have the third value is within a first range corresponding to the first sub-block, and k is an integer greater than 0.

[0152] One possible design is that the first region consists of k sub-blocks, which are obtained by dividing the columns of the first region. In other words, based on the division of the columns of the first region, k groups are obtained, and each of the k groups corresponds to a first range. For example, if the LDPC matrix is ​​a base matrix with 52 columns, and the first region of the base matrix has 19 columns with column indices from 1 to 19, the columns of the first region can be divided into two groups, i.e., k = 2. For example, one group has column indices [1, 2, ..., 14], which corresponds to a first range, and the other group has column indices [15, 16, ..., 19], which also corresponds to a first range. The difference between the number of values ​​in the first row, columns 1 to 14 of the first region being the third value and the number of values ​​in the first row, columns 1 to 14 of the first region being the third value should be within the first range corresponding to the first group. The difference between the number of values ​​in the first row, columns 15 to 19 of the first region being the third value and the number of values ​​in the first row, columns 15 to 19 of the first region being the third value should be within the first range corresponding to the second group.

[0153] Another possible design is that the first region consists of k sub-blocks, which are obtained by dividing the rows of the first region. In other words, based on the division of the rows of the first region, k groups are obtained, each group corresponding to a first range. For example, if the LDPC matrix is ​​a base matrix with 42 rows, and the first region of this base matrix has 7 rows with row indices 1 to 7, the rows of this first region can be divided into 2 groups, i.e., k = 2. For example, the row indices of the first group are [1, 2, 3, 4], which correspond to a first range, and the row indices of the second group are [5, 6, 7], which also correspond to a first range. Taking i = 3 as an example, if i belongs to the first group, then the difference between the number of elements in the i-th row that have the third value and the number of elements in the j-th row that have the third value is within the first range corresponding to the first group. Similarly, if i belongs to the second group, then the difference between the number of elements in the i-th row that have the third value and the number of elements in the j-th row that have the third value is within the first range corresponding to the second group.

[0154] Another possible design is that the first region consists of k sub-blocks, which are obtained by dividing the first region into rows and columns, with each sub-block corresponding to a first range. For example, the LDPC matrix is ​​a base matrix with 42 rows. The first region of the base matrix has 7 rows with row indices 1 to 7. The rows of the first region can be divided into two groups, such as the row indices of the first group being [1,2,3,4] and the row indices of the second group being [5,6,7]. The base matrix has 52 columns, and the first region of the base matrix has 19 columns with column indices 1 to 19. The columns of the first region can be divided into three groups, with the column indices of the first group being [1,2,…,6], the column indices of the second group being [7,8,…,14], and the column indices of the third group being [15,16,…,19]. Rows 1 to 4 and columns 1 to 6 can be considered sub-block 1, rows 1 to 4 and columns 7 to 14 can be considered sub-block 2, and rows 1 to 4 and columns 15 to 19 can be considered sub-block 3. Rows 5 to 7 and columns 1 to 6 can be considered sub-block 4; rows 5 to 7 and columns 7 to 14 can be considered sub-block 5; rows 5 to 7 and columns 15 to 17 can be considered sub-block 6. Each sub-block corresponds to a first range. Taking i=3 as an example, i belongs to the first group in the row index division. The difference between the number of values ​​with the third digit in columns 1 to 6 of row i and the number of values ​​with the third digit in columns 1 to 6 of row j is within the first range corresponding to sub-block 1; the difference between the number of values ​​with the third digit in columns 7 to 14 of row i and the number of values ​​with the third digit in columns 7 to 14 of row j is within the first range corresponding to sub-block 2; and the difference between the number of values ​​with the third digit in columns 15 to 19 of row i and the number of values ​​with the third digit in columns 15 to 19 of row j is within the first range corresponding to sub-block 3.

[0155] In the above scheme, using a sub-block to correspond to a first range helps to improve the flexibility of the above rule two.

[0156] Optionally, the columns in the first sub-block are the punched columns in the first region. That is, the columns in one of the k sub-blocks divided into the first region are the punched columns in the first region.

[0157] One possible design is that the first region consists of k sub-blocks, which are obtained by dividing the columns of the first region. In other words, based on the division of the columns of the first region, k groups are obtained, each group corresponding to a first range. The columns in one of the k sub-blocks of the first region are the punched columns in the first region. For example, if the LDPC matrix is ​​a base matrix with 52 columns, and the first region of this base matrix has 19 columns with column indices from 1 to 19, the first and second columns of this first region are punched columns. The columns of this first region can be divided into two groups, i.e., k = 2. For example, one group has column indices [1, 2], meaning the punched columns are grouped together, and this group corresponds to a first range. The other group has column indices [3, 4, ..., 19], and this group also corresponds to a first range.

[0158] Another possible design is that the first region consists of k sub-blocks, which are obtained by dividing the first region into rows and columns, with each sub-block corresponding to a first range. For example, the LDPC matrix is ​​a base matrix with 42 rows. The first region of the base matrix has 7 rows with row indices 1 to 7. The rows of the first region can be divided into two groups, such as the row indices of the first group being [1,2,3,4] and the row indices of the second group being [5,6,7]. The base matrix has 52 columns, and the first region of the base matrix has 19 columns with column indices 1 to 19. The first and second columns of the first region of the base matrix are punched columns. The columns of the first region can be divided into three groups, with the column indices of the first group being [1,2], the column indices of the second group being [3,4,…,14], and the column indices of the third group being [15,16,…,19]. Rows 1 to 4 and columns 1 and 2 can be considered sub-block 1, rows 1 to 4 and columns 3 to 14 can be considered sub-block 2, and rows 1 to 4 and columns 15 to 19 can be considered sub-block 3. Rows 5 to 7, columns 1 and 2 can be considered sub-block 4; rows 5 to 7, columns 3 to 14 can be considered sub-block 5; rows 5 to 7, columns 15 to 17 can be considered sub-block 6. Each sub-block can correspond to a first range.

[0159] Implementation Method 2: When the x-th and y-th rows of the second LDPC matrix satisfy one or more of the following conditions, the elements belonging to the first region in the x-th and y-th rows of the second LDPC matrix are row-interleaved, such as the x-th and y-th rows of the core column of the second LDPC matrix being row-interleaved: the third quantity is less than or equal to the third threshold (referred to as Rule 3), the third quantity is the sum of the number of columns in the same column where the element in the y-th row has the first value but the corresponding element in the (x-1)-th row of the first LDPC matrix has the second value, and the number of columns in the same column where the element in the 1-th row of the first LDPC matrix has the first value but the element in the y-th row of the second LDPC matrix has the second value; or, the difference between the number of elements in the x-th row having the third value and the number of elements in the y-th row having the third value is within the second range (referred to as Rule 4).

[0160] As an example, as shown in Figure 7, if the 7th row and the 15th row of the basis matrix satisfy Rule 3 and / or Rule 4, then the 7th and 15th rows of the core columns of the basis matrix are interleaved.

[0161] The following will explain rules three and four in detail.

[0162] Explanation of Rule 3: The third quantity mentioned above is the number of columns in the same column where the element in the y-th row has the first value, but the corresponding element in the (x-1)-th row of the first LDPC matrix has the second value, plus the number of columns in the same column where the element in the 1st row of the first LDPC matrix has the first value, but the element in the y-th row of the second LDPC matrix has the second value.

[0163] In one possible design, the LDPC matrix is ​​the base matrix. The aforementioned third quantity can be understood as the number of columns where the element in the y-th row is 0, but the corresponding element in the (x-1)-th row is 1, plus the number of columns where the element in the 1st row is 0, but the corresponding element in the y-th row is 1. Alternatively, the aforementioned third quantity can be understood as the number of columns where the element in the y-th row is 1, but the corresponding element in the (x-1)-th row is 0, plus the number of columns where the element in the 1st row is 1, but the corresponding element in the y-th row is 0.

[0164] For example, the column index of the x-th row of the base matrix that is not 0 (or has a value of 1) is denoted as . The column index of the non-zero column in the y-th row of the base matrix is ​​denoted as . Represents the index set and index set The intersection, express The number of elements in the matrix. If U(x) = y, then it must satisfy... Where U(x) = y indicates that the x-th row of the core column of the interleaved LDPC matrix is ​​the y-th row of the core column of the uninterleaved LDPC matrix, and vice versa. That is, row interleaving is only performed on the x-th and y-th rows corresponding to the core columns of the LDPC matrix. u can be determined by the LDPC matrix; for example, u for BG2 can be set to 3. u represents the third threshold. Furthermore, u can have different values ​​for different rows x, for example, in BG2...

[0165] In another possible design, the LDPC matrix is ​​an exponential matrix. The third quantity mentioned above can be understood as the number of columns where the element in the y-th row has a value of -1, but the corresponding element in the (x-1)-th row has a value other than -1, plus the number of columns where the element in the 1st row has a value of -1, but the corresponding element in the y-th row has a value other than -1. Alternatively, the third quantity mentioned above can be understood as the number of columns where the element in the y-th row has a value other than -1, but the corresponding element in the (x-1)-th row has a value of -1, plus the number of columns where the element in the 1st row has a value other than -1, but the corresponding element in the y-th row has a value other than -1.

[0166] Explanation of Rule 4: The difference between the number of elements in the x-th row of the second LDPC matrix that take the third value and the number of elements in the y-th row that take the third value is within a second range, where the second range can be [c, d]. That is, the difference between the number of elements in the x-th row that take the third value and the number of elements in the y-th row that take the third value can be greater than or equal to c and less than or equal to d, where c and d can be opposite numbers or any two real numbers. This application does not limit this.

[0167] In one possible design, the LDPC matrix is ​​the base matrix. For example, the third value can be 1, and the fourth rule can be that the difference between the number of 1s in the x-th row and the number of 1s in the y-th row of the base matrix is ​​within a second range. Alternatively, the third value can be 0, and the fourth rule can be that the difference between the number of 0s in the x-th row and the number of 0s in the y-th row of the base matrix is ​​within a second range.

[0168] For example, as shown in Figure 7, x = 7, y = 15, assuming the third value is 1, the number of 1s in the 15th row is 5, the number of 1s in the 7th row is 6, assuming the second range is [-1, 1], the number of 1s in the 15th row and the number of 1s in the 7th row are in the second range, then the 7th and 15th rows of the core column can interweave.

[0169] In another possible design, the LDPC matrix is ​​an exponential matrix. For example, the third value can be non--1, and the fourth rule can be that the difference between the number of non--1 elements in the x-th row and the number of non--1 elements in the y-th row is within a second range. Alternatively, the third value can be -1, and the fourth rule can be that the difference between the number of -1 elements in the x-th row and the number of -1 elements in the y-th row is within a second range.

[0170] Optionally, one possible scenario for Rule 4 above is that the number of elements in row x that take the third value is the same as the number of elements in row y that take the third value. In other words, the second range is 0.

[0171] In one possible design, the LDPC matrix is ​​the base matrix. For example, the third value can be 1, and rule four can be that the number of 1s in the x-th row of the base matrix is ​​the same as the number of 1s in the y-th row. Alternatively, the third value can be 0, and rule four can be that the number of 0s in the x-th row of the base matrix is ​​the same as the number of 0s in the y-th row.

[0172] For example, as shown in Figure 7, x = 7, y = 15, assuming the third value is 1, the number of 1s in the 15th row is 5, and the number of 1s in the 7th row is 6, then the 15th row and the 7th row of the basis matrix do not intertwine.

[0173] In another possible design, the LDPC matrix is ​​an exponential matrix. For example, the third value can be non--1, and rule four can be that the number of non--1 elements in the x-th row of the exponential matrix is ​​the same as the number of non--1 elements in the y-th row. Again, for example, the third value can be -1, and rule four can be that the number of -1 elements in the x-th row of the exponential matrix is ​​the same as the number of -1 elements in the y-th row.

[0174] By limiting the number of third values ​​in rows x and y to be the same, it is beneficial to ensure that there is basically no impact on decoding performance. For example, if the number of 1s in rows x and y is the same, it is beneficial to ensure that the decoding complexity will not increase after interleaving.

[0175] Optionally, the difference between the number of elements in the x-th row that take the third value and the number of elements in the y-th row that take the third value is within a second range, including: the second LDPC matrix is ​​composed of p sub-blocks, each of the p sub-blocks corresponds to a second range, the elements in the x-th row belong to the second sub-block among the p sub-blocks, the difference between the number of elements in the x-th row that take the third value and the number of elements in the y-th row that take the third value is within the second range corresponding to the second sub-block, and k is an integer greater than 0.

[0176] One possible design is that the second LDPC matrix consists of p sub-blocks, which are obtained by dividing the columns of the second LDPC matrix. In other words, based on the division of the columns of the second LDPC matrix, p groups are obtained, and each of the p groups corresponds to a second range.

[0177] For example, the column indices of the basis matrix are divided into p groups, denoted as R1, R2, ..., R... p ,remember R represents the x-th row of the basis matrix. t The number of non-zero elements in the columns contained in the group. R represents the y-th row of the basis matrix. t The number of non-zero elements in the columns contained in the group, t∈[1,p], rule four is [-m t ,m t ] is R t The second range corresponding to the group, where m t It can be based on the basis matrix and R1, R2, ..., R p It should be understood that the second range is merely an example, and the upper and lower limits of the second range can also be any two real numbers, which is not limited in this application.

[0178] For example, if the LDPC matrix is ​​a base matrix with 52 columns and column indices from 1 to 52, the columns can be divided into two groups: R1 = [1, 2, ..., 14], R2 = [15, 16, ..., 52], m1 = 2, m2 = 0. That is, the second range corresponding to group R1 is [-2, 2], and the second range corresponding to group R2 is 0. In other words, the number of elements with the third value in the column of group R2 in row x of the base matrix must be the same as the number of elements with the third value in the column of group R1 in row y of the base matrix.

[0179] Another possible design is that the LDPC matrix consists of p sub-blocks, which are obtained by dividing the rows of the LDPC matrix. In other words, based on the division of the rows of the LDPC matrix, p groups are obtained, and each of the p groups corresponds to a second range.

[0180] For example, the row indices of the basis matrix are divided into p groups, denoted as L1, L2, ..., L p Rule four is -m g ≤d x -d y ≤m g , where x∈L g d x d represents the number of non-zero elements in the x-th row of the basis matrix. y This represents the number of non-zero elements in the y-th row of the basis matrix, [-m g,m g ] is L g The second range corresponding to the group, m g It can be based on the basis matrix and L1, L2, ..., L p It should be understood that the second range is merely an example, and the upper and lower limits of the second range can also be any two real numbers, which is not limited in this application.

[0181] For example, the LDPC matrix is ​​a base matrix with 42 rows. The row indices are divided into three groups: L1 = [1,2,3,4], L2 = [5,6,7], and L3 = [8,9,…,42], with m1 = 2, m2 = 0, and m3 = 1. That is, the second range corresponding to group L1 is [-2,2], the second range corresponding to group L2 is 0 (meaning the number of elements in the x-th row of the base matrix that have the third value must be the same as the number of elements in the y-th row of the base matrix that have the third value), and the second range corresponding to group L3 is [-1,1].

[0182] Another possible design is that the LDPC matrix consists of p sub-blocks, which are obtained by dividing the rows and columns of the LDPC matrix, with each sub-block corresponding to a second range.

[0183] For example, the column indices of the basis matrix are divided into k groups, denoted as R1, R2, ..., R... k The row indices of the basis matrix are divided into h groups, denoted as L1, L2, ..., L h The rows contained in L1 and the columns contained in R1 can be considered as one sub-block, the rows contained in L1 and the columns contained in R2 can be considered as another sub-block, and so on. These will not be listed individually here. R represents the x-th row of the basis matrix. t The number of non-zero elements in the group, t∈[1,k]. If x∈L g If U(x) = y, then we have m t,g It can be based on the basis matrix, R1, R2, ..., R k and L1, L2, ..., L h It's confirmed.

[0184] For example, if the base matrix has 42 rows and 52 columns, the column indices can be divided into two groups: R1 = [1, 2, ..., 14] and R2 = [15, 16, ..., 52], and the row indices can be divided into three groups: L1 = [1, 2, 3, 4], L2 = [5, 6, 7], and L3 = [8, 9, ..., 42]. There are m... 1,1 =0,m 1,2 =1,m 1,3 =0,m 2,1 =0,m 2,1=0,m 2,3 =0.

[0185] Optionally, the columns in the second sub-block are the punched columns in the second LDPC matrix. That is, the columns in one of the p sub-blocks of the LDPC matrix are the punched columns in the LDPC matrix.

[0186] For example, the column indices of the basis matrix are divided into k groups, denoted as R1, R2, ..., R... k For example, k=3, R1 is the punched column, R2 is the column containing the variable node with degree 1 (that is, the column corresponding to region E in Figure 2, i.e., the column other than the core column in the basis matrix), and R3 is the remaining column. The row indices of the basis matrix are divided into h groups, denoted as L1, L2, ..., L... h .remember R represents the x-th row of the basis matrix. t The number of non-zero elements in the group, t∈[1,k]. If x∈L g If U(x) = y, then we have m t,g It can be based on the basis matrix, R1, R2, ..., R k and L1, L2, ..., L h It is definite. For example, if the base matrix has 42 rows and 52 columns, the column indices can be divided into three groups: R1 = [1,2], R2 = [3,4,…,14], R3 = [15,16,…,52], and the row indices can be divided into two groups: L1 = [1,2,…,7], L3 = [8,9,…,42], with m... 1,1 =0,m 1,2 =0,m 2,1 =1,m 2,2 =0,m 3,1 =0,m 3,2 =0.

[0187] As an example, R1 = [1,2], R2 = [3,4,…,14], R3 = [15,16,…,52], L1 = [1,2,3,4], L2 = [5,6,7], L3 = [8,9,…,42], when x∈L1, Let represent the number of non-zero elements in the columns of the x-th row Rt group of the basis matrix, where t∈[1,3]. When x∈L2, When x∈L3 And satisfy in, This represents the column index of the x-th row of the base matrix that is not 0 (or has a value of 1). This represents the column index of the y-th row of the base matrix that is not zero. Represents the index set and index set The intersection, express If the number of elements in the sequence is determined, then the interleaved sequence is {1, 2, 4, 3, 5, 6, 10, 7, 14, 8, 9, 12, 13, 11, 17, 19, 15, 24, 18, 20, 21, 22, 25, 16, 29, 35, 31, 28, 36, 37, 27, 39, 40, 41, 33, 23, 26, 34, 42, 30, 38, 32}.

[0188] Figure 8 is a schematic diagram comparing decoding delays provided in an embodiment of this application.

[0189] Figure 8 shows the time delay of reverse decoding, sequential decoding, scheduled decoding, and decoding based on the method provided in this application at different code rates. It can be seen that the decoding based on the method provided in this application has the lowest time delay.

[0190] The methods provided in the embodiments of this application have been described in detail above with reference to the accompanying drawings. The apparatus provided in the embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0191] Figure 9 is a schematic block diagram of a communication device 900 provided in an embodiment of this application.

[0192] As shown in Figure 9, the communication device 900 includes a processing module 910 and a transceiver module 920.

[0193] The transceiver module 920 can implement corresponding communication functions and can also be referred to as an input / output interface or communication unit. The processing module 910 can be used to perform processing operations. It should be understood that if the device 900 is a component configured in an access network device or terminal, such as a chip, the transceiver module 920 can be an input / output interface.

[0194] Optionally, the transceiver module 920 may include a transmitting module and a receiving module. The transmitting module is used to perform the transmitting / output operations of the first communication device / second communication device in FIG6, and the receiving module is used to perform the receiving / input operations of the first communication device / second communication device in FIG6.

[0195] It should be understood that when the device 900 is a component configured in the first communication device / second communication device, such as a chip, the transmitting module can be an output interface, and the transmitting operation involved in the embodiments of this application can be performed by the output interface; the receiving module can be an input interface, and the receiving operation involved in the embodiments of this application can be performed by the input interface.

[0196] Optionally, the device 900 may further include a storage module for storing instructions and / or data, and the processing module 910 may read the instructions and / or data from the storage module to enable the device to implement the method embodiment shown in FIG6.

[0197] In one possible design, the device 900 may include a module for implementing any function or operation of the first communication device in the method embodiment shown in FIG6, or the device 900 may include a module for implementing any function or operation of the second communication device in the method embodiment shown in FIG6, which may be implemented wholly or partially by software, hardware, firmware or any combination thereof.

[0198] When device 900 is used to implement the function of the first communication device in the method embodiment shown in FIG6, processing module 910 is used to encode information bits based on the first LDPC matrix to obtain encoded bits. The first LDPC matrix is ​​obtained by row interleaving the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix. Transceiver module 920 is used to output the above encoded bits.

[0199] When the above-mentioned device 900 can be used to implement the function of the second communication device in the method embodiment shown in FIG6, the transceiver module 920 is used to input the bit to be decoded; the processing module 910 is used to decode the bit to be decoded based on the first LDPC matrix to obtain information bits. The first LDPC matrix is ​​obtained by row interleaving the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix.

[0200] Optionally, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: when the code rate is greater than or equal to a first threshold, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix; and / or, when the number of rows of the second LDPC matrix is ​​less than or equal to a second threshold, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix.

[0201] Optionally, the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: the first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix based on an interleaving sequence, the interleaving sequence is determined according to the code rate and / or the number of rows of the second LDPC matrix, each element in the interleaving sequence is used to indicate the row of the first region of the second LDPC matrix corresponding to each row of the first region of the first LDPC matrix, one code rate interval corresponds to one interleaving sequence, and / or, one row number interval of the second LDPC matrix corresponds to one interleaving sequence.

[0202] Optionally, the i-th row and j-th row of the first region in the second LDPC matrix are intertwined if one or more of the following conditions are met: a first quantity is less than or equal to a second quantity (referred to as Rule 1); the first quantity is the number of columns in the same column of the first region where the element in the j-th row has a first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has a second value; the second quantity is the number of columns in the same column of the first region where the element in the i-th row has a first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has a second value; wherein, when i = 1, the (i-1)-th row of the first region is located above the first row of the first region in the first LDPC matrix; or, the difference between the number of elements in the i-th row of the first region that have a third value and the number of elements in the j-th row that have a third value is within a first range (referred to as Rule 2).

[0203] Optionally, the difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value is within a first range, including: the first region is composed of k sub-blocks, each of the k sub-blocks corresponds to a first range, the i-th row of the first region belongs to the first sub-block among the k sub-blocks, the difference between the number of elements in the i-th row that have the third value and the number of elements in the j-th row that have the third value is within a first range corresponding to the first sub-block, and k is an integer greater than 0.

[0204] Optionally, the number of elements in the i-th row that take the third value is the same as the number of elements in the j-th row that take the third value.

[0205] Optionally, the columns in the first sub-block are the punched columns in the first region.

[0206] Optionally, if the x-th and y-th rows of the second LDPC matrix satisfy one or more of the following conditions, the elements belonging to the first region in the x-th and y-th rows of the second LDPC matrix are row-interleaved: the third quantity is less than or equal to the third threshold (denoted as rule three), the third quantity is the sum of the number of columns in the same column where the elements in the y-th row have the first value but the corresponding elements in the (x-1)-th row of the first LDPC matrix have the second value, and the number of columns in the same column where the elements in the 1-th row of the first LDPC matrix have the first value but the elements in the y-th row of the second LDPC matrix have the second value; or, the difference between the number of elements in the x-th row having the third value and the number of elements in the y-th row having the third value is within the second range (denoted as rule four).

[0207] Optionally, the difference between the number of elements in the x-th row that take the third value and the number of elements in the y-th row that take the third value is within a second range, including: the second LDPC matrix is ​​composed of p sub-blocks, each of the p sub-blocks corresponds to a second range, the elements in the x-th row belong to the second sub-block among the p sub-blocks, the difference between the number of elements in the x-th row that take the third value and the number of elements in the y-th row that take the third value is within the second range corresponding to the second sub-block, and k is an integer greater than 0.

[0208] Optionally, the number of elements in row x that are the third value is the same as the number of elements in row y that are the third value.

[0209] Optionally, the columns in the second sub-block are the punched columns in the second LDPC matrix.

[0210] Optionally, the first region is the region corresponding to the core column in the second LDPC matrix.

[0211] A more detailed description of the above-mentioned processing module 910 and transceiver module 920 can be obtained directly from the relevant description in the method embodiment shown in Figure 6, and will not be repeated here.

[0212] It should be noted that the transceiver module can also be called a transceiver unit, transceiver, transceiver machine, or transceiver device, etc. The processing module can also be called a processor, processing board, processing unit, or processing device, etc. Optionally, the transceiver module is used to perform the sending and receiving operations on the terminal device or network device side in the above method. The device in the communication module used to implement the receiving function can be considered as the receiving module, and the device in the communication module used to implement the sending function can be considered as the sending module; that is, the transceiver module includes both a receiving module and a sending module.

[0213] In another possible design, the aforementioned transceiver module and / or processing module can be implemented using virtual modules. For example, the processing module can be implemented using software functional modules or virtual devices, and the transceiver module can also be implemented using software functional modules or virtual devices. In another possible design, the processing module or transceiver module can also be implemented using physical devices. For example, if the device is implemented using a chip / chip circuit, the transceiver module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or integrated circuit.

[0214] It should be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0215] Figure 10 is another schematic block diagram of the communication device 1000 provided in an embodiment of this application. The device 1000 can be a chip system, or it can be a device configured with a chip system to implement the above-described method embodiments. In this embodiment, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0216] As shown in FIG10, the device 1000 may include a processor 1010, which can be used to execute computer programs or instructions in memory to implement the steps executed by the first communication device or the second communication device in the method embodiment shown in FIG6.

[0217] Optionally, the device 1000 further includes a communication interface 1020. The communication interface 1020 can be used to communicate with other devices via a transmission medium, thereby enabling the device 1000 to communicate with other devices. The communication interface 1020 may be, for example, a transceiver, interface, bus, circuit, or a device capable of transmitting and receiving functions. The processor 1010 can use the communication interface 1020 to input and output data and to implement the method described in the embodiment shown in FIG6. Specifically, the device 1000 can be used to implement the functions of the first or second communication device in the above method embodiments.

[0218] When the device 1000 is used to implement the method shown in FIG6, the processor 1010 is used to implement the function of the processing module 910, and the communication interface 1020 is used to implement the function of the transceiver module 920.

[0219] Optionally, the device 1000 further includes at least one memory 1030 for storing program instructions and / or data. The memory 1030 is coupled to the processor 1010. The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1010 may operate in conjunction with the memory 1030. The processor 1010 may execute program instructions stored in the memory 1030. At least one of the at least one memory may be included in the processor.

[0220] It should be understood that the coupling in the embodiments of this application is an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information interaction between devices, units, or modules. The processor 1010 may operate in conjunction with the memory 1030. The embodiments of this application do not limit the specific connection medium between the processor 1010, communication interface 1020, and memory 1030. In Figure 10, the processor 1010, communication interface 1020, and memory 1030 are connected via a bus 1040. The bus 1040 is represented by a thick line in Figure 10. The connection methods between other components are only illustrative and not intended to be limiting. The bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 10, but this does not indicate that there is only one bus or one type of bus.

[0221] It should be understood that when the aforementioned communication device 1000 is a chip applied to the first communication device, the chip implements the functions of the first communication device in the above method embodiments. The chip of the first communication device receives signals from other modules (such as radio frequency modules or antennas) in the first communication device, and these signals may be sent to the first communication device by the second communication device; or, the chip of the first communication device sends signals to other modules (such as radio frequency modules or antennas) in the first communication device, and these signals may be sent to the second communication device by the first communication device.

[0222] When the aforementioned communication device 1000 is a chip applied to the second communication device, the chip implements the functions of the second communication device in the above method embodiments. The chip of the second communication device receives signals from other modules (such as radio frequency modules or antennas) in the first communication device, and these signals may be sent from the first communication device to the second communication device; or, the chip of the second communication device sends signals to other modules (such as radio frequency modules or antennas) in the second communication device, and these signals may be sent from the second communication device to the first communication device.

[0223] It should be noted that when the communication device 1000 is a first communication device or a second communication device, the communication interface 1020 can be a transceiver, specifically including a transmitter and a receiver. The transmitter is used to send signals, and the receiver is used to receive signals. When the communication device 1000 is a chip applied to the first or second communication device, the communication interface 1020 can be an input / output circuit, a bus, a module, a pin, or other types of communication interface input / output circuit. The input circuit in the input / output circuit can be used for receiving, and the output interface can be used for sending.

[0224] This application also provides a computer program product, which includes a computer program (also referred to as code or instructions) that, when run, can implement the method described in the embodiment shown in FIG6.

[0225] This application also provides a computer-readable storage medium storing a computer program (also referred to as code or instructions). When the computer program is run, it can implement the method described in the embodiment shown in FIG6.

[0226] It should be understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0227] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0228] The terms "unit," "module," etc., used in this specification can be used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. In the embodiments of this application, "unit" and "module" have the same meaning and can be used interchangeably.

[0229] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. In the several embodiments provided in this application, it should be understood that the disclosed apparatus, devices, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0230] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0231] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0232] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs, DVDs), or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0233] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the technology, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

Claims

1. An encoding method, characterized in that, include: Information bits are encoded based on a first low-density parity-check code (LDPC) matrix to obtain encoded bits. The first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix. Output the encoded bits.

2. A decoding method, characterized in that, include: Input the bits to be decoded; Based on the first low-density parity-check code (LDPC) matrix, the bits to be decoded are decoded to obtain information bits. The first LDPC matrix is ​​obtained by row interleaving the first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix.

3. The method as described in claim 1 or 2, characterized in that, The first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: When the code rate is greater than or equal to a first threshold, the first LDPC matrix is ​​obtained by row interleaving a first region in the second LDPC matrix; and / or, If the number of rows in the second LDPC matrix is ​​less than or equal to the second threshold, the first LDPC matrix is ​​obtained by row interleaving of the first region in the second LDPC matrix.

4. The method as described in claim 1 or 2, characterized in that, The first LDPC matrix is ​​obtained by row interleaving a first region of the second LDPC matrix according to the code rate and / or the number of rows of the second LDPC matrix, including: The first LDPC matrix is ​​obtained by row interleaving of the first region in the second LDPC matrix based on the interleaving sequence. The interleaving sequence is determined according to the code rate and / or the number of rows in the second LDPC matrix. Each element in the interleaving sequence is used to indicate the row of the first region in the second LDPC matrix corresponding to each row of the first region in the first LDPC matrix. One code rate interval corresponds to one interleaving sequence, and / or, one row number interval of the second LDPC matrix corresponds to one interleaving sequence.

5. The method according to any one of claims 1 to 4, characterized in that, The i-th row and the j-th row of the first region in the second LDPC matrix interweave if one or more of the following conditions are met: The first quantity is less than or equal to the second quantity. The first quantity is the number of columns in the first region where the element in the j-th row has the first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has the second value. The second quantity is the number of columns in the first region where the element in the i-th row has the first value, but the corresponding element in the (i-1)-th row of the first region in the first LDPC matrix has the second value. Where, when i = 1, the (i-1)-th row of the first region is located in the row above the first row of the first region in the first LDPC matrix; or... The difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value is within a first range.

6. The method as described in claim 5, characterized in that, The difference between the number of elements in the i-th row of the first region that have the third value and the number of elements in the j-th row that have the third value is within a first range, including: The first region consists of k sub-blocks, each of the k sub-blocks corresponds to a first range, the i-th row of the first region belongs to the first sub-block among the k sub-blocks, the difference between the number of elements in the i-th row that take the third value and the number of elements in the j-th row that take the third value is within the first range corresponding to the first sub-block, and k is an integer greater than 0.

7. The method as described in claim 6, characterized in that, The number of elements in the i-th row that take the third value is the same as the number of elements in the j-th row that take the third value.

8. The method as described in claim 7, characterized in that, The columns in the first sub-block are the punched columns in the first region.

9. The method according to any one of claims 1 to 4, characterized in that, If one or more of the following conditions are met in the x-th and y-th rows of the second LDPC matrix, the elements belonging to the first region in the x-th and y-th rows of the second LDPC matrix are row-interleaved: The third quantity is less than or equal to the third threshold, wherein the third quantity is the sum of the number of columns in the same column where the element in the y-th row has the first value, but the corresponding element in the (x-1)-th row of the first LDPC matrix has the second value, and the number of columns in the same column where the element in the 1-th row of the first LDPC matrix has the first value, but the element in the y-th row of the second LDPC matrix has the second value; or, The difference between the number of elements in row x that take the third value and the number of elements in row y that take the third value is within the second range.

10. The method as described in claim 9, characterized in that, The difference between the number of elements in row x that are the third value and the number of elements in row y that are the third value is within a second range, including: The second LDPC matrix consists of p sub-blocks, each of which corresponds to a second range. The element in the x-th row belongs to the second sub-block among the p sub-blocks. The difference between the number of elements in the x-th row that take the third value and the number of elements in the y-th row that take the third value is within the second range corresponding to the second sub-block. k is an integer greater than 0.

11. The method as described in claim 10, characterized in that, The number of elements in the x-th row that take the third value is the same as the number of elements in the y-th row that take the third value.

12. The method as described in claim 11, characterized in that, The columns in the second sub-block are the punched columns in the second LDPC matrix.

13. The method according to any one of claims 1 to 12, characterized in that, The first region is the region corresponding to the core column in the second LDPC matrix.

14. A communications device, characterized by include: A module for performing the method as described in any one of claims 1 to 13.

15. A communication device, characterized in that, include: A processor, when invoked a computer program in memory, causes the method as described in any one of claims 1 to 13 to be executed.

16. A computer readable storage medium characterized by: The storage medium stores a computer program or instructions, and when the computer program or instructions are executed by a computer, the method as described in any one of claims 1 to 13 is implemented.

17. A computer program product, comprising instructions therein, wherein the computer program product is characterised in that, When the instructions are executed on a computer, the method as described in any one of claims 1 to 13 is implemented.

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