Communication method and communication apparatus

Abstract

A communication method and a communication apparatus. The method comprises: coding information bit sequences to be coded to obtain m coded bit sequences; performing a first operation on the m coded bit sequences to obtain m first bit sequences, m being a positive integer greater than 1; mapping the m first bit sequences to obtain a first symbol sequence; and sending the first symbol sequence. The m first bit sequences that are mapped to obtain the first symbol sequence are obtained by performing the first operation on the m coded bit sequences, and the first operation comprises performing an exclusive OR operation on a first coded bit sequence and a second coded bit sequence among the m coded bit sequences. According to the method, the m first bit sequences obtained by the first operation are mapped to obtain the first symbol sequence, thereby reducing modification to existing protocols without changing a protocol-predefined mapping mode while ensuring a modulation effect.

Description

Communication methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202510127480.6, filed on January 27, 2025, entitled "Communication Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to a communication method and a communication device. Background Technology

[0003] In multi-level coding (MLC), a sequence of information bits to be encoded is divided into m layers, and the information bit sequence in each layer is encoded independently. Currently, MLC uses natural mapping for modulation to improve transmission performance. How to improve modulation performance while minimizing modifications to existing protocols is a current research hotspot. Summary of the Invention

[0004] This application provides a communication method that, in the modulation method of a multi-layer coding (MLC) scenario, can ensure the modulation effect while reducing modifications to existing protocols.

[0005] In a first aspect, a communication method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device is also referred to as an encoding device.

[0006] The method includes: encoding the information bit sequence to be encoded to obtain m encoded bit sequences, where m is a positive integer greater than 1; performing a first operation on the m encoded bit sequences to obtain m first bit sequences; mapping the m first bit sequences to obtain a first symbol sequence; and sending the first symbol sequence, wherein the information bit sequence to be encoded includes m information bit sequences, the m information bit sequences are used to determine the m encoded bit sequences, the m encoded bit sequences include a first encoded bit sequence and a second encoded bit sequence, and the first operation includes performing an XOR operation on the first encoded bit sequence and the second encoded bit sequence.

[0007] According to the method provided in this application, the first symbol sequence is obtained by mapping m first bit sequences. These m first bit sequences are obtained by performing a first operation on m coded bit sequences. This first operation includes an XOR operation on the first and second coded bit sequences among the m coded bit sequences. This method maps the m first bit sequences after the first operation to obtain the first symbol sequence, thereby achieving the goal of maintaining the modulation effect without changing the predefined mapping method of the protocol, thus reducing implementation complexity.

[0008] In conjunction with the first aspect, in some possible implementations, performing a first operation on m encoded bit sequences to obtain m first bit sequences includes: performing a first operation on a second encoded bit sequence to obtain a second bit sequence, wherein the m first bit sequences include the second bit sequence, and the second bit sequence satisfies: in, Seq1 represents the second encoded bit sequence, and Seq0 represents the first encoded bit sequence.

[0009] For example, the second coded bit sequence can be viewed as the second coded bit sequence among m coded bit sequences; or, the second coded bit sequence is located in the second layer among m coded bit sequences.

[0010] In conjunction with the first aspect, in some possible implementations, the m encoded bit sequences also include the a-th encoded bit sequence, where a is a positive integer greater than 2. The first operation is performed on the a-th encoded bit sequence to obtain the a-th bit sequence. The m first bit sequences include the a-th bit sequence. The first operation includes performing an XOR operation on the encoded bit sequences from the first encoded bit sequence to the a-th encoded bit sequence.

[0011] In conjunction with the first aspect, in some possible implementations, the a-th bit sequence satisfies: in, Let Seq represent the a-th bit sequence. a Seq represents the sequence of the a-th encoded bits. a-2 This represents the (a-2)th encoded bit sequence.

[0012] In conjunction with the first aspect, in some possible implementations, the m encoded bit sequences also include a third encoded bit sequence. Performing a first operation on the m encoded bit sequences to obtain m first bit sequences includes: performing a first operation on the third encoded bit sequence to obtain a third bit sequence. The m first bit sequences include the third bit sequence. The first operation includes performing an XOR operation on the first, second, and third encoded bit sequences.

[0013] For example, m can be greater than or equal to 3, where the m encoded bit sequences also include a third encoded bit sequence. This third bit sequence is obtained by processing the third encoded bit sequence through a first operation. This first operation includes processing the first encoded bit sequence. The second and third encoded bit sequences are XORed.

[0014] In conjunction with the first aspect, in some possible implementations, the third bit sequence satisfies: in, Seq1 represents the third bit sequence, Seq2 represents the third encoded bit sequence, Seq1 represents the second encoded bit sequence, and Seq0 represents the first encoded bit sequence.

[0015] In conjunction with the first aspect, in some possible implementations, the m encoded bit sequences also include a third encoded bit sequence and a fourth encoded bit sequence. A first operation is performed on the m encoded bit sequences to obtain m first bit sequences, including: performing a first operation on the fourth encoded bit sequence to obtain a fourth bit sequence. The m first bit sequences include the fourth bit sequence. The first operation includes performing an XOR operation on the first, second, third, and fourth encoded bit sequences.

[0016] For example, m takes a value greater than or equal to 4, where the m encoded bit sequences also include a third encoded bit sequence and a fourth encoded bit sequence. The m first bit sequences include the third bit sequence and the fourth bit sequence. The third bit sequence is obtained by performing the first operation on the third encoded bit sequence, and the fourth bit sequence is obtained by performing the first operation on the fourth encoded bit sequence.

[0017] In conjunction with the first aspect, in some possible implementations, the fourth bit sequence satisfies: in, Seq3 represents the fourth encoded bit sequence, Seq2 represents the third encoded bit sequence, Seq1 represents the second encoded bit sequence, and Seq0 represents the first encoded bit sequence.

[0018] It should be understood that, based on the above introduction, each of the m encoded bit sequences undergoes a first operation to obtain m first bit sequences. For example, the m encoded bit sequences include the 1st encoded bit sequence, the 2nd encoded bit sequence, ..., the mth encoded bit sequence, where the first operation corresponding to each encoded bit sequence from the 2nd to the mth encoded bit sequence is obtained by performing an XOR operation between the current encoded bit sequence and one or more encoded bit sequences preceding it.

[0019] In conjunction with the first aspect, in some possible implementations, a first operation is performed on m coded bit sequences to obtain m first bit sequences, including: performing a second operation on each of the m coded bit sequences to obtain m fifth bit sequences, wherein the second operation includes one or more of the following: channel coding, rate matching, bit interleaving, or bit scrambling; and performing the first operation on the m fifth bit sequences to obtain m first bit sequences.

[0020] For example, the second operation is performed before the first operation is performed on each of the m encoded bit sequences, thereby improving encoding performance.

[0021] In conjunction with the first aspect, in some possible implementations, the m values ​​are related to the modulation order.

[0022] Secondly, a communication device is provided, which has the function of implementing the method of the first aspect or any possible implementation thereof. This function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0023] Thirdly, a communication device is provided, including a processor and a memory. Optionally, it may also include a transceiver. The memory stores a computer program, the processor invokes and runs the computer program stored in the memory, and controls the transceiver to send and receive signals, so that the communication device performs the methods as described in the first aspect or any possible implementation thereof.

[0024] Fourthly, a communication device is provided, including a processor and a communication interface, the communication interface being configured to receive data and / or information and transmit the received data and / or information to the processor, the processor processing the data and / or information, and the communication interface being further configured to output the processed data and / or information so that a method as described in the first aspect, or any possible implementation thereof, is executed.

[0025] Fifthly, a computer-readable storage medium is provided that stores computer instructions that, when executed on a computer, cause a method as described in the first aspect or any possible implementation thereof to be performed.

[0026] Sixthly, a computer program product is provided, the computer program product including computer program code, which, when run on a computer, causes a method as described in the first aspect, or any possible implementation of any aspect of the first aspect, to be executed. Attached Figure Description

[0027] Figure 1 is a schematic diagram of the system architecture of the communication system applicable to the technical solution of this application.

[0028] Figure 2 is a schematic diagram of a modulated signal.

[0029] Figure 3 is a schematic diagram of the m-order modulation MLC process.

[0030] Figure 4 is a simulation diagram of serial demodulation and parallel demodulation.

[0031] Figure 5 is a schematic flowchart of a communication method provided in an embodiment of this application.

[0032] Figure 6 is a schematic diagram of an MLC with m=3 provided in an embodiment of this application.

[0033] Figure 7 is a schematic block diagram of the communication device 700 provided in this application.

[0034] Figure 8 is a schematic structural diagram of the communication device 800 provided in this application. Detailed Implementation

[0035] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0036] The technical solutions of this application can be applied to various communication systems, including but not limited to: satellite communication systems, the 5th generation (5G) system, Long Term Evolution (LTE) system (LTE Frequency Division Duplex (FDD) system, LTE Time Division Duplex (TDD) system), etc. The technical solutions provided in this application can also be applied to future communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0037] The technical solutions of this application embodiment can also be applied to three major application scenarios of narrowband Internet of Things (NB-IoT), Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access 2000 (CDMA2000), Time Division-Synchronization Code Division Multiple Access (TD-SCDMA), and next-generation 5G mobile communication systems: enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), and massive machine-type communications (eMTC).

[0038] Figure 1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of this application. The communication system may include one or more network devices and one or more terminal devices.

[0039] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal devices in the embodiments of this application can be mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, personal digital assistants, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and vehicle-mounted mobile terminals, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity, providing sidelink signals between UEs in V2X or D2D, etc.

[0040] In this embodiment, the device for implementing the terminal's functions can be the terminal itself, or it can be any device capable of supporting the terminal in implementing those functions, such as a chip system or a chip. This device can be installed in the terminal. In this embodiment, the chip system can consist of chips, or it can include chips and other discrete components.

[0041] For example, a network device can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5th generation (5G) communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (Wi-Fi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB, or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices in cloud radio access network (CRAN) scenarios. Furthermore, base stations may be macro base stations, micro base stations, relay nodes, donor nodes, or combinations thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future networks, or equipment performing base station functions in future communication systems. Base stations can support networks with the same or different access technologies, without limitation.

[0042] In this embodiment, the means for implementing the function of the network device can be the network device itself, or it can be a means that enables the network device to implement the function, such as a chip system or a chip, which can be installed in the network device. In this embodiment, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0043] It should be understood that the rate matching method provided in this application can be considered a channel coding scheme, which can be used in dedicated network equipment or general-purpose equipment. It can be applied to various network equipment (e.g., base station equipment) as described above, and also to various terminal equipment as described above. Specifically, this channel coding scheme is mainly implemented through the channel coding unit in these devices.

[0044] The methods provided in the embodiments of this application can also be implemented by application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or by software (e.g., program code in memory), without limitation.

[0045] Next, to facilitate understanding of the embodiments provided in this application, the terminology involved in this application will be briefly introduced below:

[0046] 1. Coding and Modulation

[0047] Coding and modulation are key technologies for improving the spectral efficiency of digital communication systems. Higher-order modulation offers significant gains in future communications and is a promising alternative technology for wireless communication. Furthermore, unlike higher-order modulation in fiber optic communication, the code rate configuration used in wireless communication is not fixed; therefore, a feasible and standardized higher-order coding and modulation scheme is needed.

[0048] In an additive white Gaussian noise (AWGN) channel, the well-known Shannon formula indicates the maximum amount of information that can be transmitted per channel use, i.e., the channel capacity, given a signal-to-noise ratio (SNR): C = 0.5 * log2(1 + SNR) (1)

[0049] The optimal input distribution for achieving channel capacity is the Gaussian distribution. However, the Gaussian distribution is a continuous distribution, while in digital communication systems, the input signals are discrete signals.

[0050] Taking a binary discrete-input digital communication system under a one-dimensional real AWGN channel as an example, if BPSK (equivalent to 2-pulse amplitude modulation (PAM)) is used, the modulator will convert one bit v i (v i(Taking a value of 0 or 1) modulated into a transmission symbol s i =1-2*v i (s i The value is +1 or -1). Even if the SNR is very high, the channel capacity in formula (1) cannot be achieved because the message transmitted each time the channel is used is only log2(2) = 1 bit. If 4-PAM modulation is used, the modulator will map log-2(4) = 2 bits into a transmission symbol. For example, in the 4PAM example in Figure 1: (v1 = 0, v2 = 0) is mapped to s1 = -3, (v1 = 1, v2 = 0) is mapped to s2 = -1, (v1 = 1, v2 = 1) is mapped to s3 = +1, and (v1 = 0, v2 = 1) is mapped to s4 = +3. At this time, the information that can be transmitted for each symbol will not exceed log2(4) = 2 bits. By analogy, if M-PAM (M = 2 m If the modulation order m is m, the modulator will map m bits into a single transmitted symbol according to a specific labeling rule. Therefore, the maximum amount of information that can be transmitted per symbol is m bits. Thus, in discrete digital communication systems, the amount of information that can be transmitted per channel use (i.e., spectral efficiency) increases with the modulation order m.

[0051] The above process can be directly extended to a two-dimensional complex AWGN channel, that is, to extend the real PAM signal on a one-dimensional straight line to a complex quadrature amplitude modulation (QAM) signal on a two-dimensional plane. Figure 1 shows the correspondence between 4-PAM signals and 16-QAM signals (to ensure average transmission). After extending to a two-dimensional plane signal, the maximum number of bits that can be transmitted for each M^2-QAM symbol is 2*log2(M) bits.

[0052] Figure 2 is a schematic diagram of a modulated signal. In Figure 2, (1) is a 4-PAM signal and (2) is a 16-QAM signal. It can be seen that after being extended to a two-dimensional plane signal, each M2-QAM symbol can transmit a maximum of 2log2(M) bits of information.

[0053] 2. Multi-layer coding

[0054] MLC (Multi-Loop Coding) technology is a modulation technique that combines coding and modulation. MLC neither increases signal bandwidth nor reduces the actual data transmission rate, while improving the reliability of data transmission; therefore, MLC is also known as "high-efficiency bandwidth coding".

[0055] According to Shannon's channel capacity theorem, MLC technology achieves better bit error rate and throughput performance when the code rate of each component code in MLC equals the equivalent channel capacity of each channel. Therefore, the design focus of MLC technology lies in the appropriate selection of component code rates. Traditional linear block codes have relatively fixed code rates, generally offering only a finite number of options, making it difficult to match the block code rate with the equivalent channel capacity under different channel conditions. Unlike linear block codes, rate-free codes can theoretically generate any number of coded symbols from the same set of information for transmission, thus achieving continuous code rate adjustment. Clearly, compared to linear block codes, rate-free codes more easily achieve code rates that approximate the channel capacity, resulting in higher throughput and lower bit error rate.

[0056] It should be understood that MLC divides a string of modulation symbols into m layers according to the different capacities of the modulated bits in the symbol, and each layer is encoded independently.

[0057] Figure 3 is a schematic diagram of the MLC process for m-order modulation. The encoding in Figure 3 is illustrated using polar codes as an example. For instance, for an m-order modulation, the bit stream z to be transmitted is first transformed from serial to parallel, dividing it into m bit streams u1, u2, u3...u m Each bitstream corresponds to a bit channel under a higher-order modulation. Encoding is performed separately for this bit channel; that is, the codeword x1 output by the m-th encoder constitutes the m-th bit in the higher-order modulation symbol. The N modulation symbols generated by the modulator (Mod) are transmitted through the channel. The demodulator (Dem) uses the channel received sequence y to demodulate the soft value v1 required by the first polar decoder. Then, the polar decoder uses the soft value sequence v1 corresponding to the first stream to decode u1. To demodulate the soft value v2 corresponding to the second stream, the polar codeword x1 corresponding to u1 needs to be input into the demodulator. The demodulator uses y and x1 to demodulate the soft value sequence v2 corresponding to the second stream and inputs it into the second polar code decoder. The second polar code decoder uses this soft value sequence to decode u2. Then, the demodulator uses the codewords x2 and x1 corresponding to u2 and u1, as well as the channel received sequence y, to demodulate the soft value sequence v3 corresponding to the third stream. Similarly, demodulating the m-th stream requires the channel received sequence y and the codewords x1 to x1 of its preceding m-1 polar codes. m .

[0058] Therefore, it can be seen that the MLC uses serial demodulation, and this MLC requires m encoders and m decoders.

[0059] Demodulation refers to converting a modulation symbol into its corresponding bit sequence (e.g., v1, v2, v3...v). mThe demodulation process can be divided into serial demodulation and parallel demodulation.

[0060] The following example uses a 4-PAM symbol to illustrate the serial demodulation and parallel demodulation methods. Assume that a 4-PAM symbol s corresponds to two bits (v1, v2), and the decoder receives symbol y after s passes through the AWGN channel.

[0061] (1) Serial demodulation

[0062] To obtain the value of v1, we deduce the probability P(v1=0|y) of v1=0 and the probability P(v1=1|y) of v1=1 based on y, and determine the value of v1 according to the following formula (2):

[0063] in

[0064] akin,

[0065] Based on the 4-PAM example given in (1) of Figure 2 above, when calculating the probabilities of P(v1=0|y) and P(v1=1|y), S 00 =-3A,S 10 =-A,S 11 =+A,S 01 =+3A, in order to ensure the average transmit power E s =1, that is, 1 / 4*(|S 00 | 2 +|S 10 | 2 +|S 11 | 2 +|S 01 | 2 ) = 1, therefore The value of v1 can be obtained by using the above formula (2).

[0066] To obtain the value of v2, serial demodulation needs to calculate the probability P(v2=0|y,v1) of v2=0 given the value of v1 and the probability P(v2=1|y,v1) of v2=1. Then, the log-likelihood ratio of the above two probabilities is calculated, and the value of v2 is obtained according to formula (3):

[0067] If v1 = 0,

[0068] but

[0069] If v1 = 1:

[0070] but

[0071] Therefore, the probabilities of P(v2=0|y,v1) and P(v2=1|y,v1) can be calculated, and then v2 can be serially demodulated according to the above formula (3).

[0072] (2) Parallel demodulation

[0073] The process of finding v1 is the same as that of serial demodulation in (1) above. Please refer to the above introduction for details.

[0074] In the process of finding v2, the parallel demodulation does not need to use the value of v1, but instead takes the average of all possible values ​​of v1 and determines the value of v2 as 0 according to the following formula (4):

[0075] in,

[0076] akin,

[0077] As can be seen, serial demodulation requires first estimating the value of v1 based on the received symbol y, and then using the estimated value of v1 and y to further estimate the value of v2. The only difference between parallel demodulation and serial demodulation is that parallel demodulation does not need to use the estimated value of v1 when calculating v2. Therefore, v1 and v2 can be obtained simultaneously and can be implemented in parallel.

[0078] It should be understood that both serial and parallel demodulation can be viewed as demodulating a data stream containing 2... mThe process of transforming a high-order modulation channel of 1 symbol into an m-bit channel. For example, taking 4-PAM as an example, the channel capacity of this modulation channel is I(Y; V1, V2). Serial demodulation decomposes this modulation channel into two bit channels, where the capacity of the first bit channel is I(Y; V1) and the capacity of the second bit channel is I(Y; V2|V1). It can be proven that I(Y; V1, V2) = I(Y; V1) + I(Y; V2|V1), that is, serial demodulation does not cause capacity loss: as shown by the solid lines in Figure 4, the first solid line from bottom to top is the bit channel capacity I(Y; V1) of V1, the second solid line is the bit channel capacity I(Y; V2|V1) of V2, and the third solid line from bottom to top is the modulation channel capacity I(Y; V1, V2) under serial demodulation. Parallel demodulation also decomposes the modulation channel into two bit channels, where the capacity of the first bit channel is I(Y;V1), but the capacity of the second bit channel is I(Y;V2). Since I(Y;V1,V2)>=I(Y;V1)+I(Y;V2), parallel demodulation will incur a certain capacity loss. As shown by the dashed lines in Figure 4, from bottom to top, the first dashed line represents the bit channel capacity I(Y;V1) of V1, the second dashed line represents the bit channel capacity I(Y;V2) of V2, and the third dashed line represents the modulation channel capacity I(Y;V1)+I(Y;V2) under parallel demodulation. It can be seen that parallel demodulation has a certain capacity loss compared to serial demodulation. However, because parallel demodulation is simple to implement and can be parallelized, it is generally used nowadays.

[0079] 3. Bit-interleaved coded modulation (BICM)

[0080] BICM (Bi-interleaved Interleaving) involves interleaving the encoded sequence to obtain the interleaved sequence; then, according to the codebook, several consecutive bits are mapped to form QAM symbols. For example, the encoded sequence A = {a0, a1, a2…} has a modulated sequence B = {b0, b1, b2…}. Each consecutive 6 bits in sequence B is modulated into a QAM64 symbol S = {s0, s1, s2…} according to the codebook C. The real and imaginary parts of QAM64 are independent. The codebook design for every three bits can be shown in Table 1 or Table 2 below.

[0081] Table 1

[0082] Table 2

[0083] After the codebook is modulated, the transmitted symbols are received. Correspondingly, the receiving end receives the modulated symbols and simultaneously demodulates the 6 bits (real part / imaginary part) of the symbols to obtain 6 LLR values ​​(for example, using the parallel demodulation method described above). Further, the interleaved sequence is deinterleaved, and the deinterleaved LLR codes are decoded to obtain the decoding result.

[0084] It should be understood that the codebooks shown in Table 1 above correspond to Gray mapping, while the codebooks shown in Table 2 correspond to natural mapping.

[0085] In MLC, both natural mapping and Gray mapping are common mapping methods. Natural mapping reduces the complexity and uncertainty of the mapping process, thus simplifying encoding and decoding and improving speed. It also helps maintain the relative relationships and order of data, reducing errors during transmission or storage. Gray mapping, in contrast, is more complex and harder to understand, increasing the difficulty of system design and implementation.

[0086] Currently, MLC uses natural mapping for modulation to improve modulation performance. However, natural mapping requires significant changes to the modulation scheme (Gray mapping) in existing protocols, which is not conducive to implementation. How to improve modulation performance while minimizing changes to existing protocols is a current research hotspot.

[0087] Based on the aforementioned problems, this application provides a communication method that can reduce modifications to existing protocols while maintaining the advantage of natural mapping in modulation methods in MLC scenarios.

[0088] Figure 5 is a schematic flowchart of a communication method provided in an embodiment of this application.

[0089] It should be understood that the method shown in Figure 5 can be executed by an encoding device and a decoding device. Unless otherwise specified, "encoding device" or "decoding device" can refer to the encoding device or decoding device itself, or it can refer to a device that enables the encoding device or decoding device to perform this function. For ease of description, the terms "encoding device" and "decoding device" will be used uniformly below. The encoding device can be a terminal device or a network device, and the decoding device can be a terminal device or a network device.

[0090] It should also be understood that the encoding device is referred to as a "transmitting device" or "transmitting equipment"; and the decoding device is referred to as a "receiving device" or "receiving equipment".

[0091] As shown in Figure 5, the method includes the following steps:

[0092] 501, The transmitting device acquires the information bit sequence to be encoded.

[0093] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0094] The process of the transmitting device acquiring the information bit sequence to be encoded can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0095] 502. The transmitting device encodes the information bit sequence to be encoded, resulting in a sequence of m encoded bits.

[0096] For example, after the sending device obtains the information bit sequence to be encoded, it encodes the information bit sequence to obtain m encoded bit sequences.

[0097] For example, the information bit sequence to be encoded comprises m information bit sequences, where the value of m corresponds to the number of coding layers in the MLC. For instance, if the modulation order of the information bit sequence to be encoded is m, and the number of coding layers in the MLC is m, the transmitting device can divide the information bit sequence to be encoded into m information bit sequences and encode each of the m information bit sequences independently to obtain m encoded bit sequences. Here, m is a positive integer greater than 1.

[0098] As an example, as shown in Figure 6, suppose the information bit sequence to be encoded is divided into m = 3 information bit sequences, for example, information bit sequence #1, information bit sequence #2, and information bit sequence #3. These 3 information bit sequences are then encoded independently to obtain 3 encoded bit sequences.

[0099] It should be understood that the encoding method corresponding to each information bit sequence in the m information bit sequence is the same, such as polar code encoding, or low-density parity check code encoding, etc. This application does not limit the specific encoding method.

[0100] 503, The transmitting device performs a first operation on m encoded bit sequences to obtain m first bit sequences.

[0101] For example, after obtaining m encoded bit sequences based on the information bit sequence to be encoded, the transmitting device performs a first operation on the m encoded bit sequences to obtain m first bit sequences. These m first bit sequences are obtained by performing the first operation on each of the m encoded bit sequences. Taking the first and second encoded bit sequences in the m encoded bit sequences as an example, the first operation includes performing an XOR operation on the first and second encoded bit sequences.

[0102] In one possible implementation, the m encoded bit sequences include a first encoded bit sequence and a second encoded bit sequence. The transmitting device performs a first operation on the first information bit sequence and the second information bit sequence respectively, resulting in two first bit sequences. The first encoded bit sequence corresponds to one of the two first bit sequences, and the second encoded bit sequence corresponds to the other first bit sequence (e.g., the second bit sequence).

[0103] For example, the coding layer corresponding to the first coded bit sequence can be located on the layer above the second coded bit sequence.

[0104] Example 1: Assume m = 2. The information bit sequence to be encoded includes two encoded bit sequences, namely the first encoded bit sequence and the second encoded bit sequence. The first encoded bit sequence is located in the first layer of the MLC system, and the second encoded bit sequence is located in the second layer of the MLC system. For example, the first encoded bit sequence can be represented as Seq0, and the second encoded bit sequence can be represented as Seq1. The transmitting device performs a first operation on the first encoded bit sequence and the second encoded bit sequence respectively. The first encoded bit sequence serves as the first layer of the MLC, and the bit sequence obtained by performing the first operation on the first encoded bit sequence can be represented as... The bit sequence obtained by processing the second encoded bit sequence through the first operation can be represented as follows: As can be seen, after the first operation, the bit sequence obtained from the first encoded bit sequence corresponding to the first layer of the MLC system is still the same first encoded bit sequence. After the first operation, the bit sequence obtained from the second encoded bit sequence corresponding to the second layer of the MLC system is obtained by XORing the first encoded bit sequence and the second encoded bit sequence corresponding to the first layer.

[0105] The first coded bit sequence is located in the first layer of the MLC. Referring to the schematic diagram of the m-order modulation MLC process shown in Figure 3 above, the first coded bit sequence can be located in the first layer of the encoding side in Figure 3 (e.g., the layer corresponding to Polar 1 encode); similarly, the second coded bit sequence can be located in the second layer of the encoding side in Figure 3 (e.g., the layer corresponding to Polar 2 encode).

[0106] For example, the first encoded bit sequence Seq0 is: 01010010, and the second encoded bit Seq1 is: 10101011. The bit sequence obtained by the first operation of the first encoded bit sequence is the same as the first encoded bit sequence Seq0. The bit sequence obtained by the first operation of the second encoded bit sequence Seq1 (e.g., the second bit sequence) can be represented as: 00000110.

[0107] In another possible implementation, the m encoded bit sequences include a first encoded bit sequence, a second encoded bit sequence, and a third encoded bit sequence. The transmitting device performs a first operation on the first, second, and third encoded bit sequences respectively, obtaining three first bit sequences. For a detailed description of the transmitting device performing the first operation on the first and second encoded bit sequences, please refer to the description in Example 1 above. The transmitting device performs a first operation on the third encoded bit sequence, obtaining a third bit sequence. This first operation on the third encoded bit sequence can be performed by XORing the first, second, and third encoded bit sequences. This third bit sequence is one of the three first bit sequences.

[0108] Example 2: Assume m = 3. The information bit sequence to be encoded includes three encoded bit sequences: the first encoded bit sequence, the second encoded bit sequence, and the third encoded bit sequence. The first encoded bit sequence is located at the first layer of the MLC system, the second encoded bit sequence is located at the second layer of the MLC system, and the third encoded bit sequence is located at the third layer of the MLC system. For example, the first encoded bit sequence can be represented as Seq0, the second encoded bit sequence can be represented as Seq1, and the third encoded bit sequence can be represented as Seq2. Specific examples of the first operation performed on the first and second encoded bit sequences by the transmitting device can be found in Example 1 above. The bit sequence obtained by performing the first operation on the third encoded bit sequence can be represented as:

[0109] For example, the first coded bit sequence Seq0 is: 01010010, the second coded bit Seq1 is: 10101011, and the third coded bit sequence Seq2 is: 11010011; the first coded bit sequence and the second coded bit... For a specific example of the first operation, please refer to Example 1 above. The bit sequence (e.g., the third bit sequence) obtained by the first operation of the third encoded bit sequence Seq2 can be represented as: 10000111.

[0110] In another possible implementation, the m information bit sequences include a first coded bit sequence, a second coded bit sequence, a third coded bit sequence, and a fourth coded bit sequence. The transmitting device performs a first operation on the first coded bit sequence, the second coded bit sequence, the third coded bit sequence, and the fourth coded bit sequence respectively, to obtain four first bit sequences. For details on the transmitting device performing the first operation on the first coded bit sequence, the second coded bit sequence, and the third coded bit sequence, please refer to the descriptions in Examples 1 and 2 above. The transmitting device performs a first operation on the fourth coded bit sequence to obtain a fourth bit sequence. This first operation on the fourth coded bit sequence can be performed by XORing the first coded bit sequence, the second coded bit sequence, the third coded bit sequence, and the fourth coded bit sequence. This fourth bit sequence is one of the four first bit sequences.

[0111] Example 3: Assume m = 4. The information bit sequence to be encoded includes four encoded bit sequences: the first encoded bit sequence, the second encoded bit sequence, the third encoded bit sequence, and the fourth encoded bit sequence. The first encoded bit sequence is located at the first layer of the MLC system, the second encoded bit sequence at the second layer, the third encoded bit sequence at the third layer, and the fourth encoded bit sequence at the fourth layer. For example, the first encoded bit sequence can be represented as Seq0, the second encoded bit sequence as Seq1, the third encoded bit sequence as Seq2, and the fourth encoded bit sequence as Seq3. Specific examples of the transmitting device performing the first operation on the first, second, and third encoded bit sequences can be found in Examples 1 and 2 above. The bit sequence obtained after the first operation on the fourth encoded bit sequence can be represented as:

[0112] For example, the first encoded bit sequence Seq0 is: 01010010, the second encoded bit Seq1 is: 10101011, the third encoded bit sequence Seq2 is: 11010011, and the fourth encoded bit sequence Seq3 is: 01011111. For specific examples of the first, second, and third encoded bit sequences after the first operation, please refer to Examples 1 and 2 above. The bit sequence (e.g., the fourth bit sequence) obtained by the first operation of the fourth encoded bit sequence Seq3 can be represented as: 00100111.

[0113] In another possible implementation, the m information bit sequences include a coded bit sequences, where a is a positive integer greater than 2. The transmitting device performs a first operation on the first to the a-th coded bit sequences of the a coded bit sequences to obtain a first bit sequences. The first operation includes performing an XOR operation on the first to the a-th coded bit sequences of the a first bit sequences. An example of the transmitting device performing the first operation on the first and second coded bit sequences of the a coded bit sequences can be found in the detailed description of Example 1 above, and will not be repeated here.

[0114] For example, taking the first operation performed on the 'a'-th encoded bit sequence to obtain the 'a'-th bit sequence as an example, the 'a'-th bit sequence satisfies:

[0115] in, Let Seq represent the a-th bit sequence. a Seq represents the sequence of the a-th encoded bits. a-2 This represents the (a-2)th encoded bit sequence.

[0116] Example 4, assuming m ≥ 3, a = 3, the transmitting device performs the first operation on the third encoded bit sequence to obtain the third bit sequence, which satisfies: in, Seq1 represents the 3rd bit sequence, Seq2 represents the 3rd encoded bit sequence, and Seq1 represents the 2nd encoded bit sequence.

[0117] Let the first encoded bit sequence Seq0 be 01010010, the second encoded bit sequence Seq1 be 10101011, and the third encoded bit sequence be 11010011. The bit sequence obtained by the first operation on the first encoded bit sequence is the same as the first encoded bit sequence Seq0. The bit sequence obtained by the first operation on the second encoded bit sequence Seq1 (e.g., the second bit sequence) can be represented as 00000110. The bit sequence obtained by the first operation on the third encoded bit sequence Seq2 (e.g., the third bit sequence) can be represented as 00101010.

[0118] Based on the above examples 1 to 4, those skilled in the art can extrapolate the specific operation methods for performing the first operation on the information bit sequences corresponding to other layers of MLC, which will not be described in detail here.

[0119] Optionally, before performing the first operation on the information bit sequence to be encoded, the transmitting device may also perform a second operation on each information bit sequence in the information bit sequence to be encoded. The second operation includes one or more of the following: channel coding, rate matching, bit interleaving, and scrambling.

[0120] Figure 6 is a schematic diagram of an MLC with m=3 provided in an embodiment of this application. The information bit sequence to be encoded includes three information bit sequences. These three information bit sequences are encoded to obtain three encoded bit sequences: encoded bit sequence #1, encoded bit sequence #2, and encoded bit sequence #3. Each of these three encoded bit sequences undergoes a first operation. A second operation can be performed before the first operation. After each of the three encoded bit sequences completes the first operation, three first bit sequences are obtained.

[0121] In this context, encoded bit sequence #1 can be understood as the first layer encoded bit sequence in the MLC system, encoded bit sequence #2 can be understood as the second layer encoded bit sequence in the MLC system, and encoded bit sequence #3 can be understood as the third layer encoded bit sequence in the MLC system. For a specific example of encoded bit sequence #1 undergoing the first operation, please refer to the above exemplary description of the first encoded bit sequence undergoing the first operation; for a specific example of encoded bit sequence #2 undergoing the first operation, please refer to the above exemplary description of the second encoded bit sequence undergoing the first operation; and for a specific example of encoded bit sequence #3 undergoing the first operation, please refer to the above exemplary description of the third encoded bit sequence undergoing the first operation.

[0122] 504. The transmitting device maps the m first bit sequences to obtain the first symbol sequence.

[0123] For example, after the transmitting device performs a first operation on m bits to obtain a sequence of m first information bits, the transmitting device further maps the m first information bit sequences to obtain a first symbol sequence. There are various mapping methods; this embodiment uses Gray mapping as an example, but it is not a limitation.

[0124] For example, referring to the schematic diagram of an MLC with m=3 provided in Figure 6 above, after the transmitting device performs the first operation on each of the three information bit sequences, it obtains three bit sequences. The transmitting device then modulates these three bit sequences based on Gray mapping to obtain modulation symbols (e.g., the first symbol sequence).

[0125] It should be understood that the specific details of the Gray mapping performed by the transmitting device on the m first information bit sequence can be found in the detailed description of existing schemes, and will not be repeated here.

[0126] 505, the transmitting device sends the first symbol sequence, and correspondingly, the receiving device receives the first symbol sequence.

[0127] 506. The receiving device demodulates the first symbol sequence to obtain the information bit sequence.

[0128] For example, step 506 is on the decoding side, corresponding to the steps on the encoding side described above. Those skilled in the art can demodulate the first symbol sequence based on existing MLC demodulation methods to obtain the information bit sequence.

[0129] For example, after receiving the first symbol sequence, the receiving device can demodulate the first symbol sequence based on the natural mapping to obtain the information bit sequence. The specific demodulation process is similar to the demodulation process in the m-order modulation MLC flowchart shown in Figure 3 above. Those skilled in the art can describe the first symbol sequence based on the description in Figure 3 above, combined with the encoding-side method provided in this application, to obtain the information bit sequence.

[0130] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0131] It is also understood that some coded sequence names are involved in the various embodiments of this application, and their naming does not limit the protection scope of the embodiments of this application.

[0132] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0133] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the first device can also be implemented by components of the first device (such as chips or circuits), without limitation.

[0134] Corresponding to the methods described in the above embodiments, this application also provides corresponding apparatuses, which include modules for executing the methods described above. These modules can be software, hardware, or a combination of both. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0135] Figure 7 is a schematic block diagram of the communication device 700 provided in this application. As shown in Figure 7, the communication device 700 includes a processing unit 710 and a communication unit 720. This device 700 can implement the steps or processes executed by the transmitting or receiving device corresponding to the above method embodiments. The processing unit 710 is used to execute processing-related operations of the transmitting or receiving device in the above method embodiments, and the communication unit 720 is used to execute transmission-related operations of the transmitting or receiving device in the above method embodiments. For example, each unit of the communication device 700 is used to implement the following functions:

[0136] In one possible implementation, processing unit 710 is configured to encode the information bit sequence to be encoded, obtaining m encoded bit sequences, where m is a positive integer greater than 1; processing unit 710 is further configured to perform a first operation on the m encoded bit sequences to obtain m first bit sequences; processing unit 710 is further configured to map the m first bit sequences to obtain a first symbol sequence; and communication unit 720 is further configured to transmit the first symbol sequence. The information bit sequence to be encoded includes m information bit sequences, which are used to determine the m encoded bit sequences. The m encoded bit sequences include a first encoded bit sequence and a second encoded bit sequence, and the first operation includes performing an XOR operation on the first encoded bit sequence and the second encoded bit sequence.

[0137] In various embodiments of the communication device 700 corresponding to the transmitting end, the processing unit 710 is used to perform processing and / or operations implemented internally by the transmitting end device or the receiving end device, other than the actions of sending and receiving. The communication unit 720 is used to perform the actions of receiving (or inputting) by the transmitting end device or the receiving end device, and / or to perform the actions of sending (or outputting) by the transmitting end device or the receiving end device.

[0138] It should be understood that the device 700 here is embodied in the form of a functional unit. The term "unit" here may refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors) and memories for executing one or more software or firmware programs, combined logic circuits, and / or other suitable components that support the described functions.

[0139] The apparatus 700 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting or receiving device in the above-described methods. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, a communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, each executing the transmission and reception operations and related processing operations in the respective method embodiments.

[0140] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of this application, the device 700 can be the transmitting end device or the receiving end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on a chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0141] Figure 8 is a schematic structural diagram of the communication device 800 provided in this application. As shown in Figure 8, the communication device 800 includes: one or more processors 810, one or more memories 820, and one or more communication interfaces 830. The processor 810 is used to control the communication interface 830 to transmit and receive signals, the memory 820 is used to store computer programs, and the processor 810 is used to call and run the computer programs from the memory 820, so that the communication device 800 performs the processing performed by the sending end device or the receiving end device in the various method embodiments of this application.

[0142] For example, processor 810 may have the functions of processing unit 710 shown in FIG. 7, and communication interface 830 may have the functions of communication unit 720 shown in FIG. 7. Specifically, processor 810 may be used to perform processing or operations performed internally by the communication device, and communication interface 830 may be used to perform sending and / or receiving operations of the communication device.

[0143] Optionally, the memory and processor in the above-described device embodiments can be physically independent units, or the memory can be integrated with the processor. This application does not impose any limitations on this.

[0144] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the operations and / or processes performed by the first device in the various method embodiments of this application to be executed.

[0145] In addition, this application also provides a computer program product, which includes computer program code or instructions, such that when the computer program code or instructions are run on a computer, the operations and / or processes performed by the first device in the various method embodiments of this application are executed.

[0146] Furthermore, this application also provides a chip including a processor, a memory for storing a computer program disposed independently of the chip, the processor being used to execute the computer program stored in the memory, such that a device on which the chip is mounted performs the operations and / or processes performed by a first device in any of the method embodiments.

[0147] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include the memory.

[0148] Optionally, the processor can be one or more, and the memory can be one or more.

[0149] Furthermore, this application also provides a communication device (e.g., a chip or chip system) including a processor and a communication interface. According to the operations and / or processing performed by the first device in any of the foregoing method embodiments, the communication interface is used to receive (or input) message bits to be encoded, and the processor encodes the message bits to be encoded. Optionally, the communication interface is also used to send (or output) data and / or information processed by the processor.

[0150] Furthermore, this application also provides a communication device including at least one processor coupled to at least one memory, the at least one processor being configured to execute a computer program or instructions stored in the at least one memory, causing the communication device to perform operations and / or processes performed by a first device in any of the method embodiments.

[0151] In addition, this application also provides a communication system, including a first device in the method embodiments of this application.

[0152] The memory in this application embodiment can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0153] The methods provided in the above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, in the form of a computer program product. The computer program product may include one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media.

[0154] To facilitate a clear description of the technical solutions in the embodiments of this application, the embodiments of this application use the designations "first," "second," etc., to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the designations "first," "second," etc., do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0155] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0156] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0157] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0158] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0159] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0160] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0161] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0162] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, include: Encode the information bit sequence to be encoded to obtain m encoded bit sequences, where m is a positive integer greater than 1; Perform the first operation on the m encoded bit sequences to obtain m first bit sequences; Map the m bits of the first bit sequence to obtain the first symbol sequence; Send the first symbol sequence, The information bit sequence to be encoded includes m information bit sequences, which are used to determine m encoded bit sequences. The m encoded bit sequences include a first encoded bit sequence and a second encoded bit sequence. The first operation includes performing an XOR operation on the first encoded bit sequence and the second encoded bit sequence.

2. The method according to claim 1, characterized in that, The first operation performed on the m encoded bit sequences to obtain m first bit sequences includes: Performing the first operation on the second encoded bit sequence yields a second bit sequence, where m first bit sequences include the second bit sequence. Wherein, the second bit sequence satisfies: in, Seq1 represents the second encoded bit sequence, and Seq0 represents the first encoded bit sequence.

3. The method according to claim 1 or 2, characterized in that, The m encoded bit sequences also include the a-th encoded bit sequence, where a is a positive integer greater than 2. The first operation is performed on the a-th encoded bit sequence to obtain the a-th bit sequence. The m first bit sequences include the a-th bit sequence. The first operation includes performing an XOR operation on the encoded bit sequences from the first encoded bit sequence to the a-th encoded bit sequence.

4. The method according to claim 3, characterized in that, The a-th bit sequence satisfies: in, Let Seq represent the a-th bit sequence. a Seq represents the a-th encoded bit sequence. a-2 This represents the (a-2)th encoded bit sequence.

5. The method according to claim 1 or 2, characterized in that, The m encoded bit sequences also include a third encoded bit sequence. The first operation performed on the m encoded bit sequences to obtain m first bit sequences includes: The first operation is performed on the third encoded bit sequence to obtain the third bit sequence. The m first bit sequences include the third bit sequence. The first operation includes performing an XOR operation on the first encoded bit sequence, the second encoded bit sequence, and the third encoded bit sequence.

6. The method according to claim 5, characterized in that, The third bit sequence satisfies: in, Seq1 represents the third bit sequence, Seq2 represents the third encoded bit sequence, Seq1 represents the second encoded bit sequence, and Seq0 represents the first encoded bit sequence.

7. The method according to any one of claims 1, 2, 5 to 6, characterized in that, The m encoded bit sequences also include a third encoded bit sequence and a fourth encoded bit sequence. The first operation performed on the m encoded bit sequences to obtain m first bit sequences includes: The first operation is performed on the fourth encoded bit sequence to obtain the fourth bit sequence. The m first bit sequences include the fourth bit sequence. The first operation includes performing an XOR operation on the first encoded bit sequence, the second encoded bit sequence, the third encoded bit sequence, and the fourth encoded bit sequence.

8. The method according to claim 7, characterized in that, The fourth bit sequence satisfies: in, Seq3 represents the fourth encoded bit sequence, Seq2 represents the third encoded bit sequence, Seq1 represents the second encoded bit sequence, and Seq0 represents the first encoded bit sequence.

9. The method according to any one of claims 1 to 8, characterized in that, The first operation performed on the m encoded bit sequences to obtain m first bit sequences includes: Perform the second operation on each of the m encoded bit sequences to obtain m fifth bit sequences. The second operation includes one or more of the following: channel coding, rate matching, bit interleaving, or bit scrambling. Perform the first operation on m of the fifth bit sequences to obtain m of the first bit sequences.

10. The method according to any one of claims 1 to 9, characterized in that, The value of m is related to the modulation order.

11. A communication device, characterized in that, Includes modules or units for performing the method according to any one of claims 1 to 10.

12. A communication device, characterized in that, The device includes at least one processor coupled to at least one memory, the at least one processor being configured to execute a computer program or instructions stored in the at least one memory to cause the communication device to perform the method as described in any one of claims 1 to 10.

13. A chip, characterized in that, The device includes a processor and a communication interface, the communication interface being used to receive a sequence to be encoded and to send the sequence to be encoded to the processor, the processor being configured according to the method of any one of claims 1 to 10.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the method as described in any one of claims 1 to 10.

15. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the method as described in any one of claims 1 to 10.

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