Stretchable display panel and display apparatus

Abstract

The present application relates to a stretchable display panel and a display apparatus. The stretchable display panel (1000) comprises: a plurality of pixel islands (1); and a plurality of telescopic bridges (2), wherein some of the telescopic bridges (2) are connected between adjacent pixel islands (1) in a first direction, the other telescopic bridges (2) are connected between adjacent pixel islands (1) in a second direction, a plurality of telescopic bridges (2) of the same number are respectively connected to two sides of each pixel island (1) in the first direction, and a plurality of telescopic bridges (2) of the same number are respectively connected to two sides of each pixel island (1) in the second direction; each telescopic bridge (2) comprises a signal line (21), and the signal line (21) of each telescopic bridge (2) connected to each pixel island (1) is correspondingly electrically connected to each signal end of a pixel circuit group (12a) of the pixel island (1); and among all the signal lines (21) electrically connected to the pixel circuit group (12a), at least one signal line is electrically connected to two different signal ends of the pixel circuit group (12a).

Description

Stretchable display panel and display device

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on January 22, 2025, with application number 202510112471X and entitled "Stretchable display panel and display device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a stretchable display panel and display device. Background Technology

[0004] Stretchable organic light-emitting diode (OLED) display panels have received considerable attention and development in the display industry in recent years due to their unique display form. Currently, stretchable OLED display panels have achieved a preliminary stretchability of 10%. However, the stretchability of stretchable OLED display panels still needs improvement. Summary of the Invention

[0005] Therefore, it is necessary to provide a stretchable display panel and display device.

[0006] In a first aspect, embodiments of this application provide a stretchable display panel, comprising:

[0007] Multiple pixel islands are arranged in rows along a first direction and in columns along a second direction intersecting the first direction; each pixel island includes a first substrate and a driving array layer and a light-emitting device layer stacked on the first substrate, the driving array layer includes a pixel circuit group, and the pixel circuit group includes multiple signal terminals;

[0008] Multiple telescopic bridges are provided, some of which connect to adjacent pixel islands in a first direction, and some of which connect to adjacent pixel islands in a second direction. Each pixel island has an equal number of telescopic bridges connected to both sides in the first direction, and an equal number of telescopic bridges connected to both sides in the second direction. Each telescopic bridge includes a signal line, and the signal line of each telescopic bridge connected to the pixel island is electrically connected to a corresponding signal terminal of each pixel circuit group of the pixel island.

[0009] Among all signal lines electrically connected to the pixel circuit group, at least one of the signal lines is electrically connected to two different signal terminals of the pixel circuit group.

[0010] In one embodiment, the first connection line includes a first sub-line, a second sub-line, and multiple third sub-lines, wherein the first sub-line, the second sub-line, and the third sub-lines are located in different metal film layers; one end of the first sub-line is electrically connected to a first power signal line, and the other end is electrically connected to the second sub-line; the multiple third sub-lines correspond one-to-one with the multiple pixel circuits; one end of the third sub-line is electrically connected to the second sub-line, and the other end is electrically connected to the reset signal terminal of the corresponding pixel circuit;

[0011] Optionally, the first connecting line further includes a fourth sub-line, the fourth sub-line and the third sub-line being located in different metal film layers, one end of the fourth sub-line being electrically connected to the first sub-line and the other end being electrically connected to the second sub-line; the driving array layer further includes a transition section, the transition section and the fourth sub-line being located in different metal film layers, the fourth sub-line being electrically connected to the transition section through a first via, and the transition section being electrically connected to the cathode power supply signal terminal of each pixel circuit;

[0012] Optionally, the first connecting line further includes a fifth sub-line disposed in the same layer and material as the first sub-line, one end of the fifth sub-line being electrically connected to another first power signal line, and the other end being electrically connected to the second sub-line;

[0013] Optionally, the first connecting line further includes a sixth sub-line disposed in the same layer and material as the third sub-line, one end of the sixth sub-line being electrically connected to the fifth sub-line and the other end being electrically connected to the second sub-line.

[0014] Optionally, the threshold compensation transistor is configured as a dual-gate transistor, the threshold compensation transistor including a first transistor and a second transistor, the first terminal of the first transistor and the second terminal of the second transistor being electrically connected, and the control terminal of the first transistor and the control terminal of the second transistor being electrically connected.

[0015] Optionally, the gate initialization transistor is configured as a dual-gate transistor, the gate initialization transistor including a third transistor and a fourth transistor, the first terminal of the third transistor and the second terminal of the fourth transistor being electrically connected, and the control terminal of the third transistor and the control terminal of the fourth transistor being electrically connected;

[0016] Optionally, the first connection line includes a first sub-line, a second sub-line, and multiple third sub-lines, wherein the first sub-line, the second sub-line, and the third sub-lines are located in different metal film layers; one end of the first sub-line is electrically connected to a first power signal line, and the other end is electrically connected to the second sub-line; the multiple third sub-lines correspond one-to-one with the multiple pixel circuits; one end of the third sub-line is electrically connected to the second sub-line, and the other end is electrically connected to the reset signal terminal of the corresponding pixel circuit;

[0017] Optionally, the orthographic projection of the second sub-line on the first substrate and the orthographic projection of the active layer of the gate initialization transistor on the first substrate have an overlapping region and together form the second capacitor;

[0018] Optionally, the first connection line further includes a seventh sub-line connected to the third sub-line, wherein the orthographic projection of the seventh sub-line on the first substrate and the orthographic projection of the active layer of the threshold compensation transistor on the first substrate have an overlapping region and together form a first capacitor.

[0019] Optionally, the fourth connecting line is made of the same layer and material as the second connecting line.

[0020] Optionally, the first adapter cable comprises multiple layers of metal;

[0021] Optionally, the dimensions of the first adapter cable along the first direction are between 24μm and 28μm.

[0022] Optionally, each pixel island is connected to four telescopic bridges on both sides along the first direction and on both sides along the second direction.

[0023] Optionally, the width of the first starting signal line is 1.2 to 2 times the width of the first output signal line;

[0024] Optionally, the width of the first starting signal line is 1.2 to 2 times the width of the second light-emitting signal line;

[0025] In one embodiment, a stretchable display panel includes:

[0026] Multiple pixel islands are arranged in rows along a first direction and in columns along a second direction intersecting the first direction; each pixel island includes a first substrate and a driving array layer and a light-emitting device layer disposed on the first substrate, wherein the driving array layer forms a pixel circuit group, and the pixel circuit group includes multiple signal terminals;

[0027] Multiple telescopic bridges are provided, some of which connect adjacent pixel islands in a first direction, and some of which connect adjacent pixel islands in a second direction. Each pixel island has an equal number of telescopic bridges connected to both sides in the first direction, and an equal number of telescopic bridges connected to both sides in the second direction. Each telescopic bridge includes a signal line, and the signal lines of each telescopic bridge connected to the pixel island are electrically connected to corresponding signal terminals of the pixel circuit group of the pixel island. Among all the signal lines electrically connected to the pixel circuit group, at least one signal line is electrically connected to two different signal terminals of the pixel circuit group.

[0028] Multiple first island groups are arranged sequentially along the second direction; the multiple first island groups are located on one side of the multiple pixel islands along the first direction, and each first island group is correspondingly connected to a row of pixel islands; the first island group includes:

[0029] The first shift register island includes a second base and a first circuit structure layer disposed on the second base, wherein the first circuit structure layer includes a first shift register circuit.

[0030] A first transition island is disposed between the first shift register island and the corresponding row of pixel islands, and the first transition island and the first shift register island are connected by the telescopic bridge; the first transition island includes a third substrate and a first trace structure layer disposed on the third substrate; the first shift register circuit is electrically connected to the first trace structure layer through the signal lines of the telescopic bridge; the first shift register circuits of the plurality of first island groups are cascaded in sequence; the first trace structure layer of the first island group is electrically connected to the signal lines of the pixel islands in the same row to provide a second scan signal, and is electrically connected to the signal lines of the pixel islands in the next row to provide a first scan signal;

[0031] Multiple second island groups are arranged sequentially along the second direction; the multiple second island groups are located on one side of the multiple pixel islands along the first direction; the second island groups include:

[0032] The second shift register island includes a fourth base and a second circuit structure layer disposed on the fourth base, the second circuit structure layer including a second shift register circuit.

[0033] The second transition island is located on the side of the second shift register island close to the first island group, and the second transition island and the second shift register island are connected through the telescopic bridge; the second transition island includes a fifth substrate and a second wiring structure layer disposed on the fifth substrate; the second shift register circuit and the second wiring structure layer are electrically connected through the signal lines of the telescopic bridge; the second shift register circuits of the plurality of second island groups are cascaded in sequence; the second wiring structure layer of the second island group is electrically connected to the signal lines of the pixel island in the same row to provide light emission control signals.

[0034] Secondly, embodiments of this application provide a display device including the stretchable display panel in any of the embodiments of the first aspect.

[0035] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the disclosed drawings without creative effort.

[0037] Figure 1 is a partial structural schematic diagram of a stretchable display panel provided in an embodiment of this application.

[0038] Figure 2 is a planar schematic diagram of the pixel islands and telescopic bridges in the stretchable display panel shown in Figure 1.

[0039] Figure 3 is a schematic diagram of the pixel circuit of the pixel island shown in Figure 2.

[0040] Figure 4 is a planar schematic diagram of the first connecting line of the pixel island shown in Figure 2.

[0041] Figure 5 is a partial planar schematic diagram of the driving array layer of the pixel island shown in Figure 2.

[0042] Figure 6 is a partial planar schematic diagram of the driving array layer of the pixel island shown in Figure 2.

[0043] Figure 7 is a planar schematic diagram of the active layer, second sub-line, and seventh sub-line of the pixel island shown in Figure 2.

[0044] Figure 8 is a schematic cross-sectional view of the threshold compensation transistor and the first capacitor in the pixel circuit shown in Figure 3.

[0045] Figure 9 is a planar schematic diagram of the first connection structure of the pixel island shown in Figure 2.

[0046] Figure 10 is a plan view of the first island group in Figure 1.

[0047] Figure 11 is a plan view of the first island group and the third transition island in Figure 1.

[0048] Figure 12 is a plan view of the second island group in Figure 1.

[0049] Figure 13 is a planar schematic diagram of the first shift register island, the second shift register island, and the second transition island in Figure 1.

[0050] Figure 14 is a planar schematic diagram of the second transition island and the first shift register island in Figure 1.

[0051] Figure 15 is a circuit diagram of the first shift register circuit.

[0052] Figure 16 is a schematic diagram of the second shift register circuit.

[0053] Figure 17 is a schematic diagram of the working principle of the first shift register circuit and the second shift register circuit.

[0054] Figure 18 is a schematic diagram of a partial cross-sectional structure of the stretchable display panel shown in Figure 1.

[0055] Explanation of reference numerals in the attached figures: 1000, Stretchable display panel; 1000a, Light-emitting area; 1000b, First circuit area; 1000c, Second circuit area; 1000d, First transition area; 1000e, Second transition area; 1000f, Third transition area; 1, Pixel island; 11, First substrate; 12, Driving array layer; 12a, Pixel circuit group; 12a1, Pixel circuit; 12a11, Signal terminal; 12a111, Reset signal terminal; 12a112, Cathode power supply signal terminal; 12a113, First scan signal terminal; 12a114, Second scan signal terminal; 12a115, Third scan signal terminal; 12a116, Light-emitting signal terminal; 12a117, Data signal terminal; 12a118, Anode power supply. Signal terminal; 12a12, Threshold compensation module; M3, Threshold compensation transistor; 12a13, Gate initialization module; M4, Gate initialization transistor; 12a14, Data writing module; 12a15, Drive transistor; 12a16, First leakage suppression module; C1, First capacitor; 12a17, Second leakage suppression module; C2, Second capacitor; 121, First connecting line; 121-1, First sub-line; 121-2, Second sub-line; 121-3, Third sub-line; 121-4, Fourth sub-line; 121-5, Fifth sub-line; 121-6, Sixth sub-line; 121-7, Seventh sub-line; 122, Adapter; 123, Second connecting line; 124, Third connecting line; 125, First span Wiring; 126. Fourth connecting line; 127. First connecting structure; 1271. Wiring mesh; 1272. First adapter line; 128. Fifth connecting line; 129. Sixth connecting line; 1210. Seventh connecting line; 1211. Eighth connecting line; 1212. First via; 13. Light-emitting device layer; 131. Light-emitting element; 2. Telescopic bridge; 21. Signal line; 2101. First power signal line; 2102. First scan signal line; 2103. Second scan signal line; 2104. First light-emitting signal line; 2105. Second power signal line; 2106. First data signal line; 2107. Second data signal line; 2108. Third data signal line; 2109. First output signal line; 211 0. First start signal line; 2111. Second light emission signal line; 2112. First clock signal line; 2113. Second clock signal line; 2114. First potential line; 2115. Second potential line; 2116. First signal transmission line; 2117. Second signal transmission line; 2118. Third signal transmission line; 2119. Fourth signal transmission line; 2120. Fifth signal transmission line; 2121. Sixth signal transmission line; 2122. Second output signal line; 2123. First input signal line; 2124. Virtual signal line; 2125. Third clock signal line; 2126. Fourth clock signal line; 2127. Third potential line; 2128. Fourth potential line; 2129. Seventh signal transmission line;2130, Eighth signal transmission line; 2131, Ninth signal transmission line; 3, First island group; 4, First shift register island; 41, Second substrate; 42, First circuit structure layer; 42a, First shift register circuit; 5, First transition island; 51, Third substrate; 52, First wiring structure layer; 521, First transition structure; 522, Second transition structure; 523, Third transition structure; 6, Second island group; 7, Second shift register island; 71, Fourth substrate; 72, Second circuit structure layer; 72a, Second shift register circuit; 8, Second transition island; 81, Fifth substrate; 82, Second wiring structure layer; 821, Fourth transition structure; 9, Third transition island: X, First direction; Y, Second direction; AL, Active layer; GI, Gate insulating layer; CI, Capacitor insulating layer; ILD, Interlayer dielectric layer; PLN, Planarization layer; PDL, Pixel confinement layer; Metal 1. First metal layer; 2. Second metal layer; 3. Third metal layer. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0058] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0060] In a first aspect, referring to Figures 1 and 2, embodiments of this application provide a stretchable display panel 1000, which includes a plurality of pixel islands 1 and a plurality of telescopic bridges 2. The plurality of pixel islands 1 are arranged in rows along a first direction X and in columns along a second direction Y intersecting the first direction X. In a specific example, the plurality of pixel islands 1 are arranged in multiple rows along the first direction X and in multiple columns along the second direction Y. The pixel island 1 includes a first substrate 11 and a driving array layer 12 and a light-emitting device layer 13 stacked on the first substrate 11. The driving array layer 12 includes pixel circuit groups 12a, and the pixel circuit groups 12a include a plurality of signal terminals 12a11. Here, the pixel circuit group 12a is a collection of a plurality of pixel circuits 12a1.

[0061] Some telescopic bridges 2 connect adjacent pixel islands 1 in the first direction X, and some telescopic bridges 2 connect adjacent pixel islands 1 in the second direction Y. Each pixel island 1 has multiple telescopic bridges 2 connected to both sides of the first direction X, and multiple telescopic bridges 2 connected to both sides of the second direction Y. Each telescopic bridge 2 includes a signal line 21, and the signal line 21 of each telescopic bridge 2 connected to the pixel island 1 is electrically connected to each signal terminal 12a11 of the pixel circuit group 12a on the pixel island 1.

[0062] In all signal lines 21 electrically connected to the pixel circuit group 12a, at least one signal line 21 is electrically connected to two different signal terminals 12a11 of the pixel circuit group 12a. It is understood that all signal lines 21 electrically connected to the pixel circuit group 12a include various types of signal lines 21, each used to transmit a different signal, and different types of signal lines 21 transmit different signals. The telescopic bridge 2 also includes a protective layer (not shown) covering the outer surface of the signal lines 21.

[0063] This embodiment of the application, by electrically connecting at least one signal line 21 to two different signal terminals 12a11 of the pixel circuit group 12a, helps to reduce the number of signal lines 21 connected to the pixel island 1. This facilitates the optimization of the number of telescopic bridges 2 connected to the pixel island 1, allowing the pixel island 1 to be connected to the same number of telescopic bridges 2 on both sides along the first direction X and the same number of telescopic bridges 2 on both sides along the second direction Y. Thus, the tensile force on the pixel island 1 in the first direction X and the second direction Y is more balanced, improving the tensile performance of the stretchable display panel 1000.

[0064] In one embodiment, the pixel circuit group 12a includes a plurality of pixel circuits 12a1. Of all the signal lines 21 electrically connected to the pixel circuit group 12a, each pixel circuit 12a1 is electrically connected to a subset of the signal lines 21. Of all the signal lines 21 electrically connected to the pixel circuit 12a1, one signal line 21 is electrically connected to both the reset signal terminal 12a111 and the cathode power signal terminal 12a112 of the pixel circuit 12a1. That is, the reset signal line 21 and the cathode power signal line 21 share the same signal line 21. In one example, this shared signal line 21 transmits the cathode power signal. Referring to FIG3, in the schematic diagram of the pixel circuit 12a1, the reset signal terminal 12a111 and the cathode power signal terminal 12a112 are electrically connected.

[0065] It should be noted that, in practical applications, since the reset voltage connected to the reset signal line 21 is similar to the cathode power supply voltage connected to the cathode power supply signal line 21, this embodiment outputs the cathode power supply and reset voltage required by the pixel circuit 12a1 to the cathode power supply signal terminal 12a112 and the reset signal terminal 12a111 respectively through the cathode power supply signal line 21, thereby reducing the number of signal lines 21. This is beneficial for optimizing the number of telescopic bridges 2 connected to the pixel island 1, so that the pixel island 1 can be connected to the same number of telescopic bridges 2 on both sides along the first direction X, and the pixel island 1 can be connected to the same number of telescopic bridges 2 on both sides along the second direction Y.

[0066] In one embodiment, the pixel circuit group 12a includes a plurality of pixel circuits 12a1. Among all the signal lines 21 electrically connected to the pixel circuit group 12a, each pixel circuit 12a1 is electrically connected to a subset of the signal lines 21. Of all the signal lines 21 electrically connected to the pixel circuit 12a1, one signal line 21 is electrically connected to the second scan signal terminal 12a114 and the third scan signal terminal 12a115 of the pixel circuit 12a1. Referring to FIG3, in the schematic diagram of the pixel circuit 12a1, the second scan signal terminal 12a114 and the third scan signal terminal 12a115 are electrically connected. That is, the S2 signal line and the S3 signal line share the same signal line 21.

[0067] It should be noted that in practical applications, the signals connected to the second scan signal terminal 12a114 and the third scan signal terminal 12a115 are the same. Therefore, in this embodiment, the second scan signal and the third scan signal required by the pixel circuit 12a1 are output to the second scan signal terminal 12a114 and the third scan signal terminal 12a115 respectively through the same signal line 21, which reduces the number of signal lines 21. This is beneficial for optimizing the number of telescopic bridges 2 connected to the pixel island 1, so that the pixel island 1 can be connected to the same number of telescopic bridges 2 on both sides along the first direction X, and the pixel island 1 can be connected to the same number of telescopic bridges 2 on both sides along the second direction Y.

[0068] It is important to emphasize that in traditional technologies, the branched routing layout within the drive array layer 12 makes it inconvenient to share the same signal line 21 for the S2 and S3 signal lines. Connecting the S2 and S3 signal lines separately would facilitate the connection. This embodiment of the application allows the S2 and S3 signal lines to share the same signal line 21, optimizing the number of signal lines 21 and thus balancing the number of telescopic bridges 2.

[0069] Optionally, the signal lines 21 of the multiple telescopic bridges 2 on one side of the pixel island 1 along the first direction X are paired with the signal lines 21 of the multiple telescopic bridges 2 on the other side of the pixel island 1 along the first direction X; similarly, the signal lines 21 of the multiple telescopic bridges 2 on one side of the pixel island 1 along the second direction Y are paired with the signal lines 21 of the multiple telescopic bridges 2 on the other side of the pixel island 1 along the second direction Y. The paired signal lines 21 transmit the same signal, and further, the paired signal lines 21 are electrically connected through connecting lines in the drive array layer 12.

[0070] Optionally, each telescopic bridge 2 includes one signal line 21. This allows for optimization of the number of telescopic bridges 2 by adjusting the number of signal lines 21. It is understood that each telescopic bridge 2 may also include multiple signal lines 21.

[0071] In one embodiment, as shown in FIG2, the multiple signal lines 21 electrically connected to the pixel circuit group 12a include two first power signal lines 2101 for transmitting a first power signal and two second scan signal lines 2103 for transmitting a second scan signal S2; the second scan signal S2 is used to control the data writing of the pixel circuit 12a1.

[0072] The telescopic bridges 2 corresponding to the two first power signal lines 2101 are respectively connected to both sides of the pixel island 1 along the first direction X, and the two first power signal lines 2101 are electrically connected to the reset signal terminal 12a111 and the cathode power signal terminal 12a112 of each pixel circuit 12a1; the telescopic bridges 2 corresponding to the two second scan signal lines 2103 are respectively connected to both sides of the pixel island 1 along the first direction X, and the two second scan signal lines 2103 are electrically connected to the second scan signal terminal 12a114 and the third scan signal terminal 12a115 of each pixel circuit 12a1. In this embodiment, the first power signal line 2101 is the signal line 21 shared by the reset signal line 21 and the cathode power signal line 21. The second scan signal line 2103 is the signal line 21 shared by the S2 signal line and the S3 signal line.

[0073] It should be noted that, as shown in Figure 2, the above settings can make the number of signal lines 21 on both sides of the pixel island 1 along the first direction X equal to the number of signal lines 21 on both sides of the pixel island 1 along the second direction Y. This makes the number of telescopic bridges 2 on the left, right, top, and bottom sides of the pixel island 1 the same, so that the stretching ratio of the pixel island 1 in the first direction X and the second direction Y tends to be consistent, thus improving the stretching performance.

[0074] Optionally, the multiple signal lines 21 electrically connected to the pixel circuit group 12a further include two first scan signal lines 2102 for transmitting the first scan signal S1. The telescopic bridges 2 corresponding to the two first scan signal lines 2102 are respectively connected to both sides of the pixel island 1 along the first direction X, and the two first scan signal lines 2102 are electrically connected to the first scan signal terminal 12a113 of each pixel circuit 12a1. The first scan signal S1 is used to control the writing of the gate signal of the driving transistor 12a15 of the pixel circuit 12a1. By setting the first scan signal lines 2102 on both sides of the pixel island 1 along the first direction X, all scan signal lines 21 can be arranged on both sides of the pixel island 1 along the first direction X, which helps to reduce the difficulty of arranging the first shift register island 4 (described in detail below) used for outputting the scan signal.

[0075] Optionally, the multiple signal lines 21 electrically connected to the pixel circuit group 12a further include two first light-emitting signal lines 2104. The telescopic bridges 2 corresponding to the two first light-emitting signal lines 2104 are respectively connected to both sides of the pixel island 1 along the first direction X, and the two first light-emitting signal lines 2104 are electrically connected to the light-emitting signal terminals 12a116 of each pixel circuit 12a1. By arranging the first light-emitting signal lines 2104 on both sides of the pixel island 1 along the first direction X, it is beneficial to reduce the difficulty of arranging the second shift register island 7 (described in detail below) used for outputting light-emitting control signals.

[0076] In one embodiment, the multiple signal lines 21 electrically connected to the pixel circuit group 12a further include two second power signal lines 2105. The telescopic bridges 2 corresponding to the two second power signal lines 2105 are respectively connected to both sides of the pixel island 1 along the second direction Y, and the two second power signal lines 2105 are electrically connected to the anode power signal terminal 12a118 of each pixel circuit 12a1.

[0077] Optionally, the light-emitting device layer 13 includes a plurality of light-emitting elements 131, which include a first light-emitting element 131, a second light-emitting element 131, and a third light-emitting element 131, each emitting light of a different color. The plurality of pixel circuits 12a1 in the same pixel circuit group 12a include a first pixel circuit 12a1, a second pixel circuit 12a1, and a third pixel circuit 12a1. The first pixel circuit 12a1 is electrically connected to the first light-emitting element 131, the second pixel circuit 12a1 is electrically connected to the second light-emitting element 131, and the third pixel circuit 12a1 is electrically connected to the third light-emitting element 131.

[0078] The multiple signal lines 21 electrically connected to the pixel circuit group 12a also include two first data signal lines 2106, two second data signal lines 2107, and two third data signal lines 2108; the telescopic bridges 2 corresponding to the two first data signal lines 2106 are respectively connected to both sides of the pixel island 1 along the second direction Y, and the two first data signal lines 2106 are electrically connected to the data signal terminal 12a117 of the first pixel circuit 12a1; the telescopic bridges 2 corresponding to the two second data signal lines 2107 are respectively connected to both sides of the pixel island 1 along the second direction Y, and the two second data signal lines 2107 are electrically connected to the data signal terminal 12a117 of the second pixel circuit 12a1; the telescopic bridges 2 corresponding to the two third data signal lines 2108 are respectively connected to both sides of the pixel island 1 along the second direction Y, and the two first data signal lines 2106 are electrically connected to the data signal terminal 12a117 of the third pixel circuit 12a1.

[0079] The above configuration makes the number of telescopic bridges 2 on both sides of the pixel island 1 along the second direction Y equal to the number of telescopic bridges 2 on both sides of the pixel island 1 along the first direction X, so that the stretching ratio of the pixel island 1 in the first direction X and the second direction Y tends to be consistent, thus improving the stretching performance.

[0080] In one specific embodiment, the pixel island 1 includes a first light-emitting element 131, a second light-emitting element 131 and a third light-emitting element 131. Correspondingly, the pixel circuit group 12a includes a first pixel circuit 12a1, a second pixel circuit 12a1 and a third pixel circuit 12a1.

[0081] In one embodiment, as shown in FIG2, the driving array layer 12 includes a first connection line 121, which connects two first power signal lines 2101 on both sides of the pixel island 1 along the first direction X, and the first connection line 121 is electrically connected to the reset signal terminal 12a111 and the cathode power signal terminal 12a112 of the pixel circuit 12a1.

[0082] In one embodiment, as shown in Figures 2, 4, and 5, the first connecting line 121 includes a first sub-line 121-1, a second sub-line 121-2, and multiple third sub-lines 121-3. The first sub-line 121-1, the second sub-line 121-2, and the third sub-lines 121-3 are located in different metal film layers. One end of the first sub-line 121-1 is electrically connected to a first power signal line 2101, and the other end is electrically connected to the second sub-line 121-2. The number of third sub-lines 121-3 is the same as the number of pixel circuits 12a1, and multiple third sub-lines 121-3 correspond one-to-one with multiple pixel circuits 12a1. One end of the third sub-line 121-3 is electrically connected to the second sub-line 121-2, and the other end is electrically connected to the reset signal terminal 12a111 of the corresponding pixel circuit 12a1.

[0083] In this way, the structure of the first connection line 121 can be simplified, the reset signal terminal 12a111 of the pixel circuit 12a1 can be easily connected to the first power signal line 2101, and it is also beneficial to arrange the metal film layer in the driving array layer 12 in a reasonable manner.

[0084] Optionally, the first sub-line 121-1 is located in the first metal layer Metal1, the second sub-line 121-2 is located in the second metal layer Metal2, and the third sub-line 121-3 is located in the third metal layer Metal3.

[0085] Optionally, the first connecting line 121 further includes a fourth sub-line 121-4, which is located in a different metal film layer from the third sub-line 121-3. One end of the fourth sub-line 121-4 is electrically connected to the first sub-line 121-1, and the other end is electrically connected to the second sub-line 121-2. The driving array layer 12 further includes a transition section 122, which is located in a different metal film layer from the fourth sub-line 121-4. The fourth sub-line 121-4 is electrically connected to the transition section 122 through a first via 1212, and the transition section 122 is electrically connected to the cathode power supply signal terminal 12a112 of each pixel circuit 12a1.

[0086] In this way, the cathode power signal terminal 12a112 of the pixel circuit 12a1 can be conveniently connected to the first power signal line 2101, which can save a trace and is also conducive to the reasonable arrangement of the metal film layer in the driving array layer 12.

[0087] Optionally, the fourth sub-line 121-4 is located in the second metal layer Metal2.

[0088] Optionally, the first connecting line 121 further includes a fifth sub-line 121-5 made of the same layer and material as the first sub-line 121-1. One end of the fifth sub-line 121-5 is electrically connected to another first power signal line 2101, and the other end of the fifth sub-line 121-5 is electrically connected to the second sub-line 121-2. In this way, the structure of the first connecting line 121 can be simplified, and the two first power signal lines 2101 can be connected together.

[0089] Optionally, the first connecting line 121 also includes a sixth sub-line 121-6 made of the same layer and material as the third sub-line 121-3. One end of the sixth sub-line 121-6 is electrically connected to the fifth sub-line 121-5, and the other end is electrically connected to the second sub-line 121-2.

[0090] In one embodiment, referring to Figures 7 and 8, the pixel circuit 12a1 includes a threshold compensation transistor M3. The orthographic projection of the first connection line 121 on the first substrate 11 overlaps with the orthographic projection of the active layer AL of the threshold compensation transistor M3 on the first substrate 11, and together they form a first capacitor C1. This reduces the leakage current of the threshold compensation transistor M3 and improves brightness uniformity.

[0091] Optionally, referring to Figures 3 and 8, the threshold compensation transistor M3 is configured as a dual-gate transistor. The threshold compensation transistor M3 includes a first transistor T1 and a second transistor T2. The first electrode of the first transistor T1 and the second electrode of the second transistor T2 are electrically connected, as are the control electrodes of the first transistor T1 and the second transistor T2. Further, one electrode of the first capacitor C1 is electrically connected to the first electrode of the first transistor T1 and the second electrode of the second transistor T2, and the other electrode of the first capacitor C1 is electrically connected to the cathode power supply signal terminal 12a112 (reset signal terminal 12a111).

[0092] In one embodiment, referring to FIG7, the pixel circuit 12a1 includes a gate initialization transistor M4. The orthographic projection of the first connection line 121 on the first substrate 11 overlaps with the orthographic projection of the active layer AL of the gate initialization transistor M4 on the first substrate 11, and together they form a second capacitor C2. In this way, the leakage current of the gate initialization transistor M4 can be reduced, and the brightness uniformity can be improved.

[0093] Optionally, referring to FIG3, the gate initialization transistor M4 is configured as a dual-gate transistor. The gate initialization transistor M4 includes a third transistor T3 and a fourth transistor T4. The first terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are electrically connected, and the control terminal of the third transistor T3 and the control terminal of the fourth transistor T4 are electrically connected. Further, one electrode of the second capacitor C2 is electrically connected to the first terminal of the third transistor T3 and the second terminal of the fourth transistor T4, and the other electrode of the second capacitor C2 is electrically connected to the cathode power supply signal terminal 12a112 (reset signal terminal 12a111).

[0094] Optionally, as shown in FIG7, the orthographic projection of the second sub-line 121-2 of the first connecting line 121 on the first substrate 11 overlaps with the orthographic projection of the active layer AL of the gate initialization transistor M4 on the first substrate 11, and together they form the second capacitor C2.

[0095] Optionally, as shown in FIG7, the first connecting line 121 further includes a seventh sub-line 121-7 connected to the third sub-line 121-3. The orthographic projection of the seventh sub-line 121-7 on the first substrate 11 and the orthographic projection of the active layer AL of the threshold compensation transistor M3 on the first substrate 11 have an overlapping area and together form the first capacitor C1.

[0096] In one embodiment, as shown in Figures 2 and 6, the driving array layer 12 further includes a second connecting line 123 and a third connecting line 124. The second connecting line 123 connects two second scan signal lines 2103 on both sides of the pixel island 1 along the first direction X, and the second connecting line 123 is electrically connected to the second scan signal terminal 12a114 of each pixel circuit 12a1; one end of the third connecting line 124 is electrically connected to the second connecting line 123, and the other end is electrically connected to the third scan signal terminal 12a115 of each pixel circuit 12a1.

[0097] Optionally, the second connecting line 123 and the third connecting line 124 are disposed in the same layer and made of the same material, and both extend along the first direction X. In one example, the second connecting line 123 and the third connecting line 124 are located in the first metal layer Metal1. The driving array layer 12 also includes a first jumper 125, which is located in a different metal film layer from the second connecting line 123. One end of the first jumper 125 is electrically connected to the second connecting line 123, and the other end is electrically connected to the third connecting line 124. In one example, the first jumper 125 is located in the third metal layer Metal3. The first jumper 125 is connected to the second connecting line 123 through a via, and the first jumper 125 is connected to the third connecting line 124 through a via.

[0098] Thus, the second scan signal S2 can control the anode reset terminal through the first jumper wire 125 and the via, realizing the multiplexing of the second scan signal line 2103 and reducing the number of signal lines 21.

[0099] Optionally, the driving array layer 12 further includes a fourth connection line 126, which connects two first light-emitting signal lines 2104 on both sides of the pixel island 1 along the first direction X, and is electrically connected to the light-emitting signal terminal 12a116 of each pixel circuit 12a1. For example, the first light-emitting signal lines 2104 extend along the first direction X.

[0100] Optionally, the fourth connecting line 126 is disposed in the same layer and with the same material as the second connecting line 123, that is, the fourth connecting line 126 is located in the first metal layer Metal1.

[0101] Optionally, the orthographic projection of the fourth connecting line 126 on the first base 11 and the orthographic projection of the first jumper 125 on the first base 11 overlap. In this way, the layout area on the first base 11 can be maximized, and the difficulty of wiring layout can be reduced.

[0102] In one embodiment, as shown in Figures 2 and 9, the driving array layer 12 further includes a first connection structure 127. The first connection structure 127 connects two second power signal lines 2105 on both sides of the pixel island 1 along the second direction Y, and the first connection structure 127 is electrically connected to the anode signal terminal 12a11 of each pixel circuit 12a1. In this way, the second power signal lines 2105 and the anode signal terminal 12a11 of each pixel circuit 12a1 can be conveniently connected.

[0103] Optionally, the first connection structure 127 includes a wiring mesh 1271 and two first adapter lines 1272. The two first adapter lines 1272 are respectively connected to both sides of the wiring mesh 1271 along the second direction Y, and the two first adapter lines 1272 are respectively electrically connected to the corresponding second power signal line 2105; the anode signal terminal 12a11 of each pixel circuit 12a1 is electrically connected to the wiring mesh 1271.

[0104] Optionally, the first adapter cable 1272 includes multiple layers of metal. This reduces the resistance of the first adapter cable 1272, which helps suppress the delay of the anode signal.

[0105] Optionally, the driving array layer 12 further includes a fifth connection line 128, a sixth connection line 129, and a seventh connection line 1210. The fifth connection line 128 connects to two first data signal lines 2106 on both sides of the pixel island 1 along the second direction Y, and is electrically connected to the data signal terminal 12a117 of the first pixel circuit 12a1. The sixth connection line 129 connects to two second data signal lines 2107 on both sides of the pixel island 1 along the second direction Y, and is electrically connected to the data signal terminal 12a117 of the second pixel circuit 12a1. The seventh connection line 1210 connects to two third data signal lines 2108 on both sides of the pixel island 1 along the second direction Y, and is electrically connected to the data signal terminal 12a117 of the third pixel circuit 12a1.

[0106] Optionally, the first adapter line 1272, the fifth connecting line 128, the sixth connecting line 129, and the seventh connecting line 1210 all extend along the second direction Y. The dimension of any one of the fifth connecting line 128, the sixth connecting line 129, and the seventh connecting line 1210 along the first direction X is smaller than the dimension of the first adapter line 1272 along the first direction X. Here, the dimension of the fifth connecting line 128 along the first direction X is the width of the fifth connecting line 128, the dimension of the sixth connecting line 129 along the first direction X is the width of the sixth connecting line 129, the dimension of the seventh connecting line 1210 along the first direction X is the width of the seventh connecting line 1210, and the dimension of the first adapter line 1272 along the first direction X is the width of the first adapter line 1272. This configuration is equivalent to widening the first adapter line 1272, reducing its resistance, and thus helping to suppress the delay of the anode signal.

[0107] Optionally, the dimension of the first adapter cable 1272 along the first direction X is between 24μm and 28μm. For example, the width of the first adapter cable 1272 can be 24μm, 25μm, 26μm, 27μm, 28μm, or between any two of the above values.

[0108] Optionally, the driving array layer 12 further includes an eighth connection line 1211, which connects two first scan signal lines 2102 on both sides of the pixel island 1 along the first direction X.

[0109] In one embodiment, each pixel island 1 is connected to an even number of telescopic bridges 2 on both sides along the first direction X and on both sides along the second direction Y, and each telescopic bridge 2 includes a signal line 21.

[0110] In this way, the number of signal lines 21 on both sides of the pixel island 1 along the first direction X can be equal to the number of signal lines 21 on both sides of the pixel island 1 along the second direction Y. This makes the number of telescopic bridges 2 on the left, right, top, and bottom sides of the pixel island 1 the same, so that the stretching ratio of the pixel island 1 in the first direction X and the second direction Y tends to be consistent, thus improving the stretching performance.

[0111] Optionally, each pixel island 1 is connected to four telescopic bridges 2 on both sides along the first direction X and on both sides along the second direction Y.

[0112] In one embodiment, multiple telescopic bridges 2 connecting the pixel island 1 to both sides along the first direction X are arranged symmetrically. For example, the multiple telescopic bridges 2 connecting the pixel island 1 to both sides along the first direction X are arranged symmetrically about a first center line, which is parallel to the first direction X. This improves the stretchability of the stretchable panel and enhances its stretch performance.

[0113] In one embodiment, multiple telescopic bridges 2 connecting the pixel island 1 to both sides along the second direction Y are arranged symmetrically. For example, the multiple telescopic bridges 2 connecting the pixel island 1 to both sides along the second direction Y are arranged symmetrically about a second center line, which is parallel to the second direction Y. This improves the stretchability of the stretchable panel and enhances its stretch performance.

[0114] In one embodiment, referring to Figures 1 and 10, the stretchable display panel 1000 further includes a plurality of first island groups 3 arranged sequentially along the second direction Y; the plurality of first island groups 3 are disposed on one side of the plurality of pixel islands 1 along the first direction X, and each first island group 3 is correspondingly connected to a row of pixel islands 1.

[0115] Further, the first island group 3 includes a first shift register island 4 and a first transition island 5. The first shift register island 4 includes a second substrate 41 and a first circuit structure layer 42 disposed on the second substrate 41. The first circuit structure layer 42 includes a first shift register circuit 42a. The first transition island 5 is disposed between the first shift register island 4 and the corresponding row of pixel islands 1, and the first transition island 5 and the first shift register island 4 are connected by a telescopic bridge 2. The first transition island 5 includes a third substrate 51 and a first wiring structure layer 52 disposed on the third substrate 51. The first shift register circuit 42a and the first wiring structure layer 52 are electrically connected through the signal line 21 of the telescopic bridge 2. The first shift register circuits 42a of multiple first island groups 3 are cascaded in sequence. The first wiring structure layer 52 of the first island group 3 is electrically connected to the signal line 21 of the same row of pixel islands 1 to provide a second scan signal, and is electrically connected to the signal line 21 of the next row of pixel islands 1 to provide a first scan signal.

[0116] This embodiment is equivalent to placing the first shift register circuit 42a and the wiring layout structure (first wiring structure layer 52) associated with the first shift register circuit 42a on two different islands. In this way, on the one hand, sufficient setting area can be provided for the first shift register circuit 42a and the wiring layout structure; on the other hand, the problem of mutual interference between the wiring of the first shift register circuit 42a and the wiring layout structure can be improved.

[0117] Optionally, each telescopic bridge 2 includes one signal line 21. It is understood that each telescopic bridge 2 may also include multiple signal lines 21; this embodiment of the application uses one signal line 21 as an example for illustration.

[0118] Optionally, the first shift register island 4 is connected to multiple telescopic bridges 2 of the same number on both sides along the first direction X, and the telescopic bridge 2 located between the first shift register island 4 and the first transition island 5 connects the first shift register island 4 and the first transition island 5; the first shift register island 4 is also connected to multiple telescopic bridges 2 of the same number on both sides along the second direction Y, and two adjacent first shift register islands 4 along the second direction Y are connected by the telescopic bridge 2 between them. In this way, the tensile force of the first shift register island 4 in the first direction X and the second direction Y is more balanced, improving the tensile performance of the stretchable display panel 1000.

[0119] In one embodiment, the first shift register island 4 is connected to four telescopic bridges 2 on both sides along the first direction X.

[0120] Of the four telescopic bridges 2 connected to the side of the first shift register island 4 near the first adapter island 5, two telescopic bridges 2 serve as first output signal lines 2109, one as a first start signal line 2110, and one as a second light-emitting signal line 2111. The first output signal lines 2109 and 2110 are electrically connected to the first shift register circuit 42a and the first trace structure layer 52. The signal line 21 of the telescopic bridge 2 connected to the side of the first shift register island 4 away from the first adapter island 5 is the second light-emitting signal line 2111, and this second light-emitting signal line 2111 is electrically connected to the second light-emitting signal line 2111 located on the side of the first shift register island 4 near the first adapter island 5. The first output signal line 2109 transmits the first output signal GOUT, and the first start signal line 2110 transmits the first start signal SIN.

[0121] Thus, by rationally designing the function of the signal line 21 between the first shift register island 4 and the first transfer island 5, it is not only beneficial for signal transmission, but also for ensuring that the number of telescopic bridges 2 meets the preset number (4 lines). By setting two first output signal lines 2109, the delay of the first output signal can be reduced.

[0122] Optionally, the width of the first start signal line 2110 is greater than the width of the first output signal line 2109 and / or the width of the second light-emitting signal line 2111. This is equivalent to thickening the width of the first start signal line 2110, which helps to reduce the resistance of the first start signal line 2110 and thus suppresses the delay of the start signal SIN.

[0123] Optionally, the width of the first start signal line 2110 is 1.2 to 2 times the width of the first output signal line 2109. For example, the width of the first start signal line 2110 can be 1.2, 1.4, 1.6, 1.8, or 2 times the width of the first output signal line 2109, or between any two of the above values.

[0124] Optionally, the width of the first start signal line 2110 is 1.2 to 2 times the width of the second light-emitting signal line 2111. For example, the width of the first start signal line 2110 can be 1.2, 1.4, 1.6, 1.8, or 2 times the width of the first output signal line 2109, or between any two of the above values.

[0125] Optionally, the first shift register island 4 is connected to four telescopic bridges 2 on both sides along the second direction Y.

[0126] The signal lines 21 of the four telescopic bridges 2 on one side of the first shift register island 4 along the second direction Y are paired with the signal lines 21 of the four telescopic bridges 2 on the other side of the first shift register island 4 along the second direction Y. The signal lines 21 of the four telescopic bridges 2 on the first shift register island 4 along the second direction Y are respectively the first clock signal line 2112, the second clock signal line 2113, the first potential line 2114, and the second potential line 2115. The first clock signal line 2112, the second clock signal line 2113, the first potential line 2114, and the second potential line 2115 are all electrically connected to the first shift register circuit 42a. Among them, the first clock signal line 2112 transmits the first clock signal SCK1, the second clock signal line 2113 transmits the second clock signal SCK2, the first potential line 2114 transmits the high-level signal VGH, and the second potential line 2115 transmits the low-level signal VGL.

[0127] The above configuration makes the number of telescopic bridges 2 on both sides of the first shift register island 4 along the second direction Y equal to the number of telescopic bridges 2 on both sides of the first shift register island 4 along the first direction X, so that the stretching ratio of the first shift register island 4 in the first direction X and the second direction Y tends to be consistent, thus improving the stretching performance.

[0128] In one embodiment, the first transition island 5 is connected to the same number of telescopic bridges 2 on both sides along the first direction X; the first transition island 5 is connected to the same number of telescopic bridges 2 on both sides along the second direction Y, and two adjacent first transition islands 5 along the second direction Y are connected by the telescopic bridges 2 between them.

[0129] Optionally, the first transition island 5 is connected to four telescopic bridges 2 on both sides along the first direction X, and the first transition island 5 is connected to four telescopic bridges 2 on both sides along the second direction Y.

[0130] The above configuration allows the number of telescopic bridges 2 on both sides of the first transition island 5 along the second direction Y to be equal to the number of telescopic bridges 2 on both sides of the first transition island 5 along the first direction X, making the tensile ratio of the first transition island 5 in the first direction X and the second direction Y more consistent, thus improving the tensile performance.

[0131] Optionally, the first wiring structure layer 52 includes a first adapter structure 521, which is connected to one of the four telescopic bridges 2 along the second direction Y side of the first adapter island 5. The signal line 21 of one telescopic bridge 2 is a first signal transmission line 2116, and the signal line 21 of another telescopic bridge 2 is a second signal transmission line 2117. The signal line 21 of one of the four telescopic bridges 2 connected to the side of the first adapter island 5 near the pixel island 1 is a third signal transmission line 2118. The two first output signal lines 2109, the first signal transmission line 2116, the second signal transmission line 2117, and the third signal transmission line 2118 on the first shift register island 4 are all connected to the first adapter structure 521.

[0132] The first signal transmission line 2116 is also electrically connected to the first trace structure layer 52 of the next-level first island group 3 to output the first start signal SIN; the second signal transmission line 2117 is also electrically connected to the first trace structure layer 52 of the next-level first island group 3 to output the first scan signal S1; the third signal transmission line 2118 is also electrically connected to a signal line 21 of the corresponding pixel island 1 in the same row to output the second scan signal S2, or the third signal transmission line 2118 is connected to a floating potential. It should be noted that, referring to Figures 10 and 11, when the first island group 3 is a first-level island group, the third signal transmission line 2118 on the first transition island 5 of the first island group 3 is connected to a floating potential. When the first island group 3 is not a first-level island group, the third signal transmission line 2118 on the first transition island 5 of the first island group 3 is electrically connected to a signal line 21 of the corresponding pixel island 1 in the same row to output the second scan signal S2.

[0133] The above arrangement allows for a reasonable layout of the first output signal line 2109, the first signal transmission line 2116, the second signal transmission line 2117, and the third signal transmission line 2118, avoiding mutual interference between the aforementioned signal lines 21.

[0134] Optionally, the first wiring structure layer 52 further includes a second transition structure 522, connected to one of the four telescopic bridges 2 along the second direction Y side of the first transition island 5. The signal lines 21 of two telescopic bridges 2 are fourth signal transmission lines 2119; the signal line 21 of one telescopic bridge 2 connected to the side of the first transition island 5 near the pixel island 1 is a fifth signal transmission line 2120. Both the fourth signal transmission line 2119 and the fifth signal transmission line 2120 are connected to the second transition structure 522. The fifth signal transmission line 2120 is electrically connected to a signal line 21 of the corresponding row of pixel islands 1, or the fifth signal transmission line 2120 is connected to a floating potential. Both the fourth signal transmission line 2119 and the fifth signal transmission line 2120 transmit cathode signals. It should be noted that, referring to Figures 10 and 11, when the first island group 3 is a first-level island group, the fifth signal transmission line 2120 on the first transition island 5 of the first island group 3 is connected to a floating potential. When the first island group 3 is not the first-level island group, the fifth signal transmission line 2120 on the first transition island 5 of the first island group 3 is electrically connected to a signal line 21 of the corresponding row of pixel island 1.

[0135] By setting up two fourth signal transmission lines 2119, the voltage drop can be reduced. It is understandable that the second adapter structure 522 could be thickened to further reduce the voltage drop.

[0136] Optionally, the signal line 21 of a telescopic bridge 2 connected to the side of the first adapter island 5 near the pixel island 1 is the ninth signal transmission line 2131, and the ninth signal transmission line 2131 is electrically connected to the second signal transmission line 2117 on the first adapter island 5.

[0137] Optionally, a signal line 21 of a telescopic bridge 2 connected to the side of the first transition island 5 near the pixel island 1 is designated as a sixth signal transmission line 2121. A second light-emitting signal line 2111 connected to the first transition island 5 is electrically connected to one end of the sixth signal transmission line 2121, and the other end of the sixth signal transmission line 2121 is electrically connected to or connected to a signal line 21 of the corresponding row of pixel islands 1 at a floating potential. The sixth signal transmission line 2121 is used to transmit the light-emitting signal EM. Referring to Figures 12 and 13, when the first island group 3 is a first-level island group, the sixth signal transmission line 2121 on the first transition island 5 of the first island group 3 is connected to a floating potential; when the first island group 3 is not a first-level island group, the other end of the sixth signal transmission line 2121 on the first transition island 5 of the first island group 3 is electrically connected to a signal line 21 of the corresponding row of pixel islands 1.

[0138] In one embodiment, referring to Figures 1, 12, and 13, the stretchable display panel 1000 further includes a plurality of second island groups 6 arranged sequentially along a second direction Y, the plurality of second island groups 6 being disposed on one side of the plurality of pixel islands 1 along a first direction X. The second island group 6 includes a second shift register island 7 and a second transition island 8. The second shift register island 7 includes a fourth substrate 71 and a second circuit structure layer 72 disposed on the fourth substrate 71. The second circuit structure layer 72 includes a second shift register circuit 72a. The second transition island 8 is located on the side of the second shift register island 7 near the first island group 3, and the second transition island 8 and the second shift register island 7 are connected by a telescopic bridge 2; the second transition island 8 includes a fifth substrate 81 and a second wiring structure layer 82 disposed on the fifth substrate 81; the second shift register circuit 72a is electrically connected to the second wiring structure layer 82 through the signal line 21 of the telescopic bridge 2; the second shift register circuits 72a of multiple second island groups 6 are cascaded in sequence; the second wiring structure layer 82 of the second island group 6 is electrically connected to the signal line 21 of the same row of pixel island 1 to provide the light emission control signal EM.

[0139] This embodiment is equivalent to placing the second shift register circuit 72a and the wiring layout structure (second circuit structure layer 72) associated with the second shift register circuit 72a on two different islands. In this way, on the one hand, sufficient setting area can be provided for the second shift register circuit 72a and the wiring layout structure; on the other hand, the problem of mutual interference between the wiring of the second shift register circuit 72a and the wiring layout structure can be improved.

[0140] Optionally, the second shift register island 7 is connected to multiple telescopic bridges 2 of the same number on both sides along the first direction X, and the telescopic bridge 2 located between the second shift register island 7 and the second transition island 8 connects the second shift register island 7 and the second transition island 8; the second shift register island 7 is also connected to multiple telescopic bridges 2 of the same number on both sides along the second direction Y, and two adjacent second shift register islands 7 along the second direction Y are connected by the telescopic bridge 2 between them. In this way, the tensile force of the second shift register island 7 in the first direction X and the second direction Y is more balanced, improving the tensile performance of the stretchable display panel 1000.

[0141] Optionally, multiple second island groups 6 are located on the side of multiple first island groups 3 facing away from pixel island 1 along the first direction X. This can improve the problem of mutual interference between the wiring of the first island groups 3 and the second island groups 6.

[0142] In one embodiment, the second shift register island 7 is connected to four telescopic bridges 2 on both sides along the first direction X.

[0143] Of the four telescopic bridges 2 connected to the side of the second shift register island 7 near the second transition island 8, two of the telescopic bridges 2 serve as second output signal lines 2122, and two of the telescopic bridges 2 serve as first input signal lines 2123. Both the second output signal lines 2122 and the first input signal lines 2123 are electrically connected to the second shift register circuit 72a and the second wiring structure layer 82. The signal lines 21 of the four telescopic bridges 2 connected to the side of the second shift register island 7 away from the second transition island 8 are all virtual signal lines 2124. The second output signal line 2122 transmits the light emission control signal EM, and the first input signal line 2123 transmits the start signal EIN. By setting the virtual signal lines 2124, the tensile force of the second shift register island 7 in the first direction X can be made more balanced.

[0144] Optionally, the second shift register island 7 is connected to four telescopic bridges 2 on both sides along the second direction Y.

[0145] The signal lines 21 of the four telescopic bridges 2 on one side of the second shift register island 7 along the second direction Y are paired with the signal lines 21 of the four telescopic bridges 2 on the other side of the second shift register island 7 along the second direction Y. The signal lines 21 of the four telescopic bridges 2 on the second side of the second shift register island 7 along the second direction Y are respectively the third clock signal line 2125, the fourth clock signal line 2126, the third potential line 2127, and the fourth potential line 2128. The third clock signal line 2125, the fourth clock signal line 2126, the third potential line 2127, and the fourth potential line 2128 are all electrically connected to the second shift register circuit 72a. Among them, the third clock signal line 2125 transmits the third clock signal ECK1, the fourth clock signal line 2126 transmits the fourth clock signal ECK2, the third potential line 2127 transmits the high-level signal VGH, and the fourth potential line 2128 transmits the low-level signal VGL.

[0146] The above configuration allows the number of telescopic bridges 2 on both sides of the second shift register island 7 along the second direction Y to be equal to the number of telescopic bridges 2 on both sides of the second shift register island 7 along the first direction X, making the stretching ratio of the second shift register island 7 in the first direction X and the second direction Y more consistent, thus improving the stretching performance.

[0147] In one embodiment, the second transition island 8 is connected to the same number of telescopic bridges 2 on both sides along the first direction X; the second transition island 8 is connected to the same number of telescopic bridges 2 on both sides along the second direction Y, and two adjacent second transition islands 8 along the second direction Y are connected by the telescopic bridges 2 between them.

[0148] Optionally, the second transition island 8 is connected to four telescopic bridges 2 on both sides along the first direction X, and the second transition island 8 is connected to four telescopic bridges 2 on both sides along the second direction Y.

[0149] The above configuration allows the number of telescopic bridges 2 on both sides of the second transition island 8 along the second direction Y to be equal to the number of telescopic bridges 2 on both sides of the second transition island 8 along the first direction X, making the tensile ratio of the second transition island 8 in the first direction X and the second direction Y more consistent, thus improving the tensile performance.

[0150] Optionally, the second wiring structure layer 82 includes a fourth adapter structure 821, which is connected to one of the four telescopic bridges 2 on the side of the second adapter island 8 away from the second shift register island 7 along the second direction Y. The signal line 21 of one telescopic bridge 2 is the second light-emitting signal line 2111, and the signal lines 21 of the three telescopic bridges 2 are the seventh signal transmission line 2129. The second light-emitting signal line 2111 and a second output signal line 2122 located between the second shift register island 7 and the second adapter island 8 are both connected to the fourth adapter structure 821.

[0151] The above arrangement allows for a reasonable layout of the second light-emitting signal line 2111 and the second output signal line 2122, avoiding mutual interference between the signal lines 21.

[0152] Optionally, referring to Figures 12 and 13, among the four telescopic bridges 2 connected to two adjacent second transition islands 8, the signal lines 21 of two telescopic bridges 2 are eighth signal transmission lines 2130, and the signal lines 21 of two telescopic bridges 2 are virtual signal lines 2124; the eighth signal transmission lines 2130 are electrically connected to the second wiring structure layers 82 of the two adjacent second transition islands 8. Specifically, the eighth signal transmission lines 2130 transmit the light emission control signal EM, one eighth signal transmission line 2130 is connected to the fourth transition structure 821, and the other eighth signal transmission line 2130 is connected to a second output signal line 2122 between the second shift register island 7 and the second transition island 8 through a wiring (not shown in the figure).

[0153] The above configuration allows the number of telescopic bridges 2 on both sides of the second transition island 8 along the second direction Y to be equal to the number of telescopic bridges 2 on both sides of the second transition island 8 along the first direction X, making the tensile ratio of the second transition island 8 in the first direction X and the second direction Y more consistent, thus improving the tensile performance.

[0154] In one embodiment, as shown in FIG13, the end of the seventh signal transmission line 2129 near the first island group 3 is connected to a floating potential.

[0155] In one embodiment, as shown in FIG14, the first trace structure layer 52 further includes a third adapter structure 523, wherein the seventh signal transmission line 2129 and the second light-emitting signal lines 2111 located on both sides of the first shift register island 4 along the first direction X are connected to the third adapter structure 523. This helps to reduce resistance, thereby suppressing the delay of the light-emitting signal.

[0156] In one embodiment, referring to FIG1, the stretchable display panel 1000 includes a light-emitting area 1000a, a first circuit area 1000b, a second circuit area 1000c, a first transition area 1000d, a second transition area 1000e, and a third transition area 1000f. Pixel island 1 is located in light-emitting area 1000a, first shift register island 4 is located in first circuit area 1000b, first transition island 5 is located in first transition area 1000d, second shift register island 7 is located in second circuit area 1000c, second transition island 8 is located in second transition area 1000e, and third transition island 9 is connected between first transition island 5 and pixel island 1, and is located in third transition area 1000f.

[0157] In one embodiment, referring to FIG3, the pixel circuit group 12a includes a plurality of pixel circuits 12a1. Each pixel circuit 12a1 includes a driving transistor 12a15, a data writing module 12a14, a threshold compensation module 12a12, and a gate initialization module 12a13. The driving transistor 12a15 is used to provide a driving current to the light-emitting element 131 in the light-emitting device layer 13. The first terminal of the data writing module 12a14 is used to receive a data signal, and the second terminal of the data writing module 12a14 is connected to the first terminal of the driving transistor 12a15. The data writing module 12a14 is used to write the data signal to the control terminal of the driving transistor 12a15 in response to a data control signal. The threshold compensation module 12a12 includes a threshold compensation transistor M3. The first terminal of the threshold compensation transistor M3 is connected to the second terminal of the driving transistor 12a15, and the second terminal of the threshold compensation transistor M3 is connected to the control terminal of the driving transistor 12a15. It is used to compensate the threshold voltage of the driving transistor 12a15 in response to a second scan signal. The gate initialization module 12a13 includes a gate initialization transistor M4. The first terminal of the gate initialization transistor M4 is connected to the control electrode of the driving transistor 12a15, and the second terminal of the gate initialization transistor M4 is connected to the cathode power supply signal terminal 12a112 and / or the reset signal terminal 12a111, for initializing the gate voltage of the driving transistor 12a15 in response to the first scan signal.

[0158] Optionally, the pixel circuit 12a1 further includes a first leakage current suppression module 12a16, the first end of which is connected to the node position of the threshold compensation transistor M3, and the second end of which is connected to the cathode power supply signal terminal 12a112 and / or the reset signal terminal 12a111, for reducing the leakage current of the threshold compensation transistor M3.

[0159] Optionally, the first leakage current suppression module 12a16 includes a first capacitor C1, the first end of the first capacitor C1 is connected to the node position of the threshold compensation transistor M3, and the second end of the first capacitor C1 is connected to the cathode power supply signal terminal 12a112 and / or the reset signal terminal 12a111.

[0160] Optionally, the pixel circuit 12a1 further includes a second leakage current suppression module 12a17. The first end of the second leakage current suppression module 12a17 is connected to the node position of the gate initialization transistor M4, and the second end of the second leakage current suppression module 12a17 is connected to the cathode power supply signal terminal 12a112 and / or the reset signal terminal 12a111, for reducing the leakage current of the gate initialization transistor M4.

[0161] Optionally, the second leakage current suppression module 12a17 includes a second capacitor C2, the first end of which is connected to the node position of the gate initialization transistor M4, and the second end of which is connected to the cathode power supply signal terminal 12a112 and / or the reset signal terminal 12a111.

[0162] In one embodiment, as shown in FIG15, the first shift register circuit 42a includes transistors M1, M2, M3, M4, M5, M6, M7, M8, capacitor C1, and capacitor C2.

[0163] The first terminal of transistor M1 is electrically connected to the input terminal of the first start signal SIN. The control terminal of transistor M1 is electrically connected to the input terminal of the first clock signal SCK1. The second terminal of transistor M1 is electrically connected to node N1. The control terminal of transistor M4, the first terminal of transistor M2, and the first terminal of transistor M8 are all electrically connected to node N1. The control terminal of transistor M2 is electrically connected to the input terminal of the second clock signal SCK2. The second terminal of transistor M2 is electrically connected to the first terminal of transistor M3. The second terminal of transistor M3 is electrically connected to the input terminal of the high-level signal VGH. The control terminal of transistor M3 is electrically connected to node N3. The second terminal of transistor M4, the second terminal of transistor M5, the first terminal of capacitor C1, and the control terminal of transistor M6 are all electrically connected to node N3. The first terminal of transistor M4 is electrically connected to the input terminal of the first clock signal SCK1. The first terminal of transistor M5 is electrically connected to the input terminal of the low-level signal VGL. The control terminal of transistor M5 is electrically connected to the input terminal of the first clock signal SCK1. The control electrode of transistor M8 is electrically connected to the low-level signal VGL input terminal. The second electrode of transistor M8, the first electrode of capacitor C2, and the control electrode of transistor M7 are all electrically connected to node N2. The second electrode of capacitor C1 and the first electrode of transistor M6 are both electrically connected to the high-level signal VGH input terminal. The second electrodes of transistor M6, capacitor C2, and M7 are all electrically connected to the output terminal GOUT of the first shift register circuit 42a. The first electrode of transistor M7 is electrically connected to the second clock signal SCK2 input terminal.

[0164] In one embodiment, as shown with reference to FIG16, the second shift register circuit 72a includes transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, capacitors C1, C2, and C3.

[0165] The first terminal of transistor M1 is electrically connected to the input terminal of the start signal EIN. The control terminal of transistor M3, the control terminal of transistor M1, and the first terminal of transistor M2 are all electrically connected to the input terminal of the third clock signal ECK1. The first terminal of transistor M8, the control terminal of transistor M5, the control terminal of transistor M7, and the first terminal of capacitor C2 are all electrically connected to the input terminal of the fourth clock signal ECK2. The control terminals of transistor M13 and transistor M12 are both electrically connected to the input terminal of the low-level signal VGL. The first terminals of transistor M4, M6, M9, and capacitor C3 are all electrically connected to the input terminal of the high-level signal VGH. The second terminal of transistor M1, the control terminal of transistor M2, the first terminal of transistor M5, the control terminal of transistor M6, and the first terminal of transistor M11 are all electrically connected. The second terminal of transistor M11, the second terminal of capacitor C2, and the control terminal of transistor M10 are all electrically connected. The second terminal of transistor M3, the second terminal of transistor M2, and the first terminal of transistor M13 are all electrically connected. The second terminal of transistor M13, the first terminal of transistor M12, the first terminal of capacitor C1, and the control terminal of transistor M8 are all electrically connected. The second terminal of transistor M12 and the control terminal of transistor M4 are electrically connected. The second terminal of capacitor C1, the second terminal of transistor M8, and the first terminal of transistor M7 are all electrically connected. The second terminal of transistor M7, the second terminal of capacitor C3, the control terminal of transistor M9, and the second terminal of transistor M6 are all electrically connected. The second terminals of transistor M9 and transistor M10 are both electrically connected to the output terminal of the second shift register circuit 72a.

[0166] Referring to Figure 17, the first start signal SIN, the high-level signal VGH, the second clock signal SCK2, the first clock signal SCK1, and the low-level signal VGL are input to the first shift register circuit 42a (Scan). The first shift register circuit 42a (Scan) outputs the first scan signal S1 to the light-emitting elements 131 in the same row (or the same level), and outputs the first start signal SIN to the next-level first shift register circuit 42a (Scan), and outputs the second scan signal S2 to the light-emitting elements 131 in the previous row (or the previous level). The start signal EIN, the fourth clock signal ECK2, the high-level signal VGH, the low-level signal VGL, and the third clock signal ECK1 are input to the second shift register circuit 72a (EM). The second shift register circuit 72a (EM) outputs the light-emitting control signal EM to the light-emitting elements 131 in the same row (or the same level), and outputs the start signal EIN to the next-level second shift register circuit 72a (EM).

[0167] Referring to Figure 18, the first substrate 11 of the pixel island 1 is provided with an active layer AL, a gate insulating layer GI, a first metal layer Metal1, a capacitor insulating layer CI, a second metal layer Metal2, an interlayer dielectric layer ILD, a third metal layer Metal3, a planarization layer PLN, and a pixel limiting layer PDL, which are stacked together.

[0168] Secondly, embodiments of this application provide a display device including the stretchable display panel in any of the embodiments of the first aspect.

[0169] The display device can be a laptop computer, mobile phone, wireless device, personal digital assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car display (e.g., odometer display), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, etc.

[0170] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0171] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A stretchable display panel, wherein, include: Multiple pixel islands are arranged in rows along a first direction and in columns along a second direction that intersects with the first direction; The pixel island includes a first substrate and a driving array layer and a light-emitting device layer disposed on the first substrate. The driving array layer forms a pixel circuit group, and the pixel circuit group includes multiple signal terminals. Multiple telescopic bridges are provided, some of which connect to adjacent pixel islands in a first direction, and some of which connect to adjacent pixel islands in a second direction. Each pixel island has an equal number of telescopic bridges connected to both sides in the first direction, and an equal number of telescopic bridges connected to both sides in the second direction. Each telescopic bridge includes a signal line, and the signal line of each telescopic bridge connected to the pixel island is electrically connected to a corresponding signal terminal of each pixel circuit group of the pixel island. Of all the signal lines electrically connected to the pixel circuit group, at least one of the signal lines is electrically connected to two different signal terminals of the pixel circuit group.

2. The stretchable display panel according to claim 1, wherein, The pixel circuit group includes multiple pixel circuits; One of the signal lines is electrically connected to the reset signal terminal and the cathode power supply signal terminal of the pixel circuit; another of the signal lines is electrically connected to the second scan signal terminal and the third scan signal terminal of the pixel circuit; or, one of the signal lines is electrically connected to the reset signal terminal and the cathode power supply signal terminal of the pixel circuit; or, one of the signal lines is electrically connected to the second scan signal terminal and the third scan signal terminal of the pixel circuit. The signal lines of the multiple telescopic bridges on one side of the pixel island along the first direction are arranged in pairs, corresponding one-to-one with the signal lines of the multiple telescopic bridges on the other side of the pixel island along the first direction; the signal lines of the multiple telescopic bridges on one side of the pixel island along the second direction are arranged in pairs, corresponding one-to-one with the signal lines of the multiple telescopic bridges on the other side of the pixel island along the second direction.

3. The stretchable display panel according to claim 2, wherein, The multiple signal lines electrically connected to the pixel circuit group include two first power signal lines for transmitting a first power signal and two second scan signal lines for transmitting a second scan signal; the second scan signal is used to control the data writing of the pixel circuit. The telescopic bridges corresponding to the two first power signal lines are respectively connected to both sides of the pixel island along the first direction, and the two first power signal lines are electrically connected to the reset signal terminal and cathode power signal terminal of each pixel circuit; the telescopic bridges corresponding to the two second scan signal lines are respectively connected to both sides of the pixel island along the first direction, and the two second scan signal lines are electrically connected to the second scan signal terminal and third scan signal terminal of each pixel circuit.

4. The stretchable display panel according to claim 3, wherein, The multiple signal lines electrically connected to the pixel circuit group also include two first scan signal lines for transmitting a first scan signal. The telescopic bridges corresponding to the two first scan signal lines are respectively connected to both sides of the pixel island along the first direction, and the two first scan signal lines are electrically connected to the first scan signal terminals of each pixel circuit. The first scan signal is used to control the writing of the gate signal of the driving transistor of the pixel circuit. The multiple signal lines electrically connected to the pixel circuit group also include two first light-emitting signal lines. The telescopic bridges corresponding to the two first light-emitting signal lines are respectively connected to both sides of the pixel island along the first direction, and the two first light-emitting signal lines are electrically connected to the light-emitting signal terminals of each pixel circuit.

5. The stretchable display panel according to claim 3, wherein, The multiple signal lines electrically connected to the pixel circuit group also include two second power signal lines. The telescopic bridges corresponding to the two second power signal lines are respectively connected to both sides of the pixel island along the second direction, and the two second power signal lines are electrically connected to the anode power signal terminals of each pixel circuit. The light-emitting device layer includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The plurality of pixel circuits in the same pixel circuit group include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit is electrically connected to the first light-emitting element, the second pixel circuit is electrically connected to the second light-emitting element, and the third pixel circuit is electrically connected to the third light-emitting element. The multiple signal lines electrically connected to the pixel circuit group also include two first data signal lines, two second data signal lines, and two third data signal lines; the telescopic bridges corresponding to the two first data signal lines are respectively connected to both sides of the pixel island along the second direction, and the two first data signal lines are electrically connected to the data signal terminals of the first pixel circuit; the telescopic bridges corresponding to the two second data signal lines are respectively connected to both sides of the pixel island along the second direction, and the two second data signal lines are electrically connected to the data signal terminals of the second pixel circuit; the telescopic bridges corresponding to the two third data signal lines are respectively connected to both sides of the pixel island along the second direction, and the two first data signal lines are electrically connected to the data signal terminals of the third pixel circuit.

6. The stretchable display panel according to claim 4, wherein, The driving array layer includes a first connection line, which connects two first power signal lines on both sides of the pixel island along the first direction, and the first connection line is electrically connected to the reset signal terminal and the cathode power signal terminal of the pixel circuit.

7. The stretchable display panel according to claim 6, wherein, The pixel circuit includes a threshold compensation transistor, and the orthographic projection of the first connection line on the first substrate and the orthographic projection of the active layer of the threshold compensation transistor on the first substrate have an overlapping area and together form a first capacitor. Alternatively, the pixel circuit includes a gate initialization transistor, wherein the orthographic projection of the first connection line on the first substrate and the orthographic projection of the active layer of the gate initialization transistor on the first substrate have an overlapping area and together form a second capacitor; Alternatively, the pixel circuit includes a threshold compensation transistor, wherein the orthographic projection of the first connection line on the first substrate and the orthographic projection of the active layer of the threshold compensation transistor on the first substrate have an overlapping area and together form a first capacitor; The pixel circuit includes a gate initialization transistor, and the orthographic projection of the first connection line on the first substrate and the orthographic projection of the active layer of the gate initialization transistor on the first substrate have an overlapping area, and together form a second capacitor.

8. The stretchable display panel according to claim 7, wherein, The driving array layer also includes a second connection line and a third connection line; The second connecting line connects the two second scanning signal lines on both sides of the pixel island along the first direction, and the second connecting line is electrically connected to the second scanning signal terminal of each pixel circuit; one end of the third connecting line is electrically connected to the second connecting line, and the other end is electrically connected to the third scanning signal terminal of each pixel circuit. The second connecting line and the third connecting line are disposed in the same layer and made of the same material, and both extend along the first direction; the driving array layer also includes a first jumper wire, which is located in a different metal film layer from the second connecting line. One end of the first jumper wire is electrically connected to the second connecting line, and the other end is electrically connected to the third connecting line.

9. The stretchable display panel according to claim 8, wherein, The driving array layer further includes a fourth connection line, which connects the two first light-emitting signal lines on both sides of the pixel island along the first direction, and the fourth connection line is electrically connected to the light-emitting signal terminal of each pixel circuit. The orthographic projection of the fourth connecting line on the first substrate overlaps with the orthographic projection of the first jumper line on the first substrate.

10. The stretchable display panel according to claim 5, wherein, The driving array layer further includes a first connection structure, which includes a wiring mesh and two first adapter wires. The two first adapter wires are respectively connected to both sides of the wiring mesh along the second direction, and the two first adapter wires are respectively electrically connected to the corresponding second power signal lines. The anode signal terminal of each pixel circuit is electrically connected to the wiring mesh.

11. The stretchable display panel according to claim 10, wherein, The driving array layer also includes a fifth connection line, a sixth connection line, and a seventh connection line; The fifth connecting line connects the two first data signal lines on both sides of the pixel island along the second direction, and the fifth connecting line is electrically connected to the data signal terminal of the first pixel circuit. The sixth connecting line connects the two second data signal lines on both sides of the pixel island along the second direction, and the sixth connecting line is electrically connected to the data signal terminal of the second pixel circuit. The seventh connecting line connects the two third data signal lines on both sides of the pixel island along the second direction, and the seventh connecting line is electrically connected to the data signal terminal of the third pixel circuit. The first adapter cable, the fifth connecting cable, the sixth connecting cable, and the seventh connecting cable all extend along the second direction; The dimension of any of the fifth, sixth, and seventh connecting lines along the first direction is smaller than the dimension of the first adapter line along the first direction.

12. The stretchable display panel according to claim 1, wherein, Each pixel island is connected to an even number of telescopic bridges on both sides along the first direction and on both sides along the second direction, and each telescopic bridge includes one signal line.

13. The stretchable display panel according to claim 1, wherein, The stretchable display panel further includes a plurality of first island groups arranged sequentially along the second direction; the plurality of first island groups are disposed on one side of the plurality of pixel islands along the first direction, and each first island group is correspondingly connected to a row of pixel islands; The first island group includes: The first shift register island includes a second base and a first circuit structure layer disposed on the second base, wherein the first circuit structure layer includes a first shift register circuit. A first transition island is disposed between the first shift register island and the corresponding row of pixel islands, and the first transition island and the first shift register island are connected by the telescopic bridge; the first transition island includes a third substrate and a first trace structure layer disposed on the third substrate; the first shift register circuit is electrically connected to the first trace structure layer through the signal lines of the telescopic bridge; the first shift register circuits of the plurality of first island groups are cascaded in sequence; the first trace structure layer of the first island group is electrically connected to the signal lines of the pixel islands in the same row to provide a second scan signal, and is electrically connected to the signal lines of the pixel islands in the next row to provide a first scan signal; Each of the aforementioned telescopic bridges includes one of the aforementioned signal lines; The first shift register island is connected to a plurality of telescopic bridges of the same number on both sides along the first direction, and the telescopic bridge located between the first shift register island and the first transition island connects the first shift register island and the first transition island; the first shift register island is connected to a plurality of telescopic bridges of the same number on both sides along the second direction, and two adjacent first shift register islands along the second direction are connected by the telescopic bridge between them.

14. The stretchable display panel according to claim 13, wherein, The first shift register island is connected to four telescopic bridges on both sides along the first direction; Of the four telescopic bridges connected to the side of the first shift register island closest to the first adapter island, two of the telescopic bridge signal lines are first output signal lines, one telescopic bridge signal line is a first start signal line, and one telescopic bridge signal line is a second light-emitting signal line. The first output signal line and the first start signal line are both electrically connected to the first shift register circuit and the first trace structure layer. The signal line of the one telescopic bridge connected to the side of the first shift register island away from the first adapter island is a second light-emitting signal line, and the second light-emitting signal line is electrically connected to the second light-emitting signal line located on the side of the first shift register island closest to the first adapter island. The width of the first starting signal line is greater than the width of at least one of the first output signal line and the second light-emitting signal line.

15. The stretchable display panel according to claim 14, wherein, The first shift register island is connected to four telescopic bridges on both sides along the second direction; The signal lines of the four telescopic bridges on one side of the first shift register island along the second direction are paired with the signal lines of the four telescopic bridges on the other side of the first shift register island along the second direction. The signal lines of the four telescopic bridges on one side of the first shift register island along the second direction are respectively a first clock signal line, a second clock signal line, a first potential line, and a second potential line. The first clock signal line, the second clock signal line, the first potential line, and the second potential line are all electrically connected to the first shift register circuit.

16. The stretchable display panel according to claim 14, wherein, The first transition island is connected to multiple telescopic bridges of the same number on both sides along the first direction; The first transition island is connected to the same number of telescopic bridges on both sides along the second direction, and two adjacent first transition islands along the second direction are connected by the telescopic bridges between them. The first transition island is connected to four telescopic bridges on both sides along the first direction, and the first transition island is connected to four telescopic bridges on both sides along the second direction.

17. The stretchable display panel according to claim 16, wherein, The first routing structure layer includes a first adapter structure connected to four telescopic bridges on one side of the first adapter island along the second direction. The signal line of one of the telescopic bridges is a first signal transmission line, and the signal line of the other telescopic bridge is a second signal transmission line. The signal line of one of the four telescopic bridges connected to the side of the first adapter island near the pixel island is a third signal transmission line. The two first output signal lines, the first signal transmission line, the second signal transmission line, and the third signal transmission line on the first shift register island are all connected to the first adapter structure. The first signal transmission line is also electrically connected to the first trace structure layer of the next-level first island group to output a first start signal; the second signal transmission line is also electrically connected to the first trace structure layer of the next-level first island group to output a first scan signal; the third signal transmission line is also electrically connected to a signal line of the corresponding pixel island in the same row to output a second scan signal, or the third signal transmission line is connected to a floating potential.

18. The stretchable display panel according to claim 16, wherein, The first routing structure layer also includes a second adapter structure, which is connected to one of the four telescopic bridges on one side of the first adapter island along the second direction. The signal lines of two of the telescopic bridges are fourth signal transmission lines. The signal line of one of the telescopic bridges connected to the first adapter island near the pixel island is a fifth signal transmission line. Both the fourth and fifth signal transmission lines are connected to the second adapter structure. The fifth signal transmission line is electrically connected to one of the signal lines of the corresponding row of pixel islands, or the fifth signal transmission line is connected to a floating potential.

19. The stretchable display panel according to claim 16, wherein, The signal line connected to a telescopic bridge on the side of the first adapter island near the pixel island is the sixth signal transmission line. The second light-emitting signal line connected to the first adapter island is electrically connected to one end of the sixth signal transmission line, and the other end of the sixth signal transmission line is electrically connected to or connected to a signal line of the corresponding row of pixel islands.

20. The stretchable display panel according to claim 13, wherein, The stretchable display panel further includes a plurality of second island groups arranged sequentially along the second direction, the plurality of second island groups being disposed on one side of the plurality of pixel islands along the first direction; the second island groups include: The second shift register island includes a fourth base and a second circuit structure layer disposed on the fourth base, the second circuit structure layer including a second shift register circuit. The second transition island is located on the side of the second shift register island close to the first island group, and the second transition island and the second shift register island are connected through the telescopic bridge; the second transition island includes a fifth substrate and a second wiring structure layer disposed on the fifth substrate; the second shift register circuit and the second wiring structure layer are electrically connected through the signal lines of the telescopic bridge; the second shift register circuits of the plurality of second island groups are cascaded in sequence; the second wiring structure layer of the second island group is electrically connected to the signal lines of the pixel islands in the same row to provide light emission control signals; The second shift register island is connected to both sides of the first direction by a plurality of telescopic bridges of the same number. The telescopic bridge located between the second shift register island and the second transition island connects the second shift register island and the second transition island. The second shift register island is connected to both sides of the second direction by a plurality of telescopic bridges of the same number. Two adjacent second shift register islands along the second direction are connected by the telescopic bridge between them. The plurality of second island groups are located on the side of the plurality of first island groups that is away from the pixel island along the first direction.

21. The stretchable display panel according to claim 20, wherein, The second shift register island is connected to four telescopic bridges on both sides along the first direction; Of the four telescopic bridges connected to the side of the second shift register island closest to the second transition island, two of the telescopic bridges are second output signal lines, and two of the telescopic bridges are first input signal lines; both the second output signal lines and the first input signal lines are electrically connected to the second shift register circuit and the second trace structure layer; the signal lines of the four telescopic bridges connected to the side of the second shift register island away from the second transition island are all virtual signal lines; The second shift register island is connected to four telescopic bridges on both sides along the second direction; The signal lines of the four telescopic bridges on one side of the second shift register island along the second direction are paired with the signal lines of the four telescopic bridges on the other side of the second shift register island along the second direction. The signal lines of the four telescopic bridges on one side of the second shift register island along the second direction are respectively a third clock signal line, a fourth clock signal line, a third potential line, and a fourth potential line. The third clock signal line, the fourth clock signal line, the third potential line, and the fourth potential line are all electrically connected to the second shift register circuit.

22. The stretchable display panel according to claim 21, wherein, The second transition island is connected to multiple telescopic bridges of the same number on both sides along the first direction; The second transition island is connected to the same number of telescopic bridges on both sides along the second direction, and two adjacent second transition islands along the second direction are connected by the telescopic bridges between them; The second transition island is connected to four telescopic bridges on both sides along the first direction, and the second transition island is connected to four telescopic bridges on both sides along the second direction.

23. The stretchable display panel according to claim 22, wherein, The second routing structure layer includes a fourth adapter structure, which is connected to four telescopic bridges on the side of the second adapter island away from the second shift register island along the second direction. The signal line of one of the telescopic bridges is a second light-emitting signal line, and the signal lines of the three telescopic bridges are a seventh signal transmission line. The second light-emitting signal line and a second output signal line located between the second shift register island and the second adapter island are both connected to the fourth adapter structure. Of the four telescopic bridges connecting two adjacent second transition islands, the signal lines of two telescopic bridges are eighth signal transmission lines, and the signal lines of the other two telescopic bridges are virtual signal lines; the eighth signal transmission lines are electrically connected to the second wiring structure layers of the two adjacent second transition islands. The seventh signal transmission line is connected to a floating potential; or, the first trace structure layer further includes a third adapter structure, wherein the seventh signal transmission line and the second light-emitting signal lines located on both sides of the first shift register island along the first direction are both connected to the third adapter structure.

24. The stretchable display panel according to claim 1, wherein, Multiple telescopic bridges connected to both sides of the pixel island along a first direction are symmetrically arranged; multiple telescopic bridges connected to both sides of the pixel island along a second direction are symmetrically arranged. Alternatively, multiple telescopic bridges connected to both sides of the pixel island along the first direction are symmetrically arranged; Alternatively, multiple telescopic bridges connected to both sides of the pixel island along the second direction are arranged symmetrically.

25. The stretchable display panel according to any one of claims 1-24, wherein, The pixel circuit group includes multiple pixel circuits, and each pixel circuit includes: A driving transistor is used to provide driving current to the light-emitting elements in the light-emitting device layer. A data writing module, wherein a first end of the data writing module is used to receive a data signal, a second end of the data writing module is connected to the first electrode of the driving transistor, and the data writing module is used to write the data signal to the control electrode of the driving transistor in response to a data control signal. A threshold compensation module includes a threshold compensation transistor, wherein a first terminal of the threshold compensation transistor is connected to a second terminal of the driving transistor, and a second terminal of the threshold compensation transistor is connected to a control terminal of the driving transistor, for compensating the threshold voltage of the driving transistor in response to a second scan signal; A gate initialization module includes a gate initialization transistor, a first terminal of which is connected to the control electrode of the driving transistor, and a second terminal of which is connected to at least one of a cathode power supply signal terminal and a reset signal terminal, for initializing the gate voltage of the driving transistor in response to a first scan signal.

26. The stretchable display panel according to claim 25, wherein, The pixel circuit also includes: A first leakage current suppression module, wherein a first end of the first leakage current suppression module is connected to the node position of the threshold compensation transistor, and a second end of the first leakage current suppression module is connected to at least one of the cathode power supply signal terminal and the reset signal terminal, for reducing the leakage current of the threshold compensation transistor; The first leakage current suppression module includes a first capacitor, a first end of which is connected to the node position of the threshold compensation transistor, and a second end of which is connected to at least one of a cathode power supply signal terminal and a reset signal terminal.

27. The stretchable display panel according to claim 25, wherein, The pixel circuit also includes: The second leakage current suppression module has a first terminal connected to the node position of the gate initialization transistor, and a second terminal connected to at least one of the cathode power supply signal terminal and the reset signal terminal, for reducing the leakage current of the gate initialization transistor. The second leakage current suppression module includes a second capacitor, the first end of which is connected to the node position of the gate initialization transistor, and the second end of which is connected to at least one of the cathode power supply signal terminal and the reset signal terminal.

28. A stretchable display panel, wherein, include: Multiple pixel islands are arranged in rows along a first direction and in columns along a second direction that intersects with the first direction; The pixel island includes a first substrate and a driving array layer and a light-emitting device layer disposed on the first substrate. The driving array layer forms a pixel circuit group, and the pixel circuit group includes multiple signal terminals. Multiple telescopic bridges, wherein some of the telescopic bridges are connected between adjacent pixel islands in a first direction, and some of the telescopic bridges are connected between adjacent pixel islands in a second direction. The pixel islands are connected to the same number of telescopic bridges on both sides of the first direction, and the pixel islands are connected to the same number of telescopic bridges on both sides of the second direction. Each of the telescopic bridges includes a signal line, and the signal line of each of the telescopic bridges connected to the pixel island is electrically connected to each of the signal terminals of the pixel circuit group of the pixel island; among all the signal lines electrically connected to the pixel circuit group, at least one of the signal lines is electrically connected to two different signal terminals of the pixel circuit group. Multiple first island groups are arranged sequentially along the second direction; the multiple first island groups are located on one side of the multiple pixel islands along the first direction, and each first island group is connected to a row of pixel islands. The first island group includes: The first shift register island includes a second base and a first circuit structure layer disposed on the second base, wherein the first circuit structure layer includes a first shift register circuit. The first transition island is located between the first shift register island and the corresponding row of pixel islands, and the first transition island and the... The first shift register island is connected via the telescopic bridge; the first transition island includes a third substrate and a first trace structure layer disposed on the third substrate; the first shift register circuit is electrically connected to the first trace structure layer via the signal lines of the telescopic bridge; the first shift register circuits of the plurality of first island groups are cascaded sequentially; the first trace structure layer of the first island group is electrically connected to the signal lines of the pixel island in the same row to provide a second scan signal, and is electrically connected to the signal lines of the pixel island in the next row to provide a first scan signal; Multiple second island groups are arranged sequentially along the second direction; the multiple second island groups are located on one side of the multiple pixel islands along the first direction; the second island groups include: The second shift register island includes a fourth base and a second circuit structure layer disposed on the fourth base, the second circuit structure layer including a second shift register circuit. The second transition island is located on the side of the second shift register island close to the first island group, and the second transition island and the second shift register island are connected through the telescopic bridge; the second transition island includes a fifth substrate and a second wiring structure layer disposed on the fifth substrate; the second shift register circuit and the second wiring structure layer are electrically connected through the signal lines of the telescopic bridge; the second shift register circuits of the plurality of second island groups are cascaded in sequence; the second wiring structure layer of the second island group is electrically connected to the signal lines of the pixel island in the same row to provide light emission control signals.

29. A display device, wherein, Includes the stretchable display panel as described in any one of claims 1-28.

Images