Encoding method, decoding method, communication apparatus and communication system

Abstract

The present application relates to the technical field of communications. Disclosed are an encoding method, a decoding method, a communication apparatus and a communication system. On the basis of the method, a first matrix is constructed on the basis of a smaller second matrix, and the size of the first matrix may be set to be a first code length; therefore, the length of an encoded bit sequence is the same as the first code length, and then modulation can be directly performed on the basis of the encoded bit sequence without performing a rate matching operation before modulation; thus, the decoding performance can be improved. In addition, since corresponding encoding schemes may be designed for different code lengths and code rates, the solution can further improve the decoding performance. Moreover, the first matrix in the solution is constructed on the basis of the smaller second matrix, which helps to accelerate polarization without increasing the decoding complexity.

Description

An encoding method, a decoding method, a communication device, and a communication system.

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202510125847.0, filed on January 26, 2025, with the title “An Encoding Method, Decoding Method, Communication Device and Communication System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a communication system. Background Technology

[0004] Polar codes were selected as the control channel coding scheme in the 5th generation (5G) communication standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity and have the advantages of good decoding performance and low complexity.

[0005] Currently, in polar coding, a generator matrix of size N*N is generally constructed using the mother code length N. This generator matrix is ​​then used to polar code the bit sequence of information to be transmitted, resulting in a encoded bit sequence of length N. Here, N is 2 to the power of n, and n is an integer greater than or equal to 1. Due to factors such as channel conditions and available transmission resources, the actual length E of the encoded bit sequence that can be transmitted is less than N. Therefore, rate matching is required for the encoded bit sequence of length N to obtain an encoded bit sequence of length E for transmission. Here, E is also called the code length.

[0006] Current polar coding schemes require rate matching after polar coding, which leads to a decrease in decoding performance. Summary of the Invention

[0007] This application provides an encoding method, a decoding method, a communication device, and a communication system to improve decoding performance.

[0008] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the communication device. The method includes: polar coding the information bit sequence according to a first matrix to obtain an encoded bit sequence; wherein the size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1; the first matrix includes t first sub-matrices, any one of the t first sub-matrices is the same as the second matrix, or can be obtained by column interleaving the second matrix, the size of the second matrix is ​​E*E, where E represents the second code length; the number of information bits corresponding to the first matrix and the number of information bits corresponding to the second matrix are both K, 1≤K≤E-1; modulating the encoded bit sequence to obtain modulated symbol information; and outputting the modulated symbol information.

[0009] Based on the above scheme, the first matrix is ​​constructed from a smaller second matrix. The size of the first matrix can be set to a first code length, so the length of the encoded bit sequence is the same as this first code length. This allows for direct modulation based on the encoded bit sequence without the need for rate matching before modulation, thus improving decoding performance. Furthermore, since corresponding encoding schemes can be designed for different code lengths and code rates, this scheme can further improve decoding performance. Moreover, the fact that the first matrix in this scheme is constructed from a smaller second matrix facilitates faster polarization without increasing decoding complexity.

[0010] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, etc.), a component of the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the communication device. The method includes: obtaining a sequence to be decoded; polar encoding the sequence to be decoded according to a first matrix to obtain an information bit sequence; wherein, the size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1; the first matrix includes t first sub-matrices, any one of the t first sub-matrices is the same as the second matrix, or can be obtained by column interleaving the second matrix; the size of the second matrix is ​​E*E, where E represents the second code length; the number of information bits corresponding to the first matrix and the number of information bits corresponding to the second matrix are both K, 1≤K≤E-1.

[0011] Based on the above scheme, the first matrix is ​​constructed from a smaller second matrix, with the size of the first matrix set to the first code length. Therefore, the length of the encoded bit sequence is the same as this first code length. Consequently, polarization decoding can be directly performed on the sequence to be decoded based on the first matrix to obtain the information bit sequence, eliminating the need for rate matching and improving decoding performance. Furthermore, since corresponding encoding schemes can be designed for different code lengths and code rates, this scheme can further improve decoding performance. Moreover, the first matrix in this scheme is constructed from a smaller second matrix, which facilitates faster polarization without increasing decoding complexity.

[0012] Based on the first or second aspect mentioned above, there are one or more possible implementation methods as follows:

[0013] As one possible implementation, when q is greater than 0, the first matrix also includes a second submatrix, which is composed of the q columns of the second matrix.

[0014] Based on the above scheme, the flexibility of encoding can be improved, enabling encoding under various code lengths and helping to improve decoding performance.

[0015] As one possible implementation, the first matrix also includes a third submatrix and a fourth submatrix, the third submatrix being an identity matrix of size (E′-E)*(E′-E) and the fourth submatrix being a zero matrix of size (E′-E)*E.

[0016] Based on the above scheme, the form of the encoding matrix can be simplified and the storage complexity can be reduced.

[0017] As one possible implementation, the first matrix is ​​determined based on a first identity matrix and first information; wherein the first information is used to indicate multiple stages for constructing the first matrix, each of the multiple stages includes at least one integer pair and the integer pair is used to indicate adding at least one first target column of the first identity matrix to at least one second target column, the integer pairs in each of the multiple stages are completely different, the multiple integer pairs in different stages of the multiple stages are not completely different, the integer pair includes the indices of two columns, the integers in the integer pair are less than or equal to the first code length, and the size of the first identity matrix is ​​E′*E′.

[0018] Based on the above scheme, the encoding matrix can be represented by the first information, thereby reducing storage complexity.

[0019] As one possible implementation, the multiple stages indicated by the first information include h stages and t stages following the h stages;

[0020] The h stages are used to construct one of the t first submatrices, which is identical to the second matrix and located at the lower right corner of the first matrix. h is a positive integer. The r-th stage in the t stages includes integer pairs {(E′-(r+1)E+u, E′-E+a}. u )}, 1≤r≤t-1, 1≤u≤E; the t-th stage in the t-th stage includes integer pairs (v,E′-E+a) E+v-q ), 1≤v≤q; where (a1,a2,…,a E ) is a permutation of 1, 2, ..., E.

[0021] Based on the above scheme, the encoding matrix can be represented by the first information, thereby reducing storage complexity.

[0022] As one possible implementation, the second matrix is ​​determined based on a second identity matrix and second information. The size of the second identity matrix is ​​E*E. The second information is used to indicate multiple stages for constructing the second matrix. Each of the multiple stages indicated by the second information includes at least one integer pair, and the integer pair is used to indicate adding at least one third target column of the second identity matrix to at least one fourth target column. The integer pairs in each of the multiple stages indicated by the second information are completely different. The multiple integer pairs in different stages indicated by the second information are not completely different. The integer pairs in the multiple stages indicated by the second information include indices of two columns. The integers in the integer pairs in the multiple stages indicated by the second information are less than or equal to the second code length.

[0023] Based on the above scheme, the second matrix is ​​the encoding matrix of the code with better decoding performance when the code length is short. Based on the second matrix, a series of construction methods of the first matrix when the code length is longer are obtained, which ensures better decoding performance while reducing the complexity of construction and storage.

[0024] As one possible implementation, the second information indicates multiple stages comprising h stages, wherein the f-th stage among the h stages indicates by the second information comprises integer pairs {(a, a+2}}. f-1 The first information indicates that the f-th stage of the h stages includes integer pairs {(E′-E+a, E′-E+a+2)}; f-1 )}; where E = 2 K -1, 1≤f≤h, and h=K; a-1 iterates through the integers whose f-th bit is 0 in the binary numbers between 0 and E-1.

[0025] Based on the above scheme, the code spectrum can be improved, which can enhance decoding performance.

[0026] As one possible implementation, E=7, K=3, the multiple stages indicated by the second information are {(1,2),(3,4),(5,6)}, {(1,3),(2,4),(5,7)}, {(1,5),(2,6),(3,7)};

[0027] E′=7t+q,0≤q≤6, the first information indicates multiple stages as {(E′-6,E′-5),(E′-4,E′-3),(E′-2,E′-1)},{(E′-6,E′-4),(E′-5,E′-3),(E′-2,E′)},{(E′-6,E′-2),(E′-5,E′-1),(E′-4,E′)},{(E′-13,E′-6),(E′-12,E′-5),…,(E′-7,E′)},….,{(E′-7s-6,E′-6),(E′-7s-5,E′-5),…,(E′-7s,E′)},…,{(1,E′-q+1),(2, E′-q+2),…,(q,E′)}, or the multiple stages indicated by the first information are {(E′-6,E′-5),(E′-4,E′-3),(E′-2,E′-1)},{(E′-6,E′-4),(E′-5,E′-3),(E′-2,E′)},{(E′-6,E′-2),( E′-5,E′-1),(E′-4,E′)},{(E′-13,E′-6),(E′-12,E′-5),(E′-11,E′-4) ,(E′-10,E′-2),(E′-9,E′-1),(E′-8,E′),(E′-7,E′-4)},…,{(1,E′-7+a 8-q),(2,E'-7+a 9-q )…(q,E′-3)}.

[0028] Based on the above scheme, the code spectrum can be improved, which can enhance decoding performance.

[0029] As one possible implementation, the multiple stages indicated by the first information include h stages, p stages following the h stages, and t stages following the p stages; the h stages are used to construct one of the t sub-matrices, which is identical to the second matrix and located at the lower right corner of the first matrix, where h is a positive integer; the two integer pairs included in the p stages fall within the same interval, which is [E′-(y+1)E+1,E′-yE] or [1,q], 1≤y≤t-1, where p is an integer greater than 0; the r-th stage among the t stages includes the integer pair {(E′-(r+1)E+u,E′-h}. r,u E+a u )}, 1≤r≤t-1, 1≤u≤E, 1≤h r,u ≤r; The t-th stage in the t-th stage includes integer pairs (v, E′-h) r,v E+a E+v-q ), 1≤h r,v ≤t, 1≤v≤q; where (a1,a2,…,a…) E ) is a permutation of 1, 2, ..., E.

[0030] Based on the above scheme, the code spectrum can be improved, which can enhance decoding performance.

[0031] As one possible implementation, the information bit corresponding to the second matrix is ​​the x-th bit. i The information bit corresponding to the first matrix is ​​the E′-E+x bit. i Bit; where 0≤i≤K-1, x i It is an integer greater than 0 and less than or equal to E.

[0032] Based on the above scheme, the information bits of the first matrix and the second matrix can be determined. The index of the information bit corresponding to the first matrix differs from the index of the information bit corresponding to the second matrix by E′-E.

[0033] Thirdly, this application provides a communication device that performs the functions described in the first aspect. For example, the communication device includes modules, units, or means corresponding to the operations described in the first aspect. These functions, units, or means can be implemented by software, hardware, or by hardware executing corresponding software.

[0034] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the first aspect described above.

[0035] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store computer programs or instructions necessary to implement the functions described in the first aspect above. The processor may execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first aspect above, when executed.

[0036] In one possible design, the communication device includes a processor and a memory, the memory of which can store the necessary computer programs or instructions for implementing the functions described in the first aspect above. The processor can execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first aspect above.

[0037] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the first aspect described above. Optionally, the communication device further includes a memory for storing computer programs or instructions that, when executed by the processor, implement the methods in any possible design or implementation of the first aspect described above.

[0038] Understandably, the processor in the third aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0039] Fourthly, this application provides a communication device that performs the functions described in the second aspect above. For example, the communication device includes modules, units, or means for performing the operations described in the second aspect above. These functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0040] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the second aspect above.

[0041] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store computer programs or instructions necessary to implement the functions described in the second aspect above. The processor may execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the second aspect above, when the computer programs or instructions are executed.

[0042] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the second and / or fourth aspects described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the second aspect described above.

[0043] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the methods in any possible design or implementation of the second aspect described above. Optionally, the communication device further includes a memory for storing computer programs or instructions that, when executed by the processor, implement the methods in any possible design or implementation of the second aspect described above.

[0044] Understandably, the processor in the fourth aspect can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separate. In specific implementations, the memory can be integrated with the processor on the same chip, or they can be set on different chips. This application does not limit the type of memory or the way the memory and processor are set.

[0045] Fifthly, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the first aspect or any possible implementation of the first aspect, and the second communication device is used to perform the method described in the second aspect or any possible implementation of the second aspect.

[0046] In a sixth aspect, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs in the first to second aspects described above is executed.

[0047] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0048] In a seventh aspect, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to second aspects described above to be performed.

[0049] Eighthly, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any of the possible designs in the first to second aspects described above are executed. Attached Figure Description

[0050] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0051] Figure 2 is a schematic diagram of a processing flow of information source and information sink according to an embodiment of this application;

[0052] Figure 3(a) shows an 8×8 polarization transformation matrix provided in an embodiment of this application;

[0053] Figure 3(b) is a schematic diagram of the serial cancellation decoding calculation process provided in the embodiment of this application;

[0054] Figure 3(c) is a schematic diagram of the decoding path in the serial cancellation list decoding method provided in the embodiments of this application;

[0055] Figure 4 is a flowchart illustrating the encoding method provided in an embodiment of this application;

[0056] Figure 5(a) is a schematic diagram of the matrix expansion provided in an embodiment of this application;

[0057] Figure 5(b) is a schematic diagram of the simulation results provided in the embodiments of this application;

[0058] Figure 6(a) is a schematic diagram of matrix expansion provided in an embodiment of this application;

[0059] Figure 6(b) is a schematic diagram of the simulation results provided in the embodiments of this application;

[0060] Figure 7 is a schematic diagram of the simulation results provided in the embodiments of this application;

[0061] Figure 8(a) is an example diagram of the first matrix provided in an embodiment of this application;

[0062] Figure 8(b) is an example diagram of the first matrix provided in an embodiment of this application;

[0063] Figure 9 is an example diagram of constructing a second matrix provided in an embodiment of this application;

[0064] Figure 10 is a flowchart illustrating the decoding method provided in an embodiment of this application;

[0065] Figure 11 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0066] Figure 12 is a schematic diagram of another communication device provided in an embodiment of this application. Detailed Implementation

[0067] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0068] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, without limitation. This application describes the communication system shown in Figure 1 as an example. When applying the technical solution of this application to other communication systems, the devices, components, modules, etc. in the embodiment can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0069] Figure 1 is a schematic diagram of the architecture of the communication system applied in the embodiments of this application. As shown in Figure 1, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as 110a and 110b in Figure 1, and may also include at least one terminal device, such as 120a-120j in Figure 1. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop computer, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in Figure 1 are 120a, 120e, 120f and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can access micro-station 110b, connect to laptop 120g and printer 120h. Mobile phone 120j can control drone 120i.

[0070] The communication system provided in this application may also include AI network elements for implementing some or all AI-related operations. AI network elements can also be referred to as AI nodes, AI devices, AI entities, AI modules, AI models, or AI units, etc. The AI ​​network elements may be built into the network elements of the communication system. For example, an AI network element may be an AI module built into: access network equipment, core network equipment, cloud server, or operation, administration, and maintenance (OAM) to implement AI-related functions. The OAM may act as the network management system for core network equipment and / or access network equipment. Alternatively, the AI ​​network element may also be an independently configured network element in the communication system. Optionally, the terminal or its built-in chip may also include AI entities for implementing AI-related functions.

[0071] (1) Network equipment

[0072] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0073] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0074] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or equipment form used in the network equipment.

[0075] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0076] (2) Terminal equipment

[0077] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. They can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, on-board units (OBUs) or telematics boxes (T-BOXs), etc.), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0078] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0079] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0080] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device. That is, 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal device functions.

[0081] Network devices and terminal devices, network devices and network devices, and terminal devices and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0082] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0083] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0084] (1) Channel coding and channel decoding

[0085] Figure 2 illustrates a processing flow diagram for the source and sink. As shown in Figure 2, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source encoding, and then performs channel encoding on the bit sequence to be encoded to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0086] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0087] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0088] (2) Modulation and demodulation

[0089] As shown in Figure 2, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and obtain the symbol sequence to be decoded by demodulation.

[0090] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0091] (3) Information bit sequence

[0092] An information bit sequence refers to a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is 10101100101. In this application, K represents the length of the information bit sequence. The information bits may include payload bits. Optionally, the information bits may also include check bits, such as cyclic redundancy check (CRC) bits.

[0093] (4) Code length

[0094] Code length refers to the length of the bit sequence to be transmitted obtained by encoding the information bit sequence. The code length is greater than or equal to the length of the information bit sequence. In this application, E represents the code length.

[0095] (5) Bitrate

[0096] The code rate is the ratio of the length of the information bit sequence to the code length. In this application, R represents the code rate, therefore R = K / E.

[0097] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding method, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS).

[0098] (6) Rate matching

[0099] Rate matching refers to removing some bits from the encoded bit sequence without transmitting them, or repeating some bits.

[0100] The rate matching method will be further explained in three categories below.

[0101] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0102] Shortening: Shortening involves fixing certain bit positions in the encoded bit sequence so that they do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0103] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0104] Taking polar codes as an example, the encoding length (i.e., the mother code length) of a polar code is an integer power of 2. In practical applications, the required length may be a non-encoded length. In this case, it is necessary to remove some bits from the encoded bit sequence without transmitting them, or to repeatedly transmit some bits.

[0105] (7) Polar code

[0106] (7.1) Polar coding

[0107] Polar codes employ encoding strategies that utilize noiseless channels to transmit useful user information, or utilize noisy channels to transmit agreed-upon information or no information at all. The generator matrix of a polar code is G. N Its encoding process is as follows It is a binary row vector with length N; and Defined as the Kronecker product of log₂N matrices F₂, where x₁N is the encoded bit sequence (also called a codeword). With the generating matrix G N Multiplying the bits yields the encoded bit sequence; the multiplication process is the encoding process. G N Also known as an Arikan polarization nucleus of length N or a canonical polarization nucleus.

[0108] During the encoding process of polar codes, A portion of the bits are used to carry information, called the information bit set, and the set of indices of these bits is denoted as A. The other portion of the bits are set to fixed values ​​agreed upon in advance by the receiver and the transmitter, called the fixed bit set or frozen bit set, and the set of bit indices of this set is denoted by the complement of A, Ac. These frozen bits are usually set to 0, but they can be arbitrarily set as long as the receiver and the transmitter agree in advance.

[0109] Currently, in NR, the frozen bits and information bits of the polar code are determined based on the reliability sequence corresponding to the mother code length. The reliability sequence corresponding to the mother code length can be calculated offline to reduce the encoding complexity. The mother code length is an integer power of 2, which is the length of the bit sequence after polar code encoding; the mother code length can also be called the encoding length. Taking a mother code length of 8 as an example, assuming the reliability sequence is [0 1 2 4 3 5 6 7], the reliability of the bits from highest to lowest is: the bit corresponding to bit number 7, the bit corresponding to bit number 6, the bit corresponding to bit number 5, the bit corresponding to bit number 3, the bit corresponding to bit number 4, the bit corresponding to bit number 2, the bit corresponding to bit number 1, and the bit corresponding to bit number 0. Here, a bit can be understood as a bit sub-channel. The bit number can be understood as the index or identifier of the bit. For example, when constructing a polar code with a master code length of 8 and an information length of 4, the bits corresponding to bit number 7, bit number 6, bit number 5, and bit number 3 are selected from the end to the beginning as information bits, while the bits corresponding to bit number 4, bit number 2, bit number 1, and bit number 0 are selected as frozen bits.

[0110] Figure 3(a) shows an 8×8 polarization transformation matrix, where the left side can be understood as the side to be encoded, and the bits on the left are represented by u. The right side can be understood as the encoding side (or codeword side), and the bits on the right are represented by x. The process from left to right is the process of the transmitter encoding the bit sequence to be encoded. The information bits to be encoded are represented by the sequence u(0, 0, 0, 0, 0, 0, 1, 1). After the polarization transformation matrix, the encoded bits are represented by the sequence x(0, ​​1, 0, 1, 0, 1, 0, 1). Then, x is mapped to a modulation symbol for transmission in channel W. The bits corresponding to high channel reliability are used to map information bits, and the bits corresponding to low channel reliability are used to map frozen bits. As shown in Figure 3(a), {u0, u1, u2, u4} are frozen bits, i.e., the positions of frozen bits, and {u3, u5, u6, u7} are information bits, i.e., the positions of information bits. In this embodiment, information bits are also called information bits, and frozen bits are also called frozen bits.

[0111] Referring to Figure 3(a), in the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and A single XOR operation between the bits in the row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output bit (with a value of 0).

[0112] (7.2) Polarization Decoding

[0113] There are several methods for decoding polar codes, such as successive cancellation (SC) decoding and successive cancellation list (SCL) decoding.

[0114] The SC decoding method refers to calculating the LLR of each decoded bit sequentially based on the LLR sequence corresponding to the bit sequence to be decoded, and making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit is greater than 0, then the decoded bit is 0; if the LLR of the decoded bit is less than 0, then the decoded bit is 1. When the decoded bit is a fixed bit, the decoding result is set to 0 regardless of the LLR value. Figure 3(b) is a schematic diagram of the SC decoding calculation process. Taking 4 decoded bits as an example, there are 8 calculation nodes in Figure 3(b), including 4 f nodes and 4 g nodes. The f nodes and g nodes correspond to the f operation and the g operation, respectively. The operation of the f node requires the two LLR inputs on its right side, and the operation of the g node requires the two LLR inputs on its right side and the output of the previous stage as inputs. Only after the input items are calculated can the output be calculated. According to the above calculation rules, the decoded bits obtained by calculating sequentially from the right side in Figure 3(b) are ①→②→③→④, and the decoding is completed.

[0115] The SCL decoding method refers to using the LLR sequence corresponding to the bit sequence to be decoded. When decoding each information bit, the decoding results corresponding to 0 and 1 are saved as two branch decoding paths (referred to as path splitting). Figure 3(c) shows a schematic diagram of the decoding paths in the SCL decoding method. As shown in Figure 3(c), each level represents one decoded bit. If the decoding result is 0, the path is developed along the left subtree; if the decoding result is 1, the path is developed along the right subtree. When the total number of decoding paths exceeds the preset path width L (generally L = 2, 4, 8, 16, or 32), the L paths with the best path metric (PM) value are selected, saved, and the path is further developed to decode subsequent bits. The PM value is used to judge the quality of the path, and the PM value is calculated using LLR. For each level of decoded bits, the PM values ​​of the L paths are sorted in ascending order, and the correct path is selected based on the PM value. This process is repeated until the last bit is decoded.

[0116] Polar codes have been selected as the control channel coding scheme in 5G communication standards. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity and have the advantages of good decoding performance and low complexity.

[0117] Currently, in polar coding, a generator matrix of size N*N is generally constructed using the mother code length N. This generator matrix is ​​then used to polar code the bit sequence of information to be transmitted, resulting in a encoded bit sequence of length N. Here, N is 2 to the power of n, and n is an integer greater than or equal to 1. Due to factors such as channel conditions and available transmission resources, the actual length E of the encoded bit sequence that can be transmitted is less than N. Therefore, rate matching is required for the encoded bit sequence of length N to obtain an encoded bit sequence of length E for transmission. Here, E is also called the code length.

[0118] Current polar coding schemes require rate matching after polar coding, which leads to a decrease in decoding performance.

[0119] To address the aforementioned issues, this application provides corresponding solutions.

[0120] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the term "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. Similarly, the term "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0121] Figure 4 is a flowchart illustrating an encoding method provided in an embodiment of this application. This method is an implementation method on the encoding side, and includes the following steps:

[0122] Step 401: The first communication device performs polarization encoding on the information bit sequence according to the first matrix to obtain the encoded bit sequence.

[0123] For example, step 401 may be: the first communication device obtains a bit sequence of length E to be encoded based on the information bit sequence, and multiplies the bit sequence to be encoded with the first matrix to obtain the encoded bit sequence.

[0124] The size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1. E is an integer greater than 1, and t and q are both integers. The length of the encoded bit sequence is equal to the first code length E′.

[0125] The first matrix includes t first submatrices. Any of the t first submatrices is the same as the second matrix, or can be obtained by column interleaving of the second matrix. The size of the second matrix is ​​E*E, where E represents the second code length.

[0126] Where E′ can be equal to a positive integer power of 2 or not, and the first code length E′ in this application can be any integer greater than 1. E can be equal to a positive integer power of 2 or not, and the second code length E in this application can be any integer greater than 1.

[0127] For example, when q is greater than 0, the first matrix also includes a second submatrix, which is composed of q columns of the second matrix. That is, the matrix composed of q columns of the second matrix is ​​the second submatrix. The q columns can be continuous or discontinuous.

[0128] For example, the first matrix also includes a third submatrix and a fourth submatrix, the third submatrix being an identity matrix of size (E′-E)*(E′-E) and the fourth submatrix being a zero matrix of size (E′-E)*E.

[0129] It can be seen that the first matrix can be obtained by extending the second matrix.

[0130] In this application, the number of information bits corresponding to the first matrix and the second matrix are both K, where 1 ≤ K ≤ E-1. This application does not limit the specific positions of the K information bits corresponding to the first matrix, nor does it limit the specific positions of the K information bits corresponding to the second matrix. K is also the length of the information bit sequence.

[0131] For example, the K information bits corresponding to the first matrix and the K information bits corresponding to the second matrix have the following relationship: the information bit corresponding to the second matrix is ​​the x-th information bit. i The information bit corresponding to the first matrix is ​​the E′-E+xth bit. i Bits. Where 0≤i≤K-1, x i It is an integer greater than 0 and less than or equal to E.

[0132] Step 402: The first communication device modulates the encoded bit sequence to obtain modulated symbol information.

[0133] This application does not limit the specific implementation method of modulation; relevant solutions in the prior art can be referred to, and will not be elaborated here.

[0134] Step 403: The first communication device outputs the modulated symbol information.

[0135] The modulated symbol information output here can be sent to the second communication device via the air interface, or it can be output to the transceiver of the first communication device via the input / output interface, and the transceiver can then send the corresponding signal to the second communication device via the air interface.

[0136] Based on the above scheme, the first matrix is ​​constructed from a smaller second matrix. The size of the first matrix can be set to a first code length, so the length of the encoded bit sequence is the same as this first code length. This allows for direct modulation based on the encoded bit sequence without the need for rate matching before modulation, thus improving decoding performance. Furthermore, since corresponding encoding schemes can be designed for different code lengths and code rates, this scheme can further improve decoding performance. Moreover, the fact that the first matrix in this scheme is constructed from a smaller second matrix facilitates faster polarization without increasing decoding complexity.

[0137] This application does not limit the specific implementation method of constructing the first matrix based on the second matrix. The bitrate corresponding to the first matrix is ​​equal to K / E′, and the bitrate corresponding to the second matrix is ​​equal to K / E. Compared to the second matrix, the bitrate corresponding to the first matrix is ​​lower; therefore, the process of constructing the first matrix based on the second matrix can also be understood as the process of constructing a low-bitrate matrix.

[0138] As one implementation method, the first matrix is ​​determined based on the first identity matrix and first information. The first information indicates multiple stages for constructing the first matrix. Each stage includes at least one integer pair, and each integer pair indicates adding at least one first target column from the first identity matrix to at least one second target column. Here, "bit addition" refers to binary addition between bits, i.e., an XOR operation. The integer pairs within each stage are completely different, and the integer pairs within different stages are not identical. Each integer pair includes two column indices, and the integers in each pair are less than or equal to the first code length E′. The size of the first identity matrix is ​​E′*E′. Each column corresponds to a polarization sub-channel, and the column index can also be the index of the polarization sub-channel.

[0139] For example, the multiple stages indicated by the first information include h stages and t stages following the h stages. These h stages are used to construct one of the t first submatrices within the first matrix, which is identical to the second matrix and located at the lower right corner of the first matrix, where h is a positive integer. The r-th stage among these t stages includes integer pairs {(E′-(r+1)E+u, E′-E+a}. u )}, 1≤r≤t-1, 1≤u≤E. The t-th stage in the t-th stage includes integer pairs (v, E′-E+a) E+v-q ), 1≤v≤q. Where, (a1,a2,…,a…) E ) is a permutation of 1, 2, ..., E.

[0140] This application does not limit the construction method of the second matrix. The second matrix can be predefined or determined based on the second identity matrix and second information. The size of the second identity matrix is ​​E*E. The second information is used to indicate multiple stages in constructing the second matrix. Each stage indicated by the second information includes at least one integer pair, and each integer pair is used to indicate adding at least one third target column of the second identity matrix to at least one fourth target column. Here, "addition" refers to binary addition, i.e., XOR operation. The integer pairs in each stage indicated by the second information are completely different, and the integer pairs in different stages indicated by the second information are not completely different. Each integer pair in each stage indicated by the second information includes indices of two columns, and the integers in each integer pair in each stage indicated by the second information are less than or equal to the second code length E.

[0141] For example, the multiple stages indicated by the second information include h stages, and the f-th stage among the h stages indicated by the second information includes integer pairs {(a, a+2)}. f-1 )}, and the f-th stage among the h stages indicated by the first information includes integer pairs {(E′-E+a, E′-E+a+2)}. f-1 )}. Where, E = 2 K -1, 1≤f≤h, and h=K. a-1 iterates through the binary numbers from 0 to E-1 where the f-th bit is 0. At this point, it can be considered that the binary numbers of length E=2 K -1, constructing a non-regularly polarized kernel of length E′ with K information bits from a simpleplex kernel of length K. This simpleplex kernel corresponds to the second matrix, and this non-regularly polarized kernel corresponds to the first matrix. The simpleplex kernel is constructed from a matrix of length 2... K The Arikan polarization kernel is obtained by shortening the last element, that is, by deleting the last row and the last column of the matrix corresponding to the Arikan polarization kernel to obtain the matrix corresponding to the simplex kernel. Using the language of non-regular polarization kernels, it can be described as T1={(1,2)(3,4)…(2 K -3,2 K -2)},{(1,3)(2,4)…(2 K -3,2 K -1)},…,{(1,2 K-1 +1)(2,2 K-1 +2)…(2 K-1 -1,2 K -1)}. Where T1 represents the simplex core. The information bits of this simplex core are the 2nd... K -2 iBits, 0≤i≤K-1. Correspondingly, the non-regular polarization kernel T1′ of length E′=tE+q and number of information bits K is of length E=2 K -1, obtained by expanding a simplex kernel T1 with K information bits, and the expansion order is (a1,…,a…). E () is a permutation of 1, 2, ..., E. The information bits of the non-canonical polarization kernel T1′ are the (E′+1-2)th bits. i For each bit, 0 ≤ i ≤ K-1.

[0142] The first matrix in this application can also be called a non-regular polarization kernel, or all integer pairs indicated by the first information can be called a non-regular polarization kernel. The second matrix in this application can also be called a non-regular polarization kernel, or all integer pairs indicated by the second information can be called a non-regular polarization kernel.

[0143] The following explanation uses three different examples.

[0144] Example 1

[0145] E=7, K=3, the second information indicates multiple stages as {(1,2),(3,4),(5,6)}, {(1,3),(2,4),(5,7)}, {(1,5),(2,6),(3,7)}.

[0146] E′=7t+q,0≤q≤6, the multiple stages indicated by the first information are {(E′-6,E′-5),(E′-4,E′-3),(E′-2,E′-1)},{(E′-6,E′-4),(E′-5,E′-3),(E′-2,E′)},{(E′-6,E′-2),(E′-5,E′-1),(E′-4,E′)},{(E′-13,E′-6),(E′-12,E′-5),…,(E′-7,E′)},….,{(E′-7s-6,E′-6),(E′-7s-5,E′-5),…,(E′-7s,E′)},…,{(1,E′-q+1),(2,E′-q+2),…,(q,E′)}.

[0147] In Example 1, the first matrix is ​​obtained by expanding the second matrix using the natural order (1,2,3,4,5,6,7). Example 1 can also be understood as follows: the non-regular polarization kernel E′=7t+q, 0≤q≤6, K=3 is expanded from the non-regular polarization kernel E=7, K=3, with the expansion order (1,2,3,4,5,6,7). This can be understood as follows: based on h stages of the multiple stages indicated by the first information, the lower right corner of the identity matrix of size E′*E′ can be transformed into a second matrix of size 7*7. Then, after t stages, the element values ​​of the first matrix, excluding the second matrix, are constructed, and these element values ​​are related to the second matrix.

[0148] Figure 5(a) is a schematic diagram of the matrix expansion corresponding to Example 1. In this example, E = 7, K = 3, t = 2, q = 2, E′ = 16. Bits 13, 15, and 16 are information bits, corresponding to rows 13, 15, and 16 of the first matrix from top to bottom. The matrix within the dashed box in the lower right corner of Figure 5(a) is the second matrix. This second matrix is ​​constructed using h stages indicated by the first information. The element values ​​of the other two dashed boxes in Figure 5(a) are constructed using t stages indicated by the first information and are related to the column values ​​of the second matrix. For example, if the expansion order is (1,2,3,4,5,6,7), then the first submatrix indicated within the middle dashed box is the same as the second matrix, and the two columns within the first dashed box are the same as columns 6 and 7 of the second matrix.

[0149] Figure 5(b) shows the simulation results for Example 1. The vertical axis represents the signal-to-noise ratio (SNR), and the horizontal axis represents the first code length E′. In this example, the SC decoding method is used, and the block error ratio (BLER) is 10. -2 It can be seen that, compared with the scheme of polar coding after shortening the Arikan polarization kernel order and the scheme of polar coding after puncturing the Arikan polarization kernel, Example 1 of this application has a smaller SNR under the same E′ and the same BLER requirement. Therefore, the scheme of Example 1 of this application can improve the code spectrum and enhance decoding performance. Furthermore, the expansion order used in Example 1 is (1,2,3,4,5,6,7), so the column order of the matrix is ​​not changed during expansion, making it simpler to implement.

[0150] Example 2

[0151] E=7, K=3, the second information indicates multiple stages as {(1,2),(3,4),(5,6)}, {(1,3),(2,4),(5,7)}, {(1,5),(2,6),(3,7)}.

[0152] E′=7t+q, 0≤q≤6, the multiple stages indicated by the first information are {(E′-6,E′-5),(E′-4,E′-3),(E′-2,E′-1)},{(E′-6,E′-4),(E′-5,E′-3),(E′-2,E′)},{(E′-6,E′-2),(E′-5 ,E′-1),(E′-4,E′)},{(E′-13,E′-6),(E′-12,E′-5),(E′-11,E′-4),( E′-10,E′-2),(E′-9,E′-1),(E′-8,E′),(E′-7,E′-4)},…,{(1,E′-7+a 8-q ),(2,E'-7+a 9-q )…(q,E′-3)}.

[0153] In Example 2, the first matrix is ​​obtained by expanding the second matrix using the natural order (1,2,3,5,6,7,4). Example 2 can also be understood as follows: the non-regular polarization kernel E′=7t+q, 0≤q≤6, K=3 is expanded from the non-regular polarization kernel E=7, K=3, with the expansion order (1,2,3,5,6,7,4). This can be understood as follows: based on h stages of the multiple stages indicated by the first information, the lower right corner of the identity matrix of size E′*E′ can be transformed into a second matrix of size 7*7. Then, after t stages, the element values ​​of the first matrix, excluding the second matrix, are constructed, and these element values ​​are related to the second matrix.

[0154] Figure 6(a) is a schematic diagram of the matrix expansion corresponding to Example 2. In this example, E = 7, K = 3, t = 2, q = 2, E′ = 16. Bits 13, 15, and 16 are information bits, corresponding to rows 13, 15, and 16 of the first matrix from top to bottom. The matrix within the dashed box in the lower right corner of Figure 6(a) is the second matrix, constructed using h stages indicated by the first information. The element values ​​of the other two dashed boxes in Figure 6(a) are constructed using t stages indicated by the first information and are related to the column values ​​of the second matrix. For example, if the expansion order is (1,2,3,5,6,7,4), then the columns of the first sub-matrix indicated in the middle dashed box are identical from left to right to columns 1, 2, 3, 5, 6, 7, and 4 of the second matrix, and the two columns within the first dashed box are identical to columns 7 and 4 of the second matrix.

[0155] Figure 6(b) shows the simulation results for Example 2. The vertical axis represents the SNR, and the horizontal axis represents the first code length E′. In this example, the SC decoding method is used, and BLER equals 10. -2It can be seen that, compared with Example 1 of this application, Example 2 has a smaller SNR under the same E′ and BLER requirements. Therefore, the solution of Example 2 can further improve the code spectrum and enhance decoding performance. Since Example 1 can improve decoding performance compared with the prior art, Example 2 can also improve decoding performance compared with the prior art.

[0156] Example 3

[0157] The non-canonical polarization nuclei with E' = 17 to 32 and K = 6 are derived from the non-canonical polarization nuclei with E = 16 and K = 6, with the expansion order being (4, 10, 2, 8, 16, 3, 9, 5, 11, 13, 1, 7, 6, 12, 15, 14).

[0158] Figure 7 shows the simulation results for Example 3. The vertical axis represents the SNR, and the horizontal axis represents the first code length E′. In this example, the SC decoding method is used, and BLER equals 10. -2 It can be seen that, compared with the scheme of polar coding after shortening the Arikan polarization kernel sequence and the scheme of polar coding after puncturing the Arikan polarization kernel, Example 3 of this application has a smaller SNR when E′ is the same and under the same BLER requirement. Therefore, the scheme of Example 3 of this application can improve the code spectrum and enhance the decoding performance.

[0159] In the above description, the multiple stages indicated by the first information include h stages and t stages following the h stages, as detailed in the foregoing description. As another implementation, the multiple stages indicated by the first information in this application may further include h stages, p stages following the h stages, and t stages following the p stages. Furthermore, the h stages are used to construct one of the t sub-matrices, which is identical to the second matrix and located at the lower right corner of the first matrix. h is a positive integer, meaning the h stages here are the same as the h stages indicated by the first information in the aforementioned implementation. The p stages here include pairs of integers where the two integers fall within the same interval, which is [E′-(y+1)E+1,E′-yE] or [1,q], 1≤y≤t-1, and p is a positive integer. Here, the size of p is predetermined and used to represent adjusting the element values ​​of one or more regions of the first matrix; the size of p is not limited in this application. Here, the r-th stage in the t-th stage includes integer pairs {(E′-(r+1)E+u,E′-h}. r,u E+a u )}, 1≤r≤t-1, 1≤u≤E, 1≤h r,u ≤r. The t-th stage in the t-th stage consists of integer pairs (v, E′-h). r,v E+a E+v-q ), 1≤hr,v ≤t, 1≤v≤q. Where, (a1,a2,…,a…) E ) is a permutation of 1, 2, ..., E. Here, t represents the divisor between the first code length E′ and the second code length E, that is, the result of E′ divided by E is equal to t, and the remainder is q.

[0160] For example, taking E=3, t=3, q=0, E′=9, K=2 as an example, if the multiple stages indicated by the first information include h stages and t stages after h stages, then the first matrix shown in Figure 8(a) can be constructed. If the multiple stages indicated by the first information include h stages, p stages after h stages, and t stages after p stages, then the first matrix shown in Figure 8(b) can be constructed. In the first matrices shown in Figures 8(a) and 8(b), the values ​​of the elements within the matrix enclosed by the solid lines can be arbitrarily set, and the values ​​of the elements within the matrix enclosed by the solid lines are set by the p stages.

[0161] Figure 8(a) contains a second matrix, which is a 3x3 matrix in the lower right corner of the matrix shown in Figure 8(a).

[0162] Figure 8(b) contains a second matrix, which is a 3x3 matrix in the lower right corner of the matrix shown in Figure 8(b).

[0163] Referring to Figure 8(a), it can be seen that the bit information in the first dashed box is copied from column 7, that is, it comes from column 7; the bit information in the second dashed box is copied from column 8, that is, it comes from column 8; and the bit information in the third dashed box is copied from column 9, that is, it comes from column 9. The information within the dashed boxes is constructed from t stages out of the multiple stages indicated by the first information.

[0164] Referring to Figure 8(b), it can be seen that the bit information in the first dashed box is copied from column 4, that is, it comes from column 4; the bit information in the second dashed box is copied from column 8, that is, it comes from column 8; and the bit information in the third dashed box is copied from column 6, that is, it comes from column 6. The information within the dashed boxes is constructed from t stages out of the multiple stages indicated by the first information.

[0165] The source columns of bit information within the dashed boxes in Figures 8(a) and 8(b) satisfy the following relationship: in Figure 8(a), 7, 8, and 9, modulo 3, yield 1, 2, and 0 respectively; in Figure 8(b), 4, 8, and 6, modulo 3, also yield 1, 2, and 0 respectively. Here, 3 refers to the size E of the second matrix.

[0166] As one implementation method, in this embodiment of the application, the row weight of at least one row of the second matrix is ​​not 2 to the power of n1, where n1 is an integer greater than or equal to 0.

[0167] The following describes the different representations or storage formats of all integer pairs indicated by the second information.

[0168] Method 1, the second information includes Z sub-information, and the f-th sub-information among the Z sub-information is (a f ,b f ,c f ), where a f and b f The integer pairs formed (a f ,b f (Located in the cth stage of multiple stages) f Each stage s i The number of integer pairs contained in the i-th stage is 1≤i≤h, where h represents the total number of stages indicated by the second information.

[0169] Method 2: The second piece of information corresponds to a table with rows of E and columns of E. The a-th column of the table... f Line b f The column takes the value c f , indicating that in the c-th step of the encoding process f The stage will encode the bth bit of the vector f Add the bit to the a-th position. f The position, and soon the bth f The value of the a-th bit is related to the value of the a-th bit. f The values ​​of each bit are added together and the result is modulo 2. The modulo result is then assigned to the value of the a-th bit. f Bit. Where E is the second code length.

[0170] Method 3: The second piece of information corresponds to a table with rows E and columns h. The a-th column of the table... f Line c f The column takes the value b f , indicating that in the c-th step of the encoding process k The stage will encode the bth bit of the vector f Add the bit to the a-th position. f The position, and soon the bth f The value of the a-th bit is related to the value of the a-th bit. f The values ​​of each bit are added together and the result is modulo 2. The modulo result is then assigned to the value of the a-th bit. f Bit. Where E is the second code length, and h is the total number of stages indicated by the second information.

[0171] Method 4: The second piece of information corresponds to a table with rows E and columns h. The bth column of the table... f Line c f The column takes the value a f , indicating that in the c-th step of the encoding processf The stage will encode the bth bit of the vector f Add the bit to the a-th position. f The position, and soon the bth f The value of the a-th bit is related to the value of the a-th bit. f The values ​​of each bit are added together and the result is modulo 2. The modulo result is then assigned to the value of the a-th bit. f Bit. Where E is the second code length, and h is the total number of stages indicated by the second information.

[0172] Method 5 involves grouping all integer pairs indicated by the second information according to the added column. Here, the added column refers to a column in the matrix that is added to other columns. For example, if column x is added to column y, then column x is the added column and column y is the added column.

[0173] Taking Example 1 above as an example, all integer pairs indicated by the second information can be represented as: {},{(1,1)},{(1,2)},{(3,1),(2,2)},{(1,3)},{(5,1),(2,3)},{(5,2),(3,3)}.

[0174] In this context, the first {} is in the first position and is empty, indicating that the first column is not an addition column. {(1,1)} is in the second position and contains one integer pair, indicating that the second column is added once, where (1,1) means the second column is added to the first column in the first stage. {(1,2)} is in the third position and contains one integer pair, indicating that the third column is added once, where (1,2) means the third column is added to the first column in the second stage. {(3,1),(2,2)} is in the fourth position and contains two integer pairs, indicating that the fourth column is added twice, where (3,1) means the fourth column is added to the third column in the first stage, and (2,2) means the fourth column is added to the second column in the second stage. {(1,3)} is the 5th column and contains one integer pair, indicating that the 5th column is added once. Here, (1,3) means that the 5th column is added to the 1st column in the 3rd stage. {(5,1),(2,3)} is the 6th column and contains two integer pairs, indicating that the 6th column is added twice. Here, (5,1) means that the 6th column is added to the 5th column in the 1st stage, and (2,3) means that the 6th column is added to the 2nd column in the 3rd stage. {(5,2),(3,3)} is the 7th column and contains two integer pairs, indicating that the 7th column is added twice. Here, (5,2) means that the 7th column is added to the 5th column in the 2nd stage, and (3,3) means that the 7th column is added to the 3rd column in the 3rd stage.

[0175] Method 6 involves grouping all integer pairs indicated by the second information according to the column being added. Here, the column being added refers to the column in the matrix that is added to other columns. For example, if column x is added to column y, then column x is the adding column and column y is the added column.

[0176] Taking Example 1 above as an example, all integer pairs indicated by the second information can be represented as: {(2,1),(3,2),(5,3)},{(4,2),(6,3)},{(4,1),(7,3)},{},{(6,1),(7,2)},{},{}.

[0177] {(2,1),(3,2),(5,3)} is the first column with three integer pairs, indicating that column 1 is added to column 1 three times. Here, (2,1) means column 2 is added to column 1 in stage 1, (3,2) means column 3 is added to column 1 in stage 2, and (5,3) means column 5 is added to column 1 in stage 3. {(4,2),(6,3)} is the second column with two integer pairs, indicating that column 2 is added to column 2 twice. Here, (4,2) means column 4 is added to column 2 in stage 2, and (6,3) means column 6 is added to column 2 in stage 3. {(4,1),(7,3)} is the third column with two integer pairs. Yes, this means that column 3 is added twice. Specifically, (4,1) indicates that column 4 is added to column 3 in stage 1, and (7,3) indicates that column 7 is added to column 3 in stage 3. The first {} is in the 4th position and is empty, indicating that column 4 is not added. {(6,1),(7,2)} is in the 5th position and has two integer pairs, indicating that column 5 is added twice. Specifically, (6,1) indicates that column 6 is added to column 5 in stage 1, and (7,2) indicates that column 7 is added to column 5 in stage 2. The second {} is in the 6th position and is empty, indicating that column 6 is not added. The third {} is in the 7th position and is empty, indicating that column 7 is not added.

[0178] The process of constructing the second matrix using integer pairs of multiple stages indicated by the second information in Example 1 above, with reference to Figure 9, is given below. In Example 1 above, E = 7, K = 3, and the multiple stages indicated by the second information include {(1,2),(3,4),(5,6)}, {(1,3),(2,4),(5,7)}, and {(1,5),(2,6),(3,7)}.

[0179] Referring to Figure 9, the process of constructing the second matrix based on the second identity matrix of size 7*7 includes the following operations:

[0180] Operation 1 corresponding to (1,2): Add the second column of the 7*7 second identity matrix to the first column to obtain matrix #1 as shown in the figure.

[0181] Operation 2 corresponding to (3,4): Add the 4th column of matrix #1 to the 3rd column to obtain matrix #2 as shown in Figure 9.

[0182] Operation 3 corresponding to (5,6): Add the 6th column of matrix #2 to the 5th column to obtain matrix #3 as shown in Figure 9.

[0183] Operation 4 corresponding to (1,3): Add the 3rd column of matrix #3 to the 1st column to obtain matrix #4 as shown in Figure 9.

[0184] Operation 5 corresponding to (2,4): Add the 4th column of matrix #4 to the 2nd column to obtain matrix #5 as shown in Figure 9.

[0185] Operation 6 corresponding to (5,7): Add the 7th column of matrix #5 to the 5th column to obtain matrix #6 as shown in Figure 9.

[0186] Operation 7 corresponding to (1,5): Add the 5th column of matrix #6 to the 1st column to obtain matrix #7 as shown in Figure 9.

[0187] Operation 8 corresponding to (2,6): Add the 6th column of matrix #7 to the 2nd column to obtain matrix #8 as shown in Figure 9.

[0188] Operation 9 corresponding to (3,7): Add the 7th column of matrix #7 to the 3rd column to obtain the second matrix as shown in Figure 9.

[0189] As one implementation method, in this embodiment of the application, the row weight of at least one row of the first matrix is ​​not 2 to the power of n2, where n2 is an integer greater than or equal to 0.

[0190] As one implementation method, the different expressions or storage forms of all integer pairs indicated by the first information can be referred to the different expressions or storage forms of all integer pairs indicated by the second information, and will not be elaborated further.

[0191] In this embodiment of the application, the process of constructing the first matrix using integer pairs of multiple stages indicated by the first information is similar to the process of constructing the second matrix using integer pairs of multiple stages indicated by the second information, and will not be described in detail here.

[0192] Figure 10 is a flowchart illustrating a decoding method provided in an embodiment of this application. This method is an implementation method on the decoding side, and includes the following steps:

[0193] Step 1001: The second communication device acquires the sequence to be decoded.

[0194] For example, the second communication device can receive the sequence to be decoded from the first communication device, or receive modulated symbol information from the first communication device and obtain the sequence to be decoded based on the modulated symbol information.

[0195] Step 1002: The second communication device performs polarization encoding on the sequence to be decoded according to the first matrix to obtain the information bit sequence.

[0196] The meaning of the first matrix is ​​the same as that of the first matrix in the embodiment of Figure 4 above, and can be referred to the above description.

[0197] The process by which the second communication device performs polar encoding on the sequence to be decoded according to the first matrix to obtain the information bit sequence is the reverse of the process by which the first communication device performs polar encoding on the information bit sequence according to the first matrix, and will not be described in detail here. The decoding algorithm used may be, for example, the SC decoding algorithm or the SCL decoding algorithm, etc., and this application is not limited to this.

[0198] Based on the above scheme, the first matrix is ​​constructed from a smaller second matrix. The size of the first matrix is ​​set to the first code length. Therefore, the length of the encoded bit sequence is the same as the first code length. This allows for direct polarization decoding of the sequence to be decoded based on the first matrix, yielding the information bit sequence without the need for rate matching, thus improving decoding performance. Furthermore, since corresponding encoding schemes can be designed for different code lengths and code rates, this scheme can further improve decoding performance. Moreover, the first matrix in this scheme is constructed from a smaller second matrix, which facilitates faster polarization, and because the process of constructing the first matrix from the second matrix is ​​relatively simple, it does not increase decoding complexity.

[0199] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0200] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0201] In the case of using integrated units, FIG11 shows a possible exemplary block diagram of the device involved in the embodiments of this application. As shown in FIG11, the device 1100 may include a processing unit 1102 and a communication unit 1103. The processing unit 1102 is used to control and manage the operation of the device 1100. The communication unit 1103 is used to support communication between the device 1100 and other devices. Optionally, the communication unit 1103 is also called a transceiver unit, and may include a receiving unit and / or a sending unit, respectively used to perform receiving and sending operations. The device 1100 may also include a storage unit 1101 for storing the program code and / or data of the device 1100.

[0202] The device 1100 can be the first communication device in the above embodiments. The processing unit 1102 can support the device 1100 in performing the actions of the first communication device in the above method embodiments. Alternatively, the processing unit 1102 mainly performs the internal actions of the first communication device in the method embodiments, and the communication unit 1103 can support communication between the device 1100 and other devices.

[0203] For example, in one embodiment, processing unit 1102 is used to polarize encode the information bit sequence according to the first matrix to obtain the encoded bit sequence; wherein, the size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1; the first matrix includes t first sub-matrices, any one of the t first sub-matrices is the same as the second matrix, or can be obtained by column interleaving the second matrix, the size of the second matrix is ​​E*E, where E represents the second code length; the number of information bits corresponding to the first matrix and the number of information bits corresponding to the second matrix are both K, 1≤K≤E-1; the encoded bit sequence is modulated to obtain modulated symbol information; and communication unit 1103 is used to output the modulated symbol information.

[0204] The device 1100 can be the second communication device in the above embodiments. The processing unit 1102 can support the device 1100 in performing the actions of the second communication device in the above method embodiments. Alternatively, the processing unit 1102 mainly performs the internal actions of the second communication device in the method embodiments, and the communication unit 1103 can support communication between the device 1100 and other devices.

[0205] For example, in one embodiment, the communication unit 1103 is used to acquire the sequence to be decoded; the processing unit 1102 is used to perform polar coding on the sequence to be decoded according to the first matrix to obtain an information bit sequence; wherein, the size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1; the first matrix includes t first sub-matrices, any first sub-matrice in the t first sub-matrices is the same as the second matrix, or can be obtained by column interleaving the second matrix, the size of the second matrix is ​​E*E, where E represents the second code length; the number of information bits corresponding to the first matrix and the number of information bits corresponding to the second matrix are both K, 1≤K≤E-1.

[0206] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0207] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0208] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0209] Based on the same technical concept, this application also provides a communication device for implementing the functions of the first or second communication device described above. As shown in FIG12, the device may be a communication equipment or a component within a communication equipment (e.g., a processor, chip, or chip system). The device includes a processor 1201 and a communication interface 1202, and optionally, a memory 1203. The memory 1203 may be independent of the processor 1201 or integrated into the processor 1201; no specific limitation is made. It is understood that FIG12 only shows the main components of the communication device. In one possible implementation, the communication device may further include an input / output device (not shown in the figure).

[0210] The processor 1201 is used to execute the program code stored in the memory 1203, specifically to perform the actions of the aforementioned processing unit 1102, which will not be described in detail here. The communication interface 1202 is specifically used to perform the actions of the aforementioned communication unit 1103, which will not be described in detail here.

[0211] Processor 1201 can be a CPU, a digital processing unit, etc. Processor 1201 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1202 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1201 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of this application do not limit the specific implementation of the above-mentioned devices.

[0212] The communication interface 1202 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1202 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Optionally, the communication interface 1202 can be an input / output interface or a chip pin.

[0213] Input / output devices, such as touchscreens, displays, and keyboards, are primarily used to receive user input data and output data to the user.

[0214] Memory 1203 is used to store programs executed by processor 1201. Memory 1203 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as cache or random-access memory (RAM). Memory 1203 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited to this.

[0215] When the communication device is powered on, the processor 1201 can read the software program in the memory 1203, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1201 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1201. The processor 1201 converts the baseband signal into data and processes the data.

[0216] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0217] This embodiment does not limit the specific connection medium between the communication interface 1202, processor 1201, and memory 1203. In Figure 12, the memory 1203, processor 1201, and communication interface 1202 are connected via a bus 1204, which is represented by a thick line. The connection methods between other components are only illustrative and not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 12, but this does not indicate that there is only one bus or one type of bus.

[0218] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0219] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0220] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0221] (3) Application-specific integrated circuit (ASIC), such as modem;

[0222] (4) Modules that can be embedded in other devices;

[0223] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0224] (6) Others, etc.

[0225] This application provides a chip (or chip system) including a processor for implementing any of the above-described method embodiments.

[0226] This application provides a computer-readable storage medium storing a computer program or instructions that, when executed, implement any of the above-described method embodiments.

[0227] This application provides a computer program product, which includes a computer program or instructions that, when executed, implement any of the above-described method embodiments.

[0228] This application provides a communication system, including a first communication device and a second communication device in the above method embodiments.

[0229] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0230] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0231] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0232] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0233] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0234] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. An encoding method, characterized in that, The method includes: According to the first matrix, the information bit sequence is polar-coded to obtain the encoded bit sequence; wherein, the size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1; the first matrix includes t first sub-matrices, any one of the t first sub-matrices is the same as the second matrix, or can be obtained by column interleaving the second matrix, the size of the second matrix is ​​E*E, where E represents the second code length; the number of information bits corresponding to the first matrix and the number of information bits corresponding to the second matrix are both K, 1≤K≤E-1; The encoded bit sequence is modulated to obtain modulated symbol information; Output the modulated symbol information.

2. A decoding method, characterized in that, The method includes: Obtain the sequence to be decoded; According to the first matrix, the sequence to be decoded is polar-coded to obtain an information bit sequence; wherein, the size of the first matrix is ​​E′*E′, where E′ represents the first code length, E′=tE+q, t≥1, 0≤q≤E-1; the first matrix includes t first sub-matrices, any one of the t first sub-matrices is the same as the second matrix, or can be obtained by column interleaving the second matrix, the size of the second matrix is ​​E*E, where E represents the second code length; the number of information bits corresponding to the first matrix and the number of information bits corresponding to the second matrix are both K, 1≤K≤E-1.

3. The method as described in claim 1 or 2, characterized in that, When q is greater than 0, the first matrix also includes a second submatrix, which is composed of the q columns of the second matrix.

4. The method according to any one of claims 1 to 3, characterized in that, The first matrix also includes a third submatrix and a fourth submatrix. The third submatrix is ​​an identity matrix of size (E′-E)*(E′-E), and the fourth submatrix is ​​a zero matrix of size (E′-E)*E.

5. The method according to any one of claims 1 to 4, characterized in that, The first matrix is ​​determined based on a first identity matrix and first information; wherein, the first information is used to indicate multiple stages for constructing the first matrix, each of the multiple stages includes at least one integer pair and the integer pair is used to indicate adding at least one first target column of the first identity matrix to at least one second target column, the integer pairs in each of the multiple stages are completely different, the multiple integer pairs in different stages of the multiple stages are not completely different, the integer pair includes the indexes of two columns, the integer in the integer pair is less than or equal to the first code length, and the size of the first identity matrix is ​​E′*E′.

6. The method as described in claim 5, characterized in that, The first information indicates multiple stages including h stages and t stages following the h stages; The h stages are used to construct one of the t first sub-matrices, wherein the first sub-matrice is the same as the second matrix and is located in the lower right corner of the first matrix, and h is a positive integer; The rth stage of the t stages includes integer pairs {(E'-(r+1)E+u, E'-E+a u )}, 1≤r≤t-1, 1≤u≤E; the tth stage of the t stages includes integer pairs (v, E'-E+a E+v-q ), 1≤v≤q; wherein (a1, a2, …, a E ) is a permutation of 1, 2, …, E.

7. The method as described in claim 6, characterized in that, The second matrix is ​​determined based on the second identity matrix and second information. The size of the second identity matrix is ​​E*E. The second information is used to indicate multiple stages for constructing the second matrix. Each of the multiple stages indicated by the second information includes at least one integer pair, and the integer pair is used to indicate adding at least one third target column of the second identity matrix to at least one fourth target column. The integer pairs in each of the multiple stages indicated by the second information are completely different. The multiple integer pairs in different stages indicated by the second information are not completely different. The integer pairs in the multiple stages indicated by the second information include indices of two columns. The integers in the integer pairs in the multiple stages indicated by the second information are less than or equal to the second code length.

8. The method as described in claim 7, characterized in that, The second information indicates a plurality of stages, and the second information indicates h stages, and the fth stage of the h stages includes an integer pair of {(a, a+2 f-1 )}. The fth stage of the h stages indicated by the first information includes integer pairs of {(E'-E+a, E'-E+a+2 f-1 )}. where E = 2 K -1, 1≤f≤h, and h = K; a is an integer that traverses the fth bit of the corresponding binary number between 0 and E-1 that is 0.

9. The method as described in claim 8, characterized in that, E=7, K=3, and the multiple stages indicated by the second information are {(1,2),(3,4),(5,6)}, {(1,3),(2,4),(5,7)}, {(1,5),(2,6),(3,7)}; E'=7t+q,0≤q≤6, the first information indicating multiple stages {(E'-6,E'-5),(E'-4,E'-3),(E'-2,E ′-1)},{(E′-6,E′-4),(E′-5,E′-3),(E′-2,E′)},{(E′-6,E′-2),(E′-5, E′-1),(E′-4,E′)},{(E′-13,E′-6),(E′-12,E′-5),…,(E′-7,E′)},….,{ (E′-7s-6,E′-6),(E′-7s-5,E′-5),…,(E′-7s,E′)},…,{(1,E′-q+1),(2, E′-q+2),…,(q,E′)}, or the multiple stages of the first information indicated are {(E′-6,E′-5),(E′-4,E′-3),(E′-2,E′-1)},{(E′-6,E′-4),(E′-5,E′-3),(E′-2,E′)},{(E′-6,E′-2),(E′-5,E′-1),(E′-4,E′)},{(E′-13,E′-6),(E′-12,E′-5),(E′-11,E′-4),(E′-10,E′-2),(E′-9,E′-1),(E′-8,E′),(E′-7,E′-4)},…,{(1,E'-7+a 8-q ),(2,E'-7+a 9-q )...(q,E'-3)}.

10. The method as described in claim 5, characterized in that, The first information indicates multiple stages including h stages, p stages following the h stages, and t stages following the p stages; The h stages are used to construct one of the t sub-matrices, the sub-matrices being identical to the second matrix and located at the lower right corner of the first matrix, where h is a positive integer; The two integers in the integer pairs included in the p stages fall into the same interval, which is [E′-(y+1)E+1,E′-yE] or [1,q], 1≤y≤t-1, and p is an integer greater than 0; The r-th stage in the t-th stage includes integer pairs {(E′-(r+1)E+u,E′-h}. r,u E+a u )}, 1≤r≤t-1, 1≤u≤E, 1≤h r,u ≤r; the t-th stage in the t-th stage includes integer pairs (v, E′-h) r,v E+a E+v-q ), 1≤h r,v ≤t, 1≤v≤q; where (a1,a2,…,a…) E ) is a permutation of 1, 2, ..., E.

11. The method according to any one of claims 1 to 10, characterized in that, The information bit corresponding to the second matrix is ​​the xth bit. i The information bit corresponding to the first matrix is ​​the E′-E+xth bit. i Bit; Where 0≤i≤K-1, x i It is an integer greater than 0 and less than or equal to E.

12. A communication device, characterized in that, It includes a processor and an interface circuit, the processor being used to communicate with other devices through the interface circuit and to implement the method of any one of claims 1, 3 to 11, or to implement the method of any one of claims 2 to 11.

13. The apparatus as claimed in claim 12, characterized in that, The communication device further includes a memory for storing computer programs or instructions, which, when executed by the processor, implement the method of any one of claims 1, 3 to 11, or the method of any one of claims 2 to 11.

14. A computer program product, characterized in that, The computer program product includes instructions that, when executed, implement the method of any one of claims 1 to 11.

15. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed, implement the method described in any one of claims 1 to 11.

16. A chip, characterized in that, The chip includes a processor for implementing the method according to any one of claims 1 to 11.

17. A communication device, characterized in that, It includes modules or units for performing the method as described in any one of claims 1, 3 to 11, or it includes modules or units for performing the method as described in any one of claims 2 to 11.

18. A communication system, characterized in that, The method includes a communication device for performing the method as described in any one of claims 1, 3 to 11, and a communication device for performing the method as described in any one of claims 2 to 11.

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