Solar cell and photovoltaic module

Abstract

Provided in the present application are a solar cell and a photovoltaic module. The solar cell comprises: a silicon substrate, wherein the silicon substrate has a first surface; the first surface comprises first conductive regions and gap regions, which are alternately distributed in a first direction; the first conductive regions comprise first doped conductive layers arranged at intervals; and the gap regions located in an edge region of the first surface are edge gap regions, and the gap regions located in a central region of the first surface are central gap regions, the depth of the edge gap regions being less than the depth of the central gap regions. The embodiments of the present application can reduce damage to the edge region of the solar cell during a cleaning process, prevent edge chipping, and improve the yield of solar cells.

Description

A solar cell and a photovoltaic module

[0001] Cross Reference to Related Applications

[0002] The present application claims priority to the Chinese Patent Application No. 2025101049009, filed on January 23, 2025, entitled "A solar cell and a photovoltaic module", the Chinese Patent Application No. 2025111021989, filed on August 7, 2025, entitled "A photovoltaic cell and a photovoltaic module", the Chinese Patent Application No. 2025117251768, filed on November 21, 2025, entitled "A solar cell and a photovoltaic module", all of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of photovoltaic processing, in particular to a solar cell and a photovoltaic module. BACKGROUND

[0004] With the development of science and technology, solar energy as a new clean photovoltaic energy has developed rapidly in recent years. Among them, the solar cell as a kind of photovoltaic semiconductor sheet that can directly generate electricity by using sunlight, its performance is also gradually pursuing high conversion efficiency, low attenuation performance and high production cost performance.

[0005] The existing solar cell usually needs to perform laser patterning on the cell sheet to form a non-metallized area on the cell sheet during processing. After laser patterning is completed, the damage caused by laser patterning usually needs to be cleaned.

[0006] However, in the process of cleaning the solar cell, the surface of the cell sheet is easily damaged during the cleaning of the non-metallized area, which greatly reduces the yield of the solar cell. SUMMARY

[0007] The present application aims to provide a solar cell and a photovoltaic module to solve the problem of surface damage and reduced yield of the solar cell in the existing cell sheet cleaning process.

[0008] In order to solve the above technical problems, the present application is implemented as follows:

[0009] In a first aspect, the present application discloses a solar cell, comprising:

[0010] a silicon substrate having a first surface, the first surface comprising a first conductive region and a spacing region;

[0011] The first conductive region comprises a first doped conductive layer arranged in intervals;

[0012] The interval region located at the edge region of the first surface is an edge interval region, and the interval region located at the center region of the first surface is a center interval region, wherein the depth of the edge interval region is less than the depth of the center interval region.

[0013] Optionally, the depth of the edge interval region has a first difference with the depth of the center interval region, the first difference is greater than 0 and less than or equal to 2um.

[0014] Optionally, the depth of the edge interval region ranges from 1um to 3um, and the depth of the center interval region ranges from 2um to 5um.

[0015] Optionally, the width of the edge interval region along a first direction is a first width, and the width of the center interval region along the first direction is a second width, the first width is less than or equal to the second width.

[0016] Optionally, the first width ranges from 100um to 700um, and the second width ranges from 500um to 1500um.

[0017] Optionally, the first conductive region is provided with a first texture structure, and the interval region is provided with a second texture structure, and the one-dimensional size of the bottom of the first texture structure is less than the one-dimensional size of the bottom of the second texture structure.

[0018] Optionally, the one-dimensional size of the bottom of the first texture structure ranges from 5um to 9um, and the one-dimensional size of the bottom of the second texture structure ranges from 9um to 18um.

[0019] Optionally, the depth of the first texture structure and the second texture structure ranges from 0.05um to 2um.

[0020] Optionally, the interval region is provided with a pyramid-like texture structure.

[0021] Optionally, the width of the center interval region along a first direction is a second width, and the distance between the centers of two adjacent first conductive regions along the first direction is a first distance, and the ratio of the second width to the first distance ranges from 0.2 to 0.7.

[0022] And / or, the distance between the centers of two adjacent first conductive regions along the first direction is 1mm to 3mm.

[0023] Optionally, the solar cell further comprises a first passivation layer, and the first passivation layer is arranged on the side of the first doped conductive layer away from the silicon substrate.

[0024] The first passivation layer comprises a first region and a second region, the first region is opposite to the center spacing region, the second region is opposite to the edge spacing region, the first region is provided with a first sub-passivation layer, and the second region is provided with a second sub-passivation layer.

[0025] The thickness of the second sub-passivation layer is greater than the thickness of the first sub-passivation layer.

[0026] Optionally, the silicon substrate further comprises a second surface arranged away from the first surface along a third direction, and a side surface connecting the first surface and the second surface, the side surface comprises a cut surface and a non-cut surface; wherein,

[0027] The first conductive region and the cut surface have a first isolation groove therebetween, the surface of the first isolation groove and the surface of the first conductive region have a height difference therebetween, and the first conductive region and the first isolation groove have a connecting side surface therebetween.

[0028] The solar cell further comprises a first passivation layer, the first passivation layer covers the surface of the first doped conductive layer away from the silicon substrate, the surface of the first isolation groove, and the surface of the connecting side surface.

[0029] Optionally, the height difference is a first height, and the first height ranges from 1 micrometer to 10 micrometers.

[0030] Optionally, the number of the first conductive regions is a plurality, and a plurality of spacing regions are further arranged on the first surface, the plurality of first conductive regions and the plurality of spacing regions are arranged alternately on the first surface along a first direction, and the first direction is perpendicular to the cut surface.

[0031] The width of the first isolation groove along the first direction is a first width, the width of the spacing region along the first direction is a second width, and the first width is less than the second width.

[0032] Optionally, the ratio of the first width to the second width ranges from 25% to 75%.

[0033] Optionally, the number of the first conductive regions is a plurality, and a plurality

[0034] The height difference between the surface of the first isolation groove and the surface of the first conductive region is a first height, the height difference between the surface of the spacing region and the surface of the first conductive region is a second height, and the difference between the first height and the second height is less than or equal to 1 micrometer.

[0035] Optionally, the cutting surface comprises a first cutting surface and a second cutting surface, the first cutting surface and the second cutting surface are oppositely arranged.

[0036] The second cutting surface and the first conductive region further comprise a second isolation groove, a surface of the second isolation groove and a surface of the first conductive region have a height difference;

[0037] The first passivation layer is arranged on the surface of the second isolation groove.

[0038] Optionally, the second surface comprises a second conductive region, the second conductive region is provided with a second doped conductive layer;

[0039] The second conductive region and the cutting surface are provided with a third isolation groove, a surface of the third isolation groove and a surface of the second conductive region have a height difference, and the height difference ranges from 2 microns to 10 microns;

[0040] The first isolation groove and the third isolation groove are correspondingly arranged along the third direction;

[0041] The first passivation layer is arranged on the side of the second doped conductive layer away from the silicon substrate and the surface of the third isolation groove.

[0042] Optionally, the solar cell further comprises a second passivation layer, the second passivation layer is located on the surface of the cutting surface;

[0043] The second passivation layer extends to the first surface, is located on the side of the first passivation layer away from the silicon substrate, and covers at least the first isolation groove and the first conductive region adjacent to the first isolation groove, and the second passivation layer covers the side of the first doped conductive layer away from the silicon substrate;

[0044] The second passivation layer extends to the first surface, is located on the side of the first passivation layer away from the silicon substrate, and covers at least the first isolation groove and the first conductive region adjacent to the first isolation groove, and the second passivation layer covers the side of the first doped conductive layer away from the silicon substrate;

[0045] The second passivation layer extends to the second surface, is located on the side of the first passivation layer away from the silicon substrate, covers at least the third isolation groove and the second conductive region adjacent to the third isolation groove, and the second passivation layer covers the side of the second doped conductive layer away from the silicon substrate.

[0046] Optionally, the first conductive region and the non-cutting surface further comprise a fourth isolation groove;

[0047] A difference between a surface height of the fourth isolation groove and a surface height of the first conductive region is less than 1 micrometer, and a width of the fourth isolation groove is less than a width of the first isolation groove.

[0048] Optionally, the first surface includes the first conductive regions spaced apart along a first direction, and a spacing region between adjacent first conductive regions, the silicon substrate further includes a second surface opposite to the first surface and a side surface connected between the first surface and the second surface, the spacing region has a second texture structure, the side surface has a fourth texture structure, and the first conductive regions have a first texture structure.

[0049] The solar cell further includes a third passivation layer on a surface of the spacing region and on at least one of the following structure surfaces: the second surface, the side surface, and a surface of the first doped conductive layer away from the silicon substrate, and

[0050] a first electrode on the first doped conductive layer and in electrical contact with the first doped conductive layer.

[0051] Optionally, a height of the second texture structure is less than a height of the first texture structure, and / or a surface size of the second texture structure is greater than a surface size of the first texture structure; and a surface size of the fourth texture structure is greater than a surface size of the second texture structure.

[0052] Optionally, a height of the fourth texture structure 104 is less than a height of the first texture structure.

[0053] Optionally, a height of the fourth texture structure 104 is greater than a height of the second texture structure.

[0054] Optionally, part of the second texture structure is arranged in a strip shape along an extension direction of the first conductive region, and part of the first texture structure is arranged in a strip shape along the extension direction of the first conductive region.

[0055] Optionally, the spacing region includes a plurality of first sub-regions and a plurality of second sub-regions.

[0056] The first sub-regions have a third texture structure 103, and the second sub-regions have the second texture structure, the first sub-regions and the second sub-regions are arranged alternately along a second direction, and the second direction intersects the first direction.

[0057] Optionally, a height of the second texture structure is less than a height of the third texture structure 103, and / or a surface size of the second texture structure is greater than a surface size of the third texture structure 103.

[0058] Optionally, the interval region comprises a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions are arranged alternately along a second direction, the second direction intersects the first direction.

[0059] The first sub-regions have third texture structures 103, and the second sub-regions have the second texture structures.

[0060] The third texture structures 103 partially overlap in the first sub-regions, and the bottom surface of the outermost third texture structure 103 is less than or equal to 2 μm away from the bottom surface of the adjacent third texture structure 103 in the direction away from the surface of the first sub-region.

[0061] Optionally, the height of the first texture structure is less than the height of the third texture structure 103.

[0062] Optionally, the surface size of the second texture structure ranges from 10 μm to 28 μm.

[0063] Or, the surface size of the first texture structure ranges from 5 μm to 15 μm.

[0064] Or, the surface size of the third texture structure 103 ranges from 5 μm to 15 μm.

[0065] Or, the surface size of the fourth texture structure 104 ranges from 15 μm to 40 μm.

[0066] Optionally, the interval region comprises a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions are arranged alternately along a second direction, the second direction intersects the first direction.

[0067] The first sub-regions have third texture structures 103, and the second sub-regions have the second texture structures.

[0068] In the second direction, the width of the first sub-region is less than or equal to 400 μm, and / or the interval between adjacent first sub-regions ranges from 20 μm to 400 μm.

[0069] Optionally, the interval region comprises a plurality of first sub-regions and a plurality of second sub-regions.

[0070] The first sub-regions have third texture structures 103, and the second sub-regions have the second texture structures, the first sub-regions and the second sub-regions are arranged alternately along a second direction, the second direction intersects the first direction.

[0071] The height of the second texture structure is less than the height of the third texture structure 103, and / or the surface size of the second texture structure is greater than the surface size of the third texture structure 103.

[0072] In the second direction, a ratio of a width of the first sub-region to a sum of the width of the first sub-region and a spacing between adjacent first sub-regions is greater than or equal to 20% and less than or equal to 70%; and / or, a ratio of an area of the first sub-region to an area of the spacing region is greater than or equal to 20% and less than or equal to 70%.

[0073] Optionally, in the third direction, a surface of the spacing region is closer to the second surface than a surface of the first conductive region.

[0074] Optionally, a height difference between the surface of the first conductive region and the surface of the spacing region is 1 μm to 5 μm.

[0075] Optionally, the first surface further comprises a transition region between the first conductive region and the spacing region.

[0076] The transition region has a convex structure, and a one-dimensional size of the convex structure is different from one-dimensional sizes of the second texture structure and the first texture structure.

[0077] Optionally, in the first direction, a width of the transition region is 1 μm to 50 μm.

[0078] And / or, in the first direction, the transition region has a convex end protruding in a direction towards the spacing region and a concave end recessed in a direction away from the spacing region, and a distance between the convex end and the concave end is less than or equal to 50 μm.

[0079] And / or, a surface of the transition region has a step different from a height of a surface of the spacing region and a surface of the first conductive region.

[0080] Optionally, the transition region extends in a plurality of sawtooth structures in a second direction intersecting the first direction.

[0081] In the second direction, a length of the sawtooth structure is less than or equal to 200 μm; and / or, at a concave end of the sawtooth structure recessed in a direction away from the spacing region, an included angle between an extension direction of the sawtooth structure and an extension direction of the first doped conductive layer is a first sawtooth angle, and the first sawtooth angle is less than or equal to 30°; and / or, at the concave end of the sawtooth structure recessed in the direction away from the spacing region, an included angle between the extension directions of the sawtooth structure is a second sawtooth angle, and the second sawtooth angle is greater than or equal to 120°.

[0082] Optionally, the spacing region comprises a plurality of first sub-regions and a plurality of second sub-regions.

[0083] The first sub-region has a third texture structure 103, and the second sub-region has the second texture structure;

[0084] The height of the second texture structure is less than the height of the third texture structure 103, and / or the surface size of the second texture structure is greater than the surface size of the third texture structure 103.

[0085] The recessed end corresponds to the region where the third texture structure 103 is located in the first direction.

[0086] Optionally, the height of the region where the fourth texture structure 104 is distributed accounts for less than or equal to 98% of the height of the side surface in the third direction.

[0087] Optionally, the solar cell comprises:

[0088] A tunneling oxide layer located on the first conductive region;

[0089] The first doped conductive layer located on the surface of the tunneling oxide layer, the first doped conductive layer having the same type of doping elements as the silicon substrate;

[0090] The third passivation layer located on the surface of the first doped conductive layer and the surface of the spacing region;

[0091] The solar cell further comprises a third doped conductive layer located on the side surface, the third doped conductive layer covering a ratio of the width of the side surface to the width of the side surface greater than or equal to 50%;

[0092] The third doped conductive layer has the same type of doping as the first doped conductive layer.

[0093] Optionally, the third passivation layer material comprises an aluminum oxide layer, the thickness of the aluminum oxide layer being greater than or equal to 5 nm and less than or equal to 10 nm.

[0094] Optionally, the first surface further comprises a third conductive region, which is alternately and spacedly distributed with the first conductive region, and the spacing region is located between the first conductive region and the third conductive region.

[0095] The solar cell further comprises a fourth doped conductive layer located on the third conductive region of the silicon substrate, the third conductive region having a fifth texture structure.

[0096] In a second aspect, the application also discloses a photovoltaic module, which comprises a cell string, and the cell string comprises the solar cell of any one of the above.

[0097] In the embodiment of the present application, the depth of the edge non-metallization region of the solar cell is less than the depth of the center non-metallization region. In the cleaning process of the laser damage of the metallization region, the edge non-metallization region can be cleaned completely by using a small cleaning intensity due to the small depth of the edge non-metallization region. In this way, the damage to the edge region of the solar cell in the cleaning process can be reduced, the edge collapse phenomenon can be avoided, and the yield of the solar cell can be improved.

[0098] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0099] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0100] FIG. 1 is a structural schematic diagram of a solar cell according to an embodiment of the present application;

[0101] FIG. 2 is a second surface structure schematic diagram of a solar cell according to an embodiment of the present application;

[0102] FIG. 3 is a first surface structure schematic diagram of the solar cell shown in FIG. 2;

[0103] FIG. 4 is a cross-sectional structure schematic diagram of the solar cell shown in FIG. 2;

[0104] FIG. 5 is a first surface structure schematic diagram of a solar cell according to an embodiment of the present application;

[0105] FIG. 6 is a cross-sectional structure schematic diagram of the solar cell shown in FIG. 5;

[0106] FIG. 7 is a cross-sectional structure schematic diagram of a solar cell according to an embodiment of the present application;

[0107] FIG. 8 is a partial cross-sectional schematic diagram of a solar cell according to an embodiment of the present application;

[0108] FIG. 9 is a top view schematic diagram of the solar cell shown in FIG. 8;

[0109] FIG. 10 is a side view schematic diagram of the solar cell shown in FIG. 8;

[0110] FIG. 11 is a structure schematic diagram of a first texture structure, a second texture structure and a fourth texture structure;

[0111] FIG. 12 is a Scanning Electron Microscope (SEM) image of a second texture structure according to an embodiment of the present application;

[0112] FIG. 13 is a top view of a solar cell according to an embodiment of the present application;

[0113] FIG. 14 is a structural diagram of a third texture structure according to an embodiment of the present application;

[0114] FIG. 15 is a top view SEM side view of a solar cell according to an embodiment of the present application;

[0115] FIG. 16 is a diagram showing a height difference between a gap region and a first conductive region according to an embodiment of the present application;

[0116] FIG. 17 is an SEM image of a transition region of a solar cell according to an embodiment of the present application;

[0117] FIG. 18 is an SEM labeled diagram of a transition region of a solar cell according to an embodiment of the present application;

[0118] FIGS. 19 and 20 are diagrams showing a step-like structure in a transition region of a solar cell according to an exemplary embodiment of the present application;

[0119] FIG. 21 is a diagram showing an overall structure of a solar cell according to an embodiment of the present application;

[0120] FIG. 22 is a diagram showing an overall structure of a solar cell according to an embodiment of the present application;

[0121] FIG. 23 is a diagram showing an overall structure of a solar cell according to an embodiment of the present application.

[0122] Reference numerals: 10 - silicon substrate, A - first surface, A1 - first conductive region, A2 - third conductive region, A3 - transition region, gap - gap region, G1 - edge gap region, G2 - center gap region, G3 - first sub-region, G4 - second sub-region, 11 - first doped conductive layer, 12 - tunneling oxide layer, 13 - fourth doped conductive layer, 14 - protrusion structure, 15 - first electrode, 15a - second electrode, 16 - first passivation layer, 17 - another tunneling oxide layer, 18 - another first passivation layer, 101 - first texture structure, 102 - second texture structure, 103 - third texture structure, 104 - fourth texture structure, B - second surface, B1 - second conductive region, 21 - second doped conductive layer, C - side surface, C1 - cut surface, C2 - non-cut surface, 31 - first cut surface, 32 - second cut surface, 33 - first isolation groove, 34 - second isolation groove, 35 - third isolation groove, 36 - second passivation layer, X - first direction, Y - second direction, Z - third direction. DETAILED DESCRIPTION

[0123] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0124] The terms "first", "second" in the description and claims of the present application can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally means that the front and rear associated objects are in an "or" relationship.

[0125] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0126] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For a person of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0127] With the development of science and technology, solar energy as a new type of clean photovoltaic energy has developed rapidly in recent years. Among them, solar cells, as a kind of photovoltaic semiconductor sheet that can directly generate electricity using sunlight, gradually pursue high conversion efficiency, low decay performance and high mass production cost performance.

[0128] In the existing double-sided contact solar cell, in order to improve the double-sided rate, a doped conductive layer is formed on the surface of the silicon substrate, a tunneling oxide layer is arranged between the doped conductive layer and the surface of the silicon substrate to realize selective transmission of carriers, reduce the recombination probability of holes on the surface of the silicon substrate, and a laser etching process is used to groove the doped conductive layer to form a spacing area, so as to reduce the large optical parasitic absorption caused by the doped conductive layer. A passivation layer is further arranged on the surface of the doped conductive layer and the spacing area to fill the dangling bonds existing on the surface and repair defects, so as to reduce the surface recombination loss, optimize light absorption and enhance stability. After laser patterning is completed, the damage caused by laser patterning usually needs to be cleaned before the passivation layer is formed.

[0129] However, in the cleaning process of the solar cell, the edge of the cell wafer is easily damaged during the cleaning of the spacing area at the edge, and the edge collapse phenomenon occurs, which greatly reduces the yield of the solar cell.

[0130] Based on this, the embodiment of the present application provides a solar cell. According to the solar cell in the present application, the damage to the edge area of the solar cell caused by the cleaning process can be reduced, the edge collapse phenomenon can be avoided, and the yield of the solar cell can be improved.

[0131] It should be noted that, in order to ensure the clarity and consistency of the present application file and avoid confusion and ambiguity, the names and reference signs of some technical features in the cross-referenced related applications are unified as follows:

[0132] For the Chinese patent application with the application number 2025101049009 and the name "a solar cell and a photovoltaic module", in the original application file, the first direction is the width direction, which is modified to the third direction (the thickness direction) to maintain unity, the metallization area is modified to the first conductive area, the non-metallization area is modified to the spacing area, the edge non-metallization area is modified to the edge spacing area, the center non-metallization area is modified to the center spacing area, the passivation layer is modified to the first passivation layer, the dielectric layer is modified to the tunneling oxide layer, and the doped conductive layer is modified to the first doped conductive layer. The reference signs of the related technical features are adjusted accordingly.

[0133] For the Chinese patent application with the application number 2025111021989 and the name "a photovoltaic cell and a photovoltaic module", the photovoltaic cell is modified to a solar cell, the back surface is modified to the first surface, the light receiving surface is modified to the second surface, the groove area is modified to the spacing area, and the tunneling layer is modified to the tunneling oxide layer. The reference signs of the related technical features are adjusted accordingly.

[0134] For the Chinese patent application with the application number 2025117251768 and the title "Solar cell and photovoltaic module", the semiconductor substrate is modified to a silicon substrate, the passivation layer is modified to a third passivation layer, the first region is modified to a first conductive region, the second region is modified to a second conductive region, the first texture structure and the second texture structure are interchanged, and the related technical feature figure numbers are adjusted accordingly.

[0135] Referring to FIG. 1, a structural schematic diagram of a solar cell according to an embodiment of the present application is shown. As shown in FIG. 1, the solar cell can specifically include: a silicon substrate 10, the silicon substrate 10 having a first surface A, the first surface A including a first conductive region A1 and a gap region gap, the first conductive region A1 including a first doped conductive layer 11 arranged at intervals on the first surface A, the gap region gap located at an edge region of the first surface A being an edge gap region G1, and the gap region gap located at a central region of the first surface A being a central gap region G2.

[0136] In some embodiments, the first conductive region A1 includes a first doped conductive layer 11 arranged at intervals on the first surface A, the first doped conductive layer 11 including a region capable of forming an electrode, so that the electrode can be in contact with the first doped conductive layer 11 of the region. Considering the accuracy of the electrode manufacturing process, the first conductive region A1 includes the electrode position and the first doped conductive layer 11 not covered by the electrode. The gap region gap located at the edge region of the solar cell is the edge gap region G1, which means that the edge first doped conductive layer 11 and the tunneling oxide layer 12 are removed, playing a role in edge isolation. The gap region gap outside the edge gap region G1 is the central gap region G2, which is mainly used to reduce the negative impact of parasitic absorption caused by the first doped conductive layer 11 on the efficiency of the solar cell.

[0137] In some embodiments, the depth H1 of the edge gap region G1 of the solar cell is less than the depth H2 of the central gap region G2. In the cleaning process of laser damage of the first conductive region A1, since the depth H1 of the edge gap region G1 is small, it is beneficial to use a smaller cleaning intensity to complete the cleaning of the edge gap region G1. In this way, the damage to the edge region of the solar cell caused by the cleaning process can be reduced, the phenomenon of edge collapse can be avoided, and the yield of the solar cell can be improved.

[0138] Specifically, the depth of the gap region gap can be the depth of the bottom of the gap region gap relative to the first surface A. In actual application, the depth of the gap region gap can be measured with the first surface A as the reference surface.

[0139] In some embodiments, the silicon substrate 10 can be used to receive incident light and generate photo-generated carriers. In some embodiments, the material of the silicon substrate 10 can include one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In other embodiments, the material of the silicon substrate 10 can also be silicon carbide, an organic material, or a multi-element compound. The multi-element compound can include, but is not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenium, and the like. Exemplarily, the silicon substrate 10 in the present application is a single crystal silicon substrate. The silicon substrate 10 has a doping element therein, and the doping element can be of N-type or P-type. The N-type element can be a Group V element such as phosphorus (P) element, bismuth (Bi) element, antimony (Sb) element, or arsenic (As) element, and the P-type element can be a Group III element such as boron (B) element, aluminum (Al) element, gallium (Ga) element, or indium (In) element. For example, when the silicon substrate 10 is a P-type silicon substrate, the doping element therein is of P-type. For another example, when the silicon substrate 10 is an N-type silicon substrate, the doping element therein is of N-type. Exemplarily, the silicon substrate 10 in the embodiments of the present application is of N-type to improve the conversion efficiency of the solar cell and reduce the manufacturing cost.

[0140] The solar cell can be applied to various cell structures, including but not limited to Tunnel Oxide Passivated Contact (TOPCon), Interdigitated Back Contact (IBC), Passivated Emitter Rear Cell (PERC), and the like, without limitation. Taking the TOPCon cell as an example, the first surface A can be the back surface of the solar cell.

[0141] It should be noted that the first surface A can also be the light-receiving surface of the solar cell, and the embodiments of the present application can not limit the specific position of the first surface A on the solar cell.

[0142] In some embodiments, the first surface A of the silicon substrate 10 includes a first conductive region A1 and a gap region gap. The first conductive region A1 includes a first doped conductive layer 11 distributed thereon in a spaced manner. The gap region gap can reduce the risk of cell leakage, or reduce the area of the first doped conductive layer 11 on the first surface A of the solar cell, reduce the negative impact of parasitic absorption caused by the first doped conductive layer 11 on the cell efficiency, or reduce the impact of leakage and parasitic absorption on the solar cell.

[0143] In some embodiments, the first conductive region A1 further includes a tunnel oxide layer 12 disposed between the surface of the first conductive region A1 and the first doped conductive layer 11.

[0144] In some embodiments, the first surface A of the silicon substrate 10 comprises a first conductive region A1, a third conductive region A2 and a gap region gap. The first conductive region A1 comprises the tunneling oxide layer 12 and the first doped conductive layer 11, and the third conductive region A2 comprises another tunneling oxide layer 17 and the fourth doped conductive layer 13.

[0145] In some embodiments, the material of the tunneling oxide layer 12 comprises one or more of a single layer or a stacked structure of silicon oxide, silicon nitride, silicon oxynitride, nanocrystalline silicon, intrinsic amorphous silicon and intrinsic polycrystalline silicon, etc. The first doped conductive layer 11 comprises one or more of a single layer or a stacked structure of doped amorphous silicon, doped microcrystalline silicon and doped polycrystalline silicon. The polarity of the doped element in the first doped conductive layer 11 is the same as that of the silicon substrate 10, and a concentration difference is formed between the first doped conductive layer 11 and the silicon substrate 10, thereby forming a high-low junction, or the polarity of the doped element is opposite to that of the silicon substrate 10, and a PN junction is formed between the first doped conductive layer 11 and the silicon substrate 10. The tunneling oxide layer 12 can achieve selective transmission of charge carriers on the surface of the silicon substrate 10, reducing the probability of hole recombination on the surface of the silicon substrate. The first doped conductive layer 11 can improve the transmission efficiency of charge carriers and reduce the contact resistance of the solar cell.

[0146] Optionally, the depth H1 of the edge gap region G1 and the depth H2 of the center gap region G2 have a first difference, the first difference is greater than 0 and less than or equal to 2um. In actual application, the first difference needs to be greater than 0, so that the depth of the edge gap region G1 is small, which facilitates cleaning the edge gap region G1 and reduces the damage to the edge of the cell piece. At the same time, the first difference needs to be less than or equal to 2um, so that the depth H1 of the edge gap region G1 is not too small to cause the edge isolation effect. That is, in the case that the first difference is greater than 0 and less than or equal to 2um, the cleaning effect and the edge isolation effect of the edge gap region G1 can be considered.

[0147] For example, the first difference can be 0.3um, 0.5um, 1.0um, 1.4um or 2um, etc. The present application does not make specific limitations on the value of the first difference.

[0148] In some embodiments, the depth H1 of the edge gap region G1 ranges from 1um to 3um, and the depth H2 of the center gap region G2 ranges from 2um to 5um. In actual application, if the depth of the gap region gap is too small, the passivation and isolation effect of the gap region gap may be affected. If the depth of the gap region gap is too large, the mechanical strength of the solar cell is affected, and the risk of fracture or edge crack of the solar cell is increased.

[0149] In some embodiments, by setting the depth of the edge spacer region G1 to 1-3 um and the depth of the center spacer region G2 to 2-5 um, both the passivation isolation effect and mechanical strength of the edge spacer region G1 and the center spacer region G2 can be considered, and at the same time, the depth H1 of the edge spacer region G1 is less than the depth H2 of the center spacer region G2.

[0150] For example, the depth H1 of the edge spacer region G1 can be 1 um, 2.5 um, 3.0 um, 3.4 um or 4 um, and the depth H2 of the center spacer region G2 can be 2 um, 2.8 um, 3.5 um, 4.4 um or 5 um. The embodiments of the present application do not make specific limitations on the depths of the edge spacer region G1 and the center spacer region G2.

[0151] In some embodiments, the width W1 of the edge spacer region G1 along the first direction X is a first width, and the width of the center spacer region G2 along the first direction X is a second width W2, and the first width W1 is less than or equal to the second width W2. In actual applications, the width of the spacer region gap along the first direction X needs to consider the transmission performance of the carriers and the processability. Generally, the edge spacer region G1 has only one side with a metallization region, so that the path selection of the carriers in the edge spacer region G1 from the spacer region gap to the first conductive region A1 is less than that of the carriers in the center spacer region G2. In order to reduce the transmission path of the carriers in the edge spacer region G1 and reduce the probability of recombination, therefore, the first width W1 of the edge spacer region G1 needs to be less than or equal to the second width W2 of the center spacer region G2. Moreover, in the process of forming the spacer region gap by laser engraving, the edge spacer region G1 with a narrower width is easier to process.

[0152] Optionally, the first width W1 is in the range of 100-700 um, and the second width W2 is in the range of 500-1500 um. In actual applications, when the width of the spacer region gap is less than 100 um, the isolation effect of the spacer region gap can be poor. When the width of the spacer region gap is greater than 1500 um, the Rs can be high due to the wide slot and the lateral transmission difference, which can cause the performance to decrease. That is, based on the size of the laser spot and the lateral transmission difference of the slot region, the first width W1 can be set to 100-700 um, and the second width W2 can be set to 500-1500 um.

[0153] For example, the first width W1 can be 100 um, 200 um, 300 um, 400 um, 500 um, 600 um or 700 um, and the second width W2 can be 500 um, 700 um, 1000 um, 1300 um or 1500 um. The embodiments of the present application do not make specific limitations on the first width W1 and the second width W2.

[0154] In some optional embodiments of the present application, the first conductive region A1 is provided with a first texture structure 101, and the gap region gap is provided with a second texture structure 102. The one-dimensional size of the bottom of the first texture structure 101 is smaller than the one-dimensional size of the bottom of the second texture structure 102.

[0155] In some embodiments, the first texture structure 101 of the first conductive region A1 and the second texture structure 102 of the gap region gap can both increase the surface area, which is beneficial to increase the coverage area of the film layer on the silicon substrate 10 in the later stage, and thus a higher passivation quality can be obtained. The gap region gap is relatively more damaged in the patterning process, and the damaged area will bring more recombination sites, and thus better passivation performance is required.

[0156] In some embodiments, the one-dimensional size of the bottom of the first texture structure 101 on the first conductive region A1 is smaller than the one-dimensional size of the bottom of the second texture structure 102 on the gap region gap, so that the actual surface area of the gap region gap is larger than the planar area, that is, the specific surface area is larger, which can increase the area of the film layer covering the gap region gap and improve the passivation quality of the gap region gap. That is, by designing different sizes of texture structures on the bottom of the first conductive region A1 and the gap region gap, the passivation quality of the gap region gap can be more targetedly improved, and the prepared solar cell can obtain a higher cell conversion efficiency.

[0157] It should be noted that in an embodiment, a laser or chemical etching method can be used to form the first texture structure 101 and the second texture structure 102 on the first conductive region A1 and the gap region gap. The one-dimensional size of the bottom of the first texture structure 101 and the second texture structure 102 can be the distance between the farthest two points of the orthographic projection of the first texture structure 101 or the second texture structure 102 on the first surface A, which is not limited herein. In some examples, when measuring the one-dimensional size, the film layer surface can be directly measured by a testing instrument (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.).

[0158] For example, the bottom of the first texture structure 101 and the second texture structure 102 is a polygonal plane, specifically, the bottom of the first texture structure 101 and the second texture structure 102 can be at least one of a rhombus, a square, a trapezoid, an approximately rhombus, an approximately square, and an approximately trapezoid. Of course, the bottom of the first texture structure 101 and the second texture structure 102 can also be other shapes of polygons, which are not limited herein.

[0159] Optionally, the one-dimensional size of the bottom of the first texture structure 101 is 5-9 um, and further, the one-dimensional size of the bottom of the first texture structure 101 can be 5 um, 6 um, 7 um, 7.5 um, 8 um or 9 um. Of course, the one-dimensional size of the bottom of the first texture structure 101 can also be other values within the above range, which can be set according to actual needs, and is not limited herein.

[0160] Optionally, the one-dimensional size of the bottom of the second texture structure 102 is 9-18 um, and further, the one-dimensional size of the bottom of the second texture structure 102 can be 9 um, 11 um, 14 um, 15 um, 17 um or 18 um. Of course, the one-dimensional size of the bottom of the second texture structure 102 can also be other values within the above range, which can be set according to actual needs, and is not limited herein.

[0161] Specifically, if the one-dimensional size of the bottom of the first texture structure 101 and the second texture structure 102 is too small, the unevenness of the surface of the first conductive area A1 and the gap area gap will be increased, which is not conducive to the subsequent film plating quality of the gap area gap. If the one-dimensional size of the bottom of the first texture structure 101 and the second texture structure 102 is too large, the preparation difficulty of the first texture structure 101 and the second texture structure 102 will be increased, and the one-dimensional size being too large will result in the specific surface area of the gap area gap being small, which cannot achieve the purpose of increasing the subsequent film plating area, thereby being not conducive to the passivation of the gap area gap. In actual application, when the one-dimensional size of the bottom of the first texture structure 101 is 5-9 um and the one-dimensional size of the bottom of the second texture structure 102 is 9-18 um, the preparation difficulty of the gap area gap can be reduced, the preparation efficiency can be improved, and the passivation quality of the gap area gap can be higher, thereby improving the conversion efficiency of the solar cell.

[0162] Optionally, the depth of the first texture structure 101 and the second texture structure 102 is 0.05-2 um. For example, the first texture structure 101 and the second texture structure 102 can be a recess structure, and the recess depth of the recess structure can be 0.05 um, 0.1 um, 0.15 um, 0.2 um, etc. Of course, the recess depth of the recess structure can also be other values within the above range, which can be set according to actual needs, and is not limited herein. In the embodiment, when the recess depth of the recess structure is 0.05 um-2 um, the unevenness of the surface of the gap area gap can be controlled within the required range, which is conducive to improving the passivation effect of the gap area gap.

[0163] In some embodiments, the gap area gap is provided with a pyramid-shaped suede structure. In actual application, the pyramid-shaped suede structure can reduce reflection, increase light absorption, improve photoelectric conversion efficiency, etc.

[0164] Specifically, the texturing process forms a layer of textured structure on the surface of the gap, which can increase the roughness of the surface of the silicon substrate 10, thereby reducing the reflection of light and increasing the absorption of light. The textured structure can change the incident angle and propagation path of light, form a light trap, further increase the density of photo-generated carriers, and ultimately improve the photoelectric conversion rate of the solar cell.

[0165] In some embodiments, the second width W2 of the central gap G2 along the first direction X is 1-3 mm, so as to control the width of the first conductive region A1 along the first direction X within a suitable range, and facilitate the setting of the tunneling oxide layer 12 and the first doped conductive layer 11 on the first conductive region A1. For example, the distance between the centers of the two adjacent first conductive regions A1 along the first direction X can be 1 mm, 1.2 mm, 1.5 mm, 2.2 mm, 2.5 mm, or 3 mm, etc. The embodiments of the present application do not make specific limitations on the distance between the centers of the two adjacent first conductive regions A1 along the first direction X.

[0166] For example, the ratio of the second width W2 to the first distance W3 can be 0.2, 0.35, 0.45, 0.5, 0.6, or 0.7, etc. The embodiments of the present application do not make specific limitations on the ratio of the second width W2 to the first distance W3.

[0167] Optionally, the second width W2 of the central gap G2 along the first direction X is 0.5-1.5 mm, so as to make the lateral transport distance of the photo-generated carriers more appropriate and facilitate processing. For example, the second width W2 of the central gap G2 along the first direction X can be 0.5 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.3 mm, or 1.5 mm, etc. The embodiments of the present application do not make specific limitations on the second width W2 of the central gap G2 along the first direction X.

[0168] Optionally, the distance between the centers of the two adjacent first conductive regions A1 along the first direction X is 1-3 mm, so as to control the width of the first conductive region A1 along the first direction X within a suitable range, and facilitate the setting of the tunneling oxide layer 12 and the first doped conductive layer 11 on the first conductive region A1. For example, the distance between the centers of the two adjacent first conductive regions A1 along the first direction X can be 1 mm, 1.2 mm, 1.5 mm, 2.2 mm, 2.5 mm, or 3 mm, etc. The embodiments of the present application do not make specific limitations on the distance between the centers of the two adjacent first conductive regions A1 along the first direction X.

[0169] In some embodiments, the solar cell further includes a first passivation layer 16, which is disposed on the side of the first doped conductive layer 11 facing away from the silicon substrate 10. The first passivation layer may include a first region and a second region, the first region being opposite to the central spacer region G2 and the second region being opposite to the edge spacer region G1. The first region is provided with a first sub-passivation layer, and the second region is provided with a second sub-passivation layer. The thickness of the second sub-passivation layer is greater than the thickness of the first sub-passivation layer. That is, the first passivation layer includes a first sub-passivation layer and a second sub-passivation layer.

[0170] In specific applications, since there are more defects on the side of the edge spacing region G1 closer to the edge of the cell, it is beneficial to obtain a better passivation effect by making the second sub-first passivation layer on the edge spacing region G1 thicker.

[0171] The following provides a processing flow for a solar cell according to an embodiment of this application:

[0172] First, a full-length tunneling oxide layer 12 and a first doped conductive layer 11 can be deposited on the first surface A of the silicon substrate 10. The tunneling oxide layer 12 can be a tunneling oxide layer, and the first doped conductive layer 11 can be a doped polysilicon layer.

[0173] Then, a laser patterning process is performed on the prepared first doped conductive layer 11 to modify the first doped conductive layer 11, forming an edge spacer region G1 and a center spacer region G2. The edge undoped region and the center undoped region can be prepared by a laser process, or by different laser processes. For example, the first doped conductive layer 11 at the edge and center can be modified by using lasers with different laser powers.

[0174] Finally, selective etching is performed. A chain etching machine is used to remove the tunneling oxide layer 12 deposited around the front and edges of the solar cell. A tank etching machine is used to remove the tunneling oxide layer 12, the first doped conductive layer 11, and a portion of the underlying silicon substrate 10 in the gap area, thus forming the gap area. It should be noted that the order of selective etching can be adjusted. For example, the chain etching machine can be used first to remove the tunneling oxide layer 12 deposited around the front and edges of the solar cell, and then the tank etching machine can be used to remove the tunneling oxide layer 12, the first doped conductive layer 11, and a portion of the underlying silicon substrate 10 in the gap area, thus forming the gap area; or the tank etching machine can be used first to remove the tunneling oxide layer 12, the first doped conductive layer 11, and a portion of the underlying silicon substrate 10 in the gap area, thus forming the gap area, and then the chain etching machine can be used to remove the tunneling oxide layer 12 deposited around the front and edges of the solar cell. No special limitation is made here.

[0175] In summary, the solar cells of this application embodiment have at least the following advantages:

[0176] In this embodiment, the depth of the edge spacing region G1 of the solar cell is less than the depth of the central spacing region G2. During the cleaning process of the laser-patterned spacing region gap, the smaller depth of the edge spacing region G1 allows for cleaning with a lower cleaning intensity. This reduces damage to the edge area of ​​the solar cell during cleaning, preventing edge chipping and improving the yield rate of the solar cell.

[0177] Laser cutting is used to cut a full-cell solar cell into multiple slabs, which are then encapsulated into photovoltaic modules. This significantly reduces current loss compared to modules made from a single-cell solar cell. However, during the implementation of this invention, it was discovered that the doped layer near the cut surface is easily damaged in laser-cut multi-slab solar cells. Significant carrier recombination easily occurs between the edges of the solar cell near the cut surface and the cut surface, severely increasing the efficiency loss of the solar cell. By setting an edge spacing region between the cut edge or non-cut edge and the conductive region, the transport path of carriers from the conductive region to the side surface can be interrupted, suppressing significant carrier recombination at the side surface and near the edge, thereby reducing cell efficiency loss.

[0178] Referring to FIG2, a schematic diagram of the light-receiving surface structure of a solar cell according to an embodiment of the present application is shown; referring to FIG3, a schematic diagram of the back-lighting surface structure of the solar cell shown in FIG2 is shown; referring to FIG4, a schematic diagram of the cross-sectional structure of the solar cell shown in FIG2 is shown; referring to FIG5, a schematic diagram of the back-lighting surface structure of another solar cell according to an embodiment of the present application is shown; and referring to FIG6, a schematic diagram of the cross-sectional structure of the solar cell shown in FIG5 is shown.

[0179] As shown in Figures 2 to 6, the solar cell may specifically include: a silicon substrate 10, which may include a first surface A and a second surface B disposed opposite to each other along a third direction Z, and a side surface C connecting the first surface A and the second surface B. The side surface C may include a cut surface C1 and a non-cut surface C2. A first conductive region A1 is disposed on the first surface A, and an edge gap region G1 between the first conductive region A1 and the cut surface C1 is called a first isolation groove 33. There is a height difference between the surface of the first isolation groove 33 and the surface of the first conductive region A1, and a connecting side is provided between the first conductive region A1 and the first isolation groove 33. A first doped conductive layer 11 is disposed on the first conductive region A1.

[0180] In this embodiment, a first isolation groove 33 is provided between the first conductive region A1 of the first surface A of the solar cell and the cut surface C1. During the slab preparation process of the solar cell, the first isolation groove 33 can prevent the force generated by the cut surface C1 during the slab preparation process from being transmitted to the edge of the first doped conductive layer 11 near the cut surface C1, thus preventing damage to the edge of the first doped conductive layer 11 and the formation of carrier recombination centers. Moreover, the first isolation groove 33 can also cut off the carrier transport channel from the first conductive region A1 to the cut surface C1, suppressing significant carrier recombination at the cut surface and the edge position near the cut surface C1, thereby reducing cell efficiency loss.

[0181] In specific applications, a first doped conductive layer 11 can be deposited on the entire first surface A of the entire solar cell, and an inner extension layer of a certain depth can be formed on the first surface A of the silicon substrate 10. A doped glass layer can also be formed on the surface of the first doped conductive layer 11. In the area of ​​the entire solar cell that needs to be sliced, the first doped conductive layer 11 in that area is removed, thus forming a first isolation trench 33 between the first conductive area A1 and the cutting surface C1. Specifically, the doped glass layer in the area of ​​the first isolation trench 33 can be formed first by laser etching, and then the residue on the surface of the area of ​​the first isolation trench 33 can be removed by wet etching, and part of the silicon substrate in that area can be etched downwards to finally form the first isolation trench 33. During the wet etching process, the area outside the first isolation trench 33 will not react with the solution because the outermost part is covered by the doped glass layer. As shown in Figures 4 and 6, the area corresponding to the first isolation trench 33 does not have the first doped conductive layer 11, and the surface of the first isolation trench 33 is lower than the surface of the first conductive area A1, that is, there is a height difference between the surface of the first isolation trench 33 and the surface of the first conductive area A1. In practical applications, there is a connecting side between the first conductive area A1 and the first isolation groove 33. The connecting side can be a vertical side or an inclined side. In this embodiment, the shape of the connecting side is not specifically limited.

[0182] In the embodiments of this application, the height difference between the surface of the first conductive region A1 and the surface of the first isolation trench 33 can ensure that the inner expansion layer of the first isolation trench 33 region is completely removed during the formation of the first isolation trench 33, further cutting off the transmission channel of photogenerated carriers from the inner expansion layer to the cutting surface C1, suppressing significant carrier recombination at the cutting surface and the edge position near the cutting surface C1, thereby reducing battery efficiency loss.

[0183] In specific applications, the silicon substrate 10 can serve as the structural body of a solar cell. The material of the silicon substrate 10 can include one or more of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In some embodiments, the material of the silicon substrate 10 can also be silicon carbide, organic materials, or multi-component compounds. Multi-component compounds can include, but are not limited to, materials such as perovskite, gallium arsenide, cadmium telluride, and copper indium selenide.

[0184] For example, the silicon substrate 10 in this application is a monocrystalline silicon substrate.

[0185] In practical applications, laser cutting can be used to form the solar cells of this embodiment when cutting a full solar cell into half or quarter solar cells. In this solar cell, the side surface C formed by laser cutting is the cutting surface C1, while the side surface C formed directly from the side of the original full solar cell can be the non-cutting surface C2.

[0186] For example, in the half-cell solar cell shown in Figures 2 to 4, the four side surfaces C of the solar cell may include one cut surface C1 and three uncut surfaces C2. Similarly, in the quad-cell solar cell shown in Figures 5 and 6, the four side surfaces C of the solar cell may include two cut surfaces C1 and two uncut surfaces C2.

[0187] In specific applications, the first surface A of the solar cell includes a first conductive region A1, on which a tunneling oxide layer 12, a first doped conductive layer 11 and an electrode are disposed, and the electrode is electrically connected to the first doped conductive layer 11.

[0188] In this embodiment, after forming the first isolation trench 33, a first passivation layer 16 can be formed on the surface of the first doped conductive layer 11 away from the silicon substrate 10, on the surface of the first isolation trench 33, and on the surface of the connecting side. The first passivation layer 16 can be used to passivate the surfaces of the first isolation trench 33 and the first doped conductive layer 11. The electrode can be electrically connected to the first doped conductive layer 11 by burning through at least a portion of the first passivation layer 16 under the electrode through a high-temperature sintering process, or by first removing the first passivation layer 16 under the electrode through a laser or etching paste, and then setting the electrode to achieve electrical connection between the electrode and the first doped conductive layer 11.

[0189] In specific applications, the first isolation trench 33 can keep the edge of the first doped conductive layer 11 near the cutting surface C1 away from the cutting position of the laser slicing during the slicing process, thereby reducing the damage to the surface of the first doped conductive layer 11 or the surface of the first isolation trench 33 caused by the particles sputtered during the laser slicing process. In addition, the first passivation layer 16 can cover part of the surface and edge of the first doped conductive layer 11 in the first conductive region A1, the first isolation trench 33 and the connecting side surface, effectively recombine the dangling bonds or other defects on these surfaces, reduce the recombination on the surface of the solar cell and improve the cell efficiency.

[0190] For example, the first passivation layer 16 may also be disposed on the second surface B, the diced surface C1, and the undicated surface C2 of the silicon substrate 10. The material of the first passivation layer 16 may include, but is not limited to, at least one of aluminum oxide, silicon nitride, silicon oxynitride, and silicon dioxide. The first passivation layer 16 may be a stacked structure of one or more of the above materials. This application embodiment does not specifically limit the material of the first passivation layer 16. For example, the structure of the first passivation layer 16 may be a stacked structure of aluminum oxide, silicon nitride, and silicon oxynitride. It should be noted that the stacked structure and thickness of the first passivation layer on the second surface B and the first surface A of the silicon substrate 10 may be the same or different. This application embodiment does not specifically limit this.

[0191] Optionally, the height difference is a first height, which ranges from 1 micrometer to 10 micrometers. By setting the depth of the first isolation trench 33 in the range of 1 to 10 micrometers, it is possible to ensure the removal of the inner extension layer formed in the silicon substrate 10 below the first doped conductive layer 11, cut off the transport channel of photogenerated carriers from the inner extension layer to the dicing surface C1, and reduce the influence of the doping elements of the inner extension layer on the passivation effect of the first passivation layer 16.

[0192] For example, the first height can be 1 micrometer, 2 micrometers, 5 micrometers, 8.5 micrometers, and 10 micrometers, etc., and the embodiment of this application does not specifically limit the value of the first height. Preferably, the depth of the first isolation groove 33 is set in the range of 2 to 6 micrometers.

[0193] Referring to Figure 7, a cross-sectional structural diagram of another solar cell according to an embodiment of this application is shown. As shown in Figure 7, a first conductive region A1 is provided on the first surface A, and a first doped conductive layer 11 is provided on the first conductive region A1. A second conductive region B1 is provided on the second surface B, and a second doped conductive layer 21 is provided on the second conductive region B1. A third isolation trench 35 can be provided between the second conductive region B1 and the cutting surface C1. By controlling the depths of the first isolation trench 33 and the third isolation trench 35 within the aforementioned range, the inner expansion layer can be removed. During the laser slicing process, reducing the pushing effect of the laser thermal effect on the inner expansion layer can reduce the probability of contact between doped conductive layers of different polarities on the cutting surface C1, thereby reducing the risk of leakage at the edge of the cell.

[0194] It should be noted that the materials of the first doped conductive layer 11 and the second doped conductive layer 21 may include at least one semiconductor material selected from monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. The doping type of the conductive layer can be N-type or P-type. Specifically, an N-type doped conductive layer can be obtained by introducing the aforementioned donor impurities into these semiconductor materials, or a P-type doped conductive layer can be obtained by introducing the aforementioned acceptor impurities into these semiconductor materials. Specifically, the first doped conductive layer 11 can be an N-type doped polycrystalline silicon layer, and the second doped conductive layer 21 can be a P-type doped monocrystalline silicon layer, that is, a P-type diffusion layer is formed on the surface of the silicon substrate by diffusion or other means. In this case, the surface of the second doped conductive layer 21 shares the same surface as the surface of the second conductive region B1.

[0195] In some optional embodiments of this application, the surface of the first isolation groove 33 is provided with a pyramid structure or a textured structure to reduce the reflectivity of the first isolation groove 33 and improve the light absorption efficiency of the first isolation groove 33.

[0196] In some optional embodiments of this application, the surface of the third isolation trench 35 is provided with a pyramid structure or a textured structure to reduce the reflectivity of the third isolation trench 35 and improve the light absorption efficiency of the third isolation trench 35.

[0197] In some optional embodiments of this application, the texture structure may be a recessed structure embedded in the surface of the first isolation groove 33 or the third isolation groove 35, and the projected shape of its bottom surface or opening may be rectangular, rhomboid, parallelogram, approximately rectangular, approximately rhomboid, or parallelogram-shaped. The bottom surface size of the texture structure ranges from 1 to 10 micrometers, specifically 1 micrometer, 2 micrometers, 5 micrometers, 8.5 micrometers, and 10 micrometers. The bottom surface size may be the long side, short side, diagonal, or distance between the farthest points of the projected shape of the bottom surface or opening, and is not specifically limited here. The bottom surface size of the texture structure may be the size of a single texture structure bottom surface or the average value of the bottom surface sizes of texture structures within a certain area.

[0198] In some optional embodiments of this application, the dimensions of the pyramid structure include the base dimension or the height of the pyramid structure. The base dimension of the pyramid structure ranges from 1 to 3 micrometers, and is the longest distance between the base dimension and the long side, short side, diagonal, or two endpoints of the projection of the base of the pyramid structure onto the backlit surface, specifically 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, and 3 micrometers; the height of the pyramid structure refers to the vertical distance from the apex of the pyramid structure to the base, specifically 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, and 3 micrometers. The dimensions of the pyramid structure can be the size of a single pyramid base dimension or the average size of the base dimension or height of a pyramid structure within a certain area.

[0199] As shown in Figures 3 and 5, there are multiple first conductive regions A1, and multiple interval regions gap are also provided on the first surface A. The multiple first conductive regions A1 and the multiple interval regions gap are alternately arranged on the first surface A along the first direction X, and the first direction X is perpendicular to the cutting surface C1. As shown in Figures 4 and 6, the width of the first isolation groove 33 along the first direction X is a first width W1, and the width of the interval region gap along the first direction X is a second width W2. The first width W1 is smaller than the second width W2.

[0200] In practical applications, the gap region is mainly used to reduce the negative impact of parasitic absorption caused by the doped conductive layer on battery efficiency and to increase the area of ​​the first surface A that receives incident light. The first isolation groove 33 is mainly used to avoid stress transmission and reduce carrier recombination. Therefore, while meeting the usage requirements, setting the area of ​​the first isolation groove 33 to be smaller than the width of the gap region allows for an increase in the area of ​​the first conductive region A1 while still meeting other structural requirements. Furthermore, since offset is more likely to occur when printing grid lines at the edge of the battery cell, increasing the width of the first conductive region A1 at the edge can reduce the alignment difficulty in subsequent electrode printing processes.

[0201] Optionally, the ratio of the first width W1 to the second width W2 is in the range of 25%-75%, so that the first isolation trench 33 can both prevent the stress of the cutting surface C1 from being transmitted to the first doped conductive layer 11, and prevent damage to the edge of the first doped conductive layer 11 and carrier recombination, and at the same time reduce the impact of the setting of the first isolation trench 33 on the energy collection of the solar cell.

[0202] In some optional embodiments of this application, the first width W1 ranges from 150 to 700 micrometers, specifically 150 micrometers, 200 micrometers, 250 micrometers, 300 micrometers, 400 micrometers, 500 micrometers, 600 micrometers, or 700 micrometers. The second width W2 ranges from 400 to 1500 micrometers, specifically 400 micrometers, 500 micrometers, 600 micrometers, 700 micrometers, 800 micrometers, 900 micrometers, 1100 micrometers, 1300 micrometers, or 1500 micrometers.

[0203] In specific applications, there are multiple first conductive regions A1, and multiple groove regions, also referred to as gap regions, are also provided on the first surface A. The multiple first conductive regions A1 and multiple gap regions are alternately arranged on the first surface A along a first direction X, which is perpendicular to the cutting surface C1. The height difference between the surface of the first isolation groove 33 and the surface of the first conductive region A1 is the first height, and the height difference between the surface of the gap region and the surface of the first conductive region A1 is the second height. The difference between the first height and the second height is less than or equal to 1 micrometer, so that the height difference between the surface of the first isolation groove 33 and the surface of the gap region is controlled within a reasonable range. Here, the gap region can be a central gap region G2.

[0204] In practical applications, the first isolation groove 33 and the gap area can be formed in the same process to control the height difference between them. This avoids the need for a separate process to manufacture the first isolation groove 33, greatly simplifying the solar cell manufacturing process and reducing the manufacturing cost of solar cells.

[0205] In some optional embodiments of this application, the height difference between the surface of the first isolation trench 33 and the surface of the first conductive region A1 is a first height, and the height difference between the surface of the gap region and the surface of the first conductive region A1 is a second height. The first height is greater than the second height, that is, the depth of the first isolation trench 33 is less than the depth of the gap region, and the difference between the first height and the second height is less than or equal to 1 micrometer. This setting can both reduce the damage to the edge area of ​​the solar cell during the cleaning process and avoid edge chipping, and control the height difference between the two areas within a reasonable range.

[0206] In some optional embodiments of this application, an edge spacing region G1 is provided between the first conductive region A1 and the non-cut edge, and the depth of the edge spacing region G1 is less than the depth of the center spacing region G2. During the cleaning process of the laser-actuated area of ​​the first conductive region A1, the smaller depth of the edge spacing region G1 allows for cleaning with a lower cleaning intensity. This reduces damage to the edge area of ​​the solar cell during the cleaning process, avoids edge chipping, and improves the yield of the solar cell.

[0207] In this embodiment, along the extension direction of the cutting surface C1, the length of the first isolation groove 33 accounts for 50% to 100% of the length of the cutting surface C1, so as to increase the area of ​​the first conductive region A1 and prepare for the subsequent setting of edge gate lines, thereby reducing the contact resistance between the edge gate lines and the silicon substrate 10.

[0208] In practical applications, when the length of the first isolation groove 33 accounts for 50% to 100% of the length of the cut surface C1, it can prevent the length of the first isolation groove 33 from being too short and failing to cut off the transmission channel of charge carriers from the first conductive region A1 or the inner expansion layer to the cut surface C1.

[0209] Furthermore, the length of the first isolation groove 33 can be matched to the actual electrode pattern, and the length of the first isolation groove 33 can be selected accordingly. For example, the length of the first isolation groove 33 as a percentage of the length of the cutting surface C1 can be 50%, 65%, 78%, 95%, or 100%, etc. In this embodiment of the application, no specific limitation is made on the percentage of the length of the first isolation groove 33 as a percentage of the length of the cutting surface C1.

[0210] In practical applications, during the process of cutting a full cell into four cells, the solar cells at the beginning and end have only one cutting surface C1 (as shown in Figures 2 to 4), while the two solar cells in the middle have two cutting surfaces C1 (as shown in Figures 5 and 6).

[0211] As shown in Figures 5 and 6, the cutting surface C1 may specifically include a first cutting surface 31 and a second cutting surface 32, which are arranged opposite to each other; the second cutting surface 32 and the first conductive region A1 may also include a second isolation groove 34, and there is a height difference between the surface of the second isolation groove 34 and the surface of the first conductive region A1, which ranges from 2 micrometers to 6 micrometers; the first passivation layer 16 is disposed on the surface of the second isolation groove 34.

[0212] In specific applications, the second isolation trench 34 functions similarly to the first isolation trench 33. Furthermore, the principle for controlling the height difference between the second isolation trench 34 and the surface of the first conductive region A1, the width of the second isolation trench 34, the structure of the first passivation layer 16, and related beneficial effects can be found in the description of the first isolation trench 33 section above, and will not be repeated here.

[0213] In some optional embodiments of this application, as shown in FIG7, the second surface B may include a second conductive region B1, the second conductive region B1 being provided with a second doped conductive layer 21; a third isolation trench 35 is provided between the second conductive region B1 and the cut surface C1, the surface of the third isolation trench 35 and the surface of the second conductive region B1 having a height difference ranging from 2 micrometers to 10 micrometers; the first isolation trench 33 and the third isolation trench 35 are correspondingly provided along the thickness direction of the solar cell. A first passivation layer 16 is provided on the side of the second doped conductive layer 21 away from the silicon substrate 10 and on the surface of the third isolation trench 35.

[0214] In specific applications, removing the second doped conductive layer 21 on the second surface B near the edge of the cut surface C1 cuts off the carrier transport channel to the cut surface C1, which can suppress carrier recombination caused by defects in the cut surface C1.

[0215] In specific applications, when the second doped conductive layer 21 is P-type doped, the second doped conductive layer 21 on the second surface B of the solar cell forms a PN junction with the silicon substrate 10. Removing the second doped conductive layer 21 near the edge of the cut surface C1 on the second surface B cuts off the carrier transport channel to the cut surface C1, suppressing carrier recombination caused by defects in the cut surface C1, and reducing the negative impact of carriers in the P-type doped layer on the field passivation effect of passivation layer materials such as alumina, thus improving the passivation effect on the cut surface C1. This structure, when applied to a battery, can reduce dark current loss, increase open-circuit voltage and fill factor, and improve photoelectric conversion efficiency.

[0216] In practical applications, the formation method of the third isolation trench 35, the height difference between the surface of the third isolation trench 35 and the surface of the second conductive region B1 and its beneficial effects, as well as the setting method and effects of the first passivation layer 16, can be referred to the first isolation trench 33, the first conductive region A1 and the first passivation layer 16 in the aforementioned embodiments, and will not be elaborated here.

[0217] It should be noted that when the second doped conductive layer 21 is a doped single-crystal silicon layer, its diffusion depth in the silicon substrate 10 is greater than the depth of the inner expansion layer formed in the silicon substrate below the first doped conductive layer 11. Therefore, the minimum height difference between the surface of the third isolation trench 35 and the surface of the second conductive region B1 should be greater than the minimum height difference between the surface of the first isolation trench 33 and the surface of the first conductive region A1.

[0218] In some optional embodiments of this application, as shown in Figures 4, 6 and 7, the solar cell may further include a second passivation layer 36, which is located on the surface of the cut surface C1; the second passivation layer 36 extends to the first surface A, located on the side of the first passivation layer 16 away from the silicon substrate 10, and the second passivation layer 36 at least covers the first isolation trench 33 and the first conductive region A1 adjacent to the first isolation trench 33, and the second passivation layer 36 covers the side of the first doped conductive layer 11 away from the silicon substrate 10.

[0219] In specific applications, the second passivation layer 36 can at least cover the diced surface C1, passivating the surface of the diced surface C1. Since the second passivation layer 36 can also extend to the first surface A and cover the first isolation trench 33 and the first conductive region A1 adjacent to the first isolation trench 33, the second passivation layer 36 can further passivate the first isolation trench 33 and the side surface formed by the recess of the first isolation trench 33 and the silicon substrate 10 portion of the first conductive region A1, achieving surface passivation of this portion, and further improving the surface passivation effect of the first isolation trench 33 and the first doped conductive layer 11 adjacent to the first isolation trench 33.

[0220] Specifically, the material of the second passivation layer 36 can be aluminum oxide, silicon oxide, silicon nitride, etc., and this application embodiment does not specifically limit the material of the second passivation layer 36. The thickness of the second passivation layer 36 can be selected from any one of 60 to 150 nanometers as needed, and this application embodiment does not specifically limit the thickness of the second passivation layer 36 accordingly.

[0221] In some optional embodiments of this application, as shown in FIG7, the solar cell may further include a second passivation layer 36, which is located on the surface of the cut surface C1; the second passivation layer 36 extends to the first surface A, located on the side of the first passivation layer 16 away from the silicon substrate 10, and the second passivation layer 36 at least covers the first isolation trench 33 and the first conductive region A1 adjacent to the first isolation trench 33, and the second passivation layer 36 covers the side of the first doped conductive layer 11 away from the silicon substrate 10; the second passivation layer 36 extends to the second surface B, located on the side of the first passivation layer 16 away from the silicon substrate 10, and the second passivation layer 36 at least covers the third isolation trench 35 and the second conductive region B1 adjacent to the third isolation trench 35, and the second passivation layer 36 covers the side of the second doped conductive layer 21 away from the silicon substrate 10.

[0222] In some alternative embodiments of this application, a fourth isolation groove is further provided between the first conductive region A1 and the non-cut surface C2; ​​the difference between the surface height of the fourth isolation groove and the surface height of the first conductive region A1 is less than 1 micrometer, and the width of the fourth isolation groove is less than the width of the first isolation groove 33.

[0223] In practical applications, during the solar cell manufacturing process, the solar cells need to float in the processing liquid. By setting a fourth isolation trench between the non-cut surface C2 and the first conductive region A1, excessive etching of the first doped conductive layer 11 at the edge of the backlight surface by the processing liquid can be prevented, thereby improving the yield of the solar cells during the manufacturing process. Furthermore, by controlling the surface height of the fourth isolation trench to be within 1 micrometer of the surface height of the first conductive region A1, and by controlling the width of the fourth isolation trench to be smaller than the width of the first isolation trench 33, the impact of the fourth isolation trench on the structure of the solar cell itself can be minimized.

[0224] In the implementation of this application, it was further discovered that in a solar cell, after removing the first doped conductive layer 11 of the spacer gap, the carriers generated in the spacer gap grow along the path from the first doped conductive layer 11 to the first electrode 15. At this point, the probability of carriers generated on the backlight surface recombinating within or on the surface of the silicon substrate 10 is greatly increased. Therefore, better passivation is needed to reduce the possibility of carrier recombination during transport. By further optimizing the surface morphology of the spacer gap and the side surface of the cell, the passivation performance of the solar cell can be improved, reducing the possibility of carrier recombination.

[0225] According to one embodiment of this application, a solar cell is provided. FIG8 is a partial cross-sectional schematic diagram of a solar cell according to an embodiment of this application, FIG9 is a top schematic diagram of the solar cell shown in FIG8, and FIG10 is a side schematic diagram of the solar cell shown in FIG8. As shown in FIG8 to FIG10, the solar cell of this application includes: a silicon substrate 10, a first doped conductive layer 11, a first passivation layer 16, and a first electrode 15, wherein: the silicon substrate 10 includes a first surface A, a second surface (not shown in the figure), and a side surface C connecting the first surface A and the second surface; the first surface A includes a first direction X. A first conductive region A1 is spaced apart, with a gap between adjacent first conductive regions A1. The gap has a second texture structure 102, and the side surface C has a fourth texture structure 104. A first doped conductive layer 11 is located on the first conductive region A1 of the silicon substrate 10. The first conductive region A1 has a first texture structure 101. A first passivation layer 16 is located on the surface of the gap and on at least one of the following structural surfaces: the second surface, the side surface C, and the surface of the first doped conductive layer 11 away from the silicon substrate 10. A first electrode 15 is located on the first doped conductive layer 11 and is in electrical contact with the first doped conductive layer 11.

[0226] It is understood that, as shown in Figure 8, in some examples, the first passivation layer 16 is located on the surface of the spacer region gap and the first doped conductive layer 11 away from the silicon substrate 10. In other examples, the first passivation layer 16 may also be located on the side surface C and / or the second surface B. The first passivation layer 16 on these surfaces may be prepared in the same deposition process or in different deposition processes without any particular limitation.

[0227] According to some embodiments of this application, the height of the second texture structure 102 is less than the height of the first texture structure 101, and / or the surface size of the second texture structure 102 is greater than the surface size of the first texture structure 101; the surface size of the fourth texture structure 104 is greater than the surface size of the first texture structure 101.

[0228] In the embodiments of this application, by removing the first doped conductive layer 11 of the non-electrode region, i.e. the gap region, and forming a patterned first doped conductive layer 11 on the first conductive region A1, i.e. the conductive region, it is beneficial to reduce optical parasitic absorption. Based on this, by forming a textured structure of different sizes between the first doped conductive layer 11 and the spacer gap, the different requirements of the first doped conductive layer 11 and the spacer gap can be taken into account. For example, an electrode is formed on the first conductive region A1. By designing a first textured structure 101 with a larger height on the surface of the first conductive region A1, it is more conducive to contact with the electrode paste and improves the electrical contact performance. The first passivation layer 16 can be deposited on the surface of the spacer gap. By setting a second textured structure 102 with a larger surface size, it is more conducive to forming a uniform passivation antireflection layer, such as an alumina layer with a nanometer-thickness or a silicon nitride stack, etc., ensuring uniformity while ensuring that it has a suitable thickness. This avoids the first passivation layer 16 being too thick, which would be detrimental to the formation of a high-density and high-uniformity first passivation layer 16, and thus affect the tunneling and passivation effect of the first passivation layer 16.

[0229] Compared to the spacer gap, the first doped conductive layer 11 provides additional passivation to the conductive region. Therefore, the spacer gap requires a higher-quality first passivation layer 16 to achieve a better passivation effect. By differentiating the texture structure between the conductive region and the spacer gap—that is, by designing a second texture structure 102 with a smaller height than the first texture structure 101 and a larger surface area than the first texture structure 101—a higher-quality first passivation layer 16 can be formed, further enhancing the passivation effect of the spacer gap. In summary, by designing a differentiated structure between the conductive region and the spacer gap, the different needs of the conductive region and the spacer gap can be better met, thereby optimizing battery performance and improving battery efficiency. According to one embodiment of this application, based on the difference in corrosion degree between the side surface C and the first surface A in acid and alkali washing processes, the surface area of ​​the fourth texture structure 104 can be adjusted to be larger than that of the second texture structure 102 by selecting appropriate acid and alkali washing conditions and cycles. The side surface C has a fourth texture structure 104, the surface size of which is larger than that of the second texture structure 102. In the solar cell of this application, the first doped conductive layer 11 of the gap region is removed. The carriers generated in the gap region grow through the path of the first doped conductive layer 11 to the first electrode 15. At this time, the probability of recombination of carriers generated on the back side within or on the surface of the semiconductor substrate is greatly increased. Therefore, better passivation is needed to reduce the possibility of carrier recombination during transport. In addition, due to the presence of the first doped conductive layer 11 or the fourth doped conductive layer 13 on some parts of the side of the cell, as well as areas with different surface heights formed during acid washing and alkaline washing processes, the roughness of the side surface C is relatively large. Therefore, designing the fourth texture structure 104 on the side surface C of the solar cell, whose surface size is larger than that of the second texture structure 102, can better improve the film quality of the first passivation layer 16 on the side surface C and improve its passivation effect. Thus, by increasing the back light-receiving area and reducing the probability of carrier recombination, the power of the back side of the solar cell is comprehensively improved, and the bifaciality of the solar cell is increased.

[0230] This design in solar cells fully utilizes the surface of the cell structure without a doped conductive layer for light absorption and efficient light conversion. In existing cell structures, surface morphology design improves power generation, particularly back-side power, thereby increasing the bifaciality. Furthermore, the size relationship between the surface dimensions of the fourth texture structure 104, the second texture structure 102, and the first texture structure 101 better balances the process of patterning the first conductive region A1 and the spacer region on the first surface A, reducing process complexity and improving production yield.

[0231] According to some embodiments of this application, similarly, based on the difference in corrosion degree between the side surface C and the first surface A in the acid and alkali washing process, by selecting appropriate acid and alkali washing conditions and times, the surface size of the fourth texture structure 104 can be adjusted to be larger than the surface size of the first texture structure 101. This size structure design can facilitate the preparation and formation of the fourth texture structure 104, improve preparation efficiency, and save preparation costs.

[0232] According to one embodiment of this application, the height of the fourth texture structure 104 on the side surface C is less than the height of the first texture structure 101, thereby reducing the surface roughness of the side surface C and further improving the coating quality of the side surface C. Roughness refers to the arithmetic mean of the absolute values ​​of the Z-direction deviation relative to the mean line over a sampling length. Roughness can be measured by comparison method, optical sectioning method, interferometry method, and stylus method.

[0233] According to one embodiment of this application, the height of the fourth texture structure 104 on the side surface C is greater than the height of the second texture structure 102. This structural design can improve the reflectivity of the side surface C, improve the reflectivity of the side surface C for light incident on the unused part of the battery and reflected onto the side surface C, further improve battery efficiency, and increase the bifaciality of the battery.

[0234] According to some embodiments of this application, the gap region can also be located in the edge region of the solar cell, in other words, it is set between the first conductive region A1 and the edge of the solar cell. In this way, when the gap region has the second texture structure 102, it is more conducive to improving the passivation effect of the edge region, improving the situation where edge carriers are prone to recombination, thereby improving the collection of edge carriers.

[0235] According to some embodiments of this application, the gap between the first conductive region A1 and the edge of the solar cell is called the edge gap G1, and the gap in the center region of the first surface is called the center gap G2. The depth of the edge gap G1 is less than the depth of the center gap G2, and the surface size of the second textured structure is greater than the surface size of the first textured structure, and the surface size of the fourth textured structure is greater than the surface size of the first textured structure. This differentiated textured structure size design, combined with the depth difference of the gaps, is more conducive to improving the passivation effect of the edge region, reducing the tendency for edge carriers to recombine, thereby improving the collection of edge carriers.

[0236] According to some embodiments of this application, the first surface A of the silicon substrate 10 can be the back surface of the battery. Generally, the front surface of the battery serves as the light-receiving surface, and the back surface serves as the back-lighting surface, or it can be light-receiving on both sides, in which case both the front and back surfaces serve as light-receiving surfaces. When the first surface A serves as the back surface of the battery, the requirements for passivation performance are relatively high. In this case, the differentiated setting between the second texture structure 102 and the first texture structure 101 is more conducive to leveraging their advantages in simultaneously improving the passivation effect of the electrical contact of the conductive area and the gap of the spacing area, which is more beneficial to improving the bifaciality and thus improving the battery efficiency. Of course, it is understood that this is not the only possibility; in some other embodiments, the first surface A can be the front surface of the battery.

[0237] According to the embodiments of this application, the doping type of the first doped conductive layer 11 can be N-type or P-type, which can be determined according to the battery type and the structure of the silicon substrate 10.

[0238] According to some embodiments of this application, the width of the first doped conductive layer 11 along the first direction X is less than or equal to 1000 μm, for example, it can be 100 μm, 200 μm, 400 μm, 600 μm, 800 μm, 1000 μm, etc. If the width of the first doped conductive layer 11 is too large, it will increase optical parasitic absorption and reduce the battery short-circuit current. If the width is too small, it will increase the difficulty of the process, seriously affect the production capacity, and also increase the tunneling resistance, affecting the series resistance of the battery.

[0239] According to some embodiments of this application, Figure 11 shows a schematic diagram of the structure of the second texture structure 102, the first texture structure 101, and the fourth texture structure 104. As shown in Figure 11, the second texture structure 102, the first texture structure 101, and the fourth texture structure 104 exhibit a polished microstructure morphology, which can be any morphology structure different from a flat surface, such as a texture structure composed of multiple grooves, a structure composed of multiple protrusions, or a texture structure composed of both grooves and protrusions. For example, the second texture structure 102 can exhibit a concave morphology, with its bottom surface being a polygonal plane. The shape of the polygonal plane includes at least one of rhombus, square, trapezoid, approximate rhombus, approximate square, and approximate trapezoid. It is understood that in the actual manufacturing process, the top surface morphology of the second texture structure 102 or the first texture structure 101 is irregular.

[0240] According to some embodiments of this application, as shown in FIG11, the height of the second texture structure 102, the first texture structure 101, and the fourth texture structure 104 refers to the vertical distance h between the bottom surface and the top surface adjacent to the bottom for a groove or protrusion. The surface dimensions of the second texture structure 102, the first texture structure 101, and the fourth texture structure 104 refer to the side length a of the bottom surface, such as the length of the long side, the width of the short side, the length of the diagonal, etc.

[0241] This application does not impose any restrictions on the measurement of the height and surface dimensions of the second texture structure 102, the first texture structure 101, and the fourth texture structure 104. Those skilled in the art can perform the measurements using conventional methods in the field. For example, the surface dimensions can be measured using a scanning electron microscope (SEM). In this case, the first passivation layer 16 on the surface of the solar cell can be removed before performing SEM testing on the surface of the solar cell. Of course, it is not limited to this. Since the first passivation layer 16 can be conformally deposited on the surface of the first doped conductive layer 11 and the gap region, and has a groove structure consistent with the surface of the first doped conductive layer 11 and the silicon substrate 10, SEM testing can also be performed directly on the second texture structure 102 and the first texture structure 101 of the solar cell from a top-view perspective, or SEM testing can be performed directly on the fourth texture structure 104 of the solar cell from a side-view perspective. Specifically, due to the varying heights of the second texture structure 102, the first texture structure 101, and the fourth texture structure 104, there is a significant brightness difference between the bottom and top surfaces. The bottom position can be determined on a top-view SEM image, and the length, width, or diagonal of the bottom surface can be measured to obtain the surface dimensions of the second texture structure 102 or the first texture structure 101. Similarly, for height measurement, the cross-section of the solar cell can be tested using SEM with or without removing the first passivation layer 16 from the solar cell surface. The height of the second texture structure 102 or the first texture structure 101 can be obtained by measuring the height difference between adjacent top and bottom surfaces.

[0242] It is understandable that the height of the second texture structure 102 is less than the height of the first texture structure 101. This can be because, in at least one comparison test area, the average height of the second texture structure 102 is less than the average height of the first texture structure 101, or, for example, the height of the second texture structure 102 is less than the minimum height of the first texture structure 101 for a proportion of 50%, 60%, 70%, or even 80% or more. Similarly, the surface size of the second texture structure 102 is greater than the surface size of the first texture structure 101. This can be because, in at least one comparison test area, the average surface size of the second texture structure 102 is greater than the average surface size of the first texture structure 101, or, for example, the maximum surface size of the second texture structure 101 is greater for a proportion of 50%, 60%, or even 80% or more. The surface size of the fourth texture structure 104 is greater than the surface size of the second texture structure 102, and this can be calculated in a similar way, which will not be elaborated further here.

[0243] According to some embodiments of this application, the height of the first texture structure 101 is less than or equal to 3 μm, for example, it can be 0.1 μm, 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm, etc. When the height of the first texture structure 101 exceeds 3 μm, the roughness of the first texture structure 101 is too large, the thickness of the doped conductive layer formed on the first texture structure 101 is larger, and the uniformity is worse, which is not conducive to the formation of a high-density and high-uniformity doped conductive layer. Setting the height of the first texture structure 101 within the above range can prevent the local phosphorus concentration from being too high due to the doped conductive layer, reduce the contact resistivity, increase the open-circuit voltage of the solar cell, and improve the fill factor and photoelectric conversion efficiency. Preferably, the height of the first texture structure 101 is less than or equal to 2 μm.

[0244] According to some embodiments of this application, the surface size of the second texture structure 102 is less than or equal to 25 μm, for example, it can be 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm, 24 μm, 25 μm, etc. If the surface size of the second texture structure 102 is too large, its surface undulations will be too gentle, which is not conducive to improving the light-trapping effect and reducing the light utilization rate. By setting the surface size of the second texture structure 102 within the above-mentioned range, and combining the differentiated surface sizes of the second texture structure 102 and the first texture structure 101, it is possible to balance ensuring the light-trapping effect and improving the passivation performance. Preferably, the surface size of the second texture structure 102 is less than or equal to 15 μm.

[0245] According to some embodiments of this application, the height of the second texture structure 102 can be 0.1–2 μm, for example, 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, etc. Thus, by controlling the height of the second texture structure 102 within the above range, it is more advantageous to ensure the formation of a first passivation layer 16 with uniform film formation and better film quality. The surface size of the second texture structure 102 can be 10–28 μm, for example, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, 20 μm, 22 μm, 24 μm, 25 μm, 28 μm, etc. Thus, by controlling the surface size of the second texture structure 102 within the above range, it is possible to simultaneously ensure light trapping effect and form a first passivation layer 16 with high density and high uniformity. For example, FIG12 is an SEM image of the second texture structure 102 of the present application embodiment. As shown in FIG12, the surface size of the second texture structure 102 is between 10 and 28 μm.

[0246] According to some embodiments of this application, the height of the first texture structure 101 can be 0.5–3 μm, for example, 0.5 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm, etc. Thus, by controlling the height of the first texture structure 101 within the above range, the uniformity of the doped conductive layer and the contact performance with the electrode can be better balanced. The surface size of the first texture structure 101 can be 1–15 μm, for example, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 15 μm, etc., and more preferably 5–15 μm. By controlling the surface size of the first texture structure 101 within the above range, its surface size will not be too small, which would lead to increased roughness and affect the uniformity and film quality of the deposited doped conductive layer.

[0247] According to some embodiments of this application, the height of the fourth texture structure 104 can be 0.2–2.5 μm, for example, 0.2 μm, 0.5 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.4 μm, 2.5 μm, etc. If the height of the fourth texture structure 104 is too high, it is not conducive to improving the coating quality; if the height is too low, it is not conducive to improving the light utilization rate. Therefore, by controlling the height of the fourth texture structure 104 within the above range, a balance can be achieved between light utilization rate and coating quality on the side surface C. The surface size of the fourth texture structure 104 can be 15–40 μm, for example, 15 μm, 18 μm, 20 μm, 22 μm, 24 μm, 26 μm, 28 μm, 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, etc. By controlling the surface dimensions of the fourth texture structure 104 within the aforementioned range, it is more beneficial to improve the coating quality on the side surface C, such as the uniformity of the film layer. In some examples, the projection shape of the fourth texture structure 104 on the side surface C can be square or rectangular, with the length of the base ranging from 25 to 40 μm, for example, 25 μm, 26 μm, 28 μm, 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, etc., and the length of the short side of the base ranging from 15 to 30 μm, for example, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, etc.

[0248] In the process of realizing the technical concept of this application, it was discovered that when using laser etching process to remove the first doped conductive layer 11, by adjusting the laser conditions, such as increasing the laser energy density, spot size and laser etching time, the texture structure of the gap region can be changed, which is beneficial to improving light utilization and thus improving battery efficiency.

[0249] Specifically, according to some embodiments of this application, Figure 13 is a top view of a solar cell according to an embodiment of this application, Figure 14 is a structural schematic diagram of the third texture structure 103 according to an embodiment of this application, and Figure 15 is a top SEM side view of a solar cell according to an embodiment of this application. As shown in Figures 13, 14, and 15, the gap region of this application may include multiple first sub-regions G3 and multiple second sub-regions G4, with the first sub-regions G3 and G4 alternately arranged along a second direction Y, where the second direction Y intersects with the first direction X; the first sub-regions G3 have a third texture structure 103, and the second sub-regions G4 have a second texture structure 102; the height of the second texture structure 102 is less than the height of the third texture structure 103, and / or the surface size of the second texture structure 102 is greater than the surface size of the third texture structure 103. It is understood that the third texture structure 103 may be a polished microstructure similar to the second texture structure 102 and the first texture structure 101, which will not be described in detail here.

[0250] Thus, after removing the doped conductive layer in the non-electrode region to reduce optical parasitic absorption, the gap on the back side can also serve as a light absorption area. The main light sources for the gap on the back side are light reflected directly from the ground and light incident from the front that is not utilized and reaches the back side. The second textured structure 102 has a larger and flatter surface size and lower reflectivity, thus better utilizing the light reflected to the back side. The third textured structure 103 has a greater depth and higher reflectivity, thus better utilizing the light incident from the front to the back side. Overall, this improves the light utilization rate of the gap and increases battery efficiency.

[0251] According to some embodiments of this application, the height of the third texture structure 103 can be 0.5–3 μm, for example, 0.5 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm, etc. Thus, by controlling the height of the third texture structure 103 within the above range, light incident from the front to the back can be better utilized, improving the light utilization rate of the gap area. The surface size of the third texture structure 103 can be 1–15 μm, for example, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 15 μm, etc., and more preferably 5–15 μm. By controlling the surface size of the third texture structure 103 within the above range, its surface size will not be too small, which would lead to increased roughness and affect the uniformity and film quality of the deposited doped conductive layer.

[0252] In some specific embodiments, the gap region of this application may include multiple first sub-regions G3 and multiple second sub-regions G4, with the first sub-regions G3 and second sub-regions G4 alternately arranged along a second direction Y, which intersects with the first direction X. The first sub-regions G3 have a third texture structure 103, and the second sub-regions G4 have a second texture structure 102. Along the second direction Y, the width (L3) of the first sub-region G3 is less than or equal to 400 μm, for example, it can be 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 μm, 400 μm, etc. For example, the width (L3) of the first sub-region G3 can be less than or equal to 200 nm, and more specifically, it can be 10 to 100 μm. If the first sub-region G3 is too wide, it will increase the laser etching time, thereby reducing the production capacity; conversely, if the first sub-region G3 is too narrow, the corresponding second sub-region G4 will be wider, which will affect the improvement of the light trapping effect, thereby reducing the short-circuit current of the battery.

[0253] In some specific embodiments, the spacing (L2) between adjacent first sub-regions G3 is 20 μm to 400 μm, for example, it can be 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 nm, 400 μm, etc. For example, the spacing (L2) between adjacent first sub-regions G3 can be 10 to 100 μm. If the spacing is too narrow, the corresponding second sub-region G4 will be narrower, which will affect the density and uniformity of the first passivation layer 16 deposited thereon. If the spacing is too wide, the corresponding second sub-region G4 will be wider, which will affect the improvement of the light-trapping effect.

[0254] Taking into account the effects of the first sub-region G3 and the second sub-region G4 on the light trapping effect, laser etching time and passivation effect, the ratio (L3 / L2) of the width of the first sub-region G3 and the distance between the first sub-region G3 and another first sub-region G3 adjacent to it is 1 to 2, for example, it can be 1, 1.2, 1.3, 1.5, 1.8, 2.0, etc.

[0255] In some examples, as shown in Figure 13, along the second direction Y, the width (L3) of the first sub-region G3 accounts for a proportion greater than or equal to 20% and less than or equal to 70% of the sum of the width of the first sub-region G3 and the spacing between adjacent first sub-regions G3 (L2+L3). For example, it could be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc. In still other examples, the area of ​​the first sub-region accounts for a proportion greater than or equal to 20% and less than or equal to 70%. For example, it could be 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, etc.

[0256] Thus, since the third texture structure 103 will disrupt the flatness of the second texture structure 102, the size of the area of ​​the third texture structure 103 can be effectively controlled by controlling the size and / or area ratio of the first sub-region, thereby balancing the passivation effect and the light trapping effect.

[0257] According to some embodiments of this application, as shown in FIG13, the gap region of this application may include multiple first sub-regions G3 and multiple second sub-regions G4. The first sub-regions G3 and second sub-regions G4 are arranged alternately along the second direction Y, and the second direction Y intersects with the first direction X. The first sub-region G3 has a third texture structure 103, and the second sub-region G4 has a second texture structure 102. As shown in FIG14 (the dashed line is a schematic diagram of different overlapping situations of the third texture structure 103), the third texture structure 103 partially overlaps in the first sub-region G3. In the direction away from the surface of the first sub-region G3, the distance h2 between the bottom surface of the outermost third texture structure 103 and the bottom surface of its adjacent third texture structure 103 is less than or equal to 2μm. With this configuration, on the one hand, the overlapping third texture structure 103 can make full use of the light incident from the front to the back, improving the light trapping effect. On the other hand, when the distance h2 exceeds 2μm, the roughness of the overlapping third texture structure 103 is too large, and the thickness of the first passivation layer 16 formed on the third texture structure 103 is larger, which is not conducive to forming a first passivation layer 16 with high density and high uniformity.

[0258] According to some embodiments of this application, the height of the first texture structure 101 is less than the height of the third texture structure 103. Because the third texture structure 103 is taller, it can better utilize light incident from the front to the back in the gap area, while the first texture structure 101 is shorter, thus better utilizing light reflected to the back in the conductive area.

[0259] Especially when the surface of the gap is closer to the second surface B than the surface of the first conductive area A1, the gap comes into contact with the front incident light before the conductive area. By setting the height of the third texture structure 103 higher, it is more conducive to the gap fully utilizing the front incident light. At the same time, the conductive area comes into contact with the back incident light before the gap. By setting the height of the first texture structure 101 lower, it is more conducive to the conductive area fully utilizing the light reflected to the back.

[0260] According to some embodiments of this application, along the third direction Z, the surface of the gap region is closer to the second surface B than the surface of the first conductive region A1. This height difference allows the gap region to contact the incident light source first, increasing the number of light reflections and improving the light-trapping effect.

[0261] For example, Figure 16 is a schematic diagram showing a height difference between the spacer region gap and the first conductive region A1 according to another embodiment of this application. As shown in Figure 16, the height difference (H3) between the surface of the first conductive region A1 and the surface of the spacer region gap is 1 μm to 5 μm, for example, it can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, or 5 μm. If the height difference is too low, it will be detrimental to improving the light trapping effect; if the height difference is too high, it will be difficult to uniformly cover the first passivation layer 16 during deposition, reducing the density and uniformity of the first passivation layer 16, thus hindering the improvement of the passivation effect. Preferably, the height difference (H3) between the surface of the first conductive region A1 and the surface of the spacer region gap is 1 μm to 3 μm.

[0262] According to some embodiments of this application, when the first doped conductive layer 11 is formed on the first surface A by deposition, a height difference is generated between the surface of the first doped conductive layer 11 and the first surface A. Based on this height difference and / or the existence of a height difference between the surfaces of the first conductive region A1 and the gap region, a transition region A3 is formed between the first conductive region A1 and the gap region by selecting an appropriate polishing process.

[0263] Therefore, in some embodiments, FIG17 is an SEM image of the transition region A3 of a solar cell according to another embodiment of this application. As shown in FIG13 and FIG17, the first surface A may further include the transition region A3, located between the first conductive region A1 and the gap region; wherein, the transition region A3 has a protrusion structure 14, and the one-dimensional dimension of the protrusion structure 14 is different from the one-dimensional dimension of the second texture structure 102 and the first texture structure 101. Thus, by setting the protrusion structure 14 in the transition region A3, the light trapping effect can be further increased.

[0264] It should be noted that the "one-dimensional dimension" here can be, for example, height, bottom dimension, etc. The meanings of height and bottom dimension are the same as those mentioned above, and will not be repeated here. The "protrusion structure 14" presents a velvety microstructure or a combination of velvety microstructure and polished microstructure. For example, the protrusion structure 14 can present at least one of the following: a prism, a pyramid, a near-prism, a near-pyramid, or an irregular protrusion.

[0265] According to some embodiments of this application, as shown in FIG13 or FIG17, the width (d1) of the transition region A3 along the first direction X can be 1μm to 50μm, for example, it can be 1μm, 3μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, etc. For example, the width (d1) of the transition region A3 can be 10 to 20μm. The width of the transition region A3 should be as small as possible; too large a width will lead to increased recombination at the interface between the silicon substrate 10 and the first doped conductive layer 11, thereby reducing the open-circuit voltage of the battery. Simultaneously, the transition region A3 should ideally be configured as a textured microstructure or a combination of a textured microstructure and a polished microstructure. This is because recombination at grain boundaries is inevitable when the transition region A3 exists. By reducing the width, the light absorption rate can be increased by adding the protrusion structure 14 to compensate for the carrier loss caused by recombination.

[0266] In some examples, the widths of the transition regions A3 located on either side of the gap can be the same or different. Under the same conditions, different regions of the cell have a relatively consistent design; under different conditions, the carrier collection balance in different regions can be adjusted according to the requirements of different regions of the solar cell.

[0267] According to some embodiments of this application, the transition region A3 can be bent and extended along the second direction Y. In this case, along the first direction X, the transition region A3 has a protruding end that bulges towards the gap region and a recessed end that is recessed away from the gap region. The distance (d2) between the protruding end and the recessed end is less than or equal to 50 μm, for example, it can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. Exemplarily, the distance (d2) can be 20–40 μm. If this distance is too large, the transition region A3 will be too wide or the bend will be too large, easily exacerbating the recombination loss of the transition region A3, thereby reducing the open-circuit voltage.

[0268] For example, Figure 18 is a SEM image of the transition region A3 of a solar cell according to another embodiment of this application, which exemplarily shows the size of a local transition region A3; as shown in Figures 17 and 18, the width (d1) of the transition region A3 is 12.52 μm, and the distance (d2) between the protruding end and the recessed end is 30.61 μm, which has a relatively suitable width (d1) and distance (d2).

[0269] According to some embodiments of this application, the transition region A3 can extend in a regularly bent manner along the second direction Y. For example, the transition region A3 extends in a bent manner along the second direction Y, which intersects the first direction X, into multiple serrated structures, as shown in Figures 17 and 18. In this way, the regularity of the surface morphology can be enhanced by setting the serrated structure.

[0270] According to some embodiments of this application, the surface of the transition region A3 has a step with a height different from the surface of the spacer region and the surface of the first conductive region A1. That is, two step-like structures are formed at the junctions of the surfaces of the first conductive region A1 and the transition region A3, and the surfaces of the transition region A3 and the spacer region gap. In this way, the number of reflections of light in the transition region A3 and at the junctions of the transition region A3 with the surfaces of the first conductive region A1 and the spacer region gap can be increased, thereby increasing the light-trapping effect.

[0271] For example, Figures 19 and 20 are schematic diagrams of a stepped structure in the transition region of a solar cell according to an exemplary embodiment of the present application. As shown in Figure 19, the stepped structure may be such that the height of the step on the surface of the transition region A3 is between the height of the surface of the spacer region and the height of the surface of the first conductive region A1. Alternatively, as shown in Figure 20, the stepped structure may also be such that the height of the step on the surface of the transition region A3 is lower than the height of the surface of the first conductive region A1, that is, the step is concave.

[0272] According to some embodiments of this application, as shown in Figures 17 and 18, along the first direction X, the recessed end of the sawtooth structure along the direction away from the gap area is correspondingly set to the area where the third texture structure 103 is located. In this way, the light reflected to the back of the battery, especially the light reflected at the third texture structure 103, can be received by the sawtooth structure more effectively again, which is beneficial to improving the light utilization rate of the back of the battery, thereby improving the double-sided ratio.

[0273] In some specific embodiments, the length (L4) of the sawtooth structure along the second direction Y is less than or equal to 200 μm; for example, it can be 10 μm, 20 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, etc. For example, it can be 15 μm to 100 μm. If the length of the sawtooth structure is too large, the improvement in light-trapping effect is relatively limited. Furthermore, a suitable length range can be adapted to the spacing between adjacent first sub-regions G3 to further improve the light-trapping effect.

[0274] According to some embodiments of this application, as shown in FIG17, at the recessed end of the sawtooth structure that is recessed away from the gap region, the angle formed by the extension direction of the sawtooth structure and the extension direction of the first doped conductive layer 11 is a first sawtooth angle (θ1), which is less than or equal to 30°, and can be, for example, 1°, 2°, 5°, 8°, 10°, 12°, 15°, 18°, 20°, 22°, 25°, 28°, 30°, etc.; and / or, at the recessed end of the sawtooth structure that is recessed away from the gap region, the angle formed between the extension directions of the sawtooth structure is a second sawtooth angle, which is greater than or equal to 120°, and can be, for example, 120°, 125°, 130°, 135°, 140°, 145°, 150°, 155°, 160°, 165°, 170°, 175°, 180°, etc. The first sawtooth angle and the second sawtooth angle (θ2) can be adjusted by changing the angle of the laser spot. By setting the first sawtooth angle and / or the second sawtooth angle within the aforementioned range, current transmission can be facilitated, the series resistance of the battery can be reduced, and the recombination loss can be reduced due to the relatively gentle bending of the transition region A3, thereby improving the open circuit voltage.

[0275] According to some embodiments of this application, the second texture structure 102 and / or the first texture structure 101 can be arranged along a certain direction, and the arrangement direction has a certain angle with the extension direction of the first conductive region A1, which can improve the regularity of the surface morphology of the first surface A and improve the uniformity of surface reflectivity. For example, as shown by the rectangle in FIG15 or FIG17, some of the second texture structures 102 are arranged in strips along the extension direction of the first conductive region A1, and some of the first texture structures 101 are arranged in strips along the extension direction of the first conductive region A1.

[0276] To facilitate understanding, a bifacial contact battery, such as a TOPCon battery, will be used as an example to illustrate the applicability of the fourth texture structure 104 in a bifacial contact battery. Figure 21 is a schematic diagram of the overall structure of the solar cell according to an embodiment of this application. As shown in Figure 21, the silicon substrate 10 also includes a side surface C connected between the first surface A and the second surface B. The side surface C has the fourth texture structure 104, as shown in Figure 10. The solar cell also includes a first passivation layer 16 located on the side surface C with the fourth texture structure 104. It is understood that this is applicable not only to bifacial contact batteries but also to back contact batteries, thereby improving the side passivation effect.

[0277] According to some embodiments of this application, as shown in FIG21, the silicon substrate 10 further includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure 104. Along the third direction Z, the height (h3) of the region where the fourth texture structure 104 is distributed accounts for a percentage (h3 / h4) of the height (h4) of the side surface C that is less than or equal to 98%, for example, it can be 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, 98%, etc.

[0278] In some implementations, the fourth textured structure 104 can be obtained during the fabrication of the solar cell by simultaneously performing alkaline washing and polishing on the first surface A and the side surface C. In this case, in a double-sided contact cell, the entire side surface C can be left untreated by alkaline washing and polishing to adjust the ratio (h3 / h4), allowing more of the fourth textured structure 104 to be formed on the side of the cell, thus ensuring the passivation performance of the cell side and reducing recombination losses. In a back-contact cell, the alkaline-washed and polished side surface C can be further texturized by alkaline washing to adjust the ratio (h3 / h4), improving light trapping effect and, in conjunction with the first passivation layer 16 on the side surface C, reducing recombination losses. At least a portion of the side surface C can have a textured microstructure; it is understood that "at least a portion of the side surface C" can be a part of the side surface C or the entire side surface C.

[0279] To facilitate understanding of the applicability of different solar cell types in this application, we will continue to use a bifacial contact cell, such as a TOPCon cell, as an example to further explain the solar cell structure. As shown in Figure 21, the solar cell includes: a tunneling oxide layer 12 located on the first conductive region A1; a first doped conductive layer 11 located on the surface of the tunneling oxide layer 12, wherein the first doped conductive layer 11 has a dopant element with the same conductivity type as the silicon substrate 10; and a first passivation layer 16 located on the surface of the first doped conductive layer 11 and the surface of the gap region. The gap region may have a second texture structure 102, and may further have a third texture structure 103. The first conductive region A1 may have a first texture structure 101. The configurations of the second texture structure 102, the first texture structure 101, and the third texture structure 103 are the same as described above and will not be repeated here.

[0280] Thus, based on the second texture structure 102 of the gap surface, good uniformity and density are ensured without the first passivation layer 16 being too thick. Since both the first doped conductive layer 11 and the first passivation layer 16 can provide good passivation effects, the electrical contact between the first doped conductive layer 11 and the first electrode 15 can be improved based on the first texture structure 101 of the first doped conductive layer 11 while ensuring passivation performance.

[0281] For example, the tunneling oxide layer 12 can be made of aluminum oxide, silicon oxide, titanium oxide, etc., to selectively pass through majority carriers and achieve a field passivation effect, thereby improving carrier separation and collection. The tunneling oxide layer 12 of the aforementioned materials also serves to prevent the first electrode 15 from corroding the silicon substrate 10 inward. For example, the first doped conductive layer 11 can be, for example, a first doped polycrystalline silicon layer, and the tunneling oxide layer 12 can form a tunneling oxide passivation contact structure with the first doped polycrystalline silicon layer.

[0282] For example, the tunneling oxide layer 12 can be prepared by low-temperature chemical vapor deposition (LPCVD) and the thickness can be 0.5 to 10 nm, such as 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 4 nm, 6 nm, 8 nm, 10 nm, etc.

[0283] According to some embodiments of this application, the first passivation layer 16 may be a single-layer film formed of silicon dioxide, aluminum oxide, silicon nitride, or silicon oxynitride, or a multilayer film composed of one or more of the aforementioned materials. In some examples, the first passivation layer 16 may include a first first passivation layer 16 and a second first passivation layer 16 sequentially disposed along a direction away from the silicon substrate 10. The first first passivation layer 16 includes at least one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a silicon oxynitride layer. The second first passivation layer 16 includes at least one of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. For example, an aluminum oxide first passivation layer 16 may be prepared first using, for example, an ALD (atomic layer deposition) method, and then one or more silicon nitride layers may be formed thereon using, for example, a PECVD (plasma chemical vapor deposition) method.

[0284] For example, the thickness of the first passivation layer 16 is 0.5nm-10nm, such as 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 4nm, 5nm, 6nm, 8nm, 10nm, etc. The thickness of the first passivation layer 16 is 60nm-200nm, such as 60nm, 80nm, 100nm, 120nm, 140nm, 160nm, 180nm, 200nm, etc., and can be further selected as 5-10nm, which can be more beneficial to improving the passivation performance of the gap region.

[0285] According to some embodiments of this application, the first electrode 15 makes electrical contact through the first passivation layer 16 and the first doped conductive layer 11. Based on the first texture structure 101 on the surface of the first doped conductive layer 11, the contact area between the first electrode 15 and the first doped conductive layer 11 is increased, thereby improving the electrical contact performance.

[0286] For example, the first electrode 15 can be made of copper, silver-plated copper, aluminum, or silver, and can be manufactured by printing or electroplating, thus eliminating the need for additional photolithography for patterning. For instance, metal paste can be printed onto the first passivation layer 16, and then the metal paste can be sintered to achieve metallization. The printing method can be, for example, screen printing or inkjet printing, preferably the lower-cost screen printing method.

[0287] According to some embodiments of this application, as shown in FIG21, the solar cell may further include a second doped conductive layer 21 disposed on at least a portion of the second surface B of the silicon substrate 10. In other words, the second doped conductive layer 21 may cover the entire second surface B or may be disposed on a portion of the second surface B. In some examples, the second surface B has a textured structure, such as including multiple pyramidal structures, to improve light trapping effect.

[0288] According to some embodiments of this application, the second doped conductive layer 21 and the first doped conductive layer 11 have opposite doping types. In some examples, as shown in FIG21, the second doped conductive layer 21 may be obtained within the second surface B of the silicon substrate 10, for example, by a doping process, ion implantation, or the like. For example, a P+ emitter formed within the surface of the n-type silicon substrate 10 by a boron diffusion process. Not limited to this, in other examples, the second doped conductive layer 21 may be deposited on the second surface B of the silicon substrate 10, for example, by a chemical vapor deposition process or the like.

[0289] According to some embodiments of this application, the first passivation layer 16 is also disposed on the surface and side surface C of the second doped conductive layer 21 away from the silicon substrate 10. The solar cell also includes a second electrode 15a, which is electrically connected through the first passivation layer 16 and the second doped conductive layer 21. The material of the second electrode 15a is similar to that of the first electrode 15, and will not be described in detail here.

[0290] It is understood that the first passivation layer 16 can be fabricated after the first doped conductive layer 11 and the second doped conductive layer 12 are fabricated, and can be double-sided coated using ALD. Therefore, it is located on the surfaces of the first doped conductive layer 11 and the second doped conductive layer 21 that are away from the silicon substrate 10, as well as on the gap surface and the side surface C. Furthermore, the aforementioned materials and structures of the first passivation layer 16, such as its thickness setting, are suitable not only for double-sided contact batteries but also for back-contact batteries.

[0291] Based on the above examples, the performance of the TOPCon cell provided in this application example and the conventional TOPCon cell were tested. The main difference between the conventional TOPCon cell and the TOPCon cell in this application example is that in the TOPCon cell provided in this application example, the first surface A of the silicon substrate 10 is provided with a second texture structure 102, a first texture structure 101, and a third texture structure 103 as described above, and the first doped conductive layer is spaced on the first conductive region A1. In the conventional TOPCon cell, the second texture structure 102 is arranged on the entire first surface A of the silicon substrate 10, and the first doped conductive layer 11 covers the first surface A. The test results are shown in Table 1 below. It can be seen that after adopting the specific texture structure setting of this application, although the series resistance (Rs) increases, which will cause some photoelectric loss and reduce the fill factor (FF), the short-circuit current (Isc), open-circuit voltage (Voc), and conversion efficiency (Eff) are all significantly improved, indicating that the photogenerated carrier capability of the solar cell provided in this application example is enhanced and the bifaciality is improved.

[0292] Table 1

[0293] In some examples, as shown in Figure 21, the silicon substrate 10 further includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure 104, the configuration of which is the same as described above and will not be repeated here. In this case, the first passivation layer 16 can be located on the side surface C with the fourth texture structure 104, which is beneficial for forming a first passivation layer 16 with higher density and uniformity, and reducing recombination loss of the side surface C, but is not limited to this.

[0294] In other examples, Figure 22 is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application. As shown in Figure 22, the silicon substrate 10 further includes a side surface C connected between the first surface A and the second surface B. The solar cell may also include a third doped conductive layer located on the side surface C. The third doped conductive layer may cover the entire side surface C or partially cover the side surface C. For example, the ratio of the width of the third doped conductive layer covering the side surface C to the width of the side surface C is greater than or equal to 50%, such as 50%, 60%, 70%, 80%, 90%, 100%, etc. The third doped conductive layer is continuously disposed with the first doped conductive layer 11 and has the same doping type.

[0295] As shown in Figure 22, the solar cell may further include an interface passivation layer located between the side surface C of the silicon substrate 10 and the third doped conductive layer. In this case, the uniformity and density of the film formation can be improved based on the fourth texture structure 104 on the side surface C, thereby improving the chemical passivation of the side surface C. Further, the interface passivation layer is a tunneling oxide layer 12. The third doped conductive layer can form a tunneling oxide passivation contact structure with the tunneling oxide layer 12 on the side surface C. The passivation contact structure reduces the probability of recombination of carriers of different polarities on the side of the solar cell by selectively utilizing the carriers, thereby improving the field passivation performance of the side surface C.

[0296] The following uses a back-contact battery, such as a TBC battery, as an example to explain its applicability in this application. Figure 23 is a schematic diagram of the overall structure of a solar cell according to another embodiment of this application. As shown in Figure 23, the first surface A further includes a third conductive region A2, which is alternately distributed with the first conductive region A1, and the gap region is located between the first conductive region A1 and the third conductive region A2; the solar cell may also include: a fourth doped conductive layer 13, located on the third conductive region A2 of the silicon substrate 10, and the third conductive region A2 has a fifth texture structure. At this time, the gap region may have a second texture structure 102, and may further have a third texture structure 103. The first conductive region A1 may have a first texture structure 101. The configuration of the second texture structure 102, the first texture structure 101 and the third texture structure 103 is the same as above, and will not be repeated here.

[0297] Since the first doped conductive layer 11 on the first conductive region A1 and the fourth doped conductive layer 13 on the third conductive region A2 are formed after different surface treatment processes, the dimensions of the fifth texture structure and the first texture structure 101 can be different. In some examples, the first doped conductive layer 11 can be a P-type doped conductive layer, and the fourth doped conductive layer 13 can be an N-type doped conductive layer. In this case, the surface size of the fifth texture structure can be larger than the surface size of the first texture structure 101, and / or, the height of the fifth texture structure can be smaller than the height of the first texture structure 101. This is more conducive to increasing the contact area between the P-type doped conductive layer and the first electrode 15, thereby improving the hole collection effect. When the conductivity of the P-type doped conductive layer is worse than that of the N-type doped conductive layer, it is beneficial to maintain the balance of hole and electron transport.

[0298] For example, the first doped conductive layer 11 may be a P-type doped polycrystalline silicon layer, the fourth doped conductive layer 13 may be an N-type doped polycrystalline silicon layer, and the solar cell may also include a tunneling oxide layer 12 located between the silicon substrate 10 and the first doped conductive layer 11, and another tunneling oxide layer 17 located between the silicon substrate 10 and the fourth doped conductive layer 13.

[0299] Of course, it is not limited to this. In other examples, the first doped conductive layer 11 can be an N-type doped conductive layer and the fourth doped conductive layer 13 can be a P-type doped conductive layer. In this case, the surface size of the fifth texture structure can be smaller than the surface size of the first texture structure 101, and the surface size of the fifth texture structure can be larger than the height of the first texture structure 101.

[0300] For example, the first doped conductive layer 11 can be an N-type doped polycrystalline silicon layer, and the fourth doped conductive layer 13 can be a P-type doped amorphous silicon layer. The solar cell may also include a tunneling oxide layer 12 located between the silicon substrate 10 and the first doped conductive layer 11, and an intrinsic amorphous silicon layer located between the silicon substrate 10 and the fourth doped conductive layer 13. In this case, the corresponding solar cell type is a hybrid cell combining TBC (TOPCon-Back Contact) and HJT phases.

[0301] In some examples, the solar cell may also include a first passivation layer 16 located on the surface of the first doped conductive layer 11, the fourth doped conductive layer 13 and the gap region, and another first passivation layer 18 located on the second surface B.

[0302] In some examples, as shown in Figure 23, the silicon substrate 10 further includes a side surface C connected between the first surface A and the second surface B. The side surface C has a fourth texture structure 104, the configuration of which is the same as described above and will not be repeated here. In this case, the first passivation layer 16 can also be located on the side surface C with the fourth texture structure 104, which is beneficial for forming a first passivation layer 16 with higher density and uniformity, and reducing recombination loss of the side surface C, but is not limited to this.

[0303] The fabrication of the second texture structure 102 and the first texture structure 101 is described below. Specifically, taking a double-sided contact battery as an example, the first texture structure 101 can be obtained by texturing and polishing the first surface A of the silicon substrate 10 to obtain a polished microstructure, i.e., the first texture structure 101. A first doped conductive layer 11 is formed on the polished first surface A. Since the first doped conductive layer 11 can be deposited relatively conformally, the first texture structure 101 with the same morphology as the polished microstructure is retained on the first doped conductive layer 11.

[0304] In some examples, after a mask is formed on the first doped conductive layer 11, appropriate laser conditions such as energy density and spot size are selected, and laser etching is used to remove part of the mask and perform alkaline washing to form the first doped conductive layer 11 with spaced distribution and the spacer gap, so that the surface of the spacer gap has a second texture structure 102.

[0305] Specifically, taking the first doped conductive layer 11 as the first doped polycrystalline silicon layer as an example, an intrinsic amorphous silicon layer is deposited on the surface by chemical vapor deposition, and then a doped polycrystalline silicon layer, namely the first doped conductive layer 11, is formed by diffusion process. At this time, a layer of phosphosilicate glass can be formed on the surface of the first doped conductive layer 11 as a mask for alkaline washing.

[0306] It is understandable that, compared to double-sided contact batteries, the preparation methods of the second texture structure 102 and the first texture structure 101 in the back contact battery are similar. The main difference is that, after patterning the first doped conductive layer 11, a fourth doped conductive layer 13 and a mask are deposited on the surface. Laser etching is used to remove part of the mask and alkaline washing is performed to form alternating first doped conductive layers 11 and fourth doped conductive layers 13 and gap regions, so that the surface of the gap regions has the second texture structure 102.

[0307] In one or more of the above embodiments, an embodiment may exist alone or in combination with other embodiments. The descriptions of each embodiment above each have their own emphasis; for parts not described in detail in a particular embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0308] In summary, the solar cells of the embodiments of this application may include at least the following advantages:

[0309] In this embodiment, a first isolation groove is provided between the first conductive region and the cut surface of the solar cell's back surface. During the slab-slab process, the first isolation groove can prevent the force generated by the cut surface during slab-slab processing from being transmitted to the edge of the first doped conductive layer near the cut surface, thus preventing damage to the edge of the first doped conductive layer and the formation of carrier recombination centers. Moreover, the first isolation groove can also cut off the carrier transport channel from the first conductive region to the cut surface, suppressing significant carrier recombination at the cut surface and the edge near the cut surface, thereby reducing cell efficiency loss.

[0310] This application also provides a photovoltaic module, which includes a battery string, specifically including the solar cells described in any of the above embodiments.

[0311] It should be noted that the structure of the solar cell in the photovoltaic module described in this application embodiment is the same as that of the solar cell described in any of the above embodiments, and its beneficial effects are also similar, so it will not be described again here.

[0312] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0313] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0314] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0315] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0316] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A solar cell, wherein, The solar cell includes: A silicon substrate having a first surface, the first surface including a first conductive region and a spacer region; The first conductive region includes a first doped conductive layer arranged at intervals; The interval region located at the edge of the first surface is called the edge interval region, and the interval region located at the center of the first surface is called the center interval region, wherein the depth of the edge interval region is less than the depth of the center interval region.

2. The solar cell according to claim 1, wherein, The depth of the edge spacing region and the depth of the center spacing region have a first difference, the first difference being greater than 0 and less than or equal to 2 μm.

3. The solar cell according to claim 1, wherein, The depth range of the edge spacing region is 1-3 μm; the depth range of the center spacing region is 2-5 μm.

4. The solar cell according to claim 1, wherein, The width of the edge spacing region along the first direction is the first width, and the width of the center spacing region along the first direction is the second width, wherein the first width is less than or equal to the second width.

5. The solar cell according to claim 4, wherein, The first width ranges from 100 to 700 μm; the second width ranges from 500 to 1500 μm.

6. The solar cell according to claim 1, wherein, The first conductive region has a first texture structure, and the interval region has a second texture structure. The one-dimensional dimension of the bottom of the first texture structure is smaller than the one-dimensional dimension of the bottom of the second texture structure.

7. The solar cell according to claim 6, wherein, The one-dimensional dimension of the bottom of the first texture structure is 5-9 μm; the one-dimensional dimension of the bottom of the second texture structure is 9-18 μm.

8. The solar cell according to claim 6, wherein, The depths of the first and second texture structures are 0.05-2 μm.

9. The solar cell according to claim 1, wherein, The interval area is provided with a pyramid-shaped velvet structure.

10. The solar cell according to claim 1, wherein, The width of the central spacing region along the first direction is the second width, the distance between the centers of two adjacent first conductive regions along the first direction is the first distance, and the ratio of the second width to the first distance is in the range of 0.2-0.

7. And / or, the distance between the centers of two adjacent first conductive regions along the first direction is 1-3 mm.

11. The solar cell according to claim 1, wherein, The solar cell further includes a first passivation layer, which is disposed on the side of the first doped conductive layer away from the silicon substrate; The first passivation layer includes a first region and a second region. The first region is opposite to the central spacing region, and the second region is opposite to the edge spacing region. The first region is provided with a first sub-passivation layer, and the second region is provided with a second sub-passivation layer. The thickness of the second sub-passivation layer is greater than the thickness of the first sub-passivation layer.

12. The solar cell according to claim 1, wherein, The silicon substrate further includes a second surface disposed opposite to the first surface in a third direction, and a side surface connecting the first surface and the second surface, the side surface including diced surfaces and non-diced surfaces; wherein, A first isolation groove is provided between the first conductive area and the cut surface, and there is a height difference between the surface of the first isolation groove and the surface of the first conductive area. A connecting side is provided between the first conductive area and the first isolation groove. The solar cell further includes a first passivation layer, which covers the surface of the first doped conductive layer away from the silicon substrate, the surface of the first isolation trench, and the surface of the connection side.

13. The solar cell according to claim 12, wherein, The height difference is the first height, which ranges from 1 micrometer to 10 micrometers.

14. The solar cell according to claim 12, wherein, The number of first conductive regions is multiple, and multiple interval regions are also provided on the first surface. The multiple first conductive regions and the multiple interval regions are alternately arranged on the first surface along a first direction, and the first direction is perpendicular to the cutting surface. Wherein, the width of the first isolation groove along the first direction is the first width, the width of the interval area along the first direction is the second width, and the first width is less than the second width.

15. The solar cell according to claim 14, wherein, The ratio of the first width to the second width ranges from 25% to 75%.

16. The solar cell according to claim 12, wherein, The number of first conductive regions is multiple, and multiple interval regions are also provided on the first surface. The multiple first conductive regions and the multiple interval regions are alternately arranged on the first surface along a first direction, and the first direction is perpendicular to the cutting surface. Wherein, the height difference between the surface of the first isolation groove and the surface of the first conductive region is the first height, the height difference between the surface of the interval region and the surface of the first conductive region is the second height, and the difference between the first height and the second height is less than or equal to 1 micrometer.

17. The solar cell according to claim 12, wherein, The cutting surface includes a first cutting surface and a second cutting surface, which are arranged opposite to each other. The second cut surface and the first conductive area are further provided with a second isolation groove, and there is a height difference between the surface of the second isolation groove and the surface of the first conductive area; The first passivation layer is disposed on the surface of the second isolation groove.

18. The solar cell according to claim 12, wherein, The second surface includes a second conductive region, and the second conductive region is provided with a second doped conductive layer; A third isolation groove is provided between the second conductive area and the cut surface. There is a height difference between the surface of the third isolation groove and the surface of the second conductive area. The height difference ranges from 2 micrometers to 10 micrometers. The first isolation groove and the third isolation groove are respectively arranged along the third direction; The first passivation layer is disposed on the side of the second doped conductive layer away from the silicon substrate and on the surface of the third isolation trench.

19. The solar cell according to claim 12, wherein, The solar cell further includes a second passivation layer, which is located on the surface of the cut surface; The second passivation layer extends to the first surface, is located on the side of the first passivation layer away from the silicon substrate, and the second passivation layer at least covers the first isolation trench and the first conductive region adjacent to the first isolation trench, and the second passivation layer covers the side of the first doped conductive layer away from the silicon substrate. The second passivation layer extends to the first surface, is located on the side of the first passivation layer away from the silicon substrate, and the second passivation layer at least covers the first isolation trench and the first conductive region adjacent to the first isolation trench, and the second passivation layer covers the side of the first doped conductive layer away from the silicon substrate. The second passivation layer extends to the second surface, located on the side of the first passivation layer away from the silicon substrate, and the second passivation layer at least covers the third isolation trench and the second conductive region adjacent to the third isolation trench, and the second passivation layer covers the side of the second doped conductive layer away from the silicon substrate.

20. The solar cell according to claim 12, wherein, A fourth isolation groove is also provided between the first conductive area and the non-cut surface; The difference between the surface height of the fourth isolation groove and the surface height of the first conductive area is less than 1 micrometer, and the width of the fourth isolation groove is less than the width of the first isolation groove.

21. The solar cell according to claim 1, wherein, The first surface includes first conductive regions spaced apart along a first direction, with a spacer region between adjacent first conductive regions. The silicon substrate also includes a second surface opposite to the first surface and a side surface connected between the first surface and the second surface. The spacer region has a second texture structure, the side surface has a fourth texture structure, and the first conductive region has a first texture structure. The solar cell further includes a third passivation layer located on the surface of the spacer region and on at least one of the following structural surfaces: the second surface, the side surface, and the surface of the first doped conductive layer away from the silicon substrate. The first electrode is located on the first doped conductive layer and is in electrical contact with the first doped conductive layer. Wherein, the height of the second texture structure is less than the height of the first texture structure, and / or, the surface size of the second texture structure is greater than the surface size of the first texture structure; the surface size of the fourth texture structure is greater than the surface size of the second texture structure.

22. The solar cell according to claim 21, wherein, The height of the fourth texture structure is less than the height of the first texture structure.

23. The solar cell according to claim 21, wherein, The height of the fourth texture structure is greater than the height of the second texture structure.

24. The solar cell according to claim 21, wherein, Some of the second texture structures are arranged in stripes along the extension direction of the first conductive region, and some of the first texture structures are arranged in stripes along the extension direction of the first conductive region.

25. The solar cell according to claim 21, wherein, The interval region includes multiple first sub-regions and multiple second sub-regions; The first sub-region has a third texture structure, the second sub-region has a second texture structure, the first sub-region and the second sub-region are arranged alternately along a second direction, and the second direction intersects with the first direction; The height of the second texture structure is less than the height of the third texture structure, and / or the surface size of the second texture structure is greater than the surface size of the third texture structure.

26. The solar cell according to claim 21, wherein, The interval region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being arranged alternately along a second direction, the second direction intersecting the first direction; The first sub-region has a third texture structure, and the second sub-region has the second texture structure; The third texture structures partially overlap in the first sub-region. Along the direction away from the surface of the first sub-region, the distance between the bottom surface of the outermost third texture structure and the bottom surface of its adjacent third texture structure is less than or equal to 2 μm.

27. The solar cell according to claim 25 or 26, wherein, The height of the first texture structure is less than the height of the third texture structure.

28. The solar cell according to claim 25 or 26, wherein, The surface size of the second texture structure ranges from 10 to 28 μm; Alternatively, the surface size of the first texture structure ranges from 5 to 15 μm; Alternatively, the surface size of the third texture structure ranges from 5 to 15 μm; Alternatively, the surface size of the fourth texture structure may range from 15 to 40 μm.

29. The solar cell according to claim 21, wherein, The interval region includes a plurality of first sub-regions and a plurality of second sub-regions, the first sub-regions and the second sub-regions being arranged alternately along a second direction, the second direction intersecting the first direction; The first sub-region has a third texture structure, and the second sub-region has the second texture structure; Along the second direction, the width of the first sub-region is less than or equal to 400 μm, and / or the spacing between adjacent first sub-regions is 20 μm to 400 μm.

30. The solar cell according to claim 21, wherein, The interval region includes multiple first sub-regions and multiple second sub-regions; The first sub-region has a third texture structure, the second sub-region has a second texture structure, the first sub-region and the second sub-region are arranged alternately along a second direction, and the second direction intersects with the first direction; The height of the second texture structure is less than the height of the third texture structure, and / or the surface size of the second texture structure is greater than the surface size of the third texture structure; Along the second direction, the width of the first sub-region accounts for a proportion of the sum of the width of the first sub-region and the spacing between adjacent first sub-regions that is greater than or equal to 20% and less than or equal to 70%. And / or, the area of ​​the first sub-region accounts for more than 20% and less than or equal to 70% of the area of ​​the interval region.

31. The solar cell according to claim 21, wherein, Along a third direction, the surface of the spacer region is closer to the second surface than the surface of the first conductive region.

32. The solar cell according to claim 31, wherein, The height difference between the surface of the first conductive region and the surface of the spacer region is 1 μm to 5 μm.

33. The solar cell according to claim 21 or 31, wherein, The first surface further includes a transition region located between the first conductive region and the spacer region; The transition region has a raised structure, and the one-dimensional dimension of the raised structure is different from the one-dimensional dimension of both the second texture structure and the first texture structure.

34. The solar cell according to claim 33, wherein, Along the first direction, the width of the transition region is 1 μm to 50 μm; And / or, along the first direction, the transition region has a protruding end that protrudes toward the interval region and a recessed end that is recessed away from the interval region, the distance between the protruding end and the recessed end being less than or equal to 50 μm; And / or, the surface of the transition region has a step with a height different from the surface of the interval region and the surface of the first conductive region.

35. The solar cell according to claim 33, wherein, The transition region bends and extends into multiple serrated structures along a second direction intersecting the first direction; Wherein, along the second direction, the length of the serrated structure is less than or equal to 200 μm; and / or, at the recessed end of the serrated structure that is recessed away from the spacer region, the angle formed by the extension direction of the serrated structure and the extension direction of the first doped conductive layer is a first serrated angle, the first serrated angle being less than or equal to 30°; and / or, at the recessed end of the serrated structure that is recessed away from the spacer region, the angle formed between the extension directions of the serrated structure is a second serrated angle, the second serrated angle being greater than or equal to 120°.

36. The solar cell according to claim 34, wherein, The interval region includes multiple first sub-regions and multiple second sub-regions; The first sub-region has a third texture structure, and the second sub-region has the second texture structure; The height of the second texture structure is less than the height of the third texture structure, and / or the surface size of the second texture structure is greater than the surface size of the third texture structure; Wherein, along the first direction, the recessed end is set in a region corresponding to the area where the third texture structure is located.

37. The solar cell according to claim 21, wherein, Along a third direction, the height of the region where the fourth texture structure is distributed accounts for less than or equal to 98% of the height of the side surface.

38. The solar cell according to claim 21, wherein, The solar cell includes: The tunneling oxide layer located on the first conductive region; The first doped conductive layer is located on the surface of the tunneling oxide layer, and the first doped conductive layer has doping elements of the same conductivity type as the silicon substrate; The third passivation layer is located on the surface of the first doped conductive layer and the surface of the spacer region; The solar cell further includes a third doped conductive layer located on the side surface, wherein the ratio of the width of the third doped conductive layer covering the side surface to the width of the side surface is greater than or equal to 50%. The third doped conductive layer has the same doping type as the first doped conductive layer.

39. The solar cell according to claim 21, wherein, The third passivation layer material includes an aluminum oxide layer, the thickness of which is greater than or equal to 5 nm and less than or equal to 10 nm.

40. The solar cell according to claim 21, wherein, The first surface further includes a third conductive region, which is distributed alternately with the first conductive region, and the interval region is located between the first conductive region and the third conductive region; The solar cell also includes: A fourth doped conductive layer is located on the third conductive region of the silicon substrate, the third conductive region having a fifth textured structure.

41. A photovoltaic module, characterized in that, The photovoltaic module includes a battery string, the battery string including a solar cell as described in any one of claims 1 to 40 and a plurality of interconnecting elements; the solar cell is electrically connected through the interconnecting elements; The solar cell includes: a silicon substrate having a first surface, the first surface including a first conductive region and a spacer region; and a first doped conductive layer arranged at intervals on the first conductive region. The interval region located at the edge region of the first surface is an edge interval region, and the interval region located at the center region of the first surface is a center interval region, wherein the depth of the edge interval region is less than the depth of the center interval region; An encapsulation layer covers the surface of the plurality of solar cells.

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