Shift register, driving method, gate driving circuit and display apparatus

Abstract

A shift register, a driving method, a gate driving circuit and a display apparatus. The shift register comprises a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a first storage sub-circuit and a first control sub-circuit; the first input sub-circuit is coupled to a signal input terminal, a first node and a first clock signal terminal; the second input sub-circuit is coupled to the first node, a second node and the first clock signal terminal; the second input sub-circuit comprises a second transistor, the second transistor being a low-temperature polysilicon transistor; the first output sub-circuit is coupled to a second clock signal terminal, the second node and a cascade signal output terminal; the first control sub-circuit is coupled to the second clock signal terminal, the cascade signal output terminal and the first node; in response to an operating level at the cascade signal output terminal, the first control sub-circuit is configured to transmit in an output stage to the first node an operating level received at the second clock signal terminal.

Description

Shift registers and driving methods, gate driving circuits and display devices

[0001] This application claims priority to Chinese patent application No. 202510125594.7, filed on January 26, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register and driving method, a gate driving circuit, and a display device. Background Technology

[0003] With the development of display technology, display devices (such as mobile phones, laptops, or tablets) are increasingly used in people's lives. Among them, organic light-emitting diode (OLED) display devices have received widespread attention due to their advantages such as active light emission, wide viewing angle, high contrast, fast response speed, low power consumption, and ultra-thin design. Summary of the Invention

[0004] On one hand, a shift register is provided. The shift register includes a first input sub-circuit, a second input sub-circuit, a first output sub-circuit, a first storage sub-circuit, and a first control sub-circuit. The first input sub-circuit is coupled to a signal input terminal, a first node, and a first clock signal terminal; the first input sub-circuit is configured to, in an input phase, in response to a first clock signal received at the first clock signal terminal, transmit a working level received at the signal input terminal to the first node; and in an output phase, in response to the first clock signal received at the first clock signal terminal, cut off the signal input terminal and the first node; and in an output phase, receive a non-working level at the signal input terminal; the first input sub-circuit includes a first transistor, the first transistor being a low-temperature polysilicon transistor; the second input sub-circuit is coupled to the first node, a second node, and the first clock signal terminal; the second input sub-circuit is configured to, in the input phase, in response to the first clock signal received at the first clock signal terminal, transmit the voltage at the first node to the second node, and in the output phase, in response to the first clock signal received at the first clock signal terminal, transmit the voltage at the first node to the second node, and in the output phase, in response to the first clock signal received at the first clock signal terminal... The first clock signal received cuts off the first node and the second node; the second input sub-circuit includes a second transistor, which is a low-temperature polysilicon transistor; the first output sub-circuit is coupled to the second clock signal terminal, the second node, and the cascaded signal output terminal; the first output sub-circuit is configured to, during the input phase, under the control of the voltage at the second node, transmit the non-operating level received at the second clock signal terminal to the cascaded signal output terminal; and during the output phase, under the control of the voltage at the second node, transmit the operating level received at the second clock signal terminal to the cascaded signal output terminal; the first control sub-circuit is coupled to the second clock signal terminal, the cascaded signal output terminal, and the first node; the first control sub-circuit is configured to, during the output phase, in response to the operating level at the cascaded signal output terminal, transmit the operating level received at the second clock signal terminal to the first node.

[0005] In some embodiments, the first control sub-circuit includes a third transistor. The first terminal of the third transistor is connected to the second clock signal terminal, the second terminal is connected to the first node, and the control terminal is connected to the cascaded signal output terminal.

[0006] In some embodiments, the shift register further includes a third input sub-circuit, a second control sub-circuit, and a second output sub-circuit. The third input sub-circuit is coupled to the first voltage signal terminal, the third node, and the fourth node. The third input sub-circuit is configured to, during the input phase, transmit the first voltage signal received at the first voltage signal terminal to the third node under the control of the voltage at the fourth node; the first voltage signal is at a non-operating level. The second control sub-circuit is coupled to the second node, the third node, the first voltage signal terminal, the second voltage signal terminal, and the third clock signal terminal. The second control sub-circuit is configured to, during the holding phase, in response to the third clock signal received at the third clock signal terminal, transmit the second voltage signal received at the second voltage signal terminal to the third node, and transmit the first voltage signal received at the first voltage signal terminal to the second node; the second voltage signal is at an operating level. The second output sub-circuit is coupled to the third voltage signal terminal, the third node, and the cascaded signal output terminal. The second output sub-circuit is configured to, during the holding phase, under the control of the voltage at the third node, transmit the third voltage signal received at the third voltage signal terminal to the cascaded signal output terminal; the third voltage signal is at a non-operating level.

[0007] In some embodiments, the second control subcircuit includes a primary control subcircuit and a secondary control subcircuit. The primary control subcircuit is coupled to the third node, the second voltage signal terminal, and the third clock signal terminal; the primary control subcircuit is configured to, during the hold phase, in response to a third clock signal received at the third clock signal terminal, transmit a second voltage signal received at the second voltage signal terminal to the third node; the second voltage signal is at a working level; the secondary control subcircuit is coupled to the second node, the third node, and the first voltage signal terminal; the secondary control subcircuit is configured to, during the hold phase, under the control of the second voltage signal at the third node, transmit a first voltage signal received at the first voltage signal terminal to the second node.

[0008] In some embodiments, the secondary control subcircuit includes a first subcircuit and a second subcircuit. The first subcircuit is coupled to the third node, the first voltage signal terminal, and the fifth node; the first subcircuit is configured to, during the output phase, turn off the first voltage signal terminal and the fifth node under the control of the voltage at the third node; the first subcircuit includes a fourth transistor, which is a low-temperature polysilicon transistor. The second subcircuit is coupled to the second node, the third node, and the fifth node; the second subcircuit is configured to, during the output phase, turn off the fifth node and the second node under the control of the voltage at the third node; the second subcircuit includes a fifth transistor, which is a low-temperature polysilicon transistor. The second control subcircuit further includes a tertiary control subcircuit coupled to the fifth node, the second node, and the second voltage signal terminal; the tertiary control subcircuit is configured to, during the output phase, under the control of the voltage at the second node, transmit the second voltage signal received at the second voltage signal terminal to the fifth node.

[0009] In some embodiments, the primary control sub-circuit includes a sixth transistor. The first terminal of the sixth transistor is connected to the second voltage signal terminal, the second terminal is connected to the third node, and the control terminal is connected to the third clock signal terminal.

[0010] In some embodiments, the fourth node is connected to the signal input terminal, or the fourth node is connected to the first node, or the fourth node is connected to the fifth node.

[0011] In some embodiments, the first output sub-circuit includes a seventh transistor, the first terminal of which is connected to the second clock signal terminal, the second terminal of which is connected to the cascaded signal output terminal, and the control terminal of which is connected to the second node; the third input sub-circuit includes an eighth transistor, the first terminal of which is connected to the first voltage signal terminal, the second terminal of which is connected to the cascaded signal output terminal, and the control terminal of which is connected to the fourth node; the second output sub-circuit includes a ninth transistor, the first terminal of which is connected to the third voltage signal terminal, the second terminal of which is connected to the cascaded signal output terminal, and the control terminal of which is connected to the third node; the three-stage control sub-circuit includes a tenth transistor, the first terminal of which is connected to the second voltage signal terminal, the second terminal of which is connected to the fifth node, and the control terminal of which is connected to the second node; the first storage sub-circuit further includes a first storage capacitor, the first plate of which is coupled to the second node, and the second plate of which is coupled to the cascaded signal output terminal.

[0012] On the other hand, a gate driving circuit is provided. The gate driving circuit includes a plurality of cascaded shift registers as described in any of the above embodiments.

[0013] In some embodiments, the shift register is connected to a first clock signal terminal, a second clock signal terminal, and a third clock signal terminal; the gate drive circuit further includes multiple clock signal lines, which are divided into multiple groups. In the same group, in adjacent shift registers, the clock signal line connected to the second clock signal terminal of the previous shift register is the same as the clock signal line connected to the first clock signal terminal of the next shift register; the clock signal line connected to the third clock signal terminal of the previous shift register is the same as the clock signal line connected to the second clock signal terminal of the next shift register; the clock signal line connected to the first clock signal terminal of the previous shift register is different from the clock signal line connected to the third clock signal terminal of the next shift register; and the clock signal lines connected to the same clock signal terminal in any two shift registers are different.

[0014] In some embodiments, the gate driving circuit further includes a first voltage signal line and a second voltage signal line. The first voltage signal line is connected to a first voltage signal terminal and a shift register; the second voltage signal line is connected to a third voltage signal terminal and a shift register; the width of the first voltage signal line is smaller than the width of the second voltage signal line.

[0015] In some embodiments, the line width of the first voltage signal line is 3μm to 10μm; and / or, the line width of the second voltage signal line is 10μm to 20μm.

[0016] In some embodiments, a plurality of shift registers are arranged at intervals along a second direction; the shift registers include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; a first voltage signal line extends along the second direction and along the first direction, the first voltage signal line being located between the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the tenth transistor, and between the seventh transistor and the ninth transistor; a second voltage signal line extends along the second direction and along the first direction, the second voltage signal line being located on the side of the seventh transistor and the ninth transistor away from the first voltage signal line; the second direction intersects the first direction.

[0017] In some embodiments, the shift register further includes a first storage capacitor; the first storage capacitor is located on the side away from the first voltage signal line between the seventh transistor and the ninth transistor, and the orthographic projection of the second voltage signal line onto the reference plane overlaps with the orthographic projection of the first storage capacitor onto the reference plane; along the first direction, the two ends of the first storage capacitor extend beyond the two ends of the second voltage signal line.

[0018] In some embodiments, the clock signal line extends along a second direction and is located on the side of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the tenth transistor, away from the first voltage signal line;

[0019] The gate drive circuit further includes a third voltage signal line, which is connected to the second voltage signal terminal and the shift register. The third voltage signal line extends along the second direction and is located between the clock signal line and the shift register.

[0020] In some embodiments, the fourth transistor and the fifth transistor are located between the first transistor, the second transistor, the third transistor, the sixth transistor, the eighth transistor, and the tenth transistor, and the first voltage signal line, along the second direction, with the fourth transistor located to one side of the fifth transistor; and / or, the third transistor and the sixth transistor are located between the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor, and the tenth transistor, and the third voltage signal line, along the second direction, with the third transistor located to one side of the sixth transistor.

[0021] In some embodiments, the eighth transistor is located between the fourth and fifth transistors, and between the third and sixth transistors, and is located on the side of the first, second, and tenth transistors away from the next-stage shift register; the fourth transistor is located on the side of the fifth transistor away from the next-stage shift register, and the ninth transistor is located on the side of the seventh transistor away from the next-stage shift register; the gate drive circuit further includes a first connection line connected to the gate of the third transistor, the second terminal of the seventh transistor, and the first terminal of the next-stage first transistor; the first connection line is located on the side of the first, second, fourth, fifth, and tenth transistors near the next-stage shift register.

[0022] In some embodiments, along the first direction, the channel portion of the first transistor is located on the side of the channel portion of the second transistor closer to the previous stage shift register; along the second direction, the channel portion of the first transistor is located on the side of the channel portion of the second transistor away from the first voltage signal line; the channel portion of the third transistor is located on the side of the channel portions of the first transistor and the second transistor away from the first voltage signal line.

[0023] In another aspect, a display device is provided. The display device includes: a shift register as described in any of the above embodiments, or a gate driving circuit as described in any of the above embodiments.

[0024] On another front, a method for driving a shift register is provided for driving a shift register as described in any of the above embodiments. A display frame cycle includes an input phase and an output phase; in the input phase, a first input sub-circuit, in response to a first clock signal received at a first clock signal terminal, transmits the operating level received at the signal input terminal to the first node; a second input sub-circuit, in response to the first clock signal received at the first clock signal terminal, transmits the operating level at the first node to the second node; a first storage sub-circuit stores the operating level at the second node; under the control of the operating level at the second node, a first output sub-circuit transmits the non-operating level received at the second clock signal terminal to the cascaded signal output terminal; in the output phase, the first input sub-circuit, in response to the first clock signal received at the first clock signal terminal… The signal input terminal and the first node are turned off, and the signal received at the signal input terminal is at a non-operating level; the second input sub-circuit responds to the first clock signal received at the first clock signal terminal by turning off the first node and the second node; under the control of the operating level at the second node, the first output sub-circuit transmits the operating level received at the second clock signal terminal to the cascaded signal output terminal; the first storage sub-circuit writes the difference between the operating level and the non-operating level received at the second clock signal terminal into the second node; under the control of the operating level at the cascaded signal output terminal, the first control sub-circuit transmits the operating level received at the cascaded signal output terminal to the first node.

[0025] In some embodiments, a display frame cycle further includes a hold phase following the output phase; in the input phase, under the control of the voltage of the fourth node, the third input sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the third node; under the control of the first voltage signal at the third node, the second output sub-circuit cuts off the third voltage signal terminal and the cascaded signal output terminal; the second control sub-circuit, in response to the third clock signal received at the third clock signal terminal, controls the third voltage signal terminal and the third node to cut off, and under the control of the first voltage signal at the third node, the second control sub-circuit cuts off the first voltage signal terminal and the second node; in the output phase, the second control sub-circuit, in response to the third clock signal received at the third clock signal terminal, controls the second voltage signal terminal and the third node to cut off. Under the control of the first voltage signal at the third node, the second output sub-circuit cuts off the third voltage signal terminal and the cascaded signal output terminal, and the second control sub-circuit cuts off the first voltage signal terminal and the second node; during the holding phase, in response to the third clock signal received at the third clock signal terminal, the second control sub-circuit transmits the second voltage signal received at the second voltage signal terminal to the third node, and transmits the first voltage signal received at the first voltage signal terminal to the second node; under the control of the first voltage signal at the second node, the first output sub-circuit cuts off the second clock signal terminal and the cascaded signal output terminal; under the control of the second voltage signal at the third node, the second output sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the cascaded signal output terminal.

[0026] In some embodiments, during the output phase, under the control of the second voltage signal at the third node, the first sub-circuit controls the second voltage signal terminal and the fifth node to be cut off, and the second sub-circuit controls the fifth node and the second node to be cut off; under the control of the voltage at the second node, the three-level control sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the fifth node. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 is a structural diagram of a display device according to some embodiments;

[0029] Figure 2 is another structural diagram of a display device according to some embodiments;

[0030] Figure 3 is a structural diagram of a display device including a display panel according to some embodiments;

[0031] Figure 4 is a structural diagram of a display panel according to some embodiments;

[0032] Figure 5 is a structural diagram of a gate drive circuit according to some embodiments;

[0033] Figure 6 is a structural diagram of an input circuit according to some embodiments;

[0034] Figure 7 is a structural diagram of an input circuit including a transistor and a capacitor according to some embodiments;

[0035] Figure 8 is a timing diagram of the input circuit according to some embodiments;

[0036] Figure 9 is another structural diagram of the input circuit according to some embodiments;

[0037] Figure 10 is another structural diagram of the input circuit according to some embodiments;

[0038] Figure 11 is a magnified view of part C in Figure 4;

[0039] Figure 12 is a structural diagram of an input circuit according to some embodiments, showing the transistors being turned on.

[0040] Figure 13 is another structural diagram of the transistors being turned on in the input circuit according to some embodiments;

[0041] Figure 14 is another structural diagram of the input circuit including the transistors being turned on according to some embodiments;

[0042] Figure 15 is another structural diagram of the input circuit including the transistors being turned on according to some embodiments;

[0043] Figure 16 is another structural diagram of the input circuit including the transistors being turned on according to some embodiments. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0049] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0054] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals less than or equal to 5% of either one.

[0055] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0056] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] In the embodiments of this disclosure, the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes. Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.

[0058] In the circuits provided in the embodiments of this disclosure, the first node, the second node, the third node, the fourth node, and the fifth node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0059] In the embodiments of this disclosure, the “operating level” of the shift register refers to a level that enables the included operated transistor to be turned on, and correspondingly, the “non-operating level” refers to a level that does not enable the included operated transistor to be turned on (i.e., the transistor is turned off).

[0060] In the embodiments of this disclosure, the control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second electrodes of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0061] As shown in FIG1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) and either text or images.

[0062] For example, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, flight display, projection device, etc.

[0063] In some examples, as shown in Figure 1, the display device 1000 can be a portable display product. For example, the display device 1000 can be a mobile phone as shown in Figure 1.

[0064] In some other examples, as shown in Figure 2, the display device 1000 can be a wearable device. For example, the display device can be a watch as shown in Figure 2.

[0065] In some embodiments, as shown in FIG3, the display device 1000 includes a display panel 100, a driving circuit board 200, a housing 300, and a cover plate 400.

[0066] The display panel 100 has a light-emitting side 100A and a non-light-emitting side 100B. The light-emitting side 100A refers to the side of the display panel 100 that can emit light (the upper side of the display panel 100 in Figure 3), and the non-light-emitting side 100B refers to the other side opposite to the light-emitting side 100A (the lower side of the display panel 100 in Figure 3).

[0067] The driving circuit board 200 is located on the non-light-emitting side of the display panel 100 and is connected to the display panel 100 to provide light-emitting signals to the display panel 100.

[0068] The housing 300 can be a box-shaped structure with an opening. The display panel 100 and the driving circuit board 200 can be disposed inside the housing 300. The cover plate 400 is disposed on the light-emitting side of the display panel 100 and is located at the opening of the housing 300.

[0069] As shown in Figure 3, the longitudinal section of the housing 300 can be U-shaped, for example. The display panel 100 and the driving circuit board 200 are disposed inside the housing 300, and the cover plate 400 is disposed at the opening of the housing 300.

[0070] The aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.

[0071] For example, the display panel 100 described above may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, a liquid crystal display (LCD) display panel, or a mini / micro light-emitting display (MLED) display panel, etc. The embodiments disclosed herein do not impose specific limitations.

[0072] For example, Micro LED refers to an LED with a size (e.g., length) of less than 50 μm, while Mini LED refers to an LED with a size (e.g., length) of 50 μm to 200 μm.

[0073] As shown in Figure 4, the display panel 100 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 3 shows an example where the peripheral area BB surrounds the display area AA.

[0074] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0075] In some embodiments, as shown in FIG4, the display panel 100 includes a substrate 10 and a plurality of sub-pixels 20.

[0076] The substrate 10 may be made of polymer resin or glass. Exemplarily, the substrate 10 may be flexible, and the material used for the substrate 10 may include polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenyl sulfide granules (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). For example, the substrate 10 may be rigid, including a glass material containing SiO2 as the main component.

[0077] As shown in Figure 4, multiple sub-pixels 20 are disposed on the substrate 10 and located in the display area AA.

[0078] The aforementioned plurality of sub-pixels 20 may include a first sub-pixel with a first emission color, a second sub-pixel with a second emission color, and a third sub-pixel with a third emission color. The first, second, and third colors are three primary colors. For example, the first color may be red, the second color blue, and the third color green; however, this embodiment does not impose specific limitations.

[0079] In some examples, multiple subpixels 20 can be arranged in multiple rows and columns, with each row of subpixels 20 including at least two subpixels 20 arranged along a first direction X, and each column of subpixels 20 including at least two subpixels 20 arranged along a second direction Y. The first direction X intersects the second direction Y; for example, the first direction X is perpendicular to the second direction Y.

[0080] In some embodiments, as shown in FIG4, the display panel 100 may further include multiple gate lines GL and multiple data lines DL.

[0081] In this configuration, multiple gate lines GL extend along a first direction X and are spaced apart along a second direction Y, with each gate line GL connected to at least one row of sub-pixels 20. For example, one gate line GL is connected to one row of sub-pixels 20.

[0082] Multiple data lines DL extend along the second direction Y and are spaced apart along the first direction X. Each data line DL is connected to at least one column of sub-pixels 20. For example, one data line DL is connected to one column of sub-pixels 20.

[0083] In some embodiments, as shown in FIG4, the display panel 100 further includes a gate driving circuit 30. The gate driving circuit 30 is located on the side of the substrate 10 near the sub-pixel 20 and is located in the peripheral region BB. The gate driving circuit 30 is connected to the gate line GL. In this way, the gate driving circuit 30 can transmit signals to the sub-pixel 20 to drive the sub-pixel 20 to display normally.

[0084] In some examples, as shown in Figure 4, the display panel 100 has a gate drive circuit 30 on one side of the peripheral area BB, which drives each gate line GL sequentially from one side, i.e., the gate drive circuit is driven on one side.

[0085] In other examples, the display panel 100 may have gate drive circuits 30 on two sides in the peripheral area BB along the extension direction of the gate line GL, and the two gate drive circuits 30 simultaneously drive each gate line GL row by row from both sides, that is, the gate drive circuits 30 are dual-sided drive.

[0086] In some other examples, the display panel 100 may have two gate drive circuits 30 on each side of the peripheral area BB along the extension direction of the gate line GL. The two gate drive circuits 30 alternately drive each gate line GL from both sides row by row, that is, the gate drive circuits 30 are cross-driven.

[0087] In some embodiments, as shown in FIG4, the gate drive circuit 30 includes N cascaded shift registers RS. In this case, the display panel 100 includes N gate lines GL, each of which is connected to one of the N cascaded shift registers RS, where N is a positive integer.

[0088] In some embodiments of the shift register RS ​​described above, as shown in FIG4, the shift register RS ​​of the gate driving circuit 30 includes a scan signal output terminal OUTPUT1, which is connected to the gate line GL. In this way, the scan signal output terminal OUTPUT1 outputs the gate scan signal to the sub-pixel 20 through the gate line GL connected to it.

[0089] In some implementations, in addition to the scan signal output terminal OUTPUT1 of the shift register RS, OUTPUT1 can also be connected to the next-level shift register RS ​​to pass cascaded signals to the next-level shift register RS ​​as input signals. That is, OUTPUT1 also serves as the cascaded signal output terminal OUTPUT2, and OUTPUT1 and OUTPUT2 are the same signal output terminal.

[0090] In some embodiments, the shift register RS ​​of the gate drive circuit 30 further includes a cascaded signal output terminal OUTPUT2, which can be connected to the next-level shift register RS ​​to pass cascaded signals to the next-level shift register RS ​​as input signals. That is, the scan signal output terminal OUTPUT1 and the cascaded signal output terminal OUTPUT2 are different signal output terminals.

[0091] In some embodiments, as shown in FIG4, the shift register RS ​​of the gate drive circuit 30 further includes a signal input terminal INPUT. In two adjacent shift registers RS, the cascaded signal output terminal OUTPUT2 of the upper-level shift register RS ​​is connected to the signal input terminal INPUT of the lower-level shift register, and the signal input terminal INPUT of the first-level shift register RS ​​is connected to the initialization signal terminal STV.

[0092] Based on the above structure, the cascaded structure of each stage of the shift register RS ​​in the gate drive circuit 30 can be as follows:

[0093] In each pair of adjacent shift registers RS, the signal input terminal INPUT of the next-stage shift register RS ​​is connected to the cascaded signal output terminal OUTPUT2 of the previous-stage shift register RS, and the signal input terminal INPUT of the first-stage shift register RS ​​is connected to the signal input terminal STV. The scan signal output terminal OUTPUT1 of each stage shift register RS ​​is connected to at least one gate line GL.

[0094] In some examples, shift registers cascaded in N stages along the second direction Y are arranged at intervals.

[0095] In some embodiments, as shown in FIG5, the shift register RS ​​includes an input circuit RS1, a noise control circuit RS2, a noise reduction circuit RS3, and an output circuit RS4.

[0096] In some embodiments, as shown in Figures 6 and 7, the input circuit RS1 includes a first input sub-circuit 1, a second input sub-circuit 2, a first output sub-circuit 3, and a first storage sub-circuit 4.

[0097] In some examples, as shown in Figures 6 and 7, the first input sub-circuit 1 is coupled to the signal input terminal INPUT, the first node N1, and the first clock signal terminal CK1. The first input sub-circuit 1 is configured to, in input phase P1, transmit the working level received at the signal input terminal INPUT to the first node N1 in response to the first clock signal received at the first clock signal terminal CK1; and in output phase P2, cut off the signal input terminal INPUT and the first node N1 in response to the first clock signal received at the first clock signal terminal CK1; and in output phase P2, receive a non-working level at the signal input terminal INPUT.

[0098] For example, as shown in Figures 6 and 7, the first input sub-circuit 1 includes a first transistor T1, the first terminal of the first transistor T1 is connected to the signal input terminal INPUT, the second terminal is connected to the first node N1, and the control terminal is connected to the first clock signal terminal CK1.

[0099] In some examples, as shown in Figures 6 and 7, the second input sub-circuit 2 is coupled to the first node N1, the second node N2, and the first clock signal terminal CK1. The second input sub-circuit 2 is configured to, in the input phase P1, transmit the operating level at the first node N1 to the second node N2 in response to the first clock signal received at the first clock signal terminal CK1, and in the output phase P2, turn off the first node N1 and the second node N2 in response to the first clock signal received at the first clock signal terminal CK1.

[0100] For example, as shown in Figures 6 and 7, the second input sub-circuit 2 includes a second transistor T2. The first terminal of the second transistor T2 is connected to the first node N1, the second terminal is connected to the second node N2, and the control terminal is connected to the first clock signal terminal CK1.

[0101] In this configuration, the first transistor T1 and the second transistor T2 form a dual-gate transistor, which can reduce leakage current.

[0102] In some examples, as shown in Figures 6 and 7, the first output sub-circuit 3 is coupled to the second clock signal terminal CK2, the second node N2, and the cascaded signal output terminal OUTPUT2. The first output sub-circuit 3 is configured to, during input phase P1, under the control of the voltage at the second node N2, transmit the non-operating level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2; and during output phase P2, under the control of the voltage at the second node N2, transmit the operating level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2.

[0103] For example, as shown in FIG7, the first output sub-circuit 3 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the second clock signal terminal CK2, the second terminal is connected to the cascaded signal output terminal OUTPUT2, and the control terminal is connected to the second node N2.

[0104] In some examples, as shown in Figures 6 and 7, the first storage sub-circuit 4 is coupled to the second node N2 and the cascaded signal output terminal OUTPUT2. The first storage sub-circuit 4 is configured to store the voltage at the second node N2 during the input phase P1, and to write the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2 during the output phase P2.

[0105] For example, as shown in FIG7, the first storage sub-circuit 4 includes a first storage capacitor C1, the first plate of the first storage capacitor C1 is connected to the second node N2, and the second plate is connected to the cascaded signal output terminal OUTPUT2.

[0106] Based on the above structure, as shown in Figure 8, in the input stage P1, the first input sub-circuit 1 responds to the first clock signal received at the first clock signal terminal CK1 and transmits the working level received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2 responds to the first clock signal received at the first clock signal terminal CK1 and transmits the working level at the first node N1 to the second node N2. The first storage sub-circuit 4 stores the working level at the second node N2. Under the control of the working level at the second node N2, the first output sub-circuit 3 transmits the non-working level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2.

[0107] In the output phase P2, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the working level at the second node N2, the first output sub-circuit 3 transmits the working level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2, and the first storage sub-circuit 4 writes the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2.

[0108] In some examples, the operating level received at the signal input terminal INPUT is low, for example, Vss, and the non-operating level received at the signal input terminal INPUT is high, for example, Vdd. The operating level received at the second clock signal terminal CK2 is low, for example, Vss, and the non-operating level received at the second clock signal terminal CK2 is high, for example, Vdd.

[0109] At this time, in the input stage P1, the Vss signal received at the signal input terminal INPUT is transmitted to the first node N1 through the first input sub-circuit 1. The Vss signal received at the first node N1 is transmitted to the second node N2 and stored in the first storage sub-circuit 4. Under the control of the Vss signal received at the second node N2, the Vdd signal received at the second clock signal terminal CK2 is transmitted to the cascaded signal output terminal OUTPUT2 through the first output sub-circuit 3.

[0110] In the output stage P2, the Vdd signal received at the signal input terminal INPUT cannot be transmitted to the first node N1 and the second node N2 through the first input sub-circuit 1. The signal at the second node N2 is still Vss. Under the control of the Vss signal at the second node N2, the Vss signal received at the second clock signal terminal CK2 is transmitted to the cascaded signal output terminal OUTPUT2 through the first output sub-circuit 3. The signal received at the cascaded signal output terminal OUTPUT2 changes from Vdd to Vss, that is, the voltage at the cascaded signal output terminal OUTPUT2 drops by Vdd-Vss. The first storage sub-circuit 4 will also cause the voltage at the second node N2 to drop by Vdd-Vss, that is, the voltage at the second node N2 is 2Vss-Vdd.

[0111] In related technologies, the display panel exhibits poor display quality. The inventors discovered that the transistors in the first input sub-circuit are made of low-temperature polycrystalline silicon (LTPS), meaning the transistors in the first input sub-circuit are LPS transistors. Similarly, the transistors in the second input sub-circuit are also made of LPS transistors. LPS transistors exhibit leakage current kick-in characteristics; that is, when the LPS transistor is off, the higher the source-drain voltage difference, the greater the leakage current.

[0112] As mentioned above, during the output stage, the voltage difference between the signal input terminal and the second node is Vdd - (2Vss - Vdd) = 2Vdd - 2Vss. This means that the voltage difference between the signal input terminal and the second node is relatively large. This leads to a large leakage current in the transistors of the first and second input sub-circuits, causing leakage from the signal input terminal to the second node. Consequently, the voltage at the second node changes, becoming unstable. This results in a change in the conduction level of the transistors in the first output sub-circuit, leading to an unstable operating level at the cascaded signal output terminal and ultimately a poor display effect on the display panel.

[0113] To address the aforementioned technical problems, as shown in Figures 6 and 7, some embodiments of this disclosure provide a shift register RS, which further includes a first control sub-circuit 5.

[0114] In some examples, the first control sub-circuit 5 is coupled to the second clock signal terminal CK2, the cascade signal output terminal OUTPUT2 (this stage), and the first node N1. The first control sub-circuit 5 is configured to, in the output stage P2, in response to the operating level at the cascade signal output terminal OUTPUT2, transmit the operating level received at the second clock signal terminal CK2 to the first node N1.

[0115] For example, the first control sub-circuit 5 includes a third transistor T3, the first terminal of the third transistor T3 is connected to the second clock signal terminal CK2, the second terminal is connected to the first node N1, and the control terminal is connected to the cascaded signal output terminal OUTPUT2.

[0116] In some examples, the working level received at the second clock signal terminal CK2 is low, for example, Vss. The non-working level received at the second clock signal terminal CK2 is high, for example, Vdd.

[0117] At this time, in the input stage P1, under the control of the Vdd signal received at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 controls the second clock signal terminal CK2 and the first node N1 to be cut off. In the output stage P2, under the control of the VSS signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 transmits the Vss signal received at the second clock signal terminal CK2 to the first node N1. At this time, the voltage difference between the first node N1 and the second node N2 is Vss - (2Vss - Vdd) = Vdd - Vss.

[0118] In this configuration, the first control sub-circuit 5 can make the voltage difference between the first node N1 and the second node N2 Vdd-Vss, that is, the source-drain voltage difference of the transistors included in the second input sub-circuit 2 is Vdd-Vss. In this way, the source-drain voltage difference of the transistors included in the second input sub-circuit 2 is small, and the leakage current of the transistors included in the second input sub-circuit 2 is small or non-existent, thereby reducing the risk of leakage current from the first node N1 to the second node N2. This is beneficial to improving the voltage stability at the second node N2, improving the stability of the conduction degree of the transistors included in the first output sub-circuit 3, and improving the stability of the operating level received at the cascaded signal output terminal OUTPUT2, thereby improving the display effect of the display panel 100.

[0119] In some embodiments, as shown in Figures 6 and 7, the shift register RS ​​further includes a third input sub-circuit 6, a second control sub-circuit 7, and a second output sub-circuit 8.

[0120] In some examples, as shown in Figures 6 and 7, the third input sub-circuit 6 is coupled to the first voltage signal terminal VDD1, the third node N3, and the fourth node N4. The third input sub-circuit 6 is configured to, during input phase P1, under the control of the voltage at the fourth node N4, transmit the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3. The first voltage signal is at a non-operating level.

[0121] For example, as shown in FIG7, the third input sub-circuit 6 includes an eighth transistor T8, the first terminal of the eighth transistor T8 is connected to the second voltage signal terminal, the second terminal is connected to the third node N3, and the control terminal is connected to the fourth node N4.

[0122] In some examples, as shown in Figures 6 and 7, the second control sub-circuit 7 is coupled to the second node N2, the third node N3, the first voltage signal terminal VDD1, the second voltage signal terminal VSS, and the third clock signal terminal CK3. The second control sub-circuit 7 is configured, during the hold phase P3, in response to the third clock signal received at the third clock signal terminal CK3, to transmit the second voltage signal received at the second voltage signal terminal VSS to the third node N3, and to transmit the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. The second voltage signal is at the operating level.

[0123] In some examples, as shown in Figures 6 and 7, the second output sub-circuit 8 is coupled to the third voltage signal terminal VDD3, the third node N3, and the cascaded signal output terminal OUTPUT2. The second output sub-circuit 8 is configured to, during the holding phase, transmit the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2 under the control of the voltage at the third node N3, wherein the third voltage signal is at a non-operating level.

[0124] For example, as shown in FIG7, the second output sub-circuit 8 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is connected to the third voltage signal terminal VDD3, the second terminal is connected to the cascaded signal output terminal OUTPUT2, and the control terminal is connected to the third node N3.

[0125] Based on the above structure, in the input stage P1, under the control of the voltage at the fourth node N4, the third input sub-circuit 6 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3. Under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascaded signal output terminal OUTPUT2. The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, controls the second voltage signal terminal VSS and the third node N3 to cut off, and under the control of the first voltage signal at the third node N3, the second control sub-circuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2.

[0126] In the output phase P2, under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascaded signal output terminal OUTPUT2. The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, controls the second voltage signal terminal VSS and the third node N3 to cut off, and under the control of the first voltage signal at the third node N3, the second control sub-circuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2.

[0127] During the hold phase P3, the second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. Under the control of the third voltage signal at the second node N2, the first input sub-circuit 1 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2.

[0128] In some examples, as shown in Figure 8, the holding phase P3 includes a first holding phase P31, a second holding phase P32, and a third holding phase P33.

[0129] During the first hold phase P31, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-operating level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the voltage at the fourth node N4, the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3. In response to the third clock signal received at the third clock signal terminal CK3, the second control sub-circuit 7 transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. The second control sub-circuit 7 also transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2. The level received at the second clock signal terminal CK2 is a non-working level. Under the control of the third voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0130] During the second hold phase P32, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-operating level received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-operating level at the first node N1 to the second node N2. Under the control of the voltage at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal and / or non-operating level at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-operating level. Under the control of the first voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the cascaded signal output terminal OUTPUT2 and the first node N1.

[0131] During the third hold phase P33, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-operating level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the voltage of the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2, and transmits the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the first voltage signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is the working level. Under the control of the first voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the cascaded signal output terminal OUTPUT2 and the first node N1.

[0132] In some examples, the operating level received at the signal input terminal INPUT is low, for example, Vss; the non-operating level received at the signal input terminal INPUT is high, for example, Vdd. The operating level received at the second clock signal terminal CK2 is low, for example, Vss; the non-operating level received at the second clock signal terminal CK2 is high, for example, Vdd. The first voltage signal received at the first voltage signal terminal VDD1 is high, for example, Vdd. The second voltage signal received at the second voltage signal terminal VSS is low, for example, Vss. The third voltage signal received at the third voltage signal terminal VDD3 is high, for example, Vdd.

[0133] At this time, in the input stage P1, the Vss signal received at the signal input terminal INPUT is transmitted to the second node N2 through the first input sub-circuit 1 and the second input sub-circuit 2. Under the control of the Vss signal at the second node N2, the first output sub-circuit 3 transmits the Vdd signal received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2.

[0134] Under the control of the voltage of the fourth node N4, the third input sub-circuit 6 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the third node N3. The second control sub-circuit 7 responds to the third clock signal received at the third clock signal terminal CK3 and controls the second voltage signal terminal VSS and the third node N3 to be cut off. The Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3 through the second control sub-circuit 7, so that the signal received at the third node N3 is the Vdd signal.

[0135] Under the control of the Vdd signal at the third node N3, the second control sub-circuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2. The Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the second node N2 through the second control sub-circuit 7, so that the signal received at the second node N2 is the Vss signal. Under the control of the Vdd signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascaded signal output terminal OUTPUT2. The Vdd signal received at the third voltage signal terminal VDD3 cannot be transmitted to the cascaded signal output terminal OUTPUT2 through the second output sub-circuit 8.

[0136] In the output phase P2, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, controls the control signal input terminal INPUT and the first node N1 to be turned off. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, controls the first node N1 and the second node N2 to be turned off. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0137] The second control sub-circuit 7 responds to the third clock signal received at the third clock signal terminal CK3 by controlling the second voltage signal terminal VSS and the third node N3 to be cut off. The Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3 through the second control sub-circuit 7, so that the signal received at the third node N3 is the Vdd signal.

[0138] Under the control of the Vdd signal at the third node N3, the second control sub-circuit 7 cuts off the first voltage signal terminal VDD1 and the second node N2. The Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the second node N2. Under the control of the Vss signal at the second node N2, the first output sub-circuit 3 transmits the Vss signal received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2. Under the control of the Vdd signal at the third node N3, the second output sub-circuit 8 cuts off the first voltage signal terminal VDD1 and the cascaded signal output terminal OUTPUT2, so that the signal at the cascaded signal output terminal OUTPUT2 is the Vss signal. The first storage sub-circuit 4 writes the difference between the Vdd signal and the Vss signal received at the second clock signal terminal into the second node, so the signal received at the second node N2 is 2Vss-Vdd.

[0139] During the first hold phase P31, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0140] Under the control of the voltage of the fourth node N4, the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3, so the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3.

[0141] The second control sub-circuit 7 responds to the third clock signal received at the third clock signal terminal CK3 and transmits the Vss signal received at the second voltage signal terminal VSS to the third node N3.

[0142] Under the control of the Vss signal at the third node N3, the second control sub-circuit 7 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the Vdd signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, preventing the Vdd signal received at the second clock signal terminal CK2 from being transmitted to the cascaded signal output terminal OUTPUT2. Under the control of the Vss signal at the third node N3, the second output sub-circuit 8 transmits the Vdd signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2.

[0143] Under the control of the Vdd signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1, so the Vdd signal received at the second clock signal terminal CK2 cannot be transmitted to the first node N1.

[0144] During the second hold phase P32, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, transmits the Vdd signal received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, transmits the Vdd signal received at the first node N1 to the second node N2.

[0145] Under the control of the voltage of the fourth node N4, the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3, so the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3.

[0146] The second control sub-circuit 7, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. The Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3. The signal received at the third node N3 is the Vss signal received at the third node N3 during the first holding phase P31, that is, during the second holding phase P32, the signal received at the third node N3 is still the Vss signal.

[0147] Under the control of the Vss signal at the third node N3, the second control sub-circuit 7 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the second node N2. Under the control of the Vdd signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, preventing the Vdd signal received at the second clock signal terminal CK2 from being transmitted to the cascaded signal output terminal OUTPUT2. Under the control of the Vss signal at the third node N3, the second output sub-circuit 8 transmits the Vdd signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2.

[0148] Under the control of the Vdd signal at the cascade signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1. The Vdd signal received at the cascade signal output terminal OUTPUT2 cannot be transmitted to the first node N1.

[0149] During the third hold phase P33, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. The Vdd signal received at the signal input terminal INPUT cannot be transmitted to the second node N2.

[0150] Under the control of the voltage of the fourth node N4, the third input sub-circuit 6 cuts off the first voltage signal terminal VDD1 and the third node N3, so the Vdd signal received at the first voltage signal terminal VDD1 cannot be transmitted to the third node N3.

[0151] In response to the third clock signal received at the third clock signal terminal CK3, the second control sub-circuit 7 cuts off the second voltage signal terminal VSS and the third node N3. The Vss signal received at the second voltage signal terminal VSS cannot be transmitted to the third node N3. The signal received at the third node N3 is the Vss signal received at the third node N3 in the second holding phase P32, that is, in the third holding phase P33, the signal received at the third node N3 is still the VSS signal.

[0152] Under the control of the Vss signal at the third node N3, the second control sub-circuit 7 transmits the Vdd signal received at the second voltage signal terminal VSS to the second node N2. Under the control of the Vdd signal received at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, preventing the Vss signal received at the second clock signal terminal CK2 from being transmitted to the cascaded signal output terminal OUTPUT2. Under the control of the Vss signal at the third node N3, the second output sub-circuit 8 transmits the Vdd signal received at the first voltage signal terminal VDD1 to the cascaded signal output terminal OUTPUT2.

[0153] Under the control of the Vdd signal received at the cascade signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1, so the Vdd signal received at the cascade signal output terminal OUTPUT2 cannot be transmitted to the first node N1.

[0154] In some embodiments, as shown in Figures 6 and 7, the second control sub-circuit 7 includes a primary control sub-circuit 71 and a secondary control sub-circuit 72.

[0155] In some examples, as shown in Figures 6 and 7, the first-level control subcircuit 71 is coupled to the third node N3, the second voltage signal terminal VSS, and the third clock signal terminal CK3. The first-level control subcircuit 71 is configured to, during the hold phase P3, in response to the third clock signal received at the third clock signal terminal CK3, transmit the second voltage signal received at the second voltage signal terminal VSS to the third node N3. The second voltage signal is at the operating level.

[0156] For example, as shown in FIG7, the first-level control sub-circuit 71 includes a sixth transistor T6. The first terminal of the sixth transistor T6 is coupled to the second voltage signal terminal VSS, the second terminal is coupled to the third node N3, and the control terminal is coupled to the third clock signal terminal CK3.

[0157] In some examples, as shown in Figures 6 and 7, the secondary control subcircuit 72 is coupled to the second node N2, the third node N3, and the first voltage signal terminal VDD1. The secondary control subcircuit 72 is configured to, during the holding phase P3, under the control of the voltage at the third node N3, transmit the first voltage signal received at the first voltage signal terminal VDD1 to the second node N2.

[0158] In some embodiments, as shown in Figures 6 and 7, the secondary control sub-circuit 72 includes a first sub-circuit 721 and a second sub-circuit 722.

[0159] In some examples, as shown in Figures 6 and 7, the first sub-circuit 721 is coupled to the third node N3, the first voltage signal terminal VDD1, and the fifth node N5. The first sub-circuit 721 is configured to, during the output phase P2, cut off the first voltage signal terminal VDD1 and the fifth node N5 under the control of the second voltage signal at the third node N3.

[0160] For example, as shown in FIG7, the first sub-circuit 721 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the first voltage signal terminal VDD1, the second terminal is connected to the fifth node N5, and the control is connected to the third node N3. For example, the fourth transistor T4 is a low-temperature polysilicon transistor.

[0161] As shown in Figures 6 and 7, the second sub-circuit 722 is coupled to the second node N2, the third node N3, and the fifth node N5. The second sub-circuit 722 is configured to cut off the fifth node N5 and the second node N2 under the control of the voltage at the third node N3 during the output phase P2.

[0162] For example, as shown in FIG7, the second sub-circuit 722 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the fifth node N5, the second terminal is connected to the second node N2, and the control terminal is connected to the third node N3. For example, the fifth transistor T5 is a low-temperature polysilicon transistor.

[0163] Based on this, as shown in Figures 6 and 7, the second control sub-circuit 7 also includes a three-level control sub-circuit 73.

[0164] In some examples, the three-level control subcircuit 73 is coupled to the fifth node N5, the second node N2, and the second voltage signal terminal VSS. The three-level control subcircuit 73 is configured to, during the output phase P2, transmit the second voltage signal received at the second voltage signal terminal VSS to the fifth node N5 under the control of the voltage at the second node N2.

[0165] For example, as shown in FIG7, the three-level control sub-circuit 73 includes a tenth transistor T10. The first terminal of the tenth transistor T10 is connected to the second voltage signal terminal VSS, the second terminal is connected to the fifth node N5, and the control terminal is connected to the second node N2.

[0166] Based on the above structure, in the output stage P2, under the control of the voltage at the third node N3, the first sub-circuit 721 controls the first voltage signal terminal VDD1 and the fifth node N5 to be cut off, and the second sub-circuit 722 controls the fifth node N5 and the second node N2 to be cut off. Under the control of the voltage at the second node N2, the three-level control sub-circuit 73 transmits the second voltage signal received at the second voltage signal terminal VSS to the fifth node N5.

[0167] In some examples, the second voltage signal received at the second voltage signal terminal VSS is low, for example, the second voltage signal received at the second voltage signal terminal VSS is Vss.

[0168] At this point, during input phase P1, under the control of the Vss signal at the second node N2, the three-level control sub-circuit 73 transmits the Vss signal received at the third voltage signal terminal VDD3 to the fifth node N5. During output phase P2, under the control of the Vss signal or the 2Vss-Vdd signal at the second node N2, the three-level control sub-circuit 73 transmits the Vss signal received at the second voltage signal terminal VSS to the fifth node N5. At this point, the voltage difference between the fifth node N5 and the second node N2 is Vss - (2Vss - Vdd) = Vdd - Vss.

[0169] In this configuration, the three-level control sub-circuit 73 can make the voltage difference between the fifth node N5 and the second node N2 Vdd-Vss, that is, the source-drain voltage difference of the transistors included in the second sub-circuit 722 is Vdd-Vss. In this way, the source-drain voltage difference of the transistors included in the second sub-circuit 722 is small, and the leakage current of the transistors included in the second sub-circuit 722 is small or non-existent. This reduces the risk of leakage current from the fifth node N5 to the second node N2, which is beneficial to further improve the voltage stability at the second node N2, improve the stability of the conduction degree of the transistors in the first output sub-circuit 3, and improve the stability of the operating level received at the cascaded signal output terminal OUTPUT2, thereby improving the display effect of the display panel 100.

[0170] In some embodiments, as shown in Figures 6 and 7, the fourth node N4 is connected to the signal input terminal INPUT.

[0171] In some other embodiments, as shown in FIG9, the fourth node N4 and the first node N1 are connected.

[0172] In some other embodiments, as shown in FIG10, the fourth node N4 and the fifth node N5 are connected.

[0173] In some implementations, as shown in Figures 6 and 7, the shift register RS ​​also includes a second storage sub-circuit 9.

[0174] In some examples, the second storage sub-circuit 9 is coupled to the third voltage signal terminal VDD3 and the third node N3. The second storage sub-circuit 9 is configured to store the voltage at the third node N3.

[0175] For example, as shown in FIG7, the second storage sub-circuit 9 includes a second storage capacitor C2, the first plate of the second storage capacitor C2 is connected to the third node N3, and the second plate is connected to the third voltage signal terminal VDD3.

[0176] In some embodiments, as shown in FIG11, the gate driving circuit 30 further includes multiple clock signal lines CL. The multiple clock signal lines CL are divided into multiple groups. In the same group, in adjacent shift registers RS, the clock signal line CL connected to the second clock signal terminal CK2 in the upper-level shift register RS ​​is the same as the clock signal line CL connected to the first clock signal terminal CK1 in the lower-level shift register RS. The clock signal line CL connected to the third clock signal terminal CK3 in the upper-level shift register RS ​​is the same as the clock signal line CL connected to the second clock signal terminal CK2 in the lower-level shift register RS. The clock signal line CL connected to the first clock signal terminal CK1 in the upper-level shift register RS ​​is different from the clock signal line CL connected to the third clock signal terminal CK3 in the lower-level shift register RS. The clock signal lines CL connected to the same clock signal terminal in any two shift registers RS are different.

[0177] With this configuration, the number of clock signal lines CL is greater than three, which reduces the clock frequency on the clock signal lines CL and helps to reduce the power consumption of the display panel 100.

[0178] In some examples, the gate drive circuit 30 includes four clock signal lines CL. For ease of description, the first clock signal line CL to the fourth clock signal line CL are labeled as the first clock signal line CL (1), the second clock signal line CL (2), the third clock signal line CL (3), and the fourth clock signal line CL (4) in the direction away from the display area AA.

[0179] Multiple shift registers RS are divided into multiple groups, and each group includes four shift registers RS. For ease of description, the four shift registers RS included in a group of shift registers RS are labeled as first-stage shift register RS(1), second-stage shift register RS(2), third-stage shift register RS(3), and fourth-stage first-stage shift register RS(4) in cascade order.

[0180] In some examples, as shown in Figure 11, the first clock signal terminal CK1 of the first-stage shift register RS(1) is connected to the first clock signal line CL(1), the second clock signal terminal CK2 is connected to the second clock signal line CL(2), and the third clock signal line CL is connected to the third clock signal line CL(3). The first clock signal terminal CK1 of the second-stage shift register RS(2) is connected to the second clock signal line CL(2), the second clock signal terminal CK2 is connected to the third clock signal line CL(3), and the third clock signal terminal CK3 is connected to the fourth clock signal line CL(4). The first clock signal terminal CK1 of the third-stage shift register RS(3) is connected to the third clock signal line CL(3), the second clock signal terminal CK2 is connected to the fourth clock signal line CL(4), and the third clock signal terminal CK3 is connected to the first clock signal line CL(1). The first clock signal terminal CK1 of the fourth-stage shift register RS(4) is connected to the fourth clock signal line CL(4), the second clock signal terminal CK2 is connected to the first clock signal line CL(1), and the third clock signal terminal CK3 is connected to the second clock signal line CL(2).

[0181] In some embodiments, as shown in FIG11, the gate driving circuit 30 further includes a first voltage signal line VL1 and a second voltage signal line VL2. The first voltage signal line VL1 is connected to the first voltage signal terminal VDD1 and the shift register RS. The second voltage signal line VL2 is connected to the third voltage signal terminal VDD3 and the shift register RS.

[0182] With this configuration, the first voltage signal terminal VDD1 and the third voltage signal terminal VDD3 are independent of each other, which can reduce the influence between the second control sub-circuit 7 and the second output sub-circuit 8, and is beneficial to improving the display effect of the display panel 100.

[0183] Based on this, the width of the first voltage signal line VL1 is smaller than the width of the second voltage signal line VL2.

[0184] With this configuration, the width of the second voltage signal line VL2 is larger, the resistance of the second voltage signal line VL2 is smaller, and the voltage drop across the second voltage signal line VL2 is smaller. This can improve the signal quality at the cascaded signal output terminal OUTPUT2, which is beneficial to improving the display effect of the display panel 100.

[0185] In some examples, the linewidth of the first voltage signal line VL1 is 3μm to 10μm.

[0186] For example, the linewidth of the first voltage signal line VL1 is 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 7μm, 8μm, 9μm or 10μm.

[0187] In some examples, the linewidth of the second voltage signal line VL2 is 10μm to 20μm.

[0188] For example, the linewidth of the second voltage signal line VL2 is 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm or 20μm.

[0189] In some embodiments, multiple shift registers RS are arranged at intervals along the second direction Y. A first voltage signal line VL1 extends along the second direction Y and along the first direction X, located between the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10, and between the seventh transistor T7 and the ninth transistor T9. A second voltage signal line VL2 extends along the second direction and along the first direction X, located on the side of the seventh transistor T7 and the ninth transistor T9 away from the first voltage signal line VL1.

[0190] With this configuration, the line width of the first voltage signal line VL1 is narrower, which can shorten the length of the connecting line that spans the first voltage signal line VL1, reduce the voltage drop of this connecting line, improve the signal quality of this connecting line, and enhance the display effect of the display panel 100.

[0191] In some embodiments, as shown in FIG11, the first storage capacitor C1 is located on the side away from the first voltage signal line VL1 between the seventh transistor T7 and the ninth transistor T9. The orthographic projection of the second voltage signal line VL2 onto the reference plane overlaps with the orthographic projection of the first storage capacitor C1 onto the reference plane. Along the first direction X, the two ends of the first storage capacitor C1 extend beyond the two ends of the second voltage signal line VL2. The reference plane is parallel to the surface of the substrate 10 near the sub-pixel 20.

[0192] With this configuration, the total width of the first storage capacitor C1, the first voltage signal line VL1, and the second voltage signal line VL2 is narrower along the first direction X, which can shorten the width of the peripheral area BB and help the display panel 100 achieve a narrow bezel.

[0193] In some embodiments, as shown in FIG11, the second storage capacitor C2 is located on the side of the first storage capacitor C1 away from the next-stage shift register RS, and on the side of the seventh transistor T7 and the ninth transistor T9 away from the first voltage signal line VL1. The orthographic projection of the second storage capacitor C2 on the reference plane overlaps with the orthographic projection of the second voltage signal line VL2 on the reference plane, and along the first direction, the two ends of the second storage capacitor C2 extend beyond the two ends of the second voltage signal line VL2.

[0194] In some embodiments, as shown in FIG11, the clock signal line CL extends along the second direction Y, and the clock signal line CL is located on the side away from the first voltage signal line VL1 of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10.

[0195] The gate drive circuit 30 also includes a third voltage signal line VL3, which is connected to the second voltage signal terminal VSS and the shift register RS. The third voltage signal line VL3 extends along the second direction and is located between the clock signal line CL and the shift register RS.

[0196] In some embodiments, as shown in FIG11, the fourth transistor T4 and the fifth transistor T5 are located between the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10, and the first voltage signal line VL1, along the second direction, with the fourth transistor T4 located on one side of the fifth transistor T5.

[0197] This configuration allows for a shorter distance between the fourth transistor T4 and the first voltage signal line VL1, reducing the length of the connection line between them and thus lowering the voltage drop on the connection line. This improves the quality of the signal transmitted from the first voltage signal line VL1 to the fourth transistor T4, which in turn enhances the display effect of the display panel 100.

[0198] In some embodiments, as shown in FIG11, the third transistor T3 and the sixth transistor T6 are located between the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8 and the tenth transistor T10, and the third voltage signal line VL3, along the second direction, with the third transistor T3 located on one side of the fifth transistor T5.

[0199] This configuration allows for a shorter distance between the third transistor T3 and the clock signal line CL, reducing the length of the connection line between them, lowering the voltage drop on the connection line, and improving the quality of the signal transmitted from the clock signal line CL to the third transistor T3. This, in turn, enhances the display effect of the display panel 100.

[0200] On the other hand, the distance between the sixth transistor T6 and the third voltage signal line VL3 can be shortened, thereby reducing the length of the connection line between the sixth transistor T6 and the third voltage signal line VL3, reducing the voltage drop on the connection line between the sixth transistor T6 and the third voltage signal line VL3, improving the quality of the signal transmitted from the third voltage signal line VL3 to the sixth transistor T6, and thus improving the display effect of the display panel 100.

[0201] In some embodiments, as shown in FIG11, the eighth transistor T8 is located between the fourth transistor T4 and the fifth transistor T5, and between the third transistor T3 and the sixth transistor T6, and is located on the side of the first transistor T1, the second transistor T2 and the tenth transistor T10 away from the next-stage shift register RS; the fourth transistor T4 is located on the side of the fifth transistor T5 away from the next-stage shift register RS, and the ninth transistor T9 is located on the side of the seventh transistor T7 away from the next-stage shift register RS;

[0202] The gate drive circuit 30 also includes a first connection line 31, which is connected to the first terminal of the third transistor T3, the second terminal of the seventh transistor T7, and the gate of the next-stage eighth transistor T8. The first connection line 31 is located on the side of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10 near the next-stage shift register RS.

[0203] This configuration allows for a shorter distance between the eighth transistor T8 and the first connection line 31, reducing the length of the connection line between the eighth transistor T8 and the first connection line 31, lowering the voltage drop on the connection line between the eighth transistor T8 and the first connection line 31, improving the quality of the signal transmitted from the first connection line 31 to the eighth transistor T8, and thus enhancing the display effect of the display panel 100.

[0204] In some embodiments, as shown in FIG11, along the second direction Y, the channel portion of the first transistor T1 is located on the side of the channel portion of the second transistor T2 closer to the previous stage shift register RS, and along the first direction X, the channel portion of the first transistor T1 is located on the side of the channel portion of the second transistor T2 away from the first voltage signal line VL1, and the channel portion of the third transistor T3 is located on the side of the channel portion of the first transistor T1 and the channel portion of the second transistor T2 away from the first voltage signal line VL1.

[0205] With this configuration, the distance between the first transistor T1 and the third transistor T3 is shorter, and the distance between the second transistor T2 and the third transistor T3 is also shorter. This helps to reduce the area occupied by the first transistor T1, the second transistor T2, and the third transistor T3, thereby facilitating the achievement of a narrow bezel for the display panel 100.

[0206] The following detailed explanation, with reference to timing diagrams, describes the operation of the shift register RS ​​within one display frame period P. The following examples use P-type transistors as an example.

[0207] In some embodiments, as shown in Figures 7 and 8, the fourth node N4 is connected to the signal input terminal INPUT. A display frame period P includes an input phase P1, an output phase P2, a first hold phase P31, a second hold phase P32, and a third hold phase P33.

[0208] As shown in Figures 8 and 12, during the input phase P1, the first input sub-circuit 1, responding to the first clock signal received at the first clock signal terminal CK1, transmits the working level received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2, responding to the first clock signal received at the first clock signal terminal CK1, transmits the working level at the first node N1 to the second node N2. The first storage sub-circuit 4 stores the working level at the second node N2. Under the control of the working level at the second node N2, the first output sub-circuit 3 transmits the non-working level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2. The first control sub-circuit 5, responding to the non-working level at the cascaded signal output terminal OUTPUT2, cuts off the second clock signal terminal CK2 and the first node N1. The third input sub-circuit 6, responding to the working level received at the second clock signal terminal CK2, transmits the first voltage signal received at the first voltage signal terminal VDD1 to the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascaded signal output terminal OUTPUT2. Also under the control of the first voltage signal at the third node N3, the first sub-circuit 721 cuts off the first voltage signal terminal VDD1 and the fifth node N5, and the second sub-circuit 722 cuts off the fifth node N5 and the second node N2. Under the control of the voltage at the second node N2, the third-level control sub-circuit 73 transmits the second voltage signal at the second voltage signal terminal VSS to the fifth node N5.

[0209] For example, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. As shown in Figure 8, in the input stage P1, the first input signal is 0, the first clock signal is 0, the second voltage signal is 0, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0210] In this configuration, as shown in Figures 8 and 12, the signal input terminal INPUT, the first clock signal terminal CK1, and the second voltage signal terminal VSS are all at low levels, while the second clock signal terminal CK2, the third clock signal terminal CK3, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are all at high levels. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned on. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned off.

[0211] At this time, the working level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and to the second node N2 through the first transistor T1 and the second transistor T2. The non-working level received at the second clock signal terminal CK2 is transmitted to the cascaded signal output terminal OUTPUT2 through the seventh transistor T7. The first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the third node N3 through the eighth transistor T8. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the fifth node N5 through the tenth transistor T10.

[0212] As shown in Figures 8 and 13, in the output stage P2, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the working level at the second node N2, the first output sub-circuit 3 transmits the working level received at the second clock signal terminal CK2 to the cascaded signal output terminal OUTPUT2, and the first storage sub-circuit 4 writes the difference between the working level and the non-working level received at the second clock signal terminal CK2 into the second node N2. The first control sub-circuit 5, in response to the working level at the cascaded signal output terminal OUTPUT2, transmits the working level received at the second clock signal terminal CK2 to the first node N1. The third input sub-circuit 6, in response to the non-working level received at the second clock signal terminal CK2, cuts off the first voltage signal terminal VDD1 and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the first voltage signal at the third node N3, the second output sub-circuit 8 cuts off the third voltage signal terminal VDD3 and the cascaded signal output terminal OUTPUT2. Also under the control of the first voltage signal at the third node N3, the first sub-circuit 721 cuts off the first voltage signal terminal VDD1 and the fifth node N5, and the second sub-circuit 722 cuts off the fifth node N5 and the second node N2. Under the control of the voltage at the second node N2, the third-level control sub-circuit 73 transmits the second voltage signal at the second voltage signal terminal VSS to the fifth node N5.

[0213] For example, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. As shown in Figure 8, during the input phase P1, the second clock signal is 0, the second voltage signal is 0, the first input signal is 1, the first clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0214] As shown in Figures 8 and 13, in this case, the second clock signal terminal CK2 and the second voltage signal terminal VSS are input at low levels, while the signal input terminals INPUT, the first clock signal terminal CK1, the third clock signal terminal CK3, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are input at high levels. The third transistor T3, the seventh transistor T7, and the tenth transistor T10 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0215] At this time, the operating level received at the second clock signal terminal CK2 is transmitted to the cascaded signal output terminal OUTPUT2 through the seventh transistor T7, and the operating level at the cascaded signal output terminal OUTPUT2 is transmitted to the first node N1 through the third transistor T3. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the fifth node N5 through the tenth transistor T10.

[0216] As shown in Figures 8 and 14, during the first holding phase P31, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at a non-working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the non-working level at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, transmits the second voltage signal received at the second voltage signal terminal VSS to the third node N3. Under the control of the second voltage signal at the third node N3, the first sub-circuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second sub-circuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-operating level. Under the control of the second voltage signal at the second node N2, the third-level control sub-circuit 73 cuts off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. Under the control of the third voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0217] For example, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. As shown in Figure 14, in the input phase P1, the third clock signal is 0, the second voltage signal is 0, the first input signal is 1, the first clock signal is 1, the second clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0218] As shown in Figures 8 and 14, in this case, the third clock signal terminal CK3 and the second voltage signal terminal VSS are input at low levels, while the signal input terminals INPUT, the first clock signal terminal CK1, the second clock signal terminal CK2, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are input at high levels. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the ninth transistor T9 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0219] At this time, the first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascaded signal output terminal OUTPUT2 through the ninth transistor T9.

[0220] As shown in Figures 8 and 15, during the second holding phase P32, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-working level received at the signal input terminal INPUT to the first node N1. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, transmits the non-working level at the first node N1 to the second node N2. Under the control of the non-working level at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the first sub-circuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second sub-circuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, and / or under the control of the non-working level at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-working level. Under the control of the second voltage signal at the second node N2, the third-level control sub-circuit 73 cuts off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. Under the control of the third voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0221] For example, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. As shown in Figure 8, in the input phase P1, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0222] As shown in Figures 8 and 15, in this case, the first clock signal terminal CK1 and the second voltage signal terminal VSS are input at low levels, while the signal input terminals INPUT, the second clock signal terminal CK2, the third clock signal terminal CK3, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are input at high levels. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are turned on. The third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0223] At this time, the operating level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and to the second node N2 through the first transistor T1 and the second transistor T2. The first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascaded signal output terminal OUTPUT2 through the ninth transistor T9.

[0224] As shown in Figures 8 and 16, during the third holding phase P33, the first input sub-circuit 1, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the signal input terminal INPUT and the first node N1, and the signal received at the signal input terminal INPUT is at the working level. The second input sub-circuit 2, in response to the first clock signal received at the first clock signal terminal CK1, cuts off the first node N1 and the second node N2. Under the control of the non-working level at the fourth node N4, the third input sub-circuit 6 cuts off the second voltage signal terminal VSS and the third node N3. The first-level control sub-circuit 71, in response to the third clock signal received at the third clock signal terminal CK3, cuts off the second voltage signal terminal VSS and the third node N3. Under the control of the second voltage signal at the third node N3, the first sub-circuit 721 transmits the first voltage signal received at the first voltage signal terminal VDD1 to the fifth node N5, and the second sub-circuit 722 transmits the first voltage signal at the fifth node N5 to the second node N2. Under the control of the second voltage signal at the second node N2, the first output sub-circuit 3 cuts off the second clock signal terminal CK2 and the cascaded signal output terminal OUTPUT2, and the level received at the second clock signal terminal CK2 is a non-operating level. Under the control of the second voltage signal at the second node N2, the third-level control sub-circuit 73 cuts off the second voltage signal terminal VSS and the fifth node N5. Under the control of the second voltage signal at the third node N3, the second output sub-circuit 8 transmits the third voltage signal received at the third voltage signal terminal VDD3 to the cascaded signal output terminal OUTPUT2. Under the control of the third voltage signal at the cascaded signal output terminal OUTPUT2, the first control sub-circuit 5 cuts off the second clock signal terminal CK2 and the first node N1.

[0225] For example, each sub-circuit in the shift register RS ​​includes a transistor or a storage capacitor. As shown in Figure 8, in the input phase P1, the first clock signal is 0, the second voltage signal is 0, the first input signal is 1, the second clock signal is 1, the third clock signal is 1, the first voltage signal is 1, and the third voltage signal is 1.

[0226] As shown in Figures 8 and 16, in this configuration, the second clock signal terminal CK2 and the second voltage signal terminal VSS are input at low levels, while the first clock signal terminal CK1, the signal input terminal INPUT, the third clock signal terminal CK3, the first voltage signal terminal VDD1, and the third voltage signal terminal VDD3 are input at high levels. The fourth transistor T4, the fifth transistor T5, and the ninth transistor T9 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0227] At this time, the operating level received at the signal input terminal INPUT is transmitted to the first node N1 through the first transistor T1, and to the second node N2 through the first transistor T1 and the second transistor T2. The first voltage signal received at the first voltage signal terminal VDD1 is transmitted to the fifth node N5 through the fourth transistor T4, and to the second node N2 through the fourth transistor T4 and the fifth transistor T5. The second voltage signal received at the second voltage signal terminal VSS is transmitted to the third node N3 through the sixth transistor T6. The third voltage signal received at the third voltage signal terminal VDD3 is transmitted to the cascaded signal output terminal OUTPUT2 through the ninth transistor T9.

[0228] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0229] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register, comprising: A first input sub-circuit is coupled to a signal input terminal, a first node, and a first clock signal terminal; the first input sub-circuit is configured to, during the input phase, in response to a first clock signal received at the first clock signal terminal, transmit the operating level received at the signal input terminal to the first node; And in the output phase, in response to the first clock signal received at the first clock signal terminal, the signal input terminal and the first node are cut off; During the output phase, a non-operating level is received at the signal input terminal; The first input sub-circuit includes a first transistor, which is a low-temperature polysilicon transistor; A second input sub-circuit is coupled to the first node, the second node, and the first clock signal terminal. The second input sub-circuit is configured to, during the input phase, transfer the voltage at the first node to the second node in response to a first clock signal received at the first clock signal terminal, and during the output phase, turn off the first node and the second node in response to a first clock signal received at the first clock signal terminal. The second input sub-circuit includes a second transistor, which is a low-temperature polysilicon transistor. A first output sub-circuit is coupled to a second clock signal terminal, a second node, and a cascaded signal output terminal; the first output sub-circuit is configured to, during the input phase, under the control of the voltage at the second node, transmit the non-operating level received at the second clock signal terminal to the cascaded signal output terminal. And in the output stage, under the control of the voltage at the second node, the operating level received at the second clock signal terminal is transmitted to the cascaded signal output terminal; A first storage sub-circuit is coupled to the second node and the cascaded signal output terminal; the first storage sub-circuit is configured to, during the input phase, store the voltage at the second node, and during the output phase, write the difference between the working level and the non-working level received at the second clock signal terminal into the second node; The first control sub-circuit is coupled to the second clock signal terminal, the cascaded signal output terminal and the first node; The first control sub-circuit is configured to, in the output phase, transmit the operating level received at the second clock signal terminal to the first node in response to the operating level at the cascaded signal output terminal.

2. The shift register according to claim 1, wherein, The first control sub-circuit includes: The third transistor has its first terminal connected to the second clock signal terminal, its second terminal connected to the first node, and its control terminal connected to the cascaded signal output terminal.

3. The shift register according to claim 1 or 2, further comprising: A third input sub-circuit is coupled to a first voltage signal terminal, a third node, and a fourth node; the third input sub-circuit is configured to, during the input phase, under the control of the voltage at the fourth node, transmit a first voltage signal received at the first voltage signal terminal to the third node; The first voltage signal is at a non-operating level; The second control sub-circuit is coupled to the second node, the third node, the first voltage signal terminal, the second voltage signal terminal, and the third clock signal terminal; the second control sub-circuit is configured to, during the holding phase, in response to a third clock signal received at the third clock signal terminal, transmit a second voltage signal received at the second voltage signal terminal to the third node, and transmit a first voltage signal received at the first voltage signal terminal to the second node; The second voltage signal is the operating level; The second output sub-circuit is coupled to the third voltage signal terminal, the third node, and the cascaded signal output terminal; the second output sub-circuit is configured to, during the holding phase, under the control of the voltage at the third node, transmit the third voltage signal received at the third voltage signal terminal to the cascaded signal output terminal; the third voltage signal is at a non-operating level.

4. The shift register according to claim 3, wherein, The second control sub-circuit includes: A primary control subcircuit is coupled to the third node, the second voltage signal terminal, and the third clock signal terminal; the primary control subcircuit is configured to, during the holding phase, in response to the third clock signal received at the third clock signal terminal, transmit the second voltage signal received at the second voltage signal terminal to the third node; the second voltage signal is at the operating level; A secondary control subcircuit is coupled to the second node, the third node, and the first voltage signal terminal; the secondary control subcircuit is configured to, during the holding phase, under the control of the second voltage signal at the third node, transmit the first voltage signal received at the first voltage signal terminal to the second node.

5. The shift register according to claim 4, wherein, The secondary control sub-circuit includes: A first sub-circuit is coupled to the third node, the first voltage signal terminal, and the fifth node; the first sub-circuit is configured to, during the output phase, cut off the first voltage signal terminal and the fifth node under the control of the voltage at the third node; the first sub-circuit includes a fourth transistor, the fourth transistor being a low-temperature polysilicon transistor. A second sub-circuit is coupled to the second node, the third node, and the fifth node; the second sub-circuit is configured to, during the output phase, turn off the fifth node and the second node under the control of the voltage at the third node; the second sub-circuit includes a fifth transistor, which is a low-temperature polysilicon transistor. The second control sub-circuit also includes: A three-level control subcircuit is coupled to the fifth node, the second node, and the second voltage signal terminal; the three-level control subcircuit is configured to, during the output phase, transmit the second voltage signal received at the second voltage signal terminal to the fifth node under the control of the voltage at the second node.

6. The shift register according to claim 4 or 5, wherein, The primary control sub-circuit includes: The sixth transistor has its first terminal connected to the second voltage signal terminal, its second terminal connected to the third node, and its control terminal connected to the third clock signal terminal.

7. The shift register according to any one of claims 4 to 6, wherein, The fourth node is connected to the signal input terminal, or the fourth node is connected to the first node, or the fourth node is connected to the fifth node.

8. The shift register according to claim 6 or 7, wherein, The first output sub-circuit includes a seventh transistor, the first terminal of which is connected to the second clock signal terminal, the second terminal of which is connected to the cascaded signal output terminal, and the control terminal of which is connected to the second node; The third input sub-circuit includes an eighth transistor, the first terminal of which is connected to the first voltage signal terminal, the second terminal of which is connected to the cascaded signal output terminal, and the control terminal of which is connected to the fourth node. The second output sub-circuit includes a ninth transistor, the first terminal of which is connected to the third voltage signal terminal, the second terminal of which is connected to the cascaded signal output terminal, and the control terminal of which is connected to the third node; The three-level control sub-circuit includes a tenth transistor, the first terminal of which is connected to the second voltage signal terminal, the second terminal of which is connected to the fifth node, and the control terminal of which is connected to the second node. The first storage sub-circuit further includes a first storage capacitor, the first plate of which is coupled to the second node, and the second plate of which is coupled to the cascaded signal output terminal.

9. A gate driving circuit, comprising: Multiple cascaded shift registers as described in any one of claims 1 to 8.

10. The gate driving circuit according to claim 9, wherein, The shift register is connected to the first clock signal terminal, the second clock signal terminal, and the third clock signal terminal; The gate driving circuit further includes: Multiple clock signal lines are divided into multiple groups. In the same group, in adjacent shift registers, the clock signal line connected to the second clock signal terminal in the previous shift register is the same as the clock signal line connected to the first clock signal terminal in the next shift register. The clock signal line connected to the third clock signal terminal in the previous shift register is the same as the clock signal line connected to the second clock signal terminal in the next shift register. The clock signal line connected to the first clock signal terminal in the previous shift register is different from the clock signal line connected to the third clock signal terminal in the next shift register. The clock signal lines connected to the same clock signal terminal in any two shift registers are different.

11. The gate drive circuit according to claim 9 or 10, further comprising: The first voltage signal line is connected to the first voltage signal terminal and the shift register; The second voltage signal line is connected to the third voltage signal terminal and the shift register; The width of the first voltage signal line is smaller than the width of the second voltage signal line.

12. The gate driving circuit according to claim 11, wherein, The line width of the first voltage signal line is 3μm to 10μm; and / or, the line width of the second voltage signal line is 10μm to 20μm.

13. The gate drive circuit according to claim 11 or 12, wherein, Along the second direction, a plurality of the shift registers are arranged at intervals; the shift registers include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The first voltage signal line extends along a second direction and along a first direction, and the first voltage signal line is located between the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the tenth transistor, and between the seventh transistor and the ninth transistor; The second voltage signal line extends along the second direction and along the first direction, and the second voltage signal line is located on the side away from the first voltage signal line between the seventh transistor and the ninth transistor; the second direction intersects the first direction.

14. The gate drive circuit according to claim 13, wherein, The shift register further includes a first storage capacitor; the first storage capacitor is located on the side away from the first voltage signal line between the seventh transistor and the ninth transistor, and the orthographic projection of the second voltage signal line on the reference plane overlaps with the orthographic projection of the first storage capacitor on the reference plane; along the first direction, the two ends of the first storage capacitor extend beyond the two ends of the second voltage signal line.

15. The gate drive circuit according to claim 13 or 14, wherein, The clock signal line extends along a second direction and is located on the side away from the first voltage signal line among the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the eighth transistor, and the tenth transistor. The gate driving circuit further includes: A third voltage signal line is connected to the second voltage signal terminal and the shift register. The third voltage signal line extends along the second direction and is located between the clock signal line and the shift register.

16. The gate drive circuit according to claim 15, wherein, The fourth and fifth transistors are located between the first, second, third, sixth, eighth, and tenth transistors and the first voltage signal line, along the second direction, with the fourth transistor located to one side of the fifth transistor; and / or, The third transistor and the sixth transistor are located between the first transistor, the second transistor, the fourth transistor, the fifth transistor, the eighth transistor, and the tenth transistor, and the third voltage signal line, along the second direction, with the third transistor located to one side of the sixth transistor.

17. The gate drive circuit according to claim 16, wherein, The eighth transistor is located between the fourth and fifth transistors, and between the third and sixth transistors, and is located on the side of the first, second, and tenth transistors away from the next-level shift register; the fourth transistor is located on the side of the fifth transistor away from the next-level shift register, and the ninth transistor is located on the side of the seventh transistor away from the next-level shift register; The gate driving circuit further includes: A first connection line is connected to the gate of the third transistor, the second terminal of the seventh transistor, and the first terminal of the next-stage first transistor; the first connection line is located on the side of the first transistor, the second transistor, the fourth transistor, the fifth transistor, and the tenth transistor near the next-stage shift register.

18. The gate drive circuit according to claim 17, wherein, Along the first direction, the channel portion of the first transistor is located on the side of the channel portion of the second transistor closer to the shift register of the previous stage; along the second direction, the channel portion of the first transistor is located on the side of the channel portion of the second transistor away from the first voltage signal line; the channel portion of the third transistor is located on the side of the channel portions of the first transistor and the channel portions of the second transistor away from the first voltage signal line.

19. A display device comprising a shift register as claimed in any one of claims 1 to 8, or a gate driving circuit as claimed in any one of claims 9 to 18.

20. A method for driving a shift register, used to drive the shift register described in any one of 1 to 8; a display frame cycle includes an input phase and an output phase; During the input phase, the first input sub-circuit responds to the first clock signal received at the first clock signal terminal and transmits the operating level received at the signal input terminal to the first node; The second input sub-circuit responds to the first clock signal received at the first clock signal terminal and transmits the working level at the first node to the second node. The first storage sub-circuit stores the operating level at the second node; Under the control of the working level at the second node, the first output sub-circuit transmits the non-working level received at the second clock signal terminal to the cascaded signal output terminal; In the output phase, the first input sub-circuit, in response to the first clock signal received at the first clock signal terminal, cuts off the signal input terminal and the first node, and the signal received at the signal input terminal is at a non-working level; the second input sub-circuit, in response to the first clock signal received at the first clock signal terminal, cuts off the first node and the second node. Under the control of the operating level at the second node, the first output sub-circuit transmits the operating level received at the second clock signal terminal to the cascaded signal output terminal; The first storage sub-circuit writes the difference between the working level and the non-working level received at the second clock signal terminal into the second node; Under the control of the operating level at the cascaded signal output terminal, the first control sub-circuit transmits the operating level received at the cascaded signal output terminal to the first node.

21. The register driving method according to claim 20, wherein, A display frame cycle also includes a hold phase, which is located after the output phase; During the input phase, under the control of the voltage of the fourth node, the third input sub-circuit transmits the first voltage signal received at the first voltage signal terminal to the third node. Under the control of the first voltage signal at the third node, the second output sub-circuit cuts off the third voltage signal terminal and the cascaded signal output terminal. The second control sub-circuit responds to the third clock signal received at the third clock signal terminal by controlling the third voltage signal terminal and the third node to be turned off, and under the control of the first voltage signal at the third node, the second control sub-circuit turns off the first voltage signal terminal and the second node. During the output phase, the second control sub-circuit responds to the third clock signal received at the third clock signal terminal by controlling the second voltage signal terminal and the third node to be turned off. Under the control of the first voltage signal at the third node, the second output sub-circuit turns off the third voltage signal terminal and the cascaded signal output terminal, and the second control sub-circuit turns off the first voltage signal terminal and the second node. During the holding phase, the second control sub-circuit responds to the third clock signal received at the third clock signal terminal by transmitting the second voltage signal received at the second voltage signal terminal to the third node, and transmits the first voltage signal received at the first voltage signal terminal to the second node. Under the control of the first voltage signal at the second node, the first output sub-circuit cuts off the second clock signal terminal and the cascaded signal output terminal; under the control of the second voltage signal at the third node, the second output sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the cascaded signal output terminal.

22. The register driving method according to claim 21, wherein, During the output phase, under the control of the second voltage signal at the third node, the first sub-circuit controls the second voltage signal terminal and the fifth node to be cut off, and the second sub-circuit controls the fifth node and the second node to be cut off; under the control of the voltage at the second node, the three-level control sub-circuit transmits the third voltage signal received at the third voltage signal terminal to the fifth node.

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