Encoding method, decoding method, communication apparatus, and communication system

Abstract

The present application relates to the technical field of communications, and discloses an encoding method, a decoding method, a communication apparatus, and a communication system. On the basis of the methods, performing a second lifting on a base matrix helps to improve error correction performance and decoding performance at short and medium code lengths. Since element value modification is further performed on a second base matrix having undergone a first lifting, flexible matrix design is achieved, and the orthogonality between rows of the base matrix can be enhanced, thereby further improving the error correction performance and the decoding performance.

Description

An encoding method, a decoding method, a communication device, and a communication system.

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202510113362.X, filed on January 23, 2025, with the State Intellectual Property Office of the People's Republic of China, entitled "An Encoding Method, Decoding Method, Communication Device and Communication System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a communication system. Background Technology

[0004] The short-code performance of current low-density parity-check (LDPC) codes is limited in certain scenarios and cannot meet business requirements. To address this, a secondary enhancement scheme has been proposed. This involves first enhancing the first basis matrix to obtain an enhanced second basis matrix, and then enhancing the second basis matrix again to obtain the parity-check matrix. The information bit sequence is then encoded based on the parity-check matrix. This secondary enhancement expands the size of the parity-check matrix, making LDPC codes suitable for encoding short to medium-length or long codes. These scenarios include enhanced mobile broadband (eMBB), high-throughput, peak rate, ultra-reliable and low-latency communication (URLLC), and massive machine-type communication (mMTC).

[0005] However, after the first boosting to obtain the second basis matrix, a short-cycle structure may appear when performing a second boosting on the second basis matrix, leading to a decrease in decoding performance. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, a communication device, and a communication system to improve decoding performance.

[0007] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: obtaining a second basis matrix based on a first basis matrix and a first boosting value; modifying the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix; wherein the elements in the first basis matrix correspond one-to-one with the submatrices in the second basis matrix; obtaining a parity check matrix based on the third basis matrix and a second boosting value; and performing LDPC channel coding on the information bit sequence based on the parity check matrix to obtain an encoded bit sequence.

[0008] Based on the above scheme, performing a second boost on the basis matrix helps improve error correction and decoding performance under short to medium code lengths. Since the element values ​​of the second basis matrix after the first boost are also modified, a flexible matrix design is achieved, which can improve the orthogonality between rows of the basis matrix, thereby further enhancing error correction and decoding performance.

[0009] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: receiving information to be decoded; obtaining a second basis matrix based on a first basis matrix and a first boost value; modifying the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix; wherein the elements in the first basis matrix correspond one-to-one with the submatrices in the second basis matrix; obtaining a parity check matrix based on the third basis matrix and a second boost value; and performing LDPC channel decoding on the information to be decoded based on the parity check matrix to obtain an information bit sequence.

[0010] Based on the above scheme, performing a second boost on the basis matrix helps improve error correction and decoding performance under short to medium code lengths. Since the element values ​​of the second basis matrix after the first boost are also modified, a flexible matrix design is achieved, which can improve the orthogonality between rows of the basis matrix, thereby further enhancing error correction and decoding performance.

[0011] Based on the first or second aspect mentioned above, the following possible implementation methods exist:

[0012] As one possible implementation, modifying the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix includes: performing one or more of a first operation, a second operation, a third operation, or a fourth operation on the at least one submatrix to obtain the third basis matrix; wherein the first operation is to increase the number of non-zero elements in the submatrix; the second operation is to reduce the number of non-zero elements in the submatrix to 1; the third operation is to perform row interleaving and / or column interleaving on the submatrix; and the fourth operation is to partially or completely set the non-zero elements in the same column of multiple submatrixes in the at least one submatrix to zero, the multiple submatrixes corresponding to the same column elements in the first basis matrix.

[0013] Based on the above scheme, the error correction performance of the parity check matrix can be improved.

[0014] As one possible implementation, the at least one submatrix includes a plurality of first submatrices, the plurality of first submatrices corresponding to a first target column of the first base matrix, and the column weight of the first target column is greater than a first threshold, and the operation corresponding to the plurality of first submatrices includes the second operation and / or the fourth operation.

[0015] Based on the above scheme, the error correction performance of the parity check matrix can be improved in scenarios with short code length or low code rate.

[0016] As one possible implementation, the first target column is the X column with the largest column weight in the first basis matrix, where X is equal to 1, 2, 3 or 4.

[0017] As one possible implementation, the first target column is a punched column of the first basis matrix, and the column weights of the punched columns of the third basis matrix are all less than the column weights of the corresponding punched columns in the first basis matrix.

[0018] As one possible implementation, the first target column is a column within a sub-region of the incremental redundancy region of the first base matrix, and the sub-region is located directly below the core verification region of the first base matrix.

[0019] Based on the above scheme, error correction performance at low bit rates can be improved.

[0020] As one possible implementation, the column weight of each column in the third base matrix corresponding to the plurality of first submatrices is less than the column weight of the first target column.

[0021] Based on the above scheme, the number of short loops under short code length can be reduced, which helps to improve error correction performance.

[0022] As one possible implementation, the at least one submatrix includes multiple second submatrixes, each of which corresponds to a second target column of the first base matrix, and the column weight of the second target column is less than a second threshold. The operation corresponding to the multiple second submatrixes includes the first operation.

[0023] Based on the above scheme, the density can be reduced without sacrificing the threshold performance of the second basis matrix.

[0024] As one possible implementation, the at least one submatrix includes multiple third submatrixes, each of which corresponds to a first target row of the first base matrix, and the row weight of the first target row is greater than a third threshold. The operation corresponding to the multiple third submatrixes includes the second operation.

[0025] Based on the above scheme, the density can be reduced without sacrificing the threshold performance of the second basis matrix.

[0026] As one possible implementation, the at least one submatrix includes multiple fourth submatrixes, each of which corresponds to a second target row of the first base matrix, and the row weight of the second target row is less than a fourth threshold. The operation corresponding to the multiple fourth submatrixes includes the first operation.

[0027] Based on the above scheme, the density can be reduced without sacrificing the threshold performance of the second basis matrix.

[0028] As one possible implementation, the at least one submatrix includes at least one fifth submatrix, the at least one fifth submatrix corresponds to the core verification region of the first basis matrix, and the operation corresponding to the at least one fifth submatrix includes the second operation and / or the third operation.

[0029] As one possible implementation, two of the at least one fifth submatrix correspond to the third target column in the core verification region of the first base matrix, and the column weight of the third target column is equal to 3. One of the two fifth submatrixes corresponds to the second operation, and the other of the two fifth submatrixes corresponds to the third operation.

[0030] As one possible implementation, the core verification region of this third basis matrix contains only one column with a weight of 3.

[0031] Based on the above scheme, error correction performance at low bit rates can be improved.

[0032] As one possible implementation, the at least one submatrix includes at least one sixth submatrix and at least one seventh submatrix, the at least one sixth submatrix each corresponding to the fourth target column of the first base matrix, the at least one seventh submatrix each corresponding to the fifth target column of the first base matrix, the column vector corresponding to the fourth target column is the same as the column vector corresponding to the fifth target column, and the operation corresponding to the at least one sixth submatrix and / or the at least one seventh submatrix includes the first operation.

[0033] As one possible implementation, the first operation is specifically: modifying the first zero element of the last row in the submatrix to a non-zero element; or, the first operation is specifically: modifying the first zero element of the first row in the submatrix to a non-zero element.

[0034] Based on the above solution, performance at low bitrates can be improved.

[0035] As one possible implementation, the first operation specifically involves modifying all zero elements in the submatrix to non-zero elements.

[0036] Based on the above solution, performance at low bitrates can be improved.

[0037] As one possible implementation, the first basis matrix includes a first element, which is a non-zero element and corresponds to a first translation value; the eighth submatrix in the second basis matrix corresponds to the first element, and the translation value corresponding to a non-zero element in the eighth submatrix is ​​the first translation value, while the translation values ​​corresponding to other non-zero elements in the eighth submatrix are different from the first translation value.

[0038] As one possible implementation, the translation values ​​corresponding to the other non-zero elements in the eighth submatrix satisfy a functional relationship with the first translation value.

[0039] As one possible implementation, the first basis matrix includes a first element, which is a non-zero element and corresponds to a first translation value; the eighth submatrix in the third basis matrix corresponds to the first element, and the translation values ​​corresponding to all non-zero elements in the eighth submatrix are different from the first translation value.

[0040] As one possible implementation, the translation values ​​corresponding to all non-zero elements in the eighth submatrix satisfy a functional relationship with the first translation value.

[0041] As one possible implementation, the functional relationship is one of the following:

[0042] Formula 1: SV i,j =P m,n +w;

[0043] Formula 2: SV i,j =mod(Pm,n +w,Zc);

[0044] Formula 3:

[0045] Formula 4:

[0046] Formula 5: SV i,j =mod(P m,n +w+t,2 s );

[0047] Formula 6:

[0048] Among them, SV i,j P represents the translation value corresponding to the non-zero element whose translation value is to be calculated within the eighth submatrix, and (i,j) represents the row and column numbers of the non-zero element whose translation value is to be calculated within the second base matrix. m,n This represents the first translation value, (m,n) represents the row and column numbers of the first element in the first base matrix, and mod represents the modulo operation. Indicates rounding down, Zc represents the second lift value, Zmax represents the maximum lift value within the lift value group containing the second lift value, w represents a preset fixed value, a value related to i, a value related to j, or a value related to both i and j, t is related to the row or column number of the non-zero element of the translation value to be calculated within the eighth submatrix, k represents the first lift value, and s represents the value satisfying 2. s The largest integer less than or equal to Zc.

[0049] Based on the above scheme, fewer short cycles are generated, which can improve the performance of the parity check matrix.

[0050] As one possible implementation, obtaining the second base matrix based on the first base matrix and the first boosting value includes: when the code length is less than or equal to a code length threshold and / or the code rate is less than or equal to a code rate threshold, then obtaining the second base matrix based on the first base matrix and the first boosting value.

[0051] Based on the above scheme, fewer short-circle structures are achieved with short code lengths, thus improving the performance of the parity check matrix.

[0052] Thirdly, embodiments of this application provide an encoding method, which can be executed by a first communication device. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: obtaining a first parity check matrix based on a third base matrix and a second boost value; and performing LDPC channel coding on the information bit sequence based on the first parity check matrix to obtain an encoded first bit sequence.

[0053] Based on the above scheme, since the third basis matrix is ​​pre-stored, there is no need to dynamically generate it, thus accelerating the encoding speed and improving communication capabilities. Furthermore, it exhibits fewer short-circuit structures with shorter code lengths, improving the performance of the parity-check matrix.

[0054] As one possible implementation method, it further includes: when the code length is greater than the code length threshold and / or the code rate is greater than the code rate threshold, obtaining a second parity check matrix based on the first base matrix and the third boosting value; and performing LDPC channel coding on the information bit sequence based on the second parity check matrix to obtain the encoded second bit sequence, wherein the third base matrix and the first base matrix satisfy the boosting relationship.

[0055] As one possible implementation method, when the code length is less than or equal to the code length threshold and / or the code rate is less than or equal to the code rate threshold, the first parity check matrix is ​​obtained based on the third base matrix and the second boost value.

[0056] As one possible implementation method, when the length of the information bit sequence is greater than or equal to the information length threshold, the first parity check matrix is ​​obtained based on the third base matrix and the second boost value.

[0057] As one possible implementation, the third basis matrix and the first basis matrix also satisfy one or more of the following:

[0058] The first element of the first basis matrix corresponds to the first submatrix in the third basis matrix, and the number of non-zero elements in the first submatrix is ​​greater than the fifth threshold.

[0059] The second element of the first basis matrix corresponds to the second submatrix in the third basis matrix, and the number of non-zero elements in the second submatrix is ​​equal to 1;

[0060] The third element of the first basis matrix corresponds to the third submatrix in the third basis matrix, and the fourth element of the first basis matrix corresponds to the fourth submatrix in the third basis matrix. The third element and the fourth element are in the same column, and all or some of the elements in the same column of the third submatrix and the fourth submatrix are zero.

[0061] The fifth element of the first basis matrix corresponds to the fifth submatrix in the third basis matrix, and the column weight of each column containing the fifth submatrix is ​​less than the column weight of the column containing the fifth element; or,

[0062] The sixth element of the first basis matrix corresponds to the sixth submatrix in the third basis matrix, and the row weight of each column of the sixth submatrix is ​​less than the column weight of the row of the fifth element.

[0063] Fourthly, embodiments of this application provide a decoding method, which can be executed by a second communication device. Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The method includes: receiving information to be decoded; obtaining a first parity check matrix based on a third base matrix and a second boost value; and performing LDPC channel decoding on the information to be decoded based on the first parity check matrix to obtain an information bit sequence.

[0064] Based on the above scheme, since the third basis matrix is ​​pre-stored, there is no need to dynamically generate it, thus accelerating the encoding speed and improving communication capabilities. Furthermore, it exhibits fewer short-circuit structures with shorter code lengths, improving the performance of the parity-check matrix.

[0065] As one possible implementation method, it further includes: when the code length is greater than the code length threshold and / or the code rate is greater than the code rate threshold, obtaining a second parity check matrix based on the first base matrix and the third boosting value; and performing LDPC channel decoding on the information bit sequence based on the second parity check matrix to obtain the information bit sequence, wherein the third base matrix and the first base matrix satisfy a boosting relationship.

[0066] As one possible implementation method, when the code length is less than or equal to the code length threshold and / or the code rate is less than or equal to the code rate threshold, the first parity check matrix is ​​obtained based on the third base matrix and the second boost value.

[0067] As one possible implementation method, when the length of the information bit sequence is greater than or equal to the information length threshold, the first parity check matrix is ​​obtained based on the third base matrix and the second boost value.

[0068] As one possible implementation, the third basis matrix and the first basis matrix also satisfy one or more of the following:

[0069] The first element of the first basis matrix corresponds to the first submatrix in the third basis matrix, and the number of non-zero elements in the first submatrix is ​​greater than the fifth threshold.

[0070] The second element of the first basis matrix corresponds to the second submatrix in the third basis matrix, and the number of non-zero elements in the second submatrix is ​​equal to 1;

[0071] The third element of the first basis matrix corresponds to the third submatrix in the third basis matrix, and the fourth element of the first basis matrix corresponds to the fourth submatrix in the third basis matrix. The third element and the fourth element are in the same column, and all or some of the elements in the same column of the third submatrix and the fourth submatrix are zero.

[0072] The fifth element of the first basis matrix corresponds to the fifth submatrix in the third basis matrix, and the column weight of each column containing the fifth submatrix is ​​less than the column weight of the column containing the fifth element; or,

[0073] The sixth element of the first basis matrix corresponds to the sixth submatrix in the third basis matrix, and the row weight of each column of the sixth submatrix is ​​less than the column weight of the row of the fifth element.

[0074] Fifthly, this application provides a communication device that performs the functions described in the first or third aspect above. For example, the communication device includes modules, units, or means corresponding to the operations described in the first or third aspect above. The functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0075] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit may correspond to the operations involved in the first or third aspect described above.

[0076] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions described in the first or third aspect above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first or third aspect above when the computer programs or instructions are executed.

[0077] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the first or third aspect described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first or third aspect described above.

[0078] In one possible design, the communication device includes a processing circuit and an interface circuit, wherein the processing circuit is used to communicate with other devices through the interface circuit and to perform the methods in any possible design or implementation of the first or third aspect described above.

[0079] Understandably, the processing circuitry in the fifth aspect can be one or more processors, or all or part of the circuitry within one or more processors used for processing or control functions. The processor can be a logic circuit, an integrated circuit, or a general-purpose processor implemented by reading software code stored in memory. Furthermore, the processors and memories in the fifth aspect can be one or more. The memory can be integrated with the processor or can be separate from the processor. In specific implementations, the memory can be integrated with the processor on the same chip or can be disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0080] Sixthly, this application provides a communication device that performs the functions described in the second or fourth aspect above. For example, the communication device includes modules, units, or means corresponding to the operations described in the second or fourth aspect above. The functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0081] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit may correspond to the operations involved in the second or fourth aspect described above.

[0082] In one possible design, the communication device includes a processor that may be coupled to a memory. The memory may store necessary computer programs or instructions for implementing the functions described in the second or fourth aspect above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the second or fourth aspect above, when executed.

[0083] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the second or fourth aspect described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the second or fourth aspect described above.

[0084] In one possible design, the communication device includes a processing circuit and an interface circuit, wherein the processing circuit is used to communicate with other devices through the interface circuit and to perform the methods in any possible design or implementation of the second or fourth aspect described above.

[0085] Understandably, the processing circuitry in the sixth aspect can be one or more processors, or all or part of the circuitry within one or more processors used for processing or control functions. The processor can be a logic circuit, an integrated circuit, or a general-purpose processor implemented by reading software code stored in memory. Furthermore, the processor and memory in the sixth aspect can be one or more. The memory can be integrated with the processor or can be separately configured. In specific implementations, the memory can be integrated with the processor on the same chip or can be configured on different chips. This application does not limit the type of memory or the configuration of the memory and processor.

[0086] In a seventh aspect, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to execute the method described in the first aspect and any implementation thereof, and the second communication device is used to execute the method described in the second aspect and any implementation thereof.

[0087] Eighthly, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the third aspect and any implementation of the third aspect, and the second communication device is used to perform the method described in the fourth aspect and any implementation of the fourth aspect.

[0088] Ninthly, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs of the first to fourth aspects described above is executed.

[0089] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0090] In a tenth aspect, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to fourth aspects described above to be performed.

[0091] In one aspect, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any of the possible designs in the first to fourth aspects described above are executed. Attached Figure Description

[0092] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0093] Figure 2 is a schematic diagram of a processing flow of information source and information sink provided in an embodiment of this application;

[0094] Figure 3 is a schematic diagram of a 4*4 cyclic shift matrix provided in an embodiment of this application;

[0095] Figure 4 is an example diagram of the base matrix in the LDPC code provided in the embodiments of this application;

[0096] Figure 5 is an example diagram of the verification matrix provided in an embodiment of this application;

[0097] Figure 6 shows the region division method of the base matrix provided in the embodiment of this application;

[0098] Figure 7 is a schematic diagram of the matrix regions corresponding to different code rates provided in the embodiments of this application;

[0099] Figure 8 is a schematic diagram of the high bit rate region of BG1 provided in the embodiment of this application;

[0100] Figure 9 is a schematic diagram of the high bit rate region of BG1 provided in the embodiment of this application;

[0101] Figure 10 is a flowchart illustrating the encoding method provided in an embodiment of this application;

[0102] Figure 11 is an example diagram showing the relationship between the first basis matrix and the second basis matrix;

[0103] Figure 12(a) is an example diagram of performing the second operation on the second basis matrix;

[0104] Figure 12(b) is an example diagram of performing the second operation on the second basis matrix;

[0105] Figure 12(c) is an example diagram of performing the second and third operations on the second basis matrix;

[0106] Figure 12(d) is an example diagram of performing the first operation on the second basis matrix;

[0107] Figure 13 is a flowchart illustrating the decoding method provided in an embodiment of this application;

[0108] Figure 14 is a schematic diagram of the simulation results under a specific example provided in this application;

[0109] Figure 15 is a flowchart illustrating the encoding method provided in an embodiment of this application;

[0110] Figure 16 is a flowchart illustrating the decoding method provided in an embodiment of this application;

[0111] Figure 17 is an exemplary block diagram of a communication device provided in an embodiment of this application;

[0112] Figure 18 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0113] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0114] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5th generation (5G) mobile communication systems (such as New Radio (NR) systems), Future Communication Systems, or other similar communication systems, without limitation. This application describes the communication system shown in Figure 1 as an example. When applying the technical solution of this application to other communication systems, the devices, components, modules, etc. in the embodiment can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0115] Figure 1 is a schematic diagram of the architecture of the communication system applied in the embodiments of this application. As shown in Figure 1, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as 110a and 110b in Figure 1, and may also include at least one terminal device, such as 120a-120j in Figure 1. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop computer, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in Figure 1 are 120a, 120e, 120f and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can access micro-station 110b, connect to laptop 120g and printer 120h. Mobile phone 120j can control drone 120i.

[0116] (1) Network equipment

[0117] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device within a radio access network (RAN) that provides wireless communication functionality to terminal devices; this is called a RAN device. The RAN can be an access network in 3GPP, such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0118] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0119] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and media access control layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or equipment form used in the network equipment.

[0120] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0121] (2) Terminal equipment

[0122] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. They can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, on-board units (OBUs) or telematics boxes (T-BOXs), etc.), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0123] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0124] Network devices and terminal devices can be fixed-location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on airplanes, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices. Furthermore, terminal devices and network devices can be hardware devices, software functions running on dedicated hardware, or software functions running on general-purpose hardware, such as virtualization functions instantiated on a platform (e.g., a cloud platform), or entities comprising dedicated or general-purpose hardware devices and software functions. This application does not limit the specific form of the terminal devices and network devices.

[0125] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device. That is, 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal device functions.

[0126] Network devices and terminal devices, network devices and network devices, and terminal devices and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0127] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0128] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0129] (1) Channel coding and channel decoding

[0130] Figure 2 illustrates a processing flow diagram for the source and sink. As shown in Figure 2, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source encoding, and then performs channel encoding on the bit sequence to be encoded to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0131] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0132] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, which not only have good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure.

[0133] (2) Modulation and demodulation

[0134] Referring to Figure 2, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and obtain the symbol sequence to be decoded by demodulation.

[0135] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the reverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0136] (3) Information bit sequence

[0137] An information bit sequence refers to a sequence of multiple information bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is: 10101100101. In this embodiment, K represents the length of the information bit sequence.

[0138] (4) Code length

[0139] Code length refers to the length of the encoded bit sequence to be transmitted, obtained by encoding the information bit sequence. The code length is greater than or equal to the length of the information bit sequence. In this embodiment, E represents the code length.

[0140] (5) Bitrate

[0141] The code rate is the ratio of the length of the information bit sequence to the code length. In this embodiment, R represents the code rate, and R = K / E.

[0142] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, media access control (MAC) signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding scheme, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme.

[0143] (6) LDPC code

[0144] LDPC codes are a channel coding scheme very close to Shannon lines, characterized by high performance and low complexity. They have been adopted by 3GPP as the coding and decoding scheme for 5G communication data channels. Mainstream LDPC codes employ a quasi-cyclic (QC) structure, which avoids short-circuit structures and improves code distance by adjusting the shift of each block. Short-circuit structures refer to paths formed by nodes in the bipartite graph corresponding to the parity-check matrix. In other words, during iterative decoding, the information received by a bit is passed back to itself through a loop to check for potential errors, leading to a decrease in decoding performance.

[0145] LDPC codes can be represented using a basis matrix, where elements are either 0 or 1. Expanding the basis matrix by adding 1 elements results in a Zc*Zc cyclic shift matrix, and expanding by adding 0 elements results in a Zc*Zc zero matrix. This expansion yields a parity-check matrix (denoted by H), which can be used for encoding or decoding. Zc can be referred to as the lifting value, spread factor, spread coefficient, lifting size, etc. BG BG is an abbreviation for base graph. A basis matrix can also be represented by a base graph, and the two have a corresponding relationship.

[0146] For example, if the element in the i-th row and j-th column of the basis matrix has a value of 1 and corresponds to a shifting value (SV), it can be represented by P. i,j This represents the shift value corresponding to the i-th row and j-th column. A shift value can be used to calculate the corresponding number of cyclic shifts.

[0147] Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4*4 identity matrix to the right by 1, 2, 3, and 0 times respectively is shown in Figure 3. That is, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0148] The following example illustrates this. Figure 4 shows an example of the basis matrix in an LDPC code. This basis matrix is ​​a 3x3 matrix, and we assume Zc = 4, and P 0,0 The corresponding right circular shift count is 1, P 0,1 The corresponding right circular shift count is 2, P 1,0 The corresponding number of right circular shifts is 3, P 1,2 The corresponding number of right circular shifts is 3, P 2,2 The corresponding right circular shift count is 1. After expanding the base matrix, we can obtain the parity check matrix as shown in Figure 5.

[0149] Currently, the 3GPP TS 38.212 protocol defines various values ​​for the lift size (Zc) as shown in Table 1.

[0150] Table 1

[0151] Referring to Table 1, the values ​​of the lifting dimension Zc can be... Where j represents the j-th row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, a0, a1, a2, a3, a 4, a 5, a6 and a7 are 2, 3, 5, 7, 9, 11, 13, and 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4, respectively.

[0152] For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7, so the value of Zc can be 2*2. 0 ,2*2 1 ,2*2 2 ,2*2 3 ,2*2 4 ,2*2 5,2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0153] The protocol also stipulates that each row of Zc in Table 1 corresponds to a set of SV. When constructing the parity check matrix, the size of Zc is first determined, then the set of SV corresponding to that Zc is determined, and then the parity check matrix is ​​constructed based on Zc and SV.

[0154] Table 2 below shows a partial example of a set of SVs defined in the 3GPP TS 38.212 protocol.

[0155] Table 2

[0156] Table 2 shows the basis matrix H. BG The translation values ​​SV corresponding to the elements with a value of 1 in row 0 i,j The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the basis matrix H BG The cyclic shift value corresponding to each element with a value of 1 in row 0 can be obtained by taking the modulo of Zc using the corresponding translation value.

[0157] It should be noted that Table 2 only shows the translation values ​​corresponding to each element in row 0. In practice, it also includes the translation values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0158] Referring to Table 2, when Zc takes the values ​​2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, then the basis matrix H... BGThe cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H... BG The elements in the 0th row that have a value of 0 correspond to a zero matrix of size 4*4.

[0159] Similarly, for other values ​​of Zc, there are corresponding translation values ​​and cyclic shift counts, as detailed in Table 2.

[0160] Similarly, for the basis matrix H BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0161] In this embodiment, the lifting and translation operations of the LDPC code are described as follows: For a given lifting size Zc, from the basis matrix H BG Upgraded to the parity check matrix H, specifically, the basis matrix H BG t in i,j (where t) i,j =1) will be replaced with a Zc×Zc matrix I(P) i,j ), where I(P i,j ) is a cyclic shift of the identity matrix I of Zc×Zc by P i,j One (either left or right circular shift is possible) or circular shift P i,j A matrix of degree mod Zc, P i,j The translation value corresponding to the i-th row and j-th column; basis matrix H BG The zeros in H will be replaced with a Zc×Zc matrix of all zeros. It can be seen that the purpose of lifting is to improve the basis matrix H. BG To transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix.

[0162] (7) The basis matrix of LDPC code

[0163] For example, the basis matrix of an LDPC code can be either BG1 or BG2. Optionally, BG1 is a 46-row, 68-column matrix, and BG2 is a 42-row, 52-column matrix. BG1 and BG2 can have the matrix structure shown in Figure 6. In this matrix, the columns of region A correspond to information bits (or information digits, system bits), region B is a square matrix and its columns correspond to core parity bits (or core parity digits). The number of rows in regions A and B is determined by the highest code rate supported by the basis matrix. Region C is an all-zero matrix region, region D is the incremental redundancy part of the basis matrix and its rows correspond to parity check equations below the highest code rate, and region E is an identity matrix. The values ​​of the basis matrix are either 0 or 1; a value of 0 represents an empty element, and a value of 1 represents an edge in the basis graph, or an association between the parity check and a variable.

[0164] In this application, the maximum bit rate refers to the bit rate threshold (hereinafter referred to as the first threshold). This application does not limit the specific value of the first threshold, which can be set according to the actual situation.

[0165] As can be seen, the columns of the LDPC basis matrix consist of information columns and parity columns. The information columns correspond to the information bits and are the columns corresponding to region A. The parity columns correspond to the parity bits and are the columns corresponding to regions B and C, with the columns corresponding to region B being the core parity columns and the columns corresponding to region C being the extended parity columns. Alternatively, the core parity columns are the parity columns in region B with a column weight greater than 1, and the extended parity columns are the remaining parity columns excluding the core parity columns.

[0166] The core rows of the LDPC basis matrix correspond to the core check columns. In other words, the core rows are the rows corresponding to high bitrate regions, or regions A, B, or C.

[0167] The core columns of the LDPC basis matrix can include all information columns and all core check columns. In other words, the core columns are the columns corresponding to high bitrate regions, or the columns corresponding to regions A and B.

[0168] The kernel matrix of the LDPC base matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high bitrate region of the LDPC base matrix, or a matrix composed of regions A and B. The bitrate corresponding to the high bitrate region is equal to a preset first threshold value.

[0169] To improve the bit rate, LDPC encoding supports puncturing. For example, referring to Figure 6, the first X columns of the matrices BG1 and BG2 are punctured columns, such as X equals 2, 3, etc. In terms of matrix characteristics, the column weight of punctured columns is relatively large, where column weight refers to the number of non-zero elements in a column; in terms of transmission characteristics, the bits corresponding to the punctured columns are not transmitted, and the receiver does not need to pay attention to the received information of this part. Its log-likelihood ratio is set to 0, and it is recovered through decoding.

[0170] It should be noted that BG1 and BG2 can be designed according to the lowest bitrate. When different bitrates need to be supported, the upper left portion of BG1 or BG2 can be used. Figure 7 is a schematic diagram of the matrix regions corresponding to different bitrates. This matrix can be BG1, BG2, or other types of base matrices. This matrix includes a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region corresponds to regions A and B in Figure 6, and is also called the core region. The all-zero region corresponds to region C in Figure 6, the incremental redundancy region corresponds to region D in Figure 6, and the raptor-like region corresponds to region E in Figure 6. Region E corresponds to the parity bits below the highest bitrate extension. In this context, regions B and E are both verification regions. Region B is defined as the core verification region, and its features can be the non-lower triangular coding part (i.e., values ​​above the diagonal are not all 0) or the coding part with a column weight greater than 1. Region E is defined as the extended verification region, and its features can be the lower triangular coding part (i.e., values ​​above the diagonal are all 0) or a diagonal matrix.

[0171] As shown in Figure 7, the base matrix formed by the rows and columns of the high-bitrate region has the highest bitrate; therefore, this base matrix is ​​also called the highest bitrate matrix. If more rows and columns are selected from BG1 or BG2 than from the high-bitrate region to form the base matrix, the bitrate of this base matrix will be lower than the highest bitrate. Furthermore, as the number of rows and columns increases, the bitrate of the corresponding matrix region gradually decreases. Referring to Figure 7, the rows and columns of each dashed box region form a base matrix; as the size of the dashed box region increases, the bitrate of the corresponding base matrix gradually decreases.

[0172] Figure 8 is a schematic diagram of a possible high-bitrate region of BG1. The high-bitrate region of BG1 is a matrix region composed of region A and region B of BG1. Region A of BG1 is a 4x22 matrix used to carry data information (or information bits), and region B of BG1 is a 4x4 matrix used to carry parity information (or parity bits). When the first two columns are perforated, the bitrate supported by the high-bitrate region is 22 / (22+4-2) = 22 / 24 ≈ 0.917. To further improve the bitrate, columns in region A can be perforated simultaneously with columns in region B. For example, in the example in Figure 9, the first two columns of region A and the last column of region B are perforated, i.e., the number of perforated columns is 3. Then the bitrate supported by the high-bitrate region is 22 / (22+4-3) = 22 / 23 ≈ 0.956.

[0173] (8) LDPC code encoding

[0174] Let the sequence of bits to be encoded be denoted as vector c, and c = [c0, c1, c2, ..., c K-1 ] T Where K is the number of information bits to be encoded. The bit sequence after LDPC encoding is denoted as vector d, and d = [d0, d1, d2, ..., dn]. N-1 ] T For LDPC base map 1 (BG1 for short), N = 66Z c For LDPC base map 2 (BG2 for short), N = 50Z c Z c This indicates the increase value.

[0175] In this context, base graph 1 is also called base matrix 1, and base graph 2 is also called base matrix 2.

[0176] The process of encoding vector c using LDPC code to obtain vector d is as follows:

[0177] Step 1: Select Z c .

[0178] Step 2: Based on the first 2Z of vector c c Other than the bit values, determine the first K-2Z of vector d. c Each bit value, the process is as follows:

[0179] Here, NULL represents empty, that is, there is no corresponding content or information.

[0180] Step 3: Generate vectors And it satisfies:

[0181] The 0 on the right side of the above formula (1) represents a column vector with all elements being 0.

[0182] The parity-check matrix H can be obtained by converting the basis matrix H BG Replace each element in with Z c ×Z c The matrix obtained is as follows:

[0183] a) Basis matrix H BG Each element with a value of 0 is replaced with an element of size Z. c ×Z c A zero matrix;

[0184] b) Basis matrix H BG Each element with a value of 1 in the array is replaced with an element of size Z. c ×Z c The identity matrix, or replaced with a matrix of size Z. c ×Z c The cyclic shift matrix is ​​obtained from the identity matrix.

[0185] Where, when matrix H BG If it is BG1, then H BG It is a matrix with 46 rows and 68 columns. When matrix H... BG If it is BG2, then H BG It is a matrix with 42 rows and 52 columns.

[0186] Step 4: Based on vector w, obtain the other N+2Z of vector d. c -K bits, the process is as follows:

[0187] From the above four steps of LDPC encoding, it can be seen that:

[0188] First, the above formula (1) implies a one-to-one correspondence between an information bit and a column in the parity check matrix H, that is, c0 corresponds to the first column of H, c1 corresponds to the second column of H, and so on.

[0189] Second, the encoded bit sequence (i.e., vector d) does not contain the first 2^Z of the information bit sequence to be encoded (i.e., vector c). c The first 2Z bits, that is, the first 2Z bits of the information bit sequence to be encoded. c Each bit is punched. For example, the first 2Z bits of the information bit sequence to be encoded are... c Each bit corresponds to a column with a larger column weight in the parity check matrix.

[0190] (9) LDPC rate matching

[0191] Rate matching refers to the process of removing some bits from the encoded bit sequence or repeating the transmission of some bits to meet the actual transmission rate. The methods of rate matching are further explained below in three categories.

[0192] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0193] Shortening: This makes certain bit positions in the encoded bit sequence fixed values, so they do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are equivalent to being known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0194] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0195] The LDPC rate matching process is as follows:

[0196] The encoded bit sequence (i.e., vector d) is placed in a circular buffer, and a bit sequence of the corresponding length is read from it as the bit sequence after rate matching. This will be explained in detail below.

[0197] The encoded bit sequence d0, d1, d2, ..., d N-1 Write to a circular buffer, the length of which is denoted as N. cb .

[0198] The redundancy version (RV) currently being transmitted is denoted as rv. id , among which, rv id = 0, 1, 2 or 3.

[0199] The bit sequence after the output rate matching of the ring buffer is denoted as e = e0, e1, e2, ..., e E-1 The process of generating this sequence is as follows:

[0200] Where k0 represents the bit sequence e0, e1, e2, ..., e after rate matching from the ring buffer. E-1 The starting bit position, that is, starting from the bit indicated by k0, is used to read e0, e1, e2, ..., eE-1 The value of k0 is related to rv. id And related to the LDPC basis matrix. Table 3 below shows the relationship between the values ​​of k0 and rv. id And an example of the relationship between the LDPC basis matrices.

[0201] Table 3: Values ​​of k0 and rv id and the relationship between LDPC basis matrices

[0202] (10) Translation value matrix

[0203] A translation value matrix is ​​a matrix obtained by replacing each non-zero element in the base matrix with its corresponding translation value. It can be seen that the size of the translation value matrix is ​​the same as the size of the base matrix, and the elements in the translation value matrix are either zero or translation values.

[0204] The short-code performance of current LDPC codes is limited in certain scenarios and cannot meet business requirements. To address this, the industry has proposed a two-stage enhancement scheme. This involves first enhancing the first basis matrix to obtain an enhanced second basis matrix, and then enhancing the second basis matrix again to obtain a parity-check matrix (JCD). The information bit sequence is then encoded based on the JCD. This two-stage enhancement expands the size of the JCD, making LDPC codes suitable for encoding short to medium-length or long codes. These scenarios include, for example, eMBB, high-throughput, peak-rate, URLLC, and mMTC scenarios.

[0205] In this application, a short code is a code with a code length lower than a first length threshold, a medium-short code is a code with a code length greater than the first length threshold and less than a second length threshold, and a long code is a code with a code length greater than the second length threshold. A code with a code length equal to the first length threshold can be a short code or a medium-short code, and a code with a code length equal to the second length threshold can be a medium-short code or a long code. The first length threshold is less than the second length threshold. This application does not limit the specific values ​​of the first and second length thresholds. For example, the first length threshold is 1024, and the second length threshold is 4096.

[0206] However, after the first boosting to obtain the second basis matrix, a short-cycle structure may appear when performing a second boosting on the second basis matrix, leading to a decrease in decoding performance.

[0207] To address the aforementioned issues, this application provides corresponding solutions.

[0208] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the term "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. Similarly, the term "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0209] Figure 10 is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps:

[0210] Step 1001: The first communication device obtains the second basis matrix based on the first basis matrix and the first boost value.

[0211] For example, the first basis matrix may be BG1, BG2 or other basis matrices, and this application does not limit the specific form of the first basis matrix.

[0212] The first promotion value is an integer greater than 1, such as 2, 3, or other values.

[0213] Optionally, in step 1002, the first communication device modifies the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix, wherein the elements in the first basis matrix correspond one-to-one with the submatrixes in the second basis matrix.

[0214] That is, the value of an element at at least one position in the second basis matrix is ​​modified.

[0215] Figure 11 illustrates the relationship between the first and second basis matrices. In this example, the first basis matrix has a size of 4 rows and 10 columns, and its elements are either 0 or 1. The second basis matrix has a size of 16 rows and 40 columns. The second basis matrix consists of 4*10 submatrices, each of size 2*2. That is, the second basis matrix is ​​obtained by combining the first basis matrix with a first lift of size 2. Elements 0 in the first basis matrix are lifted to a 2*2 zero matrix, and elements 1 are lifted to a 2*2 identity matrix (i.e., a translation value of 0) or an anti-diagonal identity matrix (i.e., a translation value of 1). For example, the translation value can be determined based on preset rules or configuration.

[0216] This application modifies the submatrices of the second basis matrix on a per-submatrix basis. The method of modifying the submatrices of the second basis matrix can be found in the following description.

[0217] Step 1003: The first communication device obtains the parity check matrix based on one item of the second or third base matrix and the second lifting value.

[0218] This application does not limit the size of the second boost value.

[0219] That is, step 1003 can be: the first communication device obtains the parity check matrix based on the second base matrix and the second lifting value, or the first communication device obtains the parity check matrix based on the third base matrix and the second lifting value.

[0220] Step 1004: The first communication device performs LDPC channel coding on the information bit sequence according to the parity check matrix to obtain the encoded bit sequence.

[0221] After obtaining the encoded bit sequence, subsequent operations can be performed, such as interleaving, modulation, and transmission via an antenna.

[0222] Based on the above scheme, performing a second boost on the basis matrix helps improve error correction and decoding performance under short to medium code lengths. Since the element values ​​of the second basis matrix after the first boost are also modified, a flexible matrix design is achieved, which can improve the orthogonality between rows of the basis matrix, thereby further enhancing error correction and decoding performance.

[0223] For example, some specific implementation methods of step 1002 above are given below.

[0224] First, this application defines some operations that can be performed on submatrices of the second basis matrix, including one or more of the following:

[0225] The first operation refers to increasing the number of non-zero elements (i.e., element 1) in the submatrix. For example, it can add one non-zero element, or modify all zero elements in the submatrix to non-zero elements. Taking Figure 11 as an example, for the submatrix in the upper left corner, if the first operation is performed, one or two of its zero elements can be modified to non-zero elements.

[0226] The second operation refers to reducing the number of non-zero elements in a submatrix to one, meaning that after the second operation, a submatrix will have only one non-zero element. Taking Figure 11 as an example, for the submatrix in the upper left corner, if the second operation is performed, one of its non-zero elements can be changed to a zero element.

[0227] The third operation refers to row interleaving and / or column interleaving of the submatrix. Row interleaving refers to swapping two or more rows of the submatrix. Column interleaving refers to swapping two or more columns of the submatrix. Taking Figure 11 as an example, for the submatrix in the upper left corner, if the third operation is performed, the first row can be swapped with the second row, or the first column can be swapped with the second column.

[0228] The fourth operation refers to setting some or all non-zero elements in the same column of multiple submatrices within at least one submatrix to zero. These multiple submatrices correspond to elements in the same column of the first base matrix. Taking Figure 11 as an example, for the two submatrices in the upper left corner, if the fourth operation is performed, either both non-zero elements in the first column of these two submatrices can be set to zero, or only one of the non-zero elements can be set to zero. Alternatively, either both non-zero elements in the second column of these two submatrices can be set to zero, or only one of the non-zero elements can be set to zero.

[0229] Based on the above four operations, step 1002 can be: the first communication device performs one or more of the first, second, third, or fourth operations on at least one submatrix in the second base matrix to obtain the third base matrix.

[0230] The following section introduces some specific applications of the four operations mentioned above.

[0231] Method 1: The at least one submatrix in the second base matrix includes multiple first submatrixes, which correspond to the first target column of the first base matrix, and the column weight of the first target column is greater than a first threshold. The operation corresponding to the multiple first submatrixes includes a second operation and / or a fourth operation.

[0232] Here, the number of the first target column can be one or more.

[0233] For example, the first threshold here can be equal to 2, 3, or other values. The specific value of the first threshold is related to the size of the first base matrix and the column weights of each column.

[0234] For example, the first target column can be the X column with the largest column weight in the first base matrix, where X is equal to 1, 2, 3 or 4.

[0235] For example, the first target column is the punched column of the first base matrix, and after performing the second operation and / or the fourth operation on the above-mentioned multiple first submatrices, the column weight of the punched column of the third base matrix is ​​less than the column weight of the corresponding punched column in the first base matrix.

[0236] If the first basis matrix has multiple punched columns, then for each row of these punched columns, only one punched column is selected, and the second operation is performed on the submatrix of the second basis matrix corresponding to the selected punched column. Specifically, the second operation can be performed on the submatrix obtained by lifting the column with the largest column weight among the multiple punched columns of the first basis matrix. When two punched columns have the same column weight, they are executed in order of column number, and then the process moves to the next row. Figure 12(a) is an example of performing the second operation on the second basis matrix. This example is based on the example shown in Figure 11, and performs the second operation on a portion of the submatrixes in the second basis matrix. Specifically, in the example of Figure 11, it is assumed that the punched columns of the first basis matrix are the first column and the second column, where the first column and the second column correspond to the 8 submatrices on the left side of the second basis matrix. The following operations are performed sequentially on the second basis matrix: operation a, operation b, operation c, and operation d. Operations a, b, c, and d are specific examples of the second operation described above. In this operation, operation a sets the top-left element (1) of submatrix #1 of the second basis matrix to 0. Submatrix #1 corresponds to the element (1) in the first row and first column of the first basis matrix. Operation b sets the bottom-right element (1) of submatrix #2 of the second basis matrix to 0. Submatrix #2 corresponds to the element (1) in the third row and second column of the first basis matrix. Operation c sets the top-right element (1) of submatrix #3 of the second basis matrix to 0. Submatrix #3 corresponds to the element (1) in the second row and first column of the first basis matrix. Operation d sets the top-left element (1) of submatrix #4 of the second basis matrix to 0. Submatrix #4 corresponds to the element (1) in the fourth row and second column of the first basis matrix. Submatrixes #1, #2, #3, and #4 are specific examples of the first submatrix mentioned above.

[0237] For example, the first target column can also be a column within a sub-region of the incremental redundancy region (i.e., region D) of the first base matrix, and this sub-region is located directly below the core verification region (i.e., region B) of the first base matrix. After performing the second operation and / or the fourth operation on the aforementioned multiple first sub-matrices, the column weights of each column in the third base matrix corresponding to the multiple first sub-matrices are all less than the column weight of the first target column. For example, the second operation can be performed on the sub-matrix of the second base matrix corresponding to the column with the largest current weight in the first base matrix. When the column weights of the two columns of the first base matrix are the same, they can be performed in the order of column numbers, and then proceed to the next row. Figure 12(b) is an example diagram of performing the second operation on the second base matrix. In this example, the following operations are performed on the two sub-matrices of a sub-region of region D of the second base matrix, respectively, and this sub-region is located directly below region B of the second base matrix. Operations a and b here are specific examples of the aforementioned second operation. Operation a sets the element 1 in the lower right corner of sub-matrix #a of the second base matrix to 0. Operation b sets the bottom-left element (1) of submatrix #b of the second basis matrix to 0. Submatrix #a and submatrix #b here are specific examples of the first submatrix mentioned above.

[0238] Method 2: The first or more submatrices in the second base matrix include multiple second submatrices, each of which corresponds to a second target column of the first base matrix, and the column weight of the second target column is less than a second threshold. The operations corresponding to the multiple second submatrices include the first operation.

[0239] Here, the number of the second target column can be one or more.

[0240] For example, the second threshold here can be equal to 2, 3, or other values. The specific value of the second threshold is related to the size of the first basis matrix and the column weights of each column.

[0241] Method 3: The first or more submatrices in the second base matrix include multiple third submatrices, each of which corresponds to the first target row of the first base matrix, and the row weight of the first target row is greater than the third threshold. The operation corresponding to the multiple third submatrices includes the second operation.

[0242] Here, the number of the first target rows can be one or more.

[0243] For example, the third threshold here can be equal to 2, 3, or other values. The specific value of the third threshold is related to the size of the first base matrix and the row weight of each row.

[0244] Method 4: The first or more submatrices in the second base matrix include multiple fourth submatrices, each of which corresponds to the second target row of the first base matrix, and the row weight of the second target row is less than the fourth threshold. The operation corresponding to the multiple fourth submatrices includes the first operation.

[0245] Here, the number of the second target rows can be one or more.

[0246] For example, the fourth threshold here can be equal to 2, 3, or other values. The specific value of the fourth threshold is related to the size of the first base matrix and the row weight of each row.

[0247] Method 5: The at least one submatrix in the second base matrix includes at least one fifth submatrix, which corresponds to the core verification region (i.e., region B) of the first base matrix, and the operation corresponding to the at least one fifth submatrix includes a second operation and / or a third operation.

[0248] For example, two of the at least one fifth submatrixes in the first base matrix correspond to the third target column within the core verification region of the first base matrix, and the column weight of the third target column is equal to 3. One of the two fifth submatrixes corresponds to the second operation, such as prioritizing the retention of non-zero elements in the first column of the fifth submatrix while deleting non-zero elements in other columns. The other of the two fifth submatrixes corresponds to the third operation. For example, after this operation, there is only one column with a column weight of 3 within the core verification region of the third base matrix. Figure 12(c) is an example diagram of performing the second and third operations on the second base matrix. In this example, operations a and b are performed on two submatrixes within a subregion of the second base matrix, respectively. This subregion is located within the core verification region of the second base matrix and corresponds to the core verification region of the first base matrix. Operation a is a specific example of the second operation mentioned above, and operation b is a specific example of the third operation mentioned above. Operation a sets the element 1 in the lower right corner of submatrix #x of the second base matrix to 0. Operation b swaps the rows or columns of submatrix #y of the second base matrix. The submatrixes #x and #y here are specific examples of the fifth submatrix mentioned above.

[0249] Method 6: The at least one submatrix in the second base matrix includes at least one sixth submatrix and at least one seventh submatrix. The at least one sixth submatrix corresponds to the fourth target column of the first base matrix, and the at least one seventh submatrix corresponds to the fifth target column of the first base matrix. The column vector corresponding to the fourth target column is the same as the column vector corresponding to the fifth target column. The operation corresponding to the at least one sixth submatrix and / or the at least one seventh submatrix includes the first operation.

[0250] For example, both the fourth and fifth target columns are located in region A of the first base matrix. This can also be understood as follows: if there are two identical column vectors in region A of the first base matrix, then the first operation is performed on the submatrix obtained by lifting at least one of these columns.

[0251] For example, the first operation in method six could specifically be: modifying the first zero element of the last row of a submatrix (e.g., at least one sixth submatrix and / or at least one seventh submatrix) to a non-zero element.

[0252] For example, the first operation in method six can specifically be: modifying the first zero element (i.e. the first zero element found starting from the first column) of the starting row (i.e. the row with the smallest row number) of the submatrix (e.g., at least one sixth submatrix and / or at least one seventh submatrix) to a non-zero element.

[0253] For example, the first operation in method six could specifically be: modifying all zero elements in a submatrix (e.g., at least one sixth submatrix and / or at least one seventh submatrix) to non-zero elements.

[0254] For example, after the processing of method six above, the proportion of columns with a weight of 2 in region A of the third base matrix is ​​less than the proportion of columns with a weight of 2 in region A of the second base matrix.

[0255] Figure 12(d) is an example diagram of performing the first operation on the second basis matrix. In this example, operations m and n are performed on two submatrices within a subregion of the second basis matrix, respectively. This subregion is located in region A of the second basis matrix, and this subregion corresponds to region A of the first basis matrix. Operations m and n are specific examples of the first operation described above. Specifically, operation m sets the top-right element (0) of submatrix #p of the second basis matrix to 1. Operation b sets the bottom-left element (0) of submatrix #q of the second basis matrix to 1.

[0256] One implementation method is to record the operations to be performed on the second basis matrix in a fixed sequence and execute them at fixed intervals between two promotions. A specific implementation involves forming a triple (i, j, k) based on the indices i and j of the non-zero elements in the first basis matrix and the operation number k. After the first promotion, the corresponding submatrix is ​​found in sequence and the corresponding operation is executed. For example, (0, 0, 1) represents performing the operation corresponding to number "1" (i.e., the first, second, third, or fourth operation) on a submatrix of the second basis matrix, and this submatrix corresponds to the non-zero element at position (0, 0) of the first basis matrix.

[0257] Methods one and three above double the size of the base matrix and halve the boost value, which can reduce the number of short cycles and improve the performance of short codes.

[0258] Methods 2, 4, 5, and 6 above can improve the performance of low-bit-rate, high-reliability communication scenarios.

[0259] For any second or third basis matrix obtained based on the aforementioned implementation method, since it has been lifted relative to the first basis matrix, and the lift value is equal to the first lift value, the second or third basis matrix has more non-zero elements than the first basis matrix. For the first basis matrix, the protocol can define a translation value corresponding to each non-zero element; however, how to define the translation value corresponding to each non-zero element in the second or third basis matrix remains to be solved. Therefore, this application provides a corresponding solution.

[0260] The following explanation uses the definition of the translation values ​​corresponding to non-zero elements in the second basis matrix as an example. The definition method for the translation values ​​corresponding to non-zero elements in the third basis matrix is ​​similar.

[0261] Method 1: The first basis matrix includes a first element, which is a non-zero element and corresponds to a first translation value. The eighth submatrix in the second basis matrix corresponds to the first element. Then, the translation value corresponding to each non-zero element in the eighth submatrix is ​​the first translation value.

[0262] Taking Figure 11 as an example, assuming the first element is element 1 in the top left corner of the first basis matrix, then the eighth submatrix is ​​the top left submatrix of the second basis matrix. This eighth submatrix is ​​an identity matrix and contains two non-zero elements, thus requiring two translation values. Based on Method 1, the translation values ​​corresponding to the two non-zero elements of this eighth submatrix are the same as the translation value corresponding to element 1 in the top left corner of the first basis matrix, i.e., both are the first translation values.

[0263] Method 2: The first basis matrix includes a first element, which is non-zero and corresponds to a first translation value. The eighth submatrix in the second basis matrix corresponds to this first element. Therefore, the translation value corresponding to a non-zero element in the eighth submatrix is ​​the first translation value, and the translation values ​​corresponding to other non-zero elements in the eighth submatrix are all different from the first translation value. For example, the translation values ​​corresponding to other non-zero elements in the eighth submatrix may satisfy a functional relationship with the first translation value.

[0264] Taking Figure 11 as an example, assuming the first element is element 1 in the top left corner of the first basis matrix, then the eighth submatrix is ​​the top left submatrix of the second basis matrix. This eighth submatrix is ​​an identity matrix and contains two non-zero elements, thus requiring two translation values. Based on Method 2, the translation value corresponding to one of the two non-zero elements in this eighth submatrix is ​​the same as the translation value corresponding to element 1 in the top left corner of the first basis matrix, i.e., both are the first translation values. The translation value corresponding to the other non-zero element in this eighth submatrix is ​​different from the first translation value, i.e., it is not the first translation value.

[0265] Method 3: The first basis matrix includes a first element, which is a non-zero element and corresponds to a first translation value. The eighth submatrix in the third basis matrix corresponds to this first element. Therefore, the translation values ​​corresponding to all non-zero elements in the eighth submatrix are different from the first translation value. For example, the translation values ​​corresponding to all non-zero elements in the eighth submatrix satisfy a functional relationship with the first translation value.

[0266] Taking Figure 11 as an example, assuming the first element is element 1 in the top left corner of the first basis matrix, then the eighth submatrix is ​​the submatrix in the top left corner of the second basis matrix. This eighth submatrix is ​​an identity matrix and contains two non-zero elements, thus requiring two translation values. Based on method three, the translation values ​​corresponding to the two non-zero elements of this eighth submatrix are different from the translation value corresponding to element 1 in the top left corner of the first basis matrix; that is, neither is the first translation value.

[0267] For example, the above functional relationship can be one of the following:

[0268] Formula 1: SV i,j =P m,n +w.

[0269] Formula 2: SV i,j =mod(P m,n +w,Zc).

[0270] Formula 3:

[0271] Formula 4:

[0272] Formula 5: SV i,j =mod(P m,n +w+t,2 s ).

[0273] Formula 6:

[0274] Among them, SV i,jThe translation value is represented by (i,j) for the non-zero element whose translation value is to be calculated in the eighth submatrix, and (i,j) represents the row and column numbers of the non-zero element whose translation value is to be calculated in the second base matrix.

[0275] P m,n The first translation value is represented by (m,n), where (m,n) represents the row and column numbers of the first element within the first base matrix.

[0276] mod represents the modulo operation. This indicates rounding down. Specifically, the rounding down symbol in formulas 3, 4, and 6 above (i.e.,...) All of these can be replaced with the round-up symbol (i.e., ... ).

[0277] Zc represents the second boost value, and Zmax represents the maximum boost value within the boost value group containing the second boost value. Taking Table 1 as an example, if Zc = 4, then Zmax = 256; if Zc = 5, then Zmax = 320; if Zc = 88, then Zmax = 352, and so on.

[0278] w represents a preset fixed value, a value related to i (e.g., w = i), a value related to j (e.g., w = j), or a value related to both i and j (e.g., w = i + j).

[0279] The value t is related to the row or column number of the non-zero element whose translation value is to be calculated within the eighth submatrix, and k represents the first lifting value. If both row and column numbers in a submatrix start from 0, then t can be the row, column, row + 1, or column + 1 of the non-zero element whose translation value is to be calculated within the eighth submatrix. If both row and column numbers in a submatrix start from 1, then t can be the row or column number of the non-zero element whose translation value is to be calculated within the eighth submatrix. That is, t∈[0,k-1] or t∈[1,k]. For example, for formulas 3 and 4 above, then t∈[1,k]. For formulas 5 and 6 above, then t∈[0,k-1] or t∈[1,k].

[0280] s represents satisfying 2 s The largest integer less than or equal to Zc.

[0281] The following example illustrates the six formulas above. Let k = 2, w = 2, and P... 1,1 =250, Zc=4, Zmax=256, t=1 or 2.

[0282] For formula 1, SV 1,1 =250,SV 2,2 =252.

[0283] For formula 2, SV 1,1 =2,SV 2,2 =0.

[0284] For formula 3, SV 1,1 =3,SV 2,2 =7.

[0285] For formula 4, SV 1,1 =0,SV 2,2 =0.

[0286] For formula 5, SV 1,1 =2,SV 2,2 =0.

[0287] For formula 6, SV 1,1 =252,SV 2,2 =254.

[0288] Based on formulas 1 to 6 above, the translation values ​​corresponding to different non-zero elements in the submatrix obtained after lifting the same non-zero element in the first base matrix are not equal. This avoids loops between non-zero elements obtained after the first lifting, thus improving LDPC performance. Furthermore, all the above methods are based on simple calculations of the translation values ​​corresponding to the first base matrix to obtain the translation values ​​of the newly added positions after expansion. Therefore, there is no need to record a new table of translation values, which reduces storage space and complexity.

[0289] As one implementation method, step 1001 above can specifically be: when the code length is less than or equal to a code length threshold (e.g., 1500 or 2000) and / or the code rate is less than or equal to a code rate threshold (e.g., 10). -4 Or 10 -5 If the code length is less than or equal to a code length threshold and / or the code rate is less than or equal to a code rate threshold, the first communication device performs a two-stage boosting scheme and ultimately uses the third base matrix and the second boosting value to generate a parity check matrix (also called the first parity check matrix). Based on this parity check matrix, the information bit sequence is LDPC channel encoded to obtain the encoded bit sequence (also called the encoded first bit sequence). Correspondingly, if the code length is greater than the code length threshold and / or the code rate is greater than the code rate threshold, the first communication device may not perform a two-stage boosting operation, but instead directly generate a parity check matrix (also called the second parity check matrix) based on the first base matrix and the third boosting value, and perform LDPC channel encoding on the information bit sequence based on this parity check matrix to obtain the encoded bit sequence (also called the encoded second bit sequence).

[0290] In addition, when the code length is equal to the code length threshold and / or the code rate is equal to the code rate threshold, the first communication device may also generate a parity check matrix (also called a second parity check matrix) based on the first base matrix and the third boost value, and perform LDPC channel coding on the information bit sequence according to the parity check matrix to obtain the encoded bit sequence (also called the encoded second bit sequence).

[0291] As another implementation method, step 1001 above can specifically be as follows: When the length of the information bit sequence is greater than or equal to the information length threshold, the first communication device obtains the second base matrix based on the first base matrix and the first boosting value. That is, when the length of the information bit sequence is greater than or equal to the information length threshold, the first communication device performs a two-stage boosting scheme and finally uses the third base matrix and the second boosting value to generate a parity check matrix (also called the first parity check matrix). Based on this parity check matrix, the information bit sequence is LDPC channel coded to obtain the encoded bit sequence (also called the encoded first bit sequence). Correspondingly, when the length of the information bit sequence is less than the information length threshold, the first communication device may not perform the two-stage boosting operation, but directly generate a parity check matrix (also called the second parity check matrix) based on the first base matrix and the third boosting value, and perform LDPC channel coding on the information bit sequence based on this parity check matrix to obtain the encoded bit sequence (also called the encoded second bit sequence).

[0292] In addition, when the length of the information bit sequence is equal to the information length threshold, the first communication device can also generate a parity check matrix (also called a second parity check matrix) based on the first base matrix and the third boost value, and perform LDPC channel coding on the information bit sequence according to the parity check matrix to obtain the encoded bit sequence (also called the encoded second bit sequence).

[0293] In the above embodiments, the first sub-matrix, second sub-matrix, third sub-matrix, fourth sub-matrix, fifth sub-matrix, sixth sub-matrix, seventh sub-matrix, and eighth sub-matrix can be different matrices from each other or they can be the same matrices. This application does not limit this.

[0294] In the above embodiments, the first target column, the second target column, the third target column, and the fourth target column may be different columns from each other or they may be the same columns. This application does not limit this.

[0295] Figure 13 is a flowchart illustrating a decoding method provided in an embodiment of this application. This method corresponds to the decoding-side method of the embodiment shown in Figure 10. The method includes the following steps:

[0296] Step 1301: The second communication device receives the information to be decoded.

[0297] For example, the second communication device receives the information to be decoded from the first communication device, or receives the signal to be decoded from the first communication device and demodulates the signal to be decoded to obtain the information to be decoded.

[0298] Step 1302: The second communication device obtains the second basis matrix based on the first basis matrix and the first boost value.

[0299] Optionally, in step 1303, the second communication device modifies the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix. The elements in the first basis matrix correspond one-to-one with the submatrices in the second basis matrix.

[0300] Step 1304: The second communication device obtains the parity check matrix based on one item of the second or third base matrix and the second lift value.

[0301] The specific implementation methods of steps 1302 to 1304 above are the same as steps 1001 to 1003 in the embodiment of Figure 10 above, and can be referred to the foregoing description.

[0302] Step 1305: The second communication device performs LDPC channel decoding on the information to be decoded according to the parity check matrix to obtain the information bit sequence.

[0303] Based on the above scheme, performing a second boost on the basis matrix helps improve error correction and decoding performance under short to medium code lengths. Since the element values ​​of the second basis matrix after the first boost are also modified, a flexible matrix design is achieved, which can improve the orthogonality between rows of the basis matrix, thereby further enhancing error correction and decoding performance.

[0304] Figure 14 is a schematic diagram of simulation results under a specific example provided in this application. It shows a performance comparison of LDPC codes using a Min-sum decoding algorithm with a maximum number of iterations of 20. For details regarding the Min-sum decoding algorithm, please refer to existing technical solutions. The horizontal axis in the figure represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error ratio (BLER). The figure compares the existing technical solutions with the solution of this invention. In the first comparison, the selected code length N = 1408, and the number of bits in the information bit sequence K = 640. In the second comparison, the selected code length N = 640, and the number of bits in the information bit sequence K = 320. It can be seen that, for both comparisons, while achieving the same BLER, the solution of this invention has a smaller SNR, and therefore superior performance.

[0305] In the embodiments shown in Figures 10 and 13 above, the third basis matrix is ​​dynamically generated. That is, when encoding is required, the second basis matrix is ​​first generated based on the first basis matrix, and then adjusted to obtain the third basis matrix. In another possible implementation, the third basis matrix can also be pre-generated and stored, and retrieved from the storage space for use when encoding is required, or the second basis matrix can be retrieved from the storage space for use. The following encoding and decoding methods are also provided for this purpose.

[0306] Figure 15 is a flowchart illustrating an encoding method provided in an embodiment of this application. The method includes the following steps:

[0307] Step 1501: The first communication device obtains the first parity check matrix based on one item of the second or third base matrix and the second boost value.

[0308] The third basis matrix is ​​the same as the third basis matrix obtained in any of the implementation methods described in the embodiment of Figure 10 above.

[0309] The second basis matrix is ​​the same as the second basis matrix in the embodiment of Figure 10 above.

[0310] The first parity check matrix here is the same as the parity check matrix described in the embodiment of Figure 10 above.

[0311] That is, step 1501 can be: the first communication device obtains the first parity check matrix based on the second base matrix and the second boosting value, or the first communication device obtains the first parity check matrix based on the third base matrix and the second boosting value.

[0312] Optionally, when the code length is less than or equal to the code length threshold and / or the code rate is less than or equal to the code rate threshold, the first communication device obtains the first parity check matrix based on the second base matrix and the second boosting value; or, the first communication device obtains the first parity check matrix based on the third base matrix and the second boosting value.

[0313] Optionally, when the length of the information bit sequence is greater than or equal to the information length threshold, the first communication device obtains the first parity check matrix based on the second base matrix and the second boosting value; or, the first communication device obtains the first parity check matrix based on the third base matrix and the second boosting value.

[0314] Step 1502: The first communication device performs LDPC channel coding on the information bit sequence according to the first parity check matrix to obtain the encoded first bit sequence.

[0315] The main difference between the embodiment in Figure 15 and the embodiment in Figure 10 is that the second basis matrix or the third basis matrix in the embodiment in Figure 15 is pre-stored. When it is determined that the second basis matrix or the third basis matrix is ​​to be used, one item in the second basis matrix or the third basis matrix and the corresponding second lifting value are obtained, and a first check matrix is ​​generated based on one item in the second basis matrix or the third basis matrix and the second lifting value.

[0316] Based on the above scheme, since the third or second basis matrix is ​​pre-stored, there is no need to dynamically generate it, thus accelerating the encoding speed and improving communication capabilities. Furthermore, it exhibits fewer short-circuit structures with shorter code lengths, improving the performance of the parity-check matrix.

[0317] In one implementation, when the code length is greater than a code length threshold and / or the code rate is greater than a code rate threshold, or when the length of the information bit sequence is less than the information length threshold, the first communication device obtains a second parity check matrix based on a first base matrix and a third boosting value, and performs LDPC channel coding on the information bit sequence based on the second parity check matrix to obtain an encoded second bit sequence. The third base matrix satisfies a boosting relationship with the first base matrix. Here, the first base matrix is ​​the same as the first base matrix in the embodiment shown in Figure 10 above.

[0318] Furthermore, when the code length is equal to the code length threshold and / or the code rate is equal to the code rate threshold, or when the length of the information bit sequence is equal to the information length threshold, the first communication device can also obtain the second parity check matrix based on the first base matrix and the third boost value, and perform LDPC channel coding on the information bit sequence based on the second parity check matrix to obtain the encoded second bit sequence.

[0319] As can be seen, based on the above scheme, pre-storing the first and third basis matrices, or pre-storing the first and second basis matrices, and determining whether to use the first or third basis matrix (or the second basis matrix) to generate the parity check matrix according to the code length and / or code rate, can achieve the selection of a suitable basis matrix, which helps to improve LDPC performance.

[0320] Furthermore, the methods for defining translation values ​​in the second or third basis matrix in the embodiment of Figure 15, such as the relationships satisfied by the translation values, can refer to the various methods for translation values ​​in the embodiment of Figure 10 above, which will not be elaborated here.

[0321] Figure 16 is a flowchart illustrating a decoding method provided in an embodiment of this application. This method corresponds to the decoding-side method of the embodiment shown in Figure 15. The method includes the following steps:

[0322] Step 1601: The second communication device receives the information to be decoded.

[0323] For example, the second communication device receives the information to be decoded from the first communication device, or receives the signal to be decoded from the first communication device and demodulates the signal to be decoded to obtain the information to be decoded.

[0324] Step 1602: The second communication device obtains the first parity check matrix based on one item of the second or third base matrix and the second boost value.

[0325] The third basis matrix is ​​the same as the third basis matrix obtained in any of the implementation methods described in the embodiment of Figure 10 above.

[0326] The second basis matrix is ​​the same as the second basis matrix in the embodiment of Figure 10 above.

[0327] The first parity check matrix here is the same as the parity check matrix described in the embodiment of Figure 10 above.

[0328] That is, step 1602 can be: the second communication device obtains the first parity check matrix based on the second base matrix and the second boosting value, or the second communication device obtains the first parity check matrix based on the third base matrix and the second boosting value.

[0329] Optionally, step 1602 may be: when the code length is less than or equal to the code length threshold and / or the code rate is less than or equal to the code rate threshold, the second communication device obtains the first parity check matrix based on the second base matrix and the second boost value, or the second communication device obtains the first parity check matrix based on the third base matrix and the second boost value.

[0330] Optionally, step 1602 can be: when the length of the information bit sequence is greater than or equal to the information length threshold, the second communication device obtains the first parity check matrix based on the second base matrix and the second boosting value, or the second communication device obtains the first parity check matrix based on the third base matrix and the second boosting value.

[0331] Step 1603: The second communication device performs LDPC channel decoding on the information to be decoded according to the first parity check matrix to obtain the information bit sequence.

[0332] Based on the above scheme, since the third or second basis matrix is ​​pre-stored, there is no need to dynamically generate it, thus accelerating the encoding speed and improving communication capabilities. Furthermore, it exhibits fewer short-circuit structures with shorter code lengths, improving the performance of the parity-check matrix.

[0333] In one implementation, when the code length is greater than a code length threshold and / or the code rate is greater than a code rate threshold, the second communication device obtains a second parity check matrix based on the first base matrix and a third boosting value. Then, based on the second parity check matrix, the information bit sequence is subjected to LDPC channel decoding to obtain the information bit sequence, where the third base matrix and the first base matrix satisfy a boosting relationship. Here, the first base matrix is ​​the same as the first base matrix in the embodiment shown in Figure 10 above.

[0334] Furthermore, when the code length is equal to the code length threshold and / or the code rate is equal to the code rate threshold, the second communication device can also obtain the second parity check matrix based on the first base matrix and the third boost value, and perform LDPC channel decoding on the information bit sequence based on the second parity check matrix to obtain the information bit sequence.

[0335] As can be seen, based on the above scheme, pre-storing the first and third basis matrices, or pre-storing the first and second basis matrices, and determining whether to use the first or third basis matrix to generate the parity check matrix (or the second basis matrix) according to the code length and / or code rate, can achieve the selection of a suitable basis matrix, which helps to improve LDPC performance.

[0336] Furthermore, the methods for defining translation values ​​in the second or third basis matrix in the embodiment of Figure 16, such as the relationships satisfied by the translation values, can refer to the various methods for translation values ​​in the embodiment of Figure 10 above, which will not be elaborated here.

[0337] As another implementation method, when the length of the information bit sequence is less than the information length threshold, the second communication device obtains the second parity check matrix based on the first base matrix and the third boosting value. Then, based on the second parity check matrix, LDPC channel decoding is performed on the information bit sequence to obtain the information bit sequence, where the third base matrix and the first base matrix satisfy a boosting relationship.

[0338] Furthermore, when the length of the information bit sequence is equal to the information length threshold, the second communication device can also obtain the second parity check matrix based on the first base matrix and the third boost value, and perform LDPC channel decoding on the information bit sequence based on the second parity check matrix to obtain the information bit sequence.

[0339] In one implementation, the third basis matrix and the first basis matrix in the embodiment of Figure 15 or Figure 16 further satisfy one or more of the following:

[0340] (1) The first element of the first basis matrix corresponds to the first submatrix in the third basis matrix, and the number of non-zero elements in the first submatrix is ​​greater than the fifth threshold. This application does not limit the specific size of the fifth threshold.

[0341] (2) The second element of the first basis matrix corresponds to the second submatrix in the third basis matrix, and the number of non-zero elements in the second submatrix is ​​equal to 1.

[0342] (3) The third element of the first basis matrix corresponds to the third submatrix in the third basis matrix, and the fourth element of the first basis matrix corresponds to the fourth submatrix in the third basis matrix. The third element and the fourth element are in the same column, and all or some of the elements in the third submatrix and the fourth submatrix in the same column are zero.

[0343] (4) The fifth element of the first basis matrix corresponds to the fifth submatrix in the third basis matrix, and the column weight of each column containing the fifth submatrix is ​​less than the column weight of the column containing the fifth element.

[0344] (5) The sixth element of the first basis matrix corresponds to the sixth submatrix in the third basis matrix, and the row weight of each column of the sixth submatrix is ​​less than the column weight of the row of the fifth element.

[0345] For other relationships between the first and third basis matrices, please refer to the relevant descriptions in the embodiment of Figure 10 above.

[0346] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0347] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0348] In the case of using integrated units, FIG17 shows a possible exemplary block diagram of the device involved in the embodiments of this application. As shown in FIG17, the device 1700 may include a processing unit 1702 and a communication unit 1703. The processing unit 1702 is used to control and manage the operation of the device 1700. The communication unit 1703 is used to support communication between the device 1700 and other devices. Optionally, the communication unit 1703 is also called a transceiver unit, and may include a receiving unit and / or a sending unit, respectively used to perform receiving and sending operations. The device 1700 may also include a storage unit 1701 for storing the program code and / or data of the device 1700.

[0349] The device 1700 can be the first communication device in the above embodiments. The processing unit 1702 can support the device 1700 in performing the operations of the first communication device in the above method embodiments. Alternatively, the processing unit 1702 mainly performs the internal operations of the first communication device in the method embodiments, and the communication unit 1703 can support communication between the device 1700 and other devices.

[0350] For example, in one embodiment, the processing unit 1702 is configured to obtain a second basis matrix based on a first basis matrix and a first boosting value; modify the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix; wherein the elements in the first basis matrix correspond one-to-one with the submatrixes in the second basis matrix; obtain a parity check matrix based on the third basis matrix and a second boosting value; and perform LDPC channel coding on the information bit sequence based on the parity check matrix to obtain the encoded bit sequence.

[0351] Processing unit 1702 is configured to obtain a second basis matrix based on a first basis matrix and a first boosting value, including: obtaining the second basis matrix based on the first basis matrix and the first boosting value when the code length is less than or equal to a code length threshold and / or the code rate is less than or equal to a code rate threshold, and when the length of the information bit sequence is greater than or equal to an information length threshold.

[0352] For example, in another embodiment, processing unit 1702 is configured to obtain a first parity check matrix based on a third base matrix and a second boosting value, and to perform LDPC channel coding on the information bit sequence based on the first parity check matrix to obtain an encoded first bit sequence. Specifically, processing unit 1702 is configured to obtain the first parity check matrix based on a third base matrix and a second boosting value when the code length is less than or equal to a code length threshold and / or the code rate is less than or equal to a code rate threshold, and when the length of the information bit sequence is greater than or equal to an information length threshold.

[0353] Processing unit 1702 is further configured to obtain a second parity check matrix based on the first base matrix and the third boosting value; and to perform LDPC channel coding on the information bit sequence based on the second parity check matrix to obtain an encoded second bit sequence, wherein the third base matrix satisfies a boosting relationship with the first base matrix. For example, processing unit 1702 is further configured to obtain the second parity check matrix based on the first base matrix and the third boosting value when the code length is greater than the code length threshold and / or the code rate is greater than the code rate threshold, or when the length of the information bit sequence is less than or equal to the information length threshold.

[0354] The device 1700 can be the second communication device in the above embodiments. The processing unit 1702 can support the device 1700 in performing the operations of the second communication device in the above method embodiments. Alternatively, the processing unit 1702 mainly performs the internal operations of the second communication device in the method embodiments, and the communication unit 1703 can support communication between the device 1700 and other devices.

[0355] For example, in one embodiment, the communication unit 1703 is used to receive information to be decoded; the processing unit 1702 is used to obtain a second basis matrix based on a first basis matrix and a first boosting value; modify the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain a third basis matrix; wherein the elements in the first basis matrix correspond one-to-one with the submatrixes in the second basis matrix; obtain a parity check matrix based on the third basis matrix and a second boosting value; and perform LDPC channel decoding on the information to be decoded based on the parity check matrix to obtain an information bit sequence.

[0356] Processing unit 1702 is configured to obtain a second base matrix based on a first base matrix and a first boosting value, including: obtaining the second base matrix based on the first base matrix and the first boosting value when the code length is less than or equal to a code length threshold and / or the code rate is less than or equal to a code rate threshold, or when the length of the information bit sequence is greater than or equal to an information length threshold.

[0357] For example, in another embodiment, the communication unit 1703 is used to receive information to be decoded; the processing unit 1702 is used to obtain a first parity check matrix based on the third base matrix and the second boosting value, and to perform LDPC channel decoding on the information to be decoded based on the first parity check matrix to obtain an information bit sequence. For instance, the processing unit 1702 is used to obtain the first parity check matrix based on the third base matrix and the second boosting value when the code length is less than or equal to a code length threshold and / or the code rate is less than or equal to a code rate threshold, or when the length of the information bit sequence is greater than or equal to an information length threshold.

[0358] Processing unit 1702 is further configured to obtain a second parity check matrix based on the first base matrix and the third boosting value; and to perform LDPC channel decoding on the information bit sequence based on the second parity check matrix to obtain the information bit sequence, wherein the third base matrix and the first base matrix satisfy a boosting relationship. For example, processing unit 1702 is further configured to obtain the second parity check matrix based on the first base matrix and the third boosting value when the code length is greater than the code length threshold and / or the code rate is greater than the code rate threshold, and when the length of the information bit sequence is less than or equal to the information length threshold.

[0359] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0360] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0361] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0362] Based on the same technical concept, this application also provides a communication device for implementing the functions of the first or second communication device described above. As shown in FIG18, the device may be a communication equipment or a component of a communication equipment (e.g., a processor, chip, or chip system). The device includes a processor 1801 and a communication interface 1802, and optionally, a memory 1803. The memory 1803 may be independent of the processor 1801 or integrated into the processor 1801; no specific limitation is made. It is understood that FIG18 only shows the main components of the communication device. Furthermore, the communication device may further include input / output devices (not shown in the figure).

[0363] The processor 1801 is used to execute the program code stored in the memory 1803, specifically to perform the actions of the aforementioned processing unit 1702, which will not be described in detail here. The communication interface 1802 is specifically used to perform the actions of the aforementioned communication unit 1703, which will not be described in detail here.

[0364] Processor 1801 can be a CPU, a digital processing unit, etc. Processor 1801 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1802 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1801 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of the present invention do not limit the specific implementation of the above-mentioned devices.

[0365] The communication interface 1802 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1802 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Optionally, the communication interface 1802 can be an input / output interface or a chip pin.

[0366] Input / output devices, such as touchscreens, displays, and keyboards, are primarily used to receive user input data and output data to the user.

[0367] Memory 1803 is used to store programs executed by processor 1801. Memory 1803 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory 1803 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited to these.

[0368] When the communication device is a communication equipment or a chip system of a communication equipment, after the communication device is powered on, the processor 1801 can read the software program in the memory 1803, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1801 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit performs RF processing on the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1801. The processor 1801 converts the baseband signal into data and processes the data.

[0369] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0370] This application embodiment does not limit the specific connection medium between the communication interface 1802, processor 1801, and memory 1803. In Figure 18, the memory 1803, processor 1801, and communication interface 1802 are connected via a bus 1804, which is represented by a thick line in Figure 18. The connection methods between other components are only illustrative and not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 18, but this does not indicate that there is only one bus or one type of bus.

[0371] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0372] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0373] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0374] (3) Application-specific integrated circuit (ASIC), such as modem;

[0375] (4) Modules that can be embedded in other devices;

[0376] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0377] (6) Others, etc.

[0378] This application provides a chip (or chip system) including a processor for implementing any of the above-described method embodiments.

[0379] This application provides a computer-readable storage medium storing a computer program or instructions that, when executed, implement any of the above-described method embodiments.

[0380] This application provides a computer program product, which includes a computer program or instructions that, when executed, implement any of the above-described method embodiments.

[0381] This application provides a communication system, including a first communication device and a second communication device in the above method embodiments.

[0382] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0383] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0384] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0385] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0386] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0387] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. An encoding method, characterized in that, include: The second basis matrix is ​​obtained based on the first basis matrix and the first lifting value; The values ​​of elements at at least one position in at least one submatrix of the second basis matrix are modified to obtain a third basis matrix; wherein, the elements in the first basis matrix correspond one-to-one with the submatrixes in the second basis matrix; The parity-check matrix is ​​obtained based on the third base matrix and the second lifting value; Based on the parity check matrix, the information bit sequence is subjected to low-density parity check (LDPC) channel coding to obtain the encoded bit sequence.

2. A decoding method, characterized in that, include: Receive the information to be decoded; The second basis matrix is ​​obtained based on the first basis matrix and the first lifting value; The values ​​of elements at at least one position in at least one submatrix of the second basis matrix are modified to obtain a third basis matrix; wherein, the elements in the first basis matrix correspond one-to-one with the submatrixes in the second basis matrix; The parity-check matrix is ​​obtained based on the third base matrix and the second lifting value; Based on the parity check matrix, the information to be decoded is subjected to LDPC channel decoding to obtain the information bit sequence.

3. The method as described in claim 1 or 2, characterized in that, The step of modifying the element values ​​at at least one position of at least one submatrix in the second basis matrix to obtain the third basis matrix includes: Perform one or more of the first, second, third, or fourth operations on the at least one submatrix to obtain the third basis matrix; The first operation is to increase the number of non-zero elements in the submatrix; The second operation is to reduce the number of non-zero elements in the submatrix to one; The third operation is to perform row interleaving and / or column interleaving on the submatrix; The fourth operation is to set some or all of the non-zero elements in the same column of multiple submatrices in the at least one submatrix to zero, wherein the multiple submatrices correspond to the elements in the same column of the first base matrix.

4. The method as described in claim 3, characterized in that, The at least one submatrix includes a plurality of first submatrixes, the plurality of first submatrixes correspond to the first target column of the first base matrix, and the column weight of the first target column is greater than a first threshold. The operation corresponding to the plurality of first submatrixes includes the second operation and / or the fourth operation.

5. The method as described in claim 4, characterized in that, The first target column is the X column with the largest column weight in the first base matrix, where X is equal to 1, 2, 3 or 4.

6. The method of claim 4 or 5, wherein, The first target column is the punched column of the first basis matrix, and the column weights of the punched columns of the third basis matrix are all less than the column weights of the corresponding punched columns in the first basis matrix.

7. The method as described in claim 4, characterized in that, The first target column is a column within a sub-region of the incremental redundancy region of the first base matrix, and the sub-region is located directly below the core verification region of the first base matrix.

8. The method as described in claim 7, characterized in that, The column weight of each column in the third base matrix corresponding to the plurality of first submatrices is less than the column weight of the first target column.

9. The method according to any one of claims 3 to 8, characterized in that, The at least one submatrix includes a plurality of second submatrixes, each of which corresponds to a second target column of the first base matrix, and the column weight of the second target column is less than a second threshold. The operation corresponding to the plurality of second submatrixes includes the first operation.

10. The method according to any one of claims 3 to 9, characterized in that, The at least one submatrix includes multiple third submatrixes, each of which corresponds to a first target row of the first base matrix, and the row weight of the first target row is greater than a third threshold. The operation corresponding to the multiple third submatrixes includes the second operation.

11. The method according to any one of claims 3 to 10, characterized in that, The at least one submatrix includes multiple fourth submatrixes, each of which corresponds to a second target row of the first base matrix, and the row weight of the second target row is less than a fourth threshold. The operation corresponding to the multiple fourth submatrixes includes the first operation.

12. The method according to any one of claims 3 to 11, characterized in that, The at least one submatrix includes at least one fifth submatrix, the at least one fifth submatrix corresponds to the core verification region of the first base matrix, and the operation corresponding to the at least one fifth submatrix includes the second operation and / or the third operation.

13. The method as described in claim 12, characterized in that, Two of the at least one fifth submatrixes correspond to the third target column within the core verification region of the first base matrix, and the column weight of the third target column is equal to 3. One of the two fifth submatrixes corresponds to the second operation, and the other of the two fifth submatrixes corresponds to the third operation.

14. The method as described in claim 12 or 13, characterized in that, The core verification region of the third basis matrix has only one column with a weight of 3.

15. The method according to any one of claims 3 to 14, characterized in that, The at least one submatrix includes at least one sixth submatrix and at least one seventh submatrix. The at least one sixth submatrix corresponds to the fourth target column of the first base matrix, and the at least one seventh submatrix corresponds to the fifth target column of the first base matrix. The column vector corresponding to the fourth target column is the same as the column vector corresponding to the fifth target column. The operation corresponding to the at least one sixth submatrix and / or the at least one seventh submatrix includes the first operation.

16. The method as described in claim 15, characterized in that, The first operation specifically involves: modifying the first zero element in the last row of the submatrix to a non-zero element; or, The first operation specifically involves modifying the first zero element in the starting row of the submatrix to a non-zero element.

17. The method as described in claim 15, characterized in that, The first operation specifically involves modifying all zero elements in the submatrix to non-zero elements.

18. The method according to any one of claims 1 to 17, characterized in that, The first basis matrix includes a first element, which is a non-zero element and corresponds to a first translation value; The eighth submatrix in the second base matrix corresponds to the first element. The translation value corresponding to a non-zero element in the eighth submatrix is ​​the first translation value, and the translation values ​​corresponding to the other non-zero elements in the eighth submatrix are different from the first translation value.

19. The method of claim 18, wherein, The translation values ​​corresponding to the other non-zero elements in the eighth submatrix satisfy a functional relationship with the first translation value.

20. The method according to any one of claims 1 to 17, characterized in that, The first basis matrix includes a first element, which is a non-zero element and corresponds to a first translation value; The eighth submatrix in the third basis matrix corresponds to the first element, and the translation values ​​corresponding to all non-zero elements in the eighth submatrix are different from the first translation value.

21. The method of claim 20, wherein, The translation values ​​corresponding to all non-zero elements in the eighth submatrix satisfy a functional relationship with the first translation value.

22. The method of claim 19 or 21, wherein, The functional relationship is one of the following: Formula 1 : SV i,j = P m,n + w; Equation 2: SV i,j = mod(P m,n + w, Zc); Equation 3: Formula 4: Formula 5: SV i,j =mod(P m,n +w+t,2 s ); Equation 6: Among them, SV i,j P represents the translation value corresponding to the non-zero element to be calculated in the eighth submatrix, (i,j) represents the row and column numbers of the non-zero element to be calculated in the second base matrix, and P represents the translation value. m,n Let (m, n) represent the first translation value, (m, n) represent the row and column numbers of the first element in the first base matrix, and mod represents the modulo operation. Zc represents the second lift value, Zmax represents the maximum lift value within the lift value group containing the second lift value, w represents a preset fixed value, a value related to i, a value related to j, or a value related to both i and j, t is related to the row or column number of the non-zero element of the translation value to be calculated in the eighth submatrix, k represents the first lift value, and s represents the value that satisfies 2 s The largest integer less than or equal to Zc.

23. The method of any one of claims 1 to 22, wherein, The process of obtaining the second basis matrix based on the first basis matrix and the first lifting value includes: When the code length is less than or equal to the code length threshold and / or the code rate is less than or equal to the code rate threshold, the second base matrix is ​​obtained based on the first base matrix and the first boost value.

24. A communications device, characterized by It includes at least one processor, the at least one processor being configured to execute a computer program or instructions, such that the communication device implements the method as described in any one of claims 1, 3 to 23.

25. The communications apparatus of claim 24, wherein The communication device further includes a memory for storing the computer program or instructions.

26. A communications device, characterized by It includes at least one processor, the at least one processor being configured to execute a computer program or instructions, such that the communication device implements the method as described in any one of claims 2 to 23.

27. The communications apparatus of claim 26, wherein The communication device further includes a memory for storing the computer program or instructions.

28. A communication system, characterized by The communication system includes a first communication device and a second communication device; wherein the first communication device is used to perform the method as described in any one of claims 1, 3 to 23, and the second communication device is used to perform the method as described in any one of claims 2 to 23.

29. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when some or all of the computer program is executed by a computer, causes the method as described in any one of claims 1, 3 to 23 to be performed, or causes the method as described in any one of claims 2 to 23 to be performed.

30. A computer program product, characterised in that, When the computer reads and executes the computer program product, the method as described in any one of claims 1, 3 to 23 is performed, or the method as described in any one of claims 2 to 23 is performed.

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