Storage circuit, control method and apparatus, computing-in-memory system, and electronic device

Abstract

A storage circuit, a control method and apparatus, a computing-in-memory system, and an electronic device. The storage circuit comprises: a storage unit, which comprises a first transistor and a second transistor, wherein the first transistor comprises a first terminal, a second terminal and a first driving terminal, and the second transistor comprises a third terminal, a fourth terminal and a second driving terminal, the first driving terminal being connected to the fourth terminal, charges at the first driving terminal being used for storing data in the storage unit, and the second driving terminal being used for controlling a turned-on or turned-off state of the second transistor; and a first trace, a second trace and a third trace, wherein the first terminal is connected to the first trace, the second terminal is connected to the second trace, and the third terminal is connected to the third trace. Current signals of the second trace and the third trace are used for controlling the writing of data into the storage unit. By means of the storage circuit, the programming performance of the storage circuit can be improved.

Description

Storage circuits, control methods and devices, memory computing systems, and electronic devices Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a storage circuit, control method and apparatus, memory computing system, and electronic device. Background Technology

[0002] In traditional computing paradigms, such as the von Neumann architecture, storage and computation are physically separated. When processing data using this paradigm, data is frequently transferred between storage devices and computing devices, resulting in data transmission latency and energy consumption. With the development of technologies such as big data and artificial intelligence, the volume of data processing is growing rapidly, and the demand for data transmission is also increasing rapidly. The resulting transmission latency and energy consumption are becoming increasingly prominent, restricting the development of data processing capabilities and making traditional computing paradigms unable to meet the demands of processing power.

[0003] In-memory computing (IMC) architectures physically merge storage and computation. This physical fusion includes, for example, integrating storage and computation components close together through packaging processes; integrating processing circuitry within memory to achieve in-memory processing integration; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. IMC architectures can reduce data transfer requirements, lower transmission latency and energy consumption, and greatly improve data processing efficiency. However, IMC architectures still face challenges; for example, their programming performance still needs improvement. Summary of the Invention

[0004] This application provides a storage circuit, a control method and apparatus, a memory computing system, and an electronic device, with the aim of improving the programming performance of the storage circuit.

[0005] In a first aspect, a storage circuit is provided, comprising: a storage cell, the storage cell including: a first transistor and a second transistor, wherein the first transistor includes a first terminal, a second terminal and a first driving terminal, the second transistor includes a third terminal, a fourth terminal and a second driving terminal, wherein the first driving terminal and the fourth terminal are connected, the charge at the first driving terminal is used for storing data in the storage cell, and the second driving terminal is used to control the on or off state of the second transistor; a first trace, a second trace and a third trace, the first terminal being connected to the first trace, the second terminal being connected to the second trace, and the third terminal being connected to the third trace, wherein the current signals of the second trace and the third trace are used to control the writing of data in the storage cell, the first trace is used to couple an input signal, and the second trace is also used to output an output signal of the storage cell, the output signal being obtained based on the input signal and the data.

[0006] In conjunction with the first aspect, some implementations of the first aspect also include: a switching circuit connected between the second terminal and the third terminal.

[0007] In one possible implementation, the switching circuit is turned on when the storage circuit is in a programming or writing state, and turned off when the storage circuit is in a calculation or reading state.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the storage circuit includes a plurality of storage cells, the first terminals of the first transistors of the plurality of storage cells are connected to different first traces, the second terminals of the first transistors of the plurality of storage cells are connected to the same second trace, the third terminals of the second transistors of the plurality of storage cells are connected to the same third trace, and a switching circuit is connected between the second trace and the third trace.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the storage circuit includes a first operating state, wherein, in the first operating state, when data is written to the storage cell, the second transistor of the storage cell is turned on, the second trace and the third trace are connected, the second trace flows through a first current signal, the third trace flows through a second current signal, and the first current signal and the second current signal are used to control the writing of data in the storage cell.

[0010] In one possible implementation, the first working state can be either a programming state or a writing state.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the storage circuit further includes a second operating state, wherein in the second operating state, the second transistor of the storage cell is turned off, the second and third traces are not connected, the first terminal is coupled to the input signal, and the storage cell converts the input signal into an output signal based on weight data, wherein the data written to the storage cell includes weight data; or, in the second operating state, the second transistor of the storage cell is turned off, the second and third traces are not connected, the first terminal is coupled to the input signal, and the storage cell outputs data under the drive of the input signal.

[0012] In one possible implementation, the second working state can be either a computation state or a read state.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the first current signal and the second current signal originate from the same signal source.

[0014] In one possible implementation, the connection between the second and third traces is broken when the magnitude of the first current signal reaches the target current or the second current signal is less than or equal to the current threshold; or, the connection between the second and third traces is broken when the programming of the memory circuit is completed.

[0015] In one possible implementation, the aforementioned signal source can be a current source.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, a first trace is used to couple a first voltage, a second trace and a third trace are used to couple a second voltage, and a first current signal and a second current signal are generated under the drive of the first voltage and the second voltage.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the connection between the second and third traces is broken when the magnitude of the first current signal reaches the target current. This prevents changes to the programming result caused by continued power supply to the write transistor, thus avoiding impact on programming accuracy.

[0018] In conjunction with the first aspect, some implementations of the first aspect also include: a current sensing module for sensing a first current signal on the second trace, the sensed first current signal being used to control the connection state between the second trace and the third trace.

[0019] In conjunction with the first aspect, some implementations of the first aspect further include: an operational amplifier connected between the second terminal and the third terminal, wherein an input terminal of the operational amplifier is connected to the second terminal and an output terminal of the operational amplifier is connected to the third terminal.

[0020] In conjunction with the first aspect, in some implementations of the first aspect, the storage circuit includes a plurality of storage cells, the first terminals of the first transistors of the plurality of storage cells are connected to different first traces, the second terminals of the first transistors of the plurality of storage cells are connected to the same second trace, the third terminals of the second transistors of the plurality of storage cells are connected to the same third trace, and an operational amplifier is connected between the second trace and the third trace.

[0021] In conjunction with the first aspect, in some implementations of the first aspect, the operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The second input terminal is connected to a second terminal or a second trace, and the output terminal is connected to a third terminal or a third trace. The storage circuit includes a first operating state. In the first operating state, when writing data to the storage cell, the second transistor of the storage cell is turned on, the first input terminal of the operational amplifier is coupled to a reference voltage, the second input terminal is coupled to a first current signal, and the output terminal outputs a second current signal. The first current signal and the second current signal are used for writing data to the storage cell.

[0022] In conjunction with the first aspect, in some implementations of the first aspect, the storage circuit further includes a second operating state. In the second operating state, the second transistor of the storage cell is turned off, the first terminal is coupled to the input signal, and the storage cell converts the input signal into an output signal based on weight data, wherein the data written to the storage cell includes weight data; or, in the second operating state, the second transistor of the storage cell is turned off, the first terminal is coupled to the input signal, and the storage cell outputs data driven by the input signal.

[0023] In conjunction with the first aspect, in some implementations of the first aspect, the storage circuit includes multiple storage cells. The first terminals of the first transistors of the multiple storage cells are connected to different first traces, the second terminals of the first transistors of the multiple storage cells are connected to the same second trace, and the third terminals of the second transistors of the multiple storage cells are connected to the same third trace. The multiple storage cells include a first storage cell and a second storage cell. In a first operating state, when data is written to the first storage cell, the second transistor of the second storage cell is turned on and turned off. The first terminal of the first transistor of the first storage cell is coupled to a third voltage, and the first terminal of the first transistor of the second storage cell is coupled to a fourth voltage. The difference between the fourth voltage and the voltage on the second trace is less than or equal to a voltage threshold.

[0024] In one possible implementation, when multiple storage cells are arranged in an array, the first storage cell and the second storage cell can be storage cells on the same column. Furthermore, the first storage cell can be located in a programmed row, and the second storage cell can be located in a non-programmed row.

[0025] In conjunction with the first aspect, in some implementations of the first aspect, the storage unit further includes a capacitor connected to the first driving terminal and the fourth terminal.

[0026] Secondly, a control method is provided for controlling the data writing of the storage circuit in any implementation of the first aspect, the method comprising: controlling the second transistor of the storage cell of the storage circuit to be turned on; and controlling the data writing of the storage cell through the current signals of the second and third traces of the storage circuit.

[0027] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: providing a first current to the storage cell and controlling the second and third traces to be turned on, wherein the current signals of the second and third traces are obtained by shunting the first current.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the method further includes: providing a first voltage to a first trace and providing a second voltage to a second or third trace, wherein the first voltage and the second voltage are used to drive current signals flowing through the second and third traces.

[0029] In conjunction with the second aspect, in some implementations of the second aspect, the storage circuit further includes an operational amplifier connected between the second and third terminals of the storage cell of the storage circuit or between the second and third traces of the storage circuit. The method further includes: in the first operating state of the storage circuit, when writing data to the storage cell, controlling the second transistor of the storage cell to turn on, providing a reference voltage to the first input terminal of the operational amplifier, providing a first current signal to the second input terminal of the operational amplifier, and using the first current signal and the second current signal output by the output terminal of the operational amplifier for writing data to the storage cell.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, the storage circuit includes a first storage cell and a second storage cell. The first terminals of the first transistors of the first storage cell and the second storage cell are connected to different first traces. The second terminals of the first transistors of the first storage cell and the second storage cell are connected to the same second trace. The third terminals of the second transistors of the first storage cell and the second storage cell are connected to the same third trace. A switching circuit or operational amplifier is connected between the second trace and the third trace. The method further includes: in a first operating state of the storage circuit, when writing data to the first storage cell, controlling the second transistor of the first storage cell to be turned on and controlling the second transistor of the second storage cell to be turned off; providing a third voltage to the first terminal of the first transistor of the first storage cell and providing a fourth voltage to the first terminal of the first transistor of the second storage cell, wherein the difference between the fourth voltage and the voltage on the second trace is less than or equal to a voltage threshold.

[0031] Thirdly, a control device is provided for controlling the data writing of the storage circuit in any implementation of the first aspect. The control device includes a first control unit and a second control unit. The first control unit is used to control the second transistor of the first storage cell of the storage circuit to be turned on. The second control unit is used to control the writing of data of the storage cell of the storage circuit through the current signals of the second and third traces of the storage circuit.

[0032] In conjunction with the third aspect, in some implementations of the third aspect, the first control unit is also used to control the conduction between the second and third traces.

[0033] In conjunction with the third aspect, in some implementations of the third aspect, the second control unit is also used to provide a first current to the first storage unit, and the current signal of the third trace and the current signal of the second trace both come from the first current.

[0034] In conjunction with the third aspect, in some implementations of the third aspect, the second control unit is also used to provide a first voltage to the second or third trace, the first voltage being used to drive the current flowing through the second and third traces.

[0035] In conjunction with the third aspect, in some implementations of the third aspect, the first control unit is also used to control the first transistor of the second storage cell of the storage circuit to turn off, and the first terminals of the first transistors of the second storage cell and the first storage cell are connected to different first traces.

[0036] Fourthly, a control device is provided, including an interface circuit and at least one processing circuit, the interface circuit being used for signal connection with a storage circuit; and at least one processing unit being used for executing the control method of any one of the second aspects described above.

[0037] Fifthly, a control device is provided, configured to execute any of the control methods described in the second aspect above.

[0038] In a sixth aspect, a storage computing system is provided, comprising: a storage circuit according to any one of the first aspects described above; and a control device for controlling the writing of data stored in the storage circuit.

[0039] In a seventh aspect, an electronic device is provided, comprising any of the storage circuits described in the first aspect, or any of the control devices described in the third to fifth aspects.

[0040] Controlling data writing to memory cells via current signals from the second and third traces significantly improves the programming performance of the memory cells. Compared to controlling the data writing process through programming voltage, controlling the data writing process through current signals allows for adaptive adjustment of the read tube, ensuring the read current approaches the target current. This enables more precise control of data writing through current control, achieving the programming goal with fewer write controls (e.g., a single write control). It reduces the need for multiple write controls and read operations to correct the data, lowering the additional power consumption caused by multiple programming operations and improving programming efficiency. Furthermore, since the programming result is evaluated through the read current, which is related to the read or calculation result, controlling programming through current allows for more direct control of the programming result, resulting in higher accuracy of the written data. During calculations, the calculation results obtained based on the input signals and the written data also exhibit high accuracy. Attached Figure Description

[0041] Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application;

[0042] Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application;

[0043] Figure 3 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application;

[0044] Figure 4 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0045] Figure 5 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0046] Figure 6 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0047] Figure 7 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0048] Figure 8 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0049] Figure 9 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0050] Figure 10 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0051] Figure 11 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0052] Figure 12 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0053] Figure 13 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0054] Figure 14 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0055] Figure 15 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0056] Figure 16 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0057] Figure 17 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application;

[0058] Figure 18 shows a flowchart of a control method according to an exemplary embodiment of this application;

[0059] Figure 19 shows a schematic structural block diagram of a control device according to an exemplary embodiment of this application;

[0060] Figure 20 shows a schematic structural block diagram of another control device according to an exemplary embodiment of this application;

[0061] Figure 21 shows a schematic structural block diagram of an electronic device according to an exemplary embodiment of the present application. Detailed Implementation

[0062] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0063] To keep the drawings concise, the figures in this application only schematically show the parts related to the corresponding embodiments, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, some figures only schematically show some structures or components, and there may actually be more or fewer identical or similar structures or components.

[0064] In this application, unless otherwise expressly specified and limited, ordinal numbers, such as "first," "second," etc., are used only to distinguish the objects being described and should not be construed as indicating or implying the relative importance or order between the objects being described. Furthermore, ordinal numbers do not represent the quantity of the objects being described. "Multiple" includes two or more, and other quantifiers are similar. "Or," "and / or," etc., are used to describe the relationship between objects, indicating a non-exclusive inclusion. For example, "A and / or B," "A or B" can include: "A alone," "B alone," or "A and B." Similarly, "A, B, and / or C," "A, B, or C" can include: "A alone," "B alone," "C alone," "A and B," "A and C," "B and C," or "A, B, and C." Additionally, the " / " in this application is used to indicate an "or" relationship between preceding and following objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of "A and / or B" or "A or B" above. "One or more of A, B and C" or "at least one of A, B and C" has the same meaning as "A, B and / or C" or "A, B or C" above.

[0065] In this application, unless otherwise expressly specified and limited, "connection" includes direct or indirect connection between objects: connected objects may be directly connected through a medium (e.g., wires, traces, etc.), or indirectly connected through other components, or may be an internal connection. "Coupling" includes signal connection between objects, which may be achieved directly through a medium (e.g., wires, traces, etc.), or through other components. "Grounding" includes direct grounding or indirect grounding, with indirect grounding including, for example, grounding through other components.

[0066] In in-memory computing technology, storage and computation (or arithmetic) are physically integrated. This physical integration includes, for example, integrating storage and computation components close together through processes such as packaging; integrating processing circuits with processing capabilities within the memory to achieve integrated processing functions within the memory; or implementing computation through storage devices or storing data in computing devices to achieve tight integration of storage and computation. According to some embodiments, an in-memory computing system may include a storage circuit and a processing circuit (or control circuit); the storage circuit is used to store data; the processing circuit (or control circuit) is used to control the operation of the storage circuit, such as controlling the writing, reading, computation, or sensing of computation results. For example, the processing circuit can call up data stored in the storage circuit and perform computation based on the called data; or the processing circuit can control the computation of the storage circuit; or the processing circuit can be used to read or sense the computation results of the storage circuit and process the computation results. This application does not limit the type of memory, which may include, but is not limited to, non-volatile memory (NVM) or volatile memory (VM). Volatile memory may include, but is not limited to, static random access memory (SRAM); non-volatile memory may include, but is not limited to, flash memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric memory (FeRAM), or phase change memory (PCM).

[0067] For ease of understanding, Figure 1 shows a schematic diagram of an in-memory computing system according to an exemplary embodiment of this application. This in-memory computing system is described as an example of implementing in-memory computing using memory as a carrier.

[0068] As shown in Figure 1, the in-memory computing system 100 may include a storage circuit (or in-memory computing circuit) 110 and a control circuit 120. The storage circuit 110 can be used to store weight data (also called weights); the control circuit 120 can be used to control the operating state of the storage circuit 110. The operating states of the storage circuit 110 include, for example, a programming state and a calculation state. In the programming state, weight data is written into the storage circuit 110. In the calculation state, the storage circuit 110 receives an input signal Sin and converts the input signal Sin into an output signal Sout based on the weight data. The storage circuit 110 can store multiple weight data, which can be equivalent to at least one vector (or matrix). The storage circuit 110 can store weight data in units of storage cells, which can also be called storage units or storage structures. For example, the storage circuit 110 includes a storage cell array, which includes multiple storage cells arranged in an array.

[0069] Storage cells can utilize the conduction capabilities of semiconductor devices, such as electrical conductance or transconductance, to store weight data. For example, a storage cell can include a resistive storage device or a transistor storage device. For instance, weight data can be stored by controlling the conductance of a resistive storage device, or by controlling the transconductance of a transistor storage device. Alternatively, a storage cell can also utilize a capacitor to store weight data.

[0070] The storage circuit 110 can perform calculations in groups. For example, a storage cell array includes at least one storage cell group, and each storage cell group includes multiple storage cells that can store multiple weight data. These multiple weight data can be equivalent to a first data vector (or a first data matrix). In programming mode, the weight data is written into the storage cells, which is equivalent to writing the first data vector (or the first data matrix) into the storage cell group in the storage cell array. In calculation mode, the storage circuit 110 receives an input signal, and the conduction capability of the storage cells can change the input signal to obtain an output signal. Accumulating the output signals in the storage cell group can achieve an equivalent multiplication operation. The storage cell array includes one-dimensional arrays, two-dimensional arrays, or three-dimensional arrays, etc., and the storage cell group includes multiple storage cells located in the same row or column, or multiple storage cells located in multiple rows or columns, etc. These multiple storage cells can output their output signals collinearly.

[0071] In some possible embodiments, the in-memory computing system 100 may further include an input circuit 130 and an output circuit 140. The input circuit 130 can convert input data D1 into at least one input signal Sin and provide it to the storage circuit 110; the storage circuit 110 converts the received input signal Sin into an output signal Sout based on weight data; the output circuit 140 can convert the output signal Sout into output data D2 for output. The at least one input signal can be equivalent to a second data vector (or a second data matrix), and the output data D2 can be equivalent to the product of a first data vector (or a first data matrix) and a second data vector (or a second data matrix).

[0072] As an example, Figure 2 shows a schematic diagram of another in-memory computing system according to an exemplary embodiment of this application.

[0073] As shown in Figure 2, the in-memory computing system 200 includes one or more memory cell arrays 210. The memory cell array 210 includes multiple memory cells S. ij Where i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Storage cell S ij It can store weight data w ij When the memory cell array 210 is in the programming state, memory cell S ij The conduction capability can be controlled based on weight data to achieve a target state, thereby achieving the storage of weight data. When the storage cell array 210 is in the calculation state, it can be controlled through storage cell S. ij The input terminal IN is directed to the storage unit S ij Provide an input signal, such as an input voltage V i Storage unit S ij The output terminal OUT outputs its output signal, such as the output current. Multiple memory cells (e.g., S...) 1j -S mj The output terminals of the memory can be collinear. According to Kirchhoff's laws, the output signals of multiple memory cells are accumulated to obtain the output signal I. j Satisfy the following formula:

[0074] In some possible embodiments, the input data includes digital input signals, such as the input signal V of the storage cell array 210. iThe input signal may include an analog signal. The input circuit 230 may include, for example, a digital-to-analog converter (DAC) to convert the digital signal into an analog signal and provide it to the memory cell array 210. In some possible embodiments, the input signal to the memory cell array 210 may include a digital signal, which is represented by the signal's waveform characteristics, such as pulse width, amplitude, or area. The input circuit 230 may adjust the waveform of the signal based on the input data to obtain the input signal, which is then provided to the memory cell array 210.

[0075] In some possible embodiments, the output circuit 240 may include at least one conversion circuit for converting the output signal of the memory cell array 210 and outputting it to a subsequent circuit. This conversion may include one or more of the following: signal type conversion, signal magnitude conversion, such as current-to-voltage conversion, analog-to-digital conversion, amplification, etc. For example, the output circuit 240 may include a first conversion circuit 241 for performing a first conversion on the output signal of the memory cell array 210. For example, if the input signal includes a voltage signal and the output signal includes a current signal, the first conversion circuit 241 can convert the current signal into a voltage signal. Alternatively, the output circuit 240 may include a second conversion circuit 242. The second conversion may be implemented, for example, through a sampling circuit, and the signal converted by the first conversion circuit 241 can be further provided to the second conversion circuit 242 for the second conversion. For example, the first conversion circuit 241 may include a transimpedance amplifier (TIA) to convert the current signal into a voltage signal; the second conversion circuit 242 may include an analog-to-digital converter (ADC) to convert the analog signal into a digital signal and provide it to the subsequent circuit. For example, the output circuit may include a sense amplifier (SA), which can sense and amplify the signal obtained from the memory cell array 210 or the first conversion circuit 241. Additionally, in the example of Figure 2, the memory computing system 200 may also include a control circuit 220, which can be used to control the memory cells S in the memory cell array 210. ij The running state, such as the programming state and computation state mentioned above.

[0076] Figure 2 is only an example illustrating a connection method of memory cells in a memory cell array 210. Other connection methods can be used besides those shown in Figure 2. For example, the input terminals of memory cells can be connected collinearly by columns, and the output terminals of memory cells can be connected collinearly by rows. Furthermore, the input terminal of a memory cell may include the gate of a transistor memory device, or it may include the source or drain of a transistor memory device; this application does not limit this. This application also does not limit the type of memory cell; for example, the memory cell may include a floating gate transistor (FGT), a memristor, a magnetic tunnel junction (MTJ), or a phase-change structure. Furthermore, a memory cell may include multiple transistors; for example, a memory cell may include a first transistor and a second transistor, with the gate of the first transistor connected to the source or drain of the second transistor. The charge stored at the gate of the first transistor can be used to characterize weight data. Optionally, the gate may also be connected to a capacitor to increase the stability and duration of the stored charge. The gate or any equal-voltage node connected to it can be understood as the storage node (SN) of the memory cell. The first transistor can be called the read transistor (or simply read tube), and the second transistor can be used to control the writing of weight data; this second transistor can be called the write transistor (or simply write tube).

[0077] During programming, the write transistor can be turned on, and a programming voltage can be supplied to it to control the voltage at the memory node, thus enabling the writing of weight data. However, unavoidable process variations exist in the manufacturing of transistors in memory cells. When the programming voltage is applied to the memory cell, it may not achieve the expected programming target; for example, the expected read current may not be obtained. In-memory computing architectures have high precision requirements for writing weight data. During programming, corrections can be made through multiple write control and read operations. For example, the read current of the read transistor can be monitored to determine whether the programming result meets the programming target. If the target is not met, the programming voltage is adjusted based on the read current, and this process is repeated until the read current reaches the target. This programming method results in poor programming performance, such as longer programming time and higher power consumption. Based on this, embodiments of this application provide a storage circuit, control method and apparatus, memory computing system, and electronic device. By using current to control the writing of storage cells and achieving data writing through adaptive current adjustment, the impact of semiconductor device process deviations on programming can be reduced, supporting higher performance programming. For example, accurate weight data can be written with fewer programming operations (e.g., one programming operation), reducing the correction process of multiple write controls and multiple read operations, significantly saving programming time and power consumption, and improving programming efficiency.

[0078] Figure 3 shows a schematic diagram of a storage circuit according to an exemplary embodiment of this application. As shown in Figure 3, the storage circuit 300 includes a storage cell 310, a first trace 321, a second trace 322, and a third trace 323. The storage cell 310 includes a first transistor T1 and a second transistor T2. The first transistor T1 includes a first terminal T11, a second terminal T12, and a first driving terminal T13. The second transistor T2 includes a third terminal T21, a fourth terminal T22, and a second driving terminal T23.

[0079] The first driving terminal T13 and the fourth terminal T22 are connected, and the charge at the first driving terminal T13 is used for data storage in the storage unit 310. According to some embodiments, the first driving terminal T13 may be connected to a capacitor C, for example, the first driving terminal T13 may have parasitic capacitance. Alternatively, the storage unit 310 may also include a capacitor connected to the first driving terminal T13, the other end of which may be coupled to a voltage V. c Voltage V c The voltage can include positive voltage, negative voltage, or ground voltage; this application is not limited to any particular type. In other figures, an example is shown where a capacitor is connected to the first driving terminal, with the other end of the capacitor grounded. The second driving terminal T23 is used to control the on or off state of the second transistor T2; the first terminal T11 is connected to the first trace 321, the second terminal T12 is connected to the second trace 322, and the third terminal T21 is connected to the third trace 323. The current signal I1 of the second trace 322 and the current signal I2 of the third trace 323 are used to control the writing of data to the storage unit 310. The first trace 321 is used to couple the input signal Sin, and the second trace 322 is also used to output the output signal Sout of the storage unit 310. The output signal Sout is obtained based on the input signal Sin and the data stored in the storage unit 310. The process of obtaining the output signal Sout is as follows: The data stored in the storage unit 310 is related to the charge or voltage at the first driving terminal T13. The charge or voltage can change the conduction capability of the first transistor T1. When the first transistor T1 receives the input signal Sin, it can generate the output signal Sout at the second terminal T12 based on the conduction capability related to the stored data.

[0080] Based on the aforementioned storage circuit, controlling the data writing of the storage cell using the current signals of the second and third traces can significantly improve the programming performance of the storage cell. For example, the current signal I2 of the third trace 323 can change the charge at the storage node and can be used to implement data writing. The current signal I1 of the second trace can change with the charge at the storage node and can be used to verify the data writing. In static current programming, for example, when the current signals of the second and third traces originate from the same signal source, the current signal I2 of the third trace can also be used to verify the data writing.

[0081] For example, compared to controlling the data writing process of a memory cell through programming voltage, controlling the data writing process through a current signal allows for more precise control of the data writing process. This enables the read current of the read tube to tend towards the target current through adaptive adjustment, achieving the programming goal with fewer write controls (e.g., a single write control). This reduces the need for multiple write controls and read operations to correct the data, lowering the additional power consumption caused by multiple programming operations and improving programming efficiency. Furthermore, since the programming result is evaluated through the read current, and this read current is related to the read or calculation result, controlling the programming through current allows for more direct control of the programming result, resulting in higher accuracy of the written data. During the calculation process, the calculation results obtained based on the input signal and the written data also exhibit high accuracy.

[0082] The first transistor T1, also known as the read transistor, is used to control the reading of data stored in the memory cell or to perform calculations based on the stored data. The second transistor T2, also known as the write transistor, is used to control the writing of data stored in the memory cell. The second terminal T12 and the third terminal T21 can be directly connected, for example, through a trace, or through a switching circuit. When the second terminal T12 and the third terminal T21 are directly connected, the third trace 323 can be floated during calculation or read operations in the memory cell 310 to prevent interference with the calculation or read operations. When the second terminal T12 and the third terminal T21 are connected through a switching circuit, the connection between the second terminal T12 and the third terminal T21 can be turned on during programming or writing, and turned off during calculation or reading.

[0083] For example, Figure 4 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. As shown in Figure 4, the storage circuit 400 includes a storage cell 410, a first trace 421, a second trace 422, and a third trace 423. The storage cell 410 can be referred to the description of the storage cell 310 above, and will not be repeated here. According to some embodiments, the storage circuit 400 may further include a switching circuit 430 connected between the second terminal T12 and the third terminal T21, or in other words, connected between the second trace 422 and the third trace 423.

[0084] Based on the aforementioned storage circuit, by configuring a switching circuit, when the storage circuit is in programming or writing mode, the switching circuit is turned on, easily enabling the first current signal to coordinate with the second current signal to write data to the storage cell; when the storage circuit is in calculation or reading mode, the switching circuit is turned off. Thus, the connection or disconnection state between the second and third traces can be controlled in different operating states of the storage circuit; in programming or writing mode, the current signals of the second and third traces can be coordinated to control the writing of data to the storage cell; in calculation or reading mode, the interference of the third trace on the calculation or reading operation of the storage cell can be reduced. Moreover, compared to the scheme of directly connecting the second and third terminals, this scheme can reduce the impact of floating the third trace, such as the effect of additional parasitic capacitance, and optimize the speed and stability of signal transmission. Furthermore, this design can effectively suppress the leakage current of the second transistor, thereby improving the accuracy of the storage circuit's calculation or reading operation.

[0085] Optionally, when the storage unit 410 is in the programming or writing state, the switching circuit 430 can be in the conducting state, and when the storage unit 410 is in the calculation or reading state, the switching circuit 430 can be in the disconnected state.

[0086] This application does not limit the implementation of the switching circuit, as long as the connection between the second and third terminals can be turned on or off in different states. Optionally, the switching circuit 430 may include a semiconductor switching device, which is beneficial for process integration with the memory cell and has a high response speed and a small footprint.

[0087] According to some embodiments, the storage circuit 400 may include a plurality of storage cells 410. The first terminal T11 of the first transistor of the plurality of storage cells 410 is connected to different first traces 421. The second terminal T12 of the first transistor T1 may be connected to the same second trace 422. The third terminal T21 of the second transistor T2 of the plurality of storage cells 410 may be connected to the same third trace 423. The switching circuit 430 is connected between the second trace and the third trace.

[0088] Based on the aforementioned storage circuit, multiple storage cells can be connected to the same second trace and the same third trace, and the second trace and the third trace are connected through a switching circuit. This design not only allows the switching circuit to flexibly control the operating state of multiple storage cells, but also significantly saves hardware structure compared to connecting multiple storage cells to different traces, reducing redundant circuits and wiring requirements, thereby reducing the complexity, area, and power consumption of the storage circuit.

[0089] Optionally, multiple memory cells can be arranged in an array, and these memory cells can be memory cells in the same column or the same row. According to some embodiments, referring to FIG4, the second terminal T12 of the first transistor T1 of multiple memory cells 410 located in the same column can be connected to the same second trace 422, and the third terminal T21 of the second transistor T2 of multiple memory cells 410 located in the same column can be connected to the same third trace 423, and the switching circuit 430 is connected between the second trace and the third trace. In other embodiments, the second terminal of the first transistor of multiple memory cells located in the same row can be connected to the same second trace, and the third terminal of the second transistor of multiple memory cells located in the same row can be connected to the same third trace; in other embodiments, the second terminal of the first transistor of multiple memory cells located in the same column can be connected to the same second trace, and the third terminal of the second transistor of multiple memory cells located in the same row can be connected to the same third trace; or, the second terminal of the first transistor of multiple memory cells located in the same row can be connected to the same second trace, and the third terminal of the second transistor of multiple memory cells located in the same column can be connected to the same third trace. The switching circuit is connected between the second and third traces. This simplifies the routing complexity, reduces the number of switching circuits, and allows memory cells connected to the same second and third traces to reuse the same switching circuit.

[0090] For example, as shown in FIG4, the plurality of storage cells 410 include a first storage cell 411 and a second storage cell 412. The first terminal T11 of the first transistor T1 of the first storage cell 411 is connected to the first trace 4211, and the first terminal T11 of the first transistor T1 of the second storage cell 412 is connected to the first trace 4212. The second terminals T12 of the first transistor T1 of the first storage cell 411 and the second storage cell 412 are connected to the same second trace 422. The third terminal T21 of the second transistor T2 of the first storage cell 411 and the second storage cell 412 is connected to the same third trace 423. The switching circuit 430 is connected between the second trace 422 and the third trace 423.

[0091] Optionally, traces connected to the same transistor can be arranged in a cross pattern to reduce routing complexity and facilitate the selection of target transistors for writing, reading, or computational control. For example, the first trace 421 and the second trace 422 can be arranged in a cross pattern, with the first trace 421 acting as an input signal to control the memory cell involved in computation or reading. As another example, the memory circuit 400 also includes a fourth trace 424, with the third trace 423 and the fourth trace 424 arranged in a cross pattern. The fourth trace 424 controls the on / off state of the second transistor T2, while the third trace 423 and the second trace 422 control the writing of data.

[0092] The first trace 421, also known as an input line, connects to the first terminal of the first transistor T1 in the storage cell 410 and is used to receive input signals in the read or calculation state. The second trace 422, also known as an output line, connects to the second terminal of the first transistor T1 in the storage cell 410 and is used to output the read signal in the read state or the calculation result in the calculation state. The fourth trace 424, also known as a control line, controls the conduction of the second transistor T2 in the storage cell to be written, thereby selecting that storage cell for data writing. The third trace 423, also known as a programming line or write line, is used for data writing control or for programming control of the storage cell. The input signals coupled to different input lines can be the same or different. For example, input line 4211 connected to the first storage cell 411 is coupled to the first input signal Sin1, and input line 4212 connected to the second storage cell 412 is coupled to the second input signal Sin2. The first input signal Sin1 and the second input signal Sin2 can be the same or different. The weight data stored in the first storage unit 411 and the second storage unit 412 may be the same or different; and the output signal Sout1 of the first storage unit 411 and the output signal Sout2 of the second storage unit 412 may be the same or different.

[0093] According to some embodiments, the storage circuit 400 includes a first operating state, wherein, in the first operating state, when data is written to the storage cell 410, the second transistor T2 of the storage cell 410 is turned on, the switching circuit 430 is turned on, the second trace 422 flows through the first current signal I1, and the third trace 423 flows through the second current signal I2. The first current signal I1 and the second current signal I2 control the writing of data to the storage cell 410. The first current signal I1 can be understood as the read current of the first transistor T1, and the second current signal I2 is used to change the charge at the storage node to implement the writing of data to the storage cell 410.

[0094] For example, as shown in FIG4, the plurality of storage cells 410 may include a first storage cell 411 and a second storage cell 412. In the first operating state, when writing data to the first storage cell 411, the second transistor T2 of the first storage cell 411 can be turned on, and the switching circuit 430 can be turned on. At this time, the first current signal I1 and the second current signal I2 can be used to control the writing of data to the first storage cell 411. Similarly, when writing data to the second storage cell 412, the data writing method of the first storage cell 411 can be referred to.

[0095] Based on the aforementioned storage circuit, in the first operating state, the writing of data to the storage unit can be controlled using a first current signal and a second current signal. This significantly improves the efficiency of the storage unit during the programming process and ensures reliable data writing. Furthermore, it enhances the stability of the storage unit in practical applications, enabling it to perform well in both high-frequency write scenarios and complex computational tasks.

[0096] Optionally, the first working state may include a programming state or a write state.

[0097] According to some embodiments, the storage circuit 400 further includes a second operating state, wherein, in the second operating state, the second transistor T2 of the storage cell 410 is turned off, the second trace 422 and the third trace 423 are not connected, the first terminal T11 is coupled to the input signal, and the storage cell 410 converts the input signal into an output signal based on the weight data, wherein the data written to the storage cell 410 (or the data stored in the storage cell 410) includes the weight data; or, in the second operating state, the second transistor T2 of the storage cell 410 is turned off, the second trace 422 and the third trace 423 are not connected, the first terminal T11 is coupled to the input signal, and the storage cell 410 outputs data under the drive of the input signal.

[0098] Based on the aforementioned storage circuit, the storage unit can perform calculations based on the input signal and weight data in the second operating state, or read data under the drive of the input signal. Because the data has high precision during the writing process, this not only improves the accuracy of data storage but also enables the storage unit to have higher reliability when performing computational tasks, reducing the accumulation of errors caused by weight deviations, thereby further improving the computational reliability of the storage circuit when used in a storage-computing architecture.

[0099] Optionally, the second working state may include a calculation state or a reading state.

[0100] For example, as shown in FIG4, the plurality of storage cells 410 may include a first storage cell 411 and a second storage cell 412. In a second operating state, the second transistor T2 of the first storage cell 411 and the second storage cell 412 can be controlled to be turned off, and the switch circuit 430 can be controlled to be turned off. The first terminals of the first storage cell 411 and the second storage cell 412 are respectively coupled to the first input signal Sin1 and the second input signal Sin2. The first storage cell 411 and the second storage cell 412 can output the calculation result on the second trace 422 based on their respective input signals and their respective stored weight data. Alternatively, in the second operating state, the second transistor T2 of the first storage cell 411 or the second storage cell 412 can be controlled to be turned off, and the switch circuit 430 can be controlled to be turned off. The first terminal of the first storage cell 411 or the second storage cell 412 is coupled to the input signal, and the first storage cell 411 or the second storage cell 412 can output the stored data on the second trace 422 under the drive of the input signal.

[0101] According to some embodiments, static programming can be used to control the writing of data to the storage unit. For example, the first current signal I1 and the second current signal I2 originate from the same signal source.

[0102] Based on the aforementioned storage circuit, the write current (or programming current) can be split into current signals on the second and third traces. Using the same signal source makes it easier to control the write current, resulting in higher accuracy in writing the weighted data. For example, by connecting the second and third traces, the same signal source can be used to split the current on both traces. Furthermore, by utilizing the adaptive adjustment capability of the read transistor, the current signals on the second and third traces can be adaptively adjusted, causing the read current to tend towards the write current. This allows for more accurate control of data writing to the storage cell via the signal source, enabling the read current to reach the programming target with fewer write controls (e.g., a single write control). This reduces the need for multiple write controls and multiple read operations to correct the data, lowers the additional power consumption caused by multiple programming operations, and improves programming efficiency. Moreover, since the first and second current signals from the same signal source have the same signal characteristics (e.g., amplitude or frequency), this implementation method of programming using static current signals can reduce errors caused by differences in signal characteristics during programming. Furthermore, compared to using multiple signal sources to provide current signals, using the same signal source can reduce hardware implementation and maintenance costs.

[0103] Optionally, the signal source may include a current source, which may be connected to a second or third trace. The current source does not restrict the direction of current flow; for example, current may flow from the current source to the memory cell, or vice versa. When the current source is connected to the second trace, a selection circuit may be provided. This selection circuit, connected to the second trace, selects the signal on the second trace to be read during calculation or read operations and inputs it to the output circuit. During programming or write operations, the current source is selected, and the write current provided by the current source is supplied to the memory cell. This write current can be shunt between the second and third traces to control data writing. Alternatively, the signal source (e.g., a current source or a voltage source) may be connected to the third trace. Optionally, it may be connected to the third trace via an intermediate circuit such as a switching circuit.

[0104] According to some embodiments, the first current signal I1 increases during the data writing process, and the second current signal I2 decreases during the data writing process. The increase or decrease of the current signal can represent an increase or decrease in the current value independent of the current direction. For example, in the first operating state, the write current may include a first current component (first current signal I1) flowing through the first transistor T1 and a second current component (second current signal I2) flowing through the second transistor T2. The first and second current components adaptively change, causing the first current component flowing through the first transistor T1 to gradually increase and the second current component flowing through the second transistor T2 to gradually decrease. For example, in the initial stage of the first operating state, the first transistor T1 is not conducting or has a low conduction capability. When the first transistor T1 is not conducting or has a low conduction capability, the write current does not flow through the first transistor T1 or flows less through it, and flows entirely or mostly through the second transistor T2; the first current component is equal to zero or substantially equal to zero, and the second current component is equal to or substantially equal to the write current. The second current component can change the conduction capability of the first transistor T1 by changing the charge at the first drive terminal T13. As the charge at the first driving terminal T13 increases, the conduction capability of the first transistor T1 gradually increases; thus, the first current component gradually increases, and the second current component gradually decreases. When the first current component is equal to or substantially equal to the write current, or the second current component is equal to or substantially equal to zero, the weight data corresponding to the write current is written to the storage cell 410. In this way, through adaptive adjustment of the storage cell, the read current of the first transistor can approach the write current, achieving the target programming result. This achieves the effect of achieving the target programming result with fewer programming operations (e.g., one programming operation), reducing the need for correction processes in multiple programming operations, significantly saving programming time and power consumption, and improving programming efficiency. For example, the programming status of the weight data can be determined during the programming process using the first current signal I1 and / or the second current signal I2.

[0105] Based on the aforementioned storage circuit, the first current signal increases as data is written, while the second current signal decreases, and the write current remains constant throughout the data writing process. This programming method utilizing a static write current is called static current programming. In static current programming, the completion of programming for the current storage cell can be determined by whether the first current signal reaches the target current, or by setting a programming time to control the programming of the current storage cell. Static current programming not only reflects the real-time status of data writing but also effectively improves data writing efficiency, significantly saving programming time and power consumption, thus enhancing programming efficiency. The target current can be equal to or close to the write current.

[0106] According to some embodiments, the end of programming can be controlled based on the time it takes for the memory cell to reach stability, thereby stopping data writing. This stability time can be referred to as the programming time. For example, the programming time can be determined based on experiments, historical data evaluation, or transistor characteristics. This programming time can include the time consumed from the input of write current to the memory cell to the output of a stable read current. This time can include a certain redundancy so that memory cells with different process variations can all reach stable output within this time. From the start of receiving write current to the expiration of this time, the supply of write current to the currently programmed memory cell can be stopped, for example, by controlling the second transistor T2 of that memory cell to turn off. This eliminates the need for current detection and reduces the complexity of programming control.

[0107] In static current programming, since the write current remains constant, the programming result can remain stable when the first current signal reaches the target current. Therefore, whether the write current supply is stopped or not will not affect the programming result. When the first current signal reaches the target current, the second transistor T2 controlling the currently programmed memory cell is turned off and / or the write current supply is stopped to stop programming the memory cell and reduce programming power consumption; alternatively, programming of the memory cell can be stopped after a period of time.

[0108] According to some embodiments, the connection between the second and third traces is controlled to disconnect when the magnitude of the first current signal I1 reaches the target current or the second current signal I2 is less than or equal to a current threshold. Alternatively, the connection between the second and third traces is controlled to disconnect when programming the memory circuit is completed. Controlling the connection between the second and third traces when programming the memory circuit completes reduces the need for connection control between the second and third traces during programming of different memory cells. For example, when programming memory cells in different rows or columns, the connection between the second and third traces can be maintained until all memory cells in the connected row or column are programmed. This application does not limit the magnitude of the current threshold; the current threshold can be equal to or close to 0 and can be set according to a tolerable error range.

[0109] Based on the above storage circuit, when the magnitude of the first current signal reaches the target current or the second current signal is less than or equal to the current threshold, the data writing process can be terminated, so that the programming operation of the current storage unit can be completed quickly, so as to start the programming of other storage units as soon as possible, and further improve the programming efficiency.

[0110] Optionally, when the second trace and the third trace are connected by a switching circuit, the connection between the second trace and the third trace is broken by controlling the switching circuit to be in an open state.

[0111] According to some embodiments, dynamic programming can also be used to program the memory cell. Figure 5 shows a schematic diagram of another memory circuit according to an exemplary embodiment of this application. As shown in Figure 5, the memory circuit 500 includes a memory cell 510, a first trace 521, a second trace 522, a third trace 523, a fourth trace 524, and a switching circuit 530. The above parts can be referred to the description of the above embodiments, and will not be repeated here. The first trace 521 is used to couple voltage V1, and the second and third traces are used to couple voltage V2. A first current signal I1 and a second current signal I2 are generated under the drive of voltages V1 and V2. This application does not limit the magnitude of voltages V1 and V2, as long as a voltage drop can be generated between them, allowing current to be generated on the second trace 522 and the third trace 523 during programming. According to some embodiments, voltage V1 may include a higher potential voltage, such as voltage Vdd, and voltage V2 may include a lower potential voltage, such as voltage Vss. Alternatively, voltage V2 may include a higher potential voltage, such as voltage Vdd, and voltage V1 may include a lower potential voltage, such as voltage Vss. Voltage Vss may, for example, include ground voltage.

[0112] According to some embodiments, when the magnitude of the first current signal I1 reaches the target current, the connection between the second trace 522 and the third trace 523 is controlled to disconnect. This prevents changes to the programming result caused by continued power supply to the write transistor, thus avoiding impact on programming accuracy.

[0113] Referring to Figure 5, the storage circuit 500 may further include a current sensing module (or current sensing circuit) 540 for sensing the current signal on the second trace 522. This sensed current signal is used to control the connection state between the second trace 522 and the third trace 523. For example, when the first current signal I1 on the second trace 522 reaches the target current, the connection between the second trace 522 and the third trace 523 is controlled to open or close. This application does not limit the magnitude of the target current; the magnitude of the target current can be determined based on the weight data to be written. The magnitudes of the target currents for different storage cells can be the same or different.

[0114] The current sensing module 540 can also be used in a statically current-programmed memory circuit. When used in a statically current-programmed memory circuit, the current sensing module 540 can sense the current signal of the second trace 422 or the third trace 423. This sensed current signal is used to control the termination of programming for the memory cell. For example, when the first current signal I1 on the second trace 422 reaches the target current, the programming of the currently programmed memory cell is terminated; or, when the second current signal I2 on the third trace 423 is less than or equal to a current threshold, the programming of the currently programmed memory cell is terminated.

[0115] In static current programming, the target current can be close to or equal to the write current, i.e., the difference between the first current signal I1 and the write current is less than or equal to the allowable error value. Alternatively, the second current signal I2 can be equal to or close to 0; for example, the above current threshold can be determined based on the allowable error value. This application does not limit the magnitude of the write current, which can be determined based on the weight data to be written. The magnitudes of the write current for different memory cells can be the same or different.

[0116] According to some embodiments, the second trace 522 may be connected to a selection circuit that selects whether to provide voltage V2 to the second trace 522 during programming and connects the second trace 522 to an output circuit during calculation or reading.

[0117] According to some embodiments, when programming a target memory cell, the write transistors of non-programmed memory cells sharing the second and third traces with the target memory cell can be turned off. Optionally, a voltage equal to or close to the voltage on the second trace can be coupled to the first terminal of the non-programmed memory cell, thereby suppressing the influence of leakage current of the non-programmed memory cell on programming and further improving programming accuracy. For example, as shown in FIG4 or FIG5, a plurality of memory cells include a first memory cell 411 / 511 and a second memory cell 412 / 512. In a first operating state, when data is written to the first memory cell 411 / 511, the second transistor T2 of the first memory cell 411 / 511 is turned on, and the second transistor T2 of the second memory cell 412 / 512 is turned off. The first terminal T11 of the first transistor T1 of the first storage cell 411 / 511 is coupled to voltage V3, and the first terminal T11 of the first transistor T1 of the second storage cell 412 / 512 is coupled to voltage V4; and the difference between voltage V4 and the voltage on the second trace 422 / 522 is less than or equal to a voltage threshold, that is, voltage V4 is the same as or close to the voltage on the second trace 422 / 522. This embodiment does not limit the size of the voltage threshold; the voltage threshold can be equal to or close to 0, and can be set according to the tolerable error range. Through the above method, when data is written to the first storage cell, the leakage current of the second storage cell can be suppressed, thereby reducing the impact of leakage current on the writing process of the first storage cell, and further improving the programming accuracy of the first storage cell. For the storage cell 411 / 511 to be programmed, voltage V3 is, for example, the voltage V1 mentioned above, and voltage V4 can be the same as or close to the voltage V2 mentioned above.

[0118] This application does not limit the magnitudes of voltages V3 and V4. For example, voltage V3 may include a higher potential voltage, such as voltage Vdd, or a lower potential voltage, such as voltage Vss. A potential difference exists between voltage V3 and voltage V2 on the second trace, causing a bias voltage across the first transistor T1 of the first memory cell, enabling the first transistor T1 to operate and change the read current according to the charge change at the first drive terminal T13 until a target current is reached. No potential difference or a small potential difference exists between voltage V4 and voltage V2 on the second trace, causing the first transistor T1 to operate in a non-operating state, suppressing leakage current in the second memory cell.

[0119] This application does not limit the supply method of voltage V4 and voltage V2 of the second trace, as long as the relationship between voltage V4 and voltage V2 is satisfied.

[0120] For example, in one possible implementation, the voltage on the second trace can be estimated, and based on the estimated voltage, a power supply can be designed to provide the same or similar voltage to power the first terminal T11 of the first transistor T1 of the unprogrammed memory cell.

[0121] For example, in another possible implementation, the voltage V2 on the second trace can be estimated, and a power supply can be designed based on the estimated voltage. This power supply can power the first terminal T11 of the first transistor T1 of the unprogrammed memory cell. The supply voltage of this power supply can also be used as a reference voltage Vref to clamp the voltage of the second trace to the reference voltage Vref. The embodiments of this application do not limit the structure of the clamping circuit, as long as voltage clamping can be achieved.

[0122] For example, in another possible implementation, the voltage V2 of the second trace can be used to power the first terminal T11 of the first transistor T1 of the unprogrammed memory cell. For instance, a buffer circuit is provided, with the voltage V2 of the second trace input to the buffer circuit. After passing through the buffer circuit, the output voltage V4 is supplied to the first terminal T11 of the first transistor T1 of the unprogrammed memory cell. This design can stably transmit the voltage signal to the first transistor T1 of the unprogrammed memory cell. The circuit is stable and simple in structure, meeting the requirements of performance and cost.

[0123] In other embodiments, other circuit structures, such as unidirectional conduction circuits or switching circuits, can be set in the storage circuit to reduce the probability of leakage current during programming and further improve programming accuracy.

[0124] According to some embodiments, a unidirectional conduction circuit can be disposed between the first terminal of the first transistor and the first trace, or it can be disposed between the second terminal of the first transistor and the second trace. For example, FIG6 shows a schematic diagram of another memory circuit according to an exemplary embodiment of the present application. As shown in FIG6, the memory circuit 600 may include a memory cell 610, and the first trace IN1-IN m Second routing line OUT1-OUT n And the third route W1-W n The storage circuit 600 may also include a fourth trace CON1-CON. m .

[0125] First route IN1-IN m It can also be called the input line, the second route OUT1-OUT n Also known as the output line, the third routing line W1-W n Also known as the programming line (or write line), the fourth trace CON1-CON mThese can also be called control lines. Figure 6 illustrates an example where input lines and control lines are connected to multiple memory cells in rows, and output lines and programming lines are connected to multiple memory cells in columns. In other embodiments, input lines can be connected to multiple memory cells in columns, control lines can be connected to multiple memory cells in columns, output lines can be connected to multiple memory cells in rows, and programming lines can be connected to multiple memory cells in rows. In other embodiments, input lines can cross output lines, and control lines can cross programming lines. The routing of input lines, output lines, programming lines, and control lines can be arbitrarily combined, and this application does not impose any limitations.

[0126] Furthermore, the storage circuit 600 also includes a one-way conduction circuit 640. As an example, as shown in FIG6, the one-way conduction circuit 640 can be connected to the second terminal T12 of the first transistor T1 of the storage cell 610 and the second trace OUT. j Alternatively, the unidirectional conduction circuit 640 can be connected between the first terminal T11 of the first transistor T1 of the memory cell 610 and the first trace IN. i Between. i∈[1,m], j∈[1,n], where m is the number of rows in the storage cell array and n is the number of columns in the storage cell array.

[0127] Based on the aforementioned storage circuit, by configuring a unidirectional conduction circuit 640 connected in series with the read tube of the storage cell, the unidirectional conduction characteristic of the circuit can be utilized to suppress leakage current in non-programmed storage cells during programming or writing, thereby improving programming accuracy. Furthermore, the unidirectional conduction characteristic of this circuit can be used to maintain a conducting state during calculation or reading, thus not affecting the normal operation of calculation and reading functions. During current programming of the storage circuit, for currently non-programmed storage cells, the unidirectional conduction circuit connected to that storage cell can effectively prevent leakage current from passing through, reducing or even eliminating the impact of leakage current on the programming current, improving the programming accuracy of the storage circuit, and further enhancing the computing performance of the storage circuit. Additionally, for currently programmed storage cells, during data writing, the unidirectional conduction characteristic of the circuit does not affect the unidirectional flow of the programming current, thus improving programming efficiency without affecting calculation or reading functions.

[0128] For example, the unidirectional conduction circuit 640 may include a diode. Optionally, the unidirectional conduction circuit 640 may include one diode or may include multiple diodes. In other embodiments, the unidirectional conduction circuit 640 may include other types of circuits with unidirectional conduction characteristics, which include one or more components, such as silicon controlled rectifiers (SCRs). This application does not specifically limit the device type or circuit structure of the unidirectional conduction circuit 640. Compared to other implementations of unidirectional conduction circuits, diodes have a simpler circuit structure, lower hardware costs, and do not require additional control signals to achieve unidirectional conduction.

[0129] Optionally, the unidirectional conduction circuits of different memory cells can have the same or different circuit structures, and the types of devices in the circuit can be found in the relevant descriptions of the embodiments above. As an example, the unidirectional conduction circuits in different memory cells can all include diodes.

[0130] In the embodiments shown in Figures 7 to 10, taking a unidirectional conduction circuit including diodes as an example, for any two memory cells connected to the same input line, the two diodes connected to those two memory cells can be connected in reverse. For example, the anode of one diode can be connected to the anode of another diode, or the cathode of one diode can be connected to the cathode of another diode.

[0131] Figure 7 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. As an example, as shown in Figure 7, in the storage circuit 700, the negative terminal of the diode in the unidirectional conduction circuit 740 is connected to the input line IN. i The positive terminal is connected to the first terminal of the first transistor T1 in the storage cell 710. Figure 8 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. As another example, as shown in Figure 8, in the storage circuit 800, the positive terminal of the diode in the unidirectional conduction circuit 840 is connected to the input line IN. i The negative terminal is connected to the first terminal of the first transistor T1 in the memory cell 810. Figure 9 shows a schematic diagram of another memory circuit according to an exemplary embodiment of this application. As another example, as shown in Figure 9, in the memory circuit 900, the negative terminal of the diode in the unidirectional conduction circuit 940 is connected to the second terminal of the first transistor T1 in the memory cell 910, and the positive terminal is connected to the output line OUT. j Figure 10 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. As another example, as shown in Figure 10, in the storage circuit 1000, the positive terminal of the diode in the unidirectional conduction circuit 1040 is connected to the second terminal of the first transistor T1 of the storage cell 1010, and the negative terminal is connected to the output line OUT. j .

[0132] Based on the circuit structure described above, the state of the unidirectional conduction circuit can be adjusted according to the state of the memory cell it is connected to. In some embodiments, the unidirectional conduction circuit can switch between a cutoff state and a unidirectional conduction state by controlling the voltage of the signal lines in the memory circuit. For example, when the memory cell is used as a programming memory cell or a calculation (or reading) memory cell, the voltage of the input lines and / or output lines connected to the memory cell can be controlled to turn on the unidirectional conduction circuit connected to the memory cell. As another example, when the memory cell is used as a non-programming memory cell or a non-calculation (or non-reading) memory cell, the voltage of the input lines and / or output lines connected to the memory cell can be controlled to turn off the unidirectional conduction circuit connected to the memory cell. Here, a programming memory cell refers to the memory cell currently to be written to, a calculation memory cell refers to the memory cell currently participating in the calculation, and a reading memory cell refers to the memory cell currently to be read from.

[0133] By controlling the voltage of the signal lines in the storage circuit, the state of the unidirectional conduction circuit can be flexibly controlled, enabling the storage cells in the storage circuit to switch between multiple states more flexibly and effectively, thereby further improving the applicability of the storage circuit in different application scenarios.

[0134] According to some embodiments, the switching circuit can be disposed between the first terminal of the first transistor and the first trace, or it can be disposed between the second terminal of the first transistor and the second trace. For example, FIG11 shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. As shown in FIG11, the storage circuit 1100 may include a storage cell 1110, and the first trace IN1-IN m Second routing line OUT1-OUT n And the third route W1-W n The storage circuit 1100 may also include a fourth trace CON. 11 -CON 1m and the fifth route CON 21 -CON 2m .

[0135] Among them, the first routing line IN1-IN m It can also be called the input line, the second route OUT1-OUT n Also known as the output line, the third routing line W1-W n Also known as the programming line (or write line), the fourth trace CON 11 -CON 1m It can be called the first control line, the fifth routing line (CON). 21 -CON 2mThis can be referred to as the second control line, used to control the on or off state of the switching circuit 1140. As an example, as shown in Figure 11, the switching circuit 1140 is connected to the second terminal T12 of the first transistor T1 in the storage cell 1110 and the second trace OUT. j In the range i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array.

[0136] Based on the aforementioned storage circuit, the switching circuit 1140 can be configured to suppress leakage current in non-programmed storage cells during programming or writing, thereby improving programming accuracy. Furthermore, the switching circuit 1140 can be controlled to be in a conducting state during calculation or reading, without affecting the normal operation of the calculation and reading functions. During current programming of the storage circuit, for currently non-programmed storage cells, the switching circuit connected to that storage cell can be controlled to be in a cut-off state, effectively preventing leakage current from passing through, reducing or even eliminating the impact of leakage current on the programming current, improving the programming accuracy of the storage circuit, and further enhancing the computing performance of the storage circuit. Conversely, for currently programmed storage cells, during data writing, the switching circuit remains in a conducting state, not affecting the flow of programming current, thus improving programming efficiency without affecting the calculation or reading functions.

[0137] In some implementations, the fifth trace CON in the control storage circuit 1100 can be used. 2i The signal causes the switching circuit 1140 to switch between a cutoff state and a conduction state. For example, when the memory cell is used as a programming memory cell or a calculation (or retrieval) memory cell, the fifth trace CON connected to that memory cell can be controlled. 2i A signal (e.g., voltage) causes the switching circuit connected to the memory cell to conduct. For example, when the memory cell is a non-programming or non-computing (or non-reading) memory cell, the fifth trace CON connected to that memory cell can be controlled. 2i The signal causes the switching circuit connected to the storage unit to be turned off. Here, the programming storage unit refers to the storage unit where data is currently to be written, the calculation storage unit refers to the storage unit currently participating in the calculation, and the reading storage unit refers to the storage unit where data is currently to be read.

[0138] Through the fifth trace CON in the storage circuit 2i The signal control on the circuit can flexibly control the state of the switching circuit, enabling the storage cells in the storage circuit to switch between multiple states more flexibly and effectively, thereby further improving the applicability of the storage circuit in different application scenarios.

[0139] As an example, the switching circuit 1140 may include a transistor. Optionally, the switching circuit 1140 may include one transistor or multiple transistors. As another example, the transistor type of the switching circuit 1140 may be the same as the transistor type of the memory cell to simplify the manufacturing process. Optionally, the circuit structures of the switching circuits of different memory cells may be the same or different, and the device types in the circuit can be referred to the relevant descriptions in the embodiments above. As an example, the switching circuits in different memory cells may all include transistors. The specific location of the transistor in the memory circuit can be referred to the location of the diode in the memory circuit in Figures 7 to 10, which will not be repeated here.

[0140] To facilitate understanding, the following section uses a storage circuit including a storage cell array as an example, and describes the programming, calculation, and reading processes of the storage circuit in conjunction with Figures 12 to 15.

[0141] As an example, Figure 12 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. Referring to Figure 12, the storage circuit 1200 includes a storage cell array, which includes a plurality of storage cells 1210. The description of the storage cells 1210 can be found in the description of the first transistor T1 and the second transistor T2 in the above embodiments. The first driving terminal of the first transistor T1 is connected to the fourth terminal of the second transistor T2 for a storage node (SN). The charge at the storage node can be used to change the conduction capability of the first transistor T1 and can be used to characterize the weight data of the storage cell where the storage node is located. Optionally, the first driving terminal of the first transistor T1 is connected to a capacitor C. For example, the first driving terminal of the first transistor T1 may have parasitic capacitance. Alternatively, the storage cell 1210 may also include a capacitor connected to the storage node, and the other end of the capacitor may be coupled to a voltage. This voltage may include a positive voltage, a negative voltage, or a ground voltage, which is not limited in this application. As shown in Figure 12, when the other end of the capacitor is grounded, the number of signals required to be connected in the circuit can be simplified, the circuit implementation can be simplified, and signal interference can be reduced. The second driving terminal of the second transistor T2 can be connected to a control line CON. i The third terminal can be connected to the programming cable W. j The first terminal of the first transistor T1 can be connected to the input line IN. i The second terminal can be connected to the output line OUT. j In programming line W j and output line OUT j A switching circuit Q can be installed between them. jWhere i∈[1,m], j∈[1,n], m is the number of rows in the storage cell array, and n is the number of columns in the storage cell array. Figure 13 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. The circuit structure of this storage circuit 1300 differs from that of Figure 12 in that, during the programming process, the programming line W in Figure 12... j It can be coupled to a lower potential voltage, such as voltage Vss, and the output line OUT. j It can be achieved via the switching circuit Q j Coupled to a lower voltage, the input line IN i It can be coupled to a higher potential voltage, such as voltage Vdd; the programming line W in Figure 13 j It can be coupled to a higher potential voltage, such as voltage Vdd, and the output line OUT. j It can be achieved via the switching circuit Q j Coupled to a higher voltage, the input line IN i It can be coupled to a lower potential voltage, such as voltage Vss.

[0142] According to some embodiments, the output line OUT j It can be coupled to voltages with lower or higher potentials, programming line W j It can be achieved via the switching circuit Q j Coupled to a voltage that is lower or higher than this potential.

[0143] In programming (or writing) mode, via the control line CON i The second drive terminal of the second transistor T2 of the control memory cell turns on the second transistor T2 of the target memory cell to be programmed (or written to), and turns off the second transistor T2 of the non-target memory cell. Input line IN i The coupled voltage can be used to read the current of the first transistor T1 in the programming memory cell. This is achieved by controlling the switching circuit Q. j The programming line W is turned on. j and output line OUT j The current can be adaptively adjusted to control the charge at the storage node, thereby enabling data writing.

[0144] According to some embodiments, data writing can be achieved using static current programming. For example, as shown in Figures 12 and 13, the programming line W... j Can be used with current source P j Connect, output line OUT j It can be achieved via the switching circuit Q j With current source P j Connection. According to some embodiments, the output line OUT... j Can be used with current source P j Connection, programming line Wj It can be achieved via the switching circuit Q j With current source P j Connection. Flow through programming line W j and output line OUT j The current signal comes from current source P j This static current programming method can achieve adaptive adjustment of the current signal and reduce errors caused by differences in signal characteristics during the programming process.

[0145] When programming the target memory cell, the common programming line W with the target memory cell... j and output line OUT j The unprogrammable memory cell can control its second transistor T2 to be in the off state. Optionally, the first terminal of the unprogrammable memory cell can be coupled to a voltage, which is related to the output line OUT. j The voltage on the output lines is equal to or close to the voltage on the output lines, thereby suppressing the influence of leakage current from unprogrammed memory cells on programming and further improving programming accuracy. For example, referring to Figure 12, this voltage can be lower than the voltage on the output lines, or lower than the lowest value of the voltage on multiple output lines. For example, referring to Figure 13, this voltage can be higher than the voltage on the output lines, or higher than the highest value of the voltage on multiple output lines.

[0146] The example described uses row-based programming; column-based programming or programming by other units is similar.

[0147] Please refer to Figure 12. Taking the programming of the first row of memory cells as an example, the other rows are similar. The second transistor T2 of the first row of memory cells 1210 is turned on via control line CON1, and the control lines CON2-CON... m The second transistor T2, which controls other row memory cells 1210, is turned off. The programming line W is then switched off. j and output line OUT j Through the switching circuit Q j Conduction. During programming, the j-th column storage unit can be connected via programming line W. j Apply a current source from the output line OUT j Extracting current. Input line IN1 can be coupled to a voltage used to read the current of the first transistor T1. For example, input line IN1 can be coupled to a higher potential voltage, such as voltage Vdd.

[0148] Please refer to Figure 13. Taking the programming of the first row of memory cells as an example, the other rows are similar. The second transistor T2 of the first row of memory cells 1310 is turned on via control line CON1, and the control lines CON2-CON... m The second transistor T2, which controls other row memory cells 1310, is turned off. The programming line W is then switched off. j and output line OUTj Through the switching circuit Q j Conduction. During programming, the j-th column storage unit can be connected via programming line W. j Apply a current source to the output line OUT j Input current. Input line IN1 can be coupled to a voltage used to read the current of the first transistor T1. For example, input line IN1 can be coupled to a lower voltage, such as voltage Vss.

[0149] Please continue referring to Figure 12 or Figure 13. According to some embodiments, the voltages of the input and output lines connected to the same memory cell are the same or close to each other to suppress leakage current in unprogrammed memory cells. The method of voltage provision can be referred to the description in the above embodiments. When the SN node voltage is stable, for example, when the output line OUT... j The read current is similar to or the same as the programming current, or the programming line W j When the current is close to or equal to 0, or, for example, after the programming stabilization time, the second transistor T2 of the first row memory cell 1210 or 1310 is turned off by the control line CON1, thus completing the programming of the first row memory cell 1210 or 1310.

[0150] The voltages of different output lines can be the same or close, which simplifies circuit control. According to some embodiments, see Figure 12, the input lines IN2-IN m The voltage can be less than or equal to the output lines OUT1-OUT n The minimum value of the voltage. According to some embodiments, see, for example, Figure 13, the input lines IN2-IN m The voltage can be greater than or equal to the output lines OUT1-OUT n The maximum value of the voltage.

[0151] In calculation mode, disconnect switching circuits Q1 to Q... n Connect to the same output line OUT j A set of storage units, connected via input lines IN1-IN m At least some of the input lines in the circuit receive multiple input signals. The storage unit that receives the input signals converts the corresponding input signals into output signals based on the stored weight data, and displays the output signals on the connected output line OUT. j The calculation result is obtained by accumulating the data. In the read state, disconnect the switching circuits Q1 to Q... n The memory cell to be read is accessed via the input line IN. i Receives a drive signal, and under the drive of the drive signal, outputs data to the connected output line OUT. j The data is output and stored.

[0152] As another example, FIG14 shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. Referring to FIG14, the storage circuit 1400 includes a storage cell array, which includes a plurality of storage cells 1410 and a control line CON. i Programming line W j Input line IN i and output line OUT j The above parts can be referred to the descriptions of the corresponding parts in the above embodiments, and will not be repeated here. Figure 15 shows a schematic diagram of another storage circuit according to an exemplary embodiment of this application. The difference between the circuit structure of the storage circuit 1500 and Figure 14 includes: during the programming process, the output line OUT in Figure 14... j It can be coupled to a lower potential voltage, for example, voltage Vss, programming line W. j It can be achieved via the switching circuit Q j Coupled to a lower voltage, the input line IN i It can be coupled to a higher potential voltage, such as voltage Vdd; the output line OUT in Figure 15 j It can be coupled to a higher potential voltage, such as voltage Vdd, programming line W. j It can be achieved via the switching circuit Q j Coupled to a higher voltage, the input line IN i It can be coupled to a lower potential voltage, such as voltage Vss.

[0153] In programming (or writing) mode, via the control line CON i The second drive terminal of the second transistor T2 of the control memory cell turns on the second transistor T2 of the target memory cell to be programmed (or written to), and turns off the second transistor T2 of the non-target memory cell. Input line IN i The coupled voltage can be used to read the current of the first transistor T1 in the programming memory cell. This is achieved by controlling the switching circuit Q. j When the circuit is turned on, the output line OUT is activated. j The current can be based on the charge change at the storage node. When the output line OUT... j When the current reaches the target current, the switching circuit Q is turned off. j This enables the control of the charge at the storage node, thereby enabling data writing.

[0154] According to some embodiments, data writing can be implemented using dynamic current programming. For example, as shown in Figures 14 and 15, the output line OUT... j It can be used with a current sensing module (or circuit) k j Connection, current sensing module k j The output line OUT can be used. jThe current signal is detected to control the switching circuit Q. j The connection state. For example, when the current signal magnitude of the output line OUT1 reaches the target current, the control switch circuit Q... j It is in the off state.

[0155] When programming the target memory cell, the common programming line W with the target memory cell... j and output line OUT j The unprogrammable memory cell can control its second transistor T2 to be in the off state. Optionally, the first terminal of the unprogrammable memory cell can be coupled to a voltage, which is related to the output line OUT. j The voltages on the memory cells are equal or close to those on the non-programmed memory cells, thereby suppressing the influence of leakage current on programming and further improving programming accuracy. The method of providing the voltage can be referred to the description in the above embodiments.

[0156] The example described uses row-based programming; column-based programming or programming by other units is similar.

[0157] Please refer to Figure 14. Taking the programming of the first row of memory cells as an example, the other rows are similar. The second transistor T2 of the first row of memory cells 1410 is turned on via control line CON1, and the control lines CON2-CON1 are used to control the conduction of the second transistor T2. m The second transistor T2, which controls other row memory cells 1410, is turned off. The programming line W is then switched off. j and output line OUT j Through a controllable switching circuit Q j The connection is established, and at the start of programming, the switching circuit Q... j The state is ON. Input line IN1 can be coupled to a voltage used to read the current of the first transistor T1. During programming, output line OUT... j It can be coupled to a lower voltage, such as voltage Vss, and the input line IN1 can be coupled to a higher voltage, such as voltage Vdd. This is achieved through the current sensing module k. j Sensing output line OUT j When the sensed current reaches or approaches the target current, the current sensing module k... j Or the control device shuts off the switch circuit Q j Disconnect programming line W j and output line OUT j The connection between them.

[0158] Please refer to Figure 15. Taking the programming of the first row of memory cells as an example, the other rows are similar. The second transistor T2 of the first row of memory cells 1510 is turned on via control line CON1, and the control lines CON2-CON... mThe second transistor T2, which controls other row memory cells 1510, is turned off. The programming line W is then switched off. j and output line OUT j Through a controllable switching circuit Q j The connection is established, and at the start of programming, the switching circuit Q... j The state is ON. During programming, the output line OUT... j It can be coupled to a higher voltage, such as voltage Vdd, and the input line IN1 can be coupled to a lower voltage, such as voltage Vss. This is achieved through the current sensing module k. j Sensing output line OUT j When the sensed current reaches or approaches the target current, the current sensing module k... j Or the control device shuts off the switch circuit Q j Disconnect programming line W j and output line OUT j The connection between them.

[0159] Please continue referring to Figure 14 or Figure 15. According to some embodiments, the voltages of the input and output lines connected to the same memory cell are the same or close to each other to suppress leakage current in unprogrammed memory cells. The method of voltage provision can be referred to the description of the embodiments above. When the SN node voltage is stable, for example, when the output line OUT... j When the read current is close to or the same as the target current, disconnect the switching circuit Q. j Furthermore, the second transistor T2 of the first row of memory cells 1410 or 1510 is turned off via the control line CON1, thus completing the programming of the first row of memory cells 1410 or 1510.

[0160] The voltages of different output lines can be the same or close, which simplifies circuit control. According to some embodiments, see Figure 14, the input lines IN2-IN... m The voltage can be less than or equal to the output lines OUT1-OUT n The minimum value of the voltage. According to some embodiments, see, for example, Figure 15, the input lines IN2-IN m The voltage can be greater than or equal to the output lines OUT1-OUT n The maximum value of the voltage.

[0161] In calculation mode, disconnect switching circuits Q1 to Q... n Connect to the same output line OUT j A group of memory cells are connected via input lines IN1-IN m At least some of the input lines in the circuit receive multiple input signals. The storage unit that receives the input signals converts the corresponding input signals into output signals based on the stored weight data, and displays the output signals on the connected output line OUT. jThe calculation result is obtained by accumulating the data. In the read state, disconnect the switching circuits Q1 to Q... n The memory cell to be read is accessed via the input line IN. i Receives a drive signal, and under the drive of the drive signal, outputs data to the connected output line OUT. j The data is output and stored.

[0162] The data writing process is controlled by a current signal, and the read current of the read tube can be adaptively adjusted to approach the target current. In some embodiments of this application, the writing efficiency can be further improved through other means.

[0163] According to some embodiments, write efficiency can be improved by using an operational amplifier. For example, FIG16 shows a schematic diagram of another memory circuit according to an exemplary embodiment of the present application. As shown in FIG16, the memory circuit 1600 includes a memory cell 1610, a first trace 1621, a second trace 1622, and a third trace 1623. The memory cell 1610 can be referred to the description of the memory cell in the above embodiments, and will not be repeated here. According to some embodiments, the memory circuit 1600 may further include an operational amplifier 1630 connected between the second terminal T12 and the third terminal T21. The input terminal 1632 of the operational amplifier 1630 is connected to the second terminal T12, and the output terminal 1633 of the operational amplifier 1630 is connected to the third terminal T21.

[0164] Based on the aforementioned storage circuit, an operational amplifier can be used to form a negative feedback loop during the programming phase, adaptively adjusting the voltage at the storage node. This causes the read current during programming to tend towards the target current, improving data writing accuracy. Furthermore, the introduction of the operational amplifier allows for additional driving capability during programming, enabling a larger current signal on the third trace, accelerating programming speed, and balancing programming efficiency and accuracy.

[0165] For example, a negative feedback loop may include a loop in which a first transistor T1 is connected to the input terminal 1632 of an operational amplifier 1630 via a second terminal T12, and to a second transistor T2 via the output terminal 1633 of the operational amplifier 1630, and then to the first drive terminal T13 of the first transistor T1 via the second transistor T2. This application does not limit the type of input terminal 1632, as long as it can be used to form a negative feedback loop. For example, input terminal 1632 may include a non-inverting input terminal or an inverting input terminal.

[0166] According to some embodiments, the storage circuit 1600 may also include a fourth trace 1624. The description of the fourth trace 1624 can be referred to the above embodiments and will not be repeated here.

[0167] According to some embodiments, operational amplifier 1630 includes an input terminal 1631, an input terminal 1632, and an output terminal 1633. Input terminal 1632 is connected to a second terminal T12 or a second trace 1622, and output terminal 1633 is connected to a third terminal T21 or a third trace 1623. The storage circuit 1600 includes a first operating state. In the first operating state, when data is written to the storage cell 1610, the second transistor T2 of the storage cell 1610 is turned on. Input terminal 1631 of operational amplifier 1630 is coupled to a reference voltage, input terminal 1632 is coupled to a current signal I1, and output terminal 1633 outputs a current signal I2. Current signals I1 and I2 are used to control the writing of data in storage cell 1610. The description of the first operating state can be found in the description of the above embodiments and will not be repeated here. This application does not limit the types of input terminals 1631 and 1632, as long as the operational amplifier 1630 can be used to form a negative feedback loop. For example, input terminal 1631 may include a non-inverting input terminal, and input terminal 1632 may include an inverting input terminal. As another example, input terminal 1632 may include a non-inverting input terminal, and input terminal 1631 may include an inverting input terminal.

[0168] In the first operating state, input terminal 1631 is coupled to the reference voltage Vr, and input terminal 1632 is coupled to the current signal I1. Initially, the feedback loop has not reached a stable state, and the output of operational amplifier 1630's output terminal 1633 drives the third terminal T21 or the third trace 1623 to flow through a large current signal I2, thereby accelerating the voltage change at the storage node and speeding up programming. Under the influence of the negative feedback loop based on the operational amplifier, the current signal I2 can change the voltage of the storage node (i.e., at the first drive terminal T13), making the conduction capability of the first transistor T1 more consistent with the current signal I1 under the influence of the voltage at the first drive terminal T13, thus achieving more accurate data writing.

[0169] In addition, the input terminal 1631 of the operational amplifier 1630 is coupled to the reference voltage Vr. Based on the characteristics of the operational amplifier, such as virtual short, the voltage at the input terminal 1632 of the operational amplifier 1630 can be equal to or close to the reference voltage Vr. This allows the second terminal T12 connected to the input terminal 1632 to establish a terminal voltage that matches the reference voltage Vr when writing data. This facilitates the establishment of voltage conditions for calculation or reading at the second terminal T12 based on the same or similar voltage reference as during writing, thereby improving the accuracy of calculation or reading.

[0170] According to some embodiments, the storage circuit 1600 further includes a second operating state. In the second operating state, the second transistor T2 of the storage cell 1610 is turned off, the first terminal T11 is coupled to the input signal, and the storage cell 1610 converts the input signal into an output signal based on weight data, wherein the data written to the storage cell 1610 includes weight data; or, in the second operating state, the second transistor T2 of the storage cell 1610 is turned off, the first terminal T11 is coupled to the input signal, and the storage cell 1610 outputs data driven by the input signal. A description of the second operating state can be found in the description of the above embodiments, and will not be repeated here.

[0171] The storage unit can perform calculations based on the input signal and weight data in the second operating state, or read data driven by the input signal. Because the data is written with high precision, this not only improves the accuracy of data storage but also enhances the reliability of the storage unit when performing computational tasks. It reduces the accumulation of errors caused by weight deviations, thereby further improving the computational reliability of the storage circuit when used in a memory-computing architecture.

[0172] According to some embodiments, the storage circuit may include multiple storage cells, the first terminals of the first transistors of the multiple storage cells are connected to different first traces, the second terminals of the first transistors may be connected to the same second trace, the third terminals of the second transistors of the multiple storage cells may be connected to the same third trace, and the operational amplifier is connected between the second trace and the third trace.

[0173] Based on the above storage circuit, multiple storage cells can be connected to the same second trace and the same third trace, and the second trace and the third trace are connected through an operational amplifier. This design not only allows the operational amplifier to flexibly control the operating state of multiple storage cells, but also significantly saves hardware structure compared to connecting multiple storage cells to different traces, reducing redundant circuits and wiring requirements, thereby reducing the complexity, area, and power consumption of the storage circuit.

[0174] For example, FIG17 shows a schematic diagram of another storage circuit according to an exemplary embodiment of the present application. As shown in FIG17, the storage circuit 1700 includes a plurality of storage cells 1710, a first trace 1721, a second trace 1722, a third trace 1723, and an operational amplifier 1730. The operational amplifier 1730 includes an input terminal 1731, an input terminal 1732, and an output terminal 1733. Descriptions of the various parts can be found in the relevant descriptions of the above embodiments, and will not be repeated here.

[0175] Optionally, multiple memory cells can be arranged in an array, and these memory cells can be memory cells in the same column or the same row. According to some embodiments, referring to FIG17, the second terminal T12 of the first transistor T1 of multiple memory cells 1710 located in the same column can be connected to the same second trace 1722, and the third terminal T21 of the second transistor T2 of multiple memory cells 1710 located in the same column can be connected to the same third trace 1723. In other embodiments, the second terminals of the first transistors of multiple memory cells located in the same row can be connected to the same second trace, and the third terminals of the second transistors of multiple memory cells located in the same row can be connected to the same third trace; in other embodiments, the second terminals of the first transistors of multiple memory cells located in the same column can be connected to the same second trace, and the third terminals of the second transistors of multiple memory cells located in the same row can be connected to the same third trace; or, the second terminals of the first transistors of multiple memory cells located in the same row can be connected to the same second trace, and the third terminals of the second transistors of multiple memory cells located in the same column can be connected to the same third trace. This simplifies the routing complexity, reduces the number of operational amplifiers, and allows memory cells connected by the same second and third routing lines to reuse the same operational amplifier.

[0176] For example, as shown in FIG17, a plurality of memory cells 1710 include a first memory cell 1711 and a second memory cell 1712. The first terminal T11 of the first transistor T1 of the first memory cell 1711 is connected to a first trace 1721. The first terminal T11 of the first transistor T1 of the second memory cell 1712 is connected to another first trace 1721. The second terminal T12 of the first transistor T1 of the first memory cell 1711 and the second memory cell 1712 is connected to the same second trace 1722. The third terminal T21 of the second transistor T2 of the first memory cell 1711 and the second memory cell 1712 is connected to the same third trace 1723.

[0177] For example, as shown in FIG17, in the second operating state, the second transistor T2 of the first storage cell 1711 and the second storage cell 1712 can be controlled to be turned off. The first terminals of the first storage cell 1711 and the second storage cell 1712 are respectively coupled to the first input signal Sin1 and the second input signal Sin2. The first storage cell 1711 and the second storage cell 1712 (and may also include other storage cells connected by the second trace 1722) can output the calculation result on the second trace 1722 based on their respective input signals and their respective stored weight data. Alternatively, in the second operating state, the second transistor T2 of the first storage cell 1711 or the second storage cell 1712 can be controlled to be turned off, and the first terminal of the first storage cell 1711 or the second storage cell 1712 is coupled to the input signal. The first storage cell 1711 or the second storage cell 1712 can output the stored data on the second trace 1722 under the drive of the input signal.

[0178] The current signal I1 can originate from a signal source. The signal source can include a current source, which can be connected to the second trace 1722. The current source does not restrict the direction of current flow; for example, current can flow from the current source to the memory cell, or current can flow from the memory cell to the current source.

[0179] According to some embodiments, a selection circuit can be set up, which is connected to the second trace. In the calculation or reading state, the signal on the second trace is selected to be read and input to the output circuit. In the programming or writing state, the write current is selected to be coupled, for example, the branch where the current source is located is selected, and the write current provided by the current source is provided to the storage unit to control the writing of data.

[0180] According to some embodiments, a selection circuit may not be required; instead, the second trace can be configured to have different coupling states under different operating conditions through other means. For example, the second trace may have different connection branches, one branch including an output circuit and the other including a signal source. Under different operating conditions, the different branches can be enabled by circuit settings within the branches. For example, the storage circuit 1700 may also include an output circuit 1740 for converting the output signal into output data for output. In some embodiments, the second terminal T12 and / or the second trace 1722 may be coupled to the signal source generating the first current signal I1 and the output circuit 1740. Optionally, both the signal source and the output circuit 1740 include a high-impedance state. In a first operating state, the signal source is configured to generate and output the first current signal I1, and the output circuit 1740 is in a high-impedance state. In a second operating state, the signal source is in a high-impedance state, and the output circuit 1740 is configured to convert the output signal on the second trace (i.e., the output line) 1722 into output data for output.

[0181] In some embodiments, the storage circuit 1700 may further include a selection circuit 1750, which includes terminals 1751, 1752, and 1753, and can selectively connect terminal 1751 to one of terminals 1752 and 1753. Terminal 1751 of the selection circuit 1750 is connected to the second terminal T12 and / or the second trace 1722, terminal 1752 of the selection circuit 1750 is coupled to the current signal I1 or the current source of the current signal I1, and terminal 1753 of the selection circuit 1750 is connected to the output circuit 1740.

[0182] In some embodiments, the selection circuit 1750 is configured to, in a first operating state, select the second terminal T12 and / or the second trace 1722 to couple the current signal I1; and in a second operating state, select the second terminal T12 to connect to the output circuit 1740. Optionally, the selection circuit 1750 may include a multiplexer to select the corresponding connection / coupling method in different operating states. Optionally, the selection circuit 1750 may include multiple branches, one branch including a selection switch circuit, the selection switch circuit selecting the connection of terminal 1751 and terminal 1752 or terminal 1753 to connect the corresponding branch in different operating states and select the corresponding connection / coupling method.

[0183] Figure 18 shows a flowchart of a control method according to an exemplary embodiment of this application. This control method can be used to control data writing in any of the memory circuits described in the foregoing embodiments. Referring to Figure 18, the control method 1800 may include:

[0184] S1810: The second transistor of the memory cell in the control memory circuit is turned on.

[0185] S1820: The writing of data to the memory cell is controlled by the current signals of the second and third traces of the storage circuit.

[0186] According to the above control method, controlling the data writing of the memory cell through the current signals of the second and third traces can significantly improve the programming accuracy of the memory cell, reduce the process of multiple write control and multiple read operations to correct the data, reduce the additional power consumption caused by multiple programming operations, and improve programming efficiency.

[0187] For example, the current signal of the second trace can be the first current signal in the aforementioned embodiment, and the current signal of the third trace can be the second current signal in the aforementioned embodiment.

[0188] According to some embodiments, method 1800 further includes: controlling the second and third traces to be connected.

[0189] Optionally, when the second and third traces are connected by a switching circuit, controlling the second and third traces to be on includes: controlling the switching circuit to be in a conducting state.

[0190] According to one embodiment, method 1800 further includes providing a first current to the memory cell, wherein the current signals of the second and third traces are both derived from the first current, i.e., obtained by shunting the first current.

[0191] Optionally, when the second and third traces are connected by a switching circuit, controlling the second and third traces to be on includes: controlling the switching circuit to be in a conducting state.

[0192] The above control method can achieve adaptive current adjustment. In addition, since the current signals on the second and third traces both originate from the first current, that is, the current signals on the second and third traces have the same signal characteristics (e.g., amplitude or frequency), errors caused by differences in signal characteristics during programming can be reduced.

[0193] According to some embodiments, method 1800 further includes providing a first voltage to a first trace and providing a second voltage to a second and a third trace, the first and second voltages being used to drive current signals flowing through the second and third traces.

[0194] According to some embodiments, the storage circuit further includes an operational amplifier connected between the second and third terminals of the storage cell of the storage circuit or between the second and third traces of the storage circuit. The above method 1800 further includes: in the first operating state of the storage circuit, when writing data to the storage cell, controlling the second transistor of the storage cell to turn on, providing a reference voltage to the first input terminal of the operational amplifier, providing a first current signal to the second input terminal of the operational amplifier, and using the first current signal and the second current signal output by the output terminal of the operational amplifier for writing data to the storage cell.

[0195] According to some embodiments, the storage circuit includes a plurality of storage cells, including a first storage cell and a second storage cell. The first terminals of the first transistors of the first storage cell and the second storage cell are connected to different first traces, the second terminals of the first transistors of the first storage cell and the second storage cell are connected to the same second trace, and the third terminals of the second transistors of the first storage cell and the second storage cell are connected to the same third trace. A switching circuit or operational amplifier is connected between the second trace and the third trace. The above method 1800 further includes: in a first operating state of the storage circuit, when writing data to the first storage cell, controlling the second transistor of the first storage cell to be turned on and controlling the second transistor of the second storage cell to be turned off; providing a third voltage to the first terminal of the first transistor of the first storage cell and providing a fourth voltage to the first terminal of the first transistor of the second storage cell, wherein the difference between the fourth voltage and the voltage on the second trace is less than or equal to a voltage threshold.

[0196] According to the above control method, during the programming process, controlling the first transistor of the second storage cell to be turned off can suppress the leakage current of the first transistor of the second storage cell when data is written to the first storage cell. This reduces the impact of leakage current on the writing process of the first storage cell and improves the accuracy of the programming process of the first storage cell. During the programming process, controlling the second transistor of the second storage cell to be turned off can prevent changes to the data in the second storage cell and suppress the leakage current of the second transistor of the second storage cell when data is written to the first storage cell. This reduces the impact of leakage current on the writing process of the first storage cell and improves the accuracy of the programming process of the first storage cell.

[0197] In the above method embodiments, the order of the process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0198] This application also provides a control device, including units or means for performing the steps of any of the above control methods. For example, FIG19 shows a schematic structural block diagram of a control device according to an exemplary embodiment of this application. Referring to FIG19, the control device 1900 includes a first control unit 1910 and a second control unit 1920. The steps performed by the first control unit 1910 can refer to the above embodiments, for example, method 1800 or step S1810. The steps performed by the second control unit 1920 can refer to the above embodiments, for example, method 1800 or step S1820.

[0199] It should be understood that the above division of units is only a logical functional division. In actual implementation, all or part of them can be integrated into a single physical entity, or they can be physically separated. Furthermore, the above units can be implemented in the form of a processor calling software; for example, a control device may include a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above control methods. The memory can be internal to the control device or external to it. Alternatively, the above units can be implemented in the form of hardware circuits. The functions of some or all units can be achieved through the design of the hardware circuits, which can be understood as one or more processing circuits. For example, in some embodiments, the hardware circuit may include an application-specific integrated circuit (ASIC), which implements the functions of some or all of the above units through the design of the logical relationships between the devices within the circuit. Furthermore, in some embodiments, the hardware circuit can be implemented using a programmable logic device (PLD) circuit, which may include a large number of logic devices. The logical relationships between the logic devices are configured through a configuration file, thereby achieving the functions of some or all of the above units. The above control devices can be implemented by a processor calling a program; or by a hardware circuit; or partially by a processor calling a program and partially by a hardware circuit.

[0200] In some possible embodiments, the processor or processing circuit is a circuit with signal processing capabilities. For example, the processor may be a circuit with instruction read and execute capabilities. In other possible embodiments, the processor can implement its functions through the logical relationships of hardware circuits, which are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as a field-programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. This application does not limit the type of processor, including, for example, a central processing unit (CPU), a microcontroller unit (MCU), a graphics processing unit (GPU), or a digital signal processor (DSP). Alternatively, it may be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU).

[0201] In some possible embodiments, the units in the above control device may be integrated in whole or in part, or may be implemented independently. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC).

[0202] Figure 20 shows a schematic structural block diagram of another control device according to an exemplary embodiment of the present application. Referring to Figure 20, the control device 2000 includes: at least one processing circuit (or processor) 2010 and an interface circuit 2020. The interface circuit 2020 is used to be signal-connected to a storage circuit, and the at least one processing circuit 2010 is used to execute any of the control methods provided in the above embodiments.

[0203] This application also provides a storage computing system, which includes: any of the storage circuits and control devices in the foregoing embodiments, wherein the control device is used to control the writing of data stored in the storage circuit.

[0204] This application also provides a computer program product, which includes instructions that, when executed by a processor, cause the control methods described above to be executed.

[0205] This application also provides a computer-readable medium storing instructions that, when executed by a processor, cause the control methods described above to be performed.

[0206] Figure 21 shows a schematic structural block diagram of an electronic device according to an exemplary embodiment of this application. As shown in Figure 21, the electronic device 2100 may include an in-memory computing system 2110 for processing data of the electronic device. The electronic device may also include an input / output device 2120 for receiving user input or outputting processing results. This application does not limit the input type and output type; for example, input may include voice input, text input, image input, or video input, etc. The output may include text output, voice output, image output, or video output, etc. The electronic device may also include a processor 2130, which can process data provided to the in-memory computing system 2110 or process the output data of the in-memory computing system 2110. The output of the input / output device 2120 may be based on the output of the processor 2130 or the output of the in-memory computing system 2110.

[0207] This application does not limit the type of electronic device. For example, according to some embodiments, the electronic device may include wearable devices. Wearable devices include, but are not limited to: head-mounted devices (e.g., helmets or hats), devices worn on the ears (e.g., headphones), devices worn on the wrist (e.g., watches), and devices worn on other parts of the body (e.g., electronic necklaces, medical monitoring devices, or glasses). According to some embodiments, the electronic device may include portable terminals. For example, the electronic device may include, but is not limited to, mobile phones, general-purpose computing devices (e.g., laptops or tablets), personal digital assistants, etc. According to some embodiments, the electronic device may include other types of edge devices, such as personal computers, in-vehicle computers or in-vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device may also include devices such as servers.

[0208] For ease of description and brevity, the working process of the devices, systems, apparatuses and units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0209] In the above embodiments, the descriptions of different embodiments each have their own emphasis. Parts not described in detail or recorded in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the different embodiments described above can be freely combined as needed. Moreover, as technology evolves, the elements described in this application can be replaced by equivalent elements appearing after this application.

Claims

1. A storage circuit, comprising: A storage unit, comprising: a first transistor and a second transistor, wherein the first transistor includes a first terminal, a second terminal and a first driving terminal, and the second transistor includes a third terminal, a fourth terminal and a second driving terminal, wherein the first driving terminal and the fourth terminal are connected, the charge at the first driving terminal is used for storing data in the storage unit, and the second driving terminal is used to control the on or off state of the second transistor. A first trace, a second trace, and a third trace are provided. A first terminal is connected to the first trace, a second terminal is connected to the second trace, and a third terminal is connected to the third trace. The current signals of the second trace and the third trace are used to control the writing of data in the memory cell. The first trace is used to couple an input signal, and the second trace is also used to output an output signal of the memory cell. The output signal is obtained based on the input signal and the data.

2. The storage circuit as described in claim 1, further comprising: A switching circuit is connected between the second terminal and the third terminal.

3. The storage circuit as claimed in claim 2, wherein the storage circuit includes a plurality of storage cells, the first terminals of the first transistors of the plurality of storage cells are connected to different first traces, the second terminals of the first transistors of the plurality of storage cells are connected to the same second trace, the third terminals of the second transistors of the plurality of storage cells are connected to the same third trace, and the switching circuit is connected between the second trace and the third trace.

4. The storage circuit according to any one of claims 1 to 3, wherein the storage circuit includes a first operating state, wherein, In the first operating state, when data is written to the storage unit, the second transistor of the storage unit is turned on, the second trace and the third trace are connected, the second trace flows through the first current signal, and the third trace flows through the second current signal. The first current signal and the second current signal are used to control the writing of data in the storage unit.

5. The storage circuit as described in claim 4, further comprising a second operating state, wherein, In the second operating state, the second transistor of the memory cell is turned off, the second trace and the third trace are not connected, the first terminal is coupled to the input signal, and the memory cell converts the input signal into an output signal based on the weight data, wherein the data written to the memory cell includes the weight data; or, In the second operating state, the second transistor of the storage cell is turned off, the second trace and the third trace are not connected, the first terminal is coupled to the input signal, and the storage cell outputs the data under the drive of the input signal.

6. The storage circuit as described in claim 4 or 5, wherein the first current signal and the second current signal originate from the same signal source.

7. The storage circuit as described in claim 6, wherein when the magnitude of the first current signal reaches the target current or the second current signal is less than or equal to the current threshold, the connection between the second trace and the third trace is broken; or, When programming the memory circuit is completed, the connection between the second trace and the third trace is broken.

8. The storage circuit as described in claim 4 or 5, wherein the first trace is used to couple to a first voltage, the second trace and the third trace are used to couple to a second voltage, and the first current signal and the second current signal are generated under the drive of the first voltage and the second voltage.

9. The storage circuit as described in claim 8, wherein when the magnitude of the first current signal reaches the target current, the connection between the second trace and the third trace is broken.

10. The storage circuit of claim 9, further comprising: A current sensing module is used to sense the first current signal on the second trace, and the sensed first current signal is used to control the connection state between the second trace and the third trace.

11. The storage circuit of claim 1, further comprising: An operational amplifier is connected between the second terminal and the third terminal, wherein an input terminal of the operational amplifier is connected to the second terminal and an output terminal of the operational amplifier is connected to the third terminal.

12. The storage circuit of claim 11, wherein the storage circuit comprises a plurality of storage cells, the first terminals of the first transistors of the plurality of storage cells are connected to different first traces, the second terminals of the first transistors of the plurality of storage cells are connected to the same second trace, the third terminals of the second transistors of the plurality of storage cells are connected to the same third trace, and the operational amplifier is connected between the second trace and the third trace.

13. The storage circuit as described in claim 11 or 12, wherein the operational amplifier includes a first input terminal, a second input terminal, and an output terminal, the second input terminal is connected to the second terminal or the second trace, the output terminal is connected to the third terminal or the third trace, and the storage circuit includes a first operating state, wherein... In the first operating state, when writing data to the storage unit, the second transistor of the storage unit is turned on, the first input terminal of the operational amplifier is coupled to a reference voltage, the second input terminal is coupled to a first current signal, and the output terminal outputs a second current signal. The first current signal and the second current signal are used for writing data to the storage unit.

14. The storage circuit according to any one of claims 11 to 13, wherein the storage circuit further comprises a second operating state, wherein, In the second operating state, the second transistor of the storage cell is turned off, the first terminal is coupled to the input signal, and the storage cell converts the input signal into an output signal based on the weight data, wherein the data written to the storage cell includes the weight data; or, In the second operating state, the second transistor of the storage unit is turned off, the first terminal is coupled to the input signal, and the storage unit outputs the data under the drive of the input signal.

15. The memory circuit according to any one of claims 2 to 14, wherein the memory circuit comprises a plurality of memory cells, the first terminals of the first transistors of the plurality of memory cells are connected to different first traces, the second terminals of the first transistors of the plurality of memory cells are connected to the same second trace, and the third terminals of the second transistors of the plurality of memory cells are connected to the same third trace, wherein the plurality of memory cells includes a first memory cell and a second memory cell, wherein, In the first working state, when data is written to the first storage cell, the second transistor of the first storage cell is turned on and the second transistor of the second storage cell is turned off. The first terminal of the first transistor of the first memory cell is coupled to a third voltage, and the first terminal of the first transistor of the second memory cell is coupled to a fourth voltage, wherein the difference between the fourth voltage and the voltage on the second trace is less than or equal to a voltage threshold.

16. The storage circuit according to any one of claims 1 to 15, wherein the storage cell further comprises: A capacitor is connected to the first driving terminal and the fourth terminal.

17. A control method for controlling data writing to a storage circuit as described in any one of claims 1 to 16, the method comprising: The second transistor of the storage cell in the storage circuit is turned on; The writing of data to the storage cell is controlled by the current signals of the second and third traces of the storage circuit.

18. The method of claim 17, further comprising: A first current is provided to the memory cell, and the second and third traces are controlled to be turned on. The current signals of the second and third traces are obtained by shunting the first current.

19. The method of claim 17 or 18, further comprising: A first voltage is provided to the first trace, and a second voltage is provided to the second and third traces. The first voltage and the second voltage are used to drive the current signal flowing through the second and third traces.

20. The method of claim 17, wherein the storage circuit further comprises an operational amplifier connected between a second terminal and a third terminal of a storage cell of the storage circuit or between a second trace and a third trace of the storage circuit, the method further comprising: In the first operating state of the storage circuit, when writing data to the storage cell, the second transistor of the storage cell is controlled to be turned on, providing a reference voltage to the first input terminal of the operational amplifier and a first current signal to the second input terminal of the operational amplifier. The first current signal and the second current signal output by the output terminal of the operational amplifier are used for writing data to the storage cell.

21. The method of any one of claims 17 to 20, wherein the storage circuit comprises a first storage cell and a second storage cell, the first terminals of the first transistors of the first storage cell and the second storage cell are connected to different first traces, the second terminals of the first transistors of the first storage cell and the second storage cell are connected to the same second trace, the third terminals of the second transistors of the first storage cell and the second storage cell are connected to the same third trace, and a switching circuit or operational amplifier is connected between the second trace and the third trace, the method further comprising: In the first operating state of the storage circuit, when writing data to the first storage cell, the second transistor of the first storage cell is turned on, and the second transistor of the second storage cell is turned off. A third voltage is provided to the first terminal of the first transistor of the first memory cell, and a fourth voltage is provided to the first terminal of the first transistor of the second memory cell, wherein the difference between the fourth voltage and the voltage on the second trace is less than or equal to a voltage threshold.

22. A control device, comprising an interface circuit and at least one processing circuit, the interface circuit being configured to signal-connect with a storage circuit; The at least one processing circuit is used to perform the control method as described in any one of claims 17 to 21.

23. An in-memory computing system, comprising: The storage circuit as described in any one of claims 1 to 16; A control device is used to control the writing of data stored in the storage circuit.

24. An electronic device comprising a storage circuit as claimed in any one of claims 1 to 16, or comprising a control device as claimed in claim 22.

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