An interleaved converter and a method for operation thereof

Abstract

The present disclosure relates to an interleaved converter (10) and a method (M100) for operation thereof. The interleaved converter (10) hereby comprises at least two cells (110) that are controlled in an interleaved manner, wherein each cell (110) comprises: at least two semiconductor switches (110SW); and a measurement device (115) for measuring operation parameters of the respective cell (110). The interleaved converter (10) further comprises: a controller (1110) for controlling the at least two cells (110) by supplying respective control signals (1150), wherein the controller is configured to control each cell (110) with a same switching period (tSW) and with a same duty cycle (dSW); and a fault protection device (1140). The fault protection device (1140) is configured to monitor the operation of the cells (110) and to detect a fault condition (F), wherein when a fault condition (F) is detected, to fault protection device (1140) is configured to disable the cells (110). By disabling the at least two cells (110) a respective portion of the duty cycle (dSW) of each cell (110) is lost, resulting in a respective individual lost duty cycle value (Δd) of each cell (110). The disabled at least two cells (110) are enabled when the individual lost duty cycle value (Δd) of each cell (110) is equal and when the fault condition (F) is resolved.

Description

[0001] AN INTERLEAVED CONVERTER AND A METHOD FOR OPERATION THEREOF

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to interleaved converters and to operation of interleaved converters. Such interleaved converters may be used in solar photovoltaic systems, battery storage systems, or the like, and in general may be used where AC / DC conversion and / or DC / AC conversion is desired.

[0004] BACKGROUND

[0005] Conventional interleaved converters are power electronics circuits commonly used to improve efficiency, reduce ripple, and enhance reliability in energy conversion systems. These converters employ multiple converter cells, operating in parallel and phase-shifted to evenly distribute load current and reduce stress on individual components. Hereby for operation of such conventional interleaved converters various methods for managing steady-state and known transient conditions are available. However conventional interleaved converters and conventional methods for operation thereof often do not provide a solution for balancing of the conventional interleaved converter during abnormal conditions, i.e. fault conditions.

[0006] SUMMARY

[0007] The present disclosure and its solutions are further based on the following considerations.

[0008] In view of the above, an objective of this disclosure is to provide a transistor device that allows overcoming the issues that affect the interleaved converter and its operation. Hence, this disclosure aims to provide an improved apparatus, namely an interleaved converter, and method for operation of such an interleaved converter. An objective of this disclosure is to provide an apparatus, respectively an interleaved converter, and a method for operation thereof, that achieves an improved balanced operation during fault conditions, while protecting the inductors of the interleaved converter from saturation and optimizing the loss distribution among the interleaved converter cells.

[0009] These and other objectives are achieved by the solution of this disclosure as described in the independent claims. Advantageous implementations are further defined in the dependent claims.

[0010] A first aspect of this disclosure provides an interleaved converter comprising:

[0011] at least two cells, that are controlled in an interleaved manner, wherein each cell comprises: at least two semiconductor switches; a measurement device for measuring operation parameters of the respective cell;

[0012] a controller for controlling the at least two cells by supplying respective control signals, wherein the controller is configured to control each cell with a same switching period and with a same duty cycle;

[0013] a fault protection device, wherein the fault protection device is configured:

[0014] to monitor the operation parameter signals from each measurement device, and hereby further configured to detect a fault condition in the operation parameter signals;when a fault condition is detected, to disable the at least two cells, wherein by disabling the at least two cells a respective portion of the duty cycle of each cell is lost, resulting in a respective individual lost duty cycle value of each cell;

[0015] when the at least two cells are disabled, determine a first reset condition for enabling the disabled at least two cells, wherein the first reset condition is met when the individual lost duty cycle value of each cell is equal; when the at least two cells are disabled, to enable the disabled at least two cells when the first reset condition is met and when a second reset condition is met, wherein the second reset condition is met when the fault condition is resolved.

[0016] With this first aspect an interleaved converter is provided, achieving a respective fault protection of the interleaved converter upon detection of a fault condition by disabling the respective cells of the interleaved converter, and further achieving a balanced operation by respective control of the interleaved converter during the respective fault condition. The controlled enabling of the previously disabled respective cells is hereby crucial, whereas the first reset condition is determined by the fault protection device. Here, the respective lost duty cycle value of each cell is regarded, wherein the reset of the cells of the interleaved converter is permitted only at respective determined time points that fulfil the first reset condition to ensure that the interleaved cells experience an equal lost duty cycle value. Hence, imbalances are prevented and components of the interleaved converter are protected from stress and potential inductor saturation, so that overall with this first aspect the reliability and stability of interleaved converters under fault conditions are enhanced. Furthermore, with this first aspect the size and cost of coupled / uncoupled inductors is reduced by achieving an improved current balancing, thereby lowering the risk of saturation. Additionally, loss distribution between cells is optimized, eliminating the need for oversized semiconductors and further enhancing overall efficiency, power density and cost-effectiveness of the interleaved converter.

[0017] In an implementation form of the first aspect the first reset condition is met when each cell has a same effective duty cycle, wherein the effective duty cycle of a respective cell is the difference of the duty cycle and the respective individual lost duty cycle value. Thus, with this configuration the determination of the first reset condition is based on known quantities (such as the desired set duty cycle value) and measurable quantities (such as the lost duty cycle value respectively the effective duty cycle of a respective cell).

[0018] In an implementation form of the first aspect the first reset condition of each cell having a same effective duty cycle is met when a disabling-duration of the disabling of the at least two cells is a positive integer multiple of the switching period. Thus, with this exemplary configuration a simple but effective first reset condition determination is achieved.

[0019] In an implementation form of the first aspect the fault protection device is configured to enable the disabled at least two cells simultaneously, when the first reset condition and the second reset condition are met. This exemplary configuration provides a simple but effective control of the reset of the respective cells.

[0020] In an implementation form of the first aspect the fault protection device is configured to enable the disabled at least two cells individually per cell, when the first reset condition and the second reset condition are met. This allows for an individual control of the reset of the respective cells. In an implementation form of the first aspect the fault protection device is configured to perform the enabling of at least two of the at least two deactivated cells by the fault protection device in a staggered manner. This allows for a further individual and situation specific control of the reset of the respective cells.

[0021] In an implementation form of the first aspect the fault protection device is configured to disable the at least two cells when a fault condition is detected by sending a trip signal. This trip signal indicates to (immediately) disable the respective cells,ensuring protection of the respective components of the interleaved converter. The trip signal hereby may overrule any other control signals.

[0022] In an implementation form of the first aspect the fault protection device is configured to send the trip signal to the controller upon detection of the fault condition, whereby the controller is configured to disable the at least two cells upon receival of the trip signal. In an implementation form of the first aspect the controller is configured to disable the at least two cells by disabling the control signal supply. Hereby, various exemplary implementations of the disabling are conceivable such as the stop of signal supply towards the cells, respectively their semiconductor switches, or via a sending of the respective trip signal to the cells, respectively their semiconductor switches, or via other configurations, whereas in any case of these examples the disabling of the respective cells is achieved.

[0023] In an implementation form of the first aspect the interleaved converter comprises a hardware protection device, wherein the fault protection device is configured to send the trip signal to the hardware protection device upon detection of the fault condition, and wherein the hardware protection device is configured to disable the at least two cells upon receival of the trip signal. This exemplary implementation provides a further additional or alternative configuration for disabling the respective cells. In an implementation form of the first aspect the hardware protection device is configured to disable the at least two cells by disabling control signal supply of the controller.

[0024] In an implementation form of the first aspect the fault protection device is configured to uphold the trip signal until the enabling of the disabled at least two cells when the first reset condition and the second reset condition are met. With this exemplary configuration the uphold trip signal may overrule any other control signal so that the disable of the respective cells, respectively their semiconductor switches, is continued.

[0025] In an implementation form of the first aspect the fault protection device is configured to enable the at least two disabled cells when the first reset condition and the second reset condition are met, by terminating the uphold trip signal. This ensures a further safe operation of the interleaved converter, as the enabling is only performed when no trip signal is present.

[0026] In an implementation form of the first aspect the fault protection device is configured to enable the at least two disabled cells when the first reset condition and the second reset condition are met, by sending a reset signal. In an implementation form of the first aspect the fault protection device is further configured to send the reset signal to the controller and / or the hardware protection device. In an implementation form of the first aspect the controller and / or the hardware protection device is configured to enable the disabled at least two cells upon receival of the reset signal. In an implementation form of the first aspect the controller and / or the hardware protection device is configured to enable the disabled at least two cells by enabling the control signal supply. This provides additional or alternative exemplary configurations for a safe and effective enabling of the respective cells.

[0027] In an implementation form of the first aspect the fault protection device is configured to detect a normal operation in the operation parameter signals, whereby the fault protection device is further configured to detect the resolve of the fault condition by detecting the normal operation. With this exemplary configuration the monitoring of the interleaved converter, respectively of the interleaved converter cells, even during a fault event, i.e. when a fault condition was detected, allows for a simple and effective way to determine the resolve of the fault condition. Based on this detection it may be determined that a normal operation is again possible after enabling of the respective cells.

[0028] In an implementation form of the first aspect the fault protection device is configured to control the control signal supply of the controller towards the at least two cells. This exemplary configuration allows for an enhanced secure control of the cells.In an implementation form of the first aspect the fault protection device is at least partially part of the controller; and / or the fault protection device is at least partially an external component to the controller; and / or the fault protection device is at least partially part of the hardware protection device. Thus, with these possible exemplary configurations it is apparent that the fault protection device can be implemented on the controller implemented via a respective software that actuates the controller in the desired manner; or the fault protection device can be implemented with the hardware protection device as a hardware implementation; or the fault protection device can also be implemented as another entity external to the controller and / or external to the hardware protection device; or any mixture of these implementations.

[0029] In an implementation form of the first aspect the fault condition is at least one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like; whereby the fault protection device is respectively configured for at least one of: an overcurrent protection, an undercurrent protection, an overvoltage protection, an undervoltage protection, an overtemperature protection, a short circuit protection, or the like. Thus, various fault scenarios are manageable with such an exemplary implementation of the respective interleaved converter.

[0030] A second aspect of this disclosure provides a method for operation of an interleaved converter, the interleaved converter comprising:

[0031] at least two cells, wherein each cell comprises: at least two semiconductor switches a measurement device for measuring operation parameters of the respective cell;

[0032] a controller for controlling the at least two cells;

[0033] a fault protection device;

[0034] wherein the method comprises the method steps of:

[0035] controlling, by the controller, in normal operation the at least two cells in an interleaved manner via respective control signals, wherein each cell is controlled with a same switching period and each cell has a same duty cycle; measuring, by each measurement device, operation parameters of the respective cell;

[0036] monitoring, by the fault protection device, the operation parameter signals from each measurement device; wherein when a fault condition is present with at least one of the at least two cells, the method comprising:

[0037] a. detecting, by the fault protection device, the fault condition in the operation parameter signals;

[0038] b. disabling, by the fault protection device, the at least two cells wherein by disabling the at least two cells a respective portion of the duty cycle of each cell is lost, resulting in a respective individual lost duty cycle value of each cell; c. determining, by the fault protection device, a first reset condition for enabling the disabled at least two cells, wherein the first reset condition is met when the individual lost duty cycle value of each cell is equal;

[0039] d. enabling, by the fault protection device, the disabled at least two cells when the first reset condition is met and when a second reset condition is met, wherein the second reset condition is met when the fault condition is resolved.

[0040] With this second aspect a method for operation of a respective interleaved converter is provided, achieving a respective fault protection upon detection of a fault condition by disabling the respective cells of the interleaved converter, and further achieving a balanced operation by respective control of the interleaved converter during the respective fault condition. The controlled enabling of the previously disabled respective cells is hereby crucial, whereas the first reset condition is determined by the fault protection device. Here, the respective lost duty cycle value of each cell is regarded, wherein the reset of the cells of the interleaved converter is permitted only at respective determined time points that fulfil the first reset condition to ensure that the interleaved cells experience an equal lost duty cycle value. Hence, imbalances are prevented and components of the interleaved converter are protected from stress and potential inductor saturation, so that overall with this first aspect the reliability and stability of interleaved converters under fault conditions are enhanced. Furthermore, with this first aspect the size and cost of coupled / uncoupled inductors is reduced by achieving an improved current balancing, thereby lowering the risk of saturation.Additionally, loss distribution between cells is optimized, eliminating the need for oversized semiconductors and further enhancing overall efficiency, power density and cost-effectiveness of the interleaved converter.

[0041] In an implementation form of the second aspect the first reset condition is met when each cell has a same effective duty cycle, wherein the effective duty cycle of a respective cell is the difference of the duty cycle and the respective individual lost duty cycle value. Thus, with this exemplary configuration the determination of the first reset condition is based on known quantities (such as the desired set duty cycle value) and measurable quantities (such as the lost duty cycle value respectively the effective duty cycle of a respective cell).

[0042] In an implementation form of the second aspect the first reset condition of each cell having a same effective duty cycle is met when a disabling-duration of the disabling of the at least two cells is a positive integer multiple of the switching period. Thus, with this exemplary configuration a simple but effective first reset condition determination is achieved.

[0043] In an implementation form of the second aspect the method step of enabling, by the fault protection device, the disabled at least two cells is performed simultaneously for the at least two cells. This exemplary configuration provides a simple but effective control of the reset of the respective cells.

[0044] In an implementation form of the second aspect the method step of enabling, by the fault protection device, the disabled at least two cells is performed by the fault protection device individually per cell. This allows for an individualized control of the reset of the respective cells. In an implementation form of the second aspect the method step of enabling, by the fault protection device, the disabled at least two cells is performed by the fault protection device in a staggered manner. This allows for a further individual and situation specific control of the reset of the respective cells.

[0045] In an implementation form of the second aspect the method step of disabling, by the fault protection device, the at least two cells comprise the additional method step of:

[0046] sending, by the fault protection device, a trip signal.

[0047] This trip signal indicates to (immediately) disable the respective cells, ensuring protection of the respective components of the interleaved converter. The trip signal hereby may overrule any other control signals. In an implementation form of the second aspect the fault protection device sends the trip signal to the controller upon detecting the fault condition, whereby the controller performs the method step of disabling the at least two cells upon receival of the trip signal, possibly by the additional method step of:

[0048] disabling the controlling of the at least two via respective control signals.

[0049] Hereby, various exemplary implementations of the disabling are conceivable such as the stop of signal supply towards the cells, respectively their semiconductor switches, or via a sending of the respective trip signal to the cells, respectively their semiconductor switches, or via other configurations, whereas in any case of these examples the disabling of the respective cells is achieved.

[0050] In an implementation form of the second aspect the interleaved converter comprises a hardware protection device, whereby the fault protection device sends the trip signal to the hardware protection device upon detecting the fault condition, whereby the hardware protection device performs the method step of disabling the at least two cells upon receival of the trip signal, exemplary by the additional method step of:

[0051] disabling the controlling of the at least two cells via respective control signals.This exemplary implementation provides a further additional or alternative configuration for disabling the respective cells. In an implementation form of the first aspect the hardware protection device is configured to disable the at least two cells by disabling control signal supply of the controller.

[0052] In an implementation form of the second aspect the method step of sending the trip signal is uphold (e.g., continuously) by the fault protection device until the method step of enabling of the disabled at least two cells when the first reset condition and the second reset condition are met is performed. With this exemplary configuration the uphold trip signal may overrule any other control signal so that the disable of the respective cells, respectively their semiconductor switches, is continued. The method step of enabling of the disabled at least two cells hereby may comprise terminating the uphold sending of the trip signal. This ensures a further safe operation of the interleaved converter, as the enabling is only performed when no trip signal is present.

[0053] In an implementation form of the second aspect the method step of enabling, by the fault protection device, the at least two disabled cells comprise the method step of:

[0054] sending a reset signal, exemplary to the controller and / or the hardware protection device; whereby further exemplary the controller and / or the hardware protection device performs the method step of enabling the disabled at least two cells upon receival of the reset signal, exemplary with the additional method step of:

[0055] enabling the controlling of the at least two cells via respective control signals.

[0056] This provides additional or alternative exemplary configurations for a safe and effective enabling of the respective cells.

[0057] In an implementation form of the second aspect the method further comprises the method step of:

[0058] detecting, by the fault protection device, a normal operation in the operation parameter signals, whereby upon detecting the normal operation in the operation parameter signals the fault protection detects the resolve of the fault condition.

[0059] With this exemplary configuration the monitoring of the interleaved converter, respectively of the interleaved converter cells, even during a fault event, i.e. when a fault condition was detected, allows for a simple and effective way to determine the resolve of the fault condition. Based on this detection it may be determined that a normal operation is again possible after enabling of the respective cells.

[0060] In an implementation form of the second aspect the fault condition is at least one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like; whereby the fault protection device is respectively configured for at least one of: an overcurrent protection, an undercurrent protection, an overvoltage protection, an undervoltage protection, an overtemperature protection, a short circuit protection, or the like. Thus, various fault scenarios are manageable with such an exemplary implementation of the method for operation of the respective interleaved converter.

[0061] A third aspect of this disclosure provides a computer program comprising instructions which, when the program is executed by a computer, cause the computer to perform the method according to the second aspect or any of its implementation forms.

[0062] A fourth aspect of this disclosure provides a storage medium storing executable program code which, when executed by a processor, causes the method according to the second aspect or any of its implementation forms to be performed.

[0063] The present disclosure accordingly proposes the balanced operation of a respective interleaved converter in a fault event, i.e. when a fault condition occurs, by controlling the reset timing, i.e. the enabling timing, of the respectively disabled cells of the interleaved converter. Hereby, as contrary to conventional interleaved converters where the reset is performed as soon as the fault condition is resolved, it is ensured that the interleaved cells experience an equal reduction in their duty cycles during thetrip period, i.e. during the period where the cells are disabled due to a respective trip triggering fault event (e.g., such as an overcurrent protection event).

[0064] It is noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. The various implementation forms of the herein disclosed aspects are combinable with one another as should be clear for a skilled person.

[0065] BRIEF DESCRIPTION OF DRAWINGS

[0066] The above described aspects and implementation forms will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which:

[0067] FIG. 1 shows schematically an interleaved converter according to an exemplary embodiment of this disclosure;

[0068] FIG. 2 shows schematically a part of an interleaved converter according to an exemplary embodiment of this disclosure;

[0069] FIG. 3 shows schematically a part of an interleaved converter according to an exemplary embodiment of this disclosure with an exemplary implementation of the cells of the interleaved converter;

[0070] FIG. 4 shows schematically a part of an exemplary embodiment of an interleaved converter;

[0071] FIG. 5 shows schematically an exemplary pulse width modulation, PWM, operation of an exemplary embodiment of an interleaved converter as shown in Figure 4;

[0072] FIG. 6A shows schematically exemplary operation parameter curves of an exemplary embodiment of an interleaved converter as shown in Figure 5 with current values through each of the respective conventional interleaved converter cells and the combined current value;

[0073] FIG. 6B shows schematically an enlarged portion of the operation parameter curves of Figure 6A;

[0074] FIG. 7 shows schematically a part of an interleaved converter according to a further exemplary embodiment of this disclosure;

[0075] FIG. 8 shows schematically an exemplary pulse width modulation, PWM, operation of an exemplary embodiment of an interleaved converter according to an exemplary embodiment of this disclosure;FIG. 9A shows schematically exemplary operation parameter curves of an exemplary embodiment of an interleaved converter according to an exemplary embodiment of this disclosure with current values through each of the respective interleaved converter cells and the combined current value;

[0076] FIG. 9B shows schematically an enlarged portion of the operation parameter curves of Figure 9A;

[0077] FIG. 10 shows schematically a method according to an exemplary embodiment of this disclosure.

[0078] DETAILED DESCRIPTION OF EMBODIMENTS

[0079] Conventional interleaved converters are used in a broad variety of applications. Hereby, interfacing DC load or source to an AC load or source can be achieved via respective DC / AC or AC / DC converter structures. Such power converters in a DC / AC implementation (DC / AC power converter) are used in many applications such as energy harvesting process from renewable energy (RE) sources and powering electric vehicles (EV). Also, in an AC / DC implementation such power converters (AC / DC rectifiers) are widely used in grid connected applications such as battery chargers and power factor correction applications. Their impact on system efficiency, reliability and cost-effectiveness make them a crucial stage in power conversion systems.

[0080] Interleaving is a prominent technique applied in power electronics, especially within AC / DC or DC / AC converters, such as those used in solar inverters, uninterruptible power supplies, UPS, fast chargers, and so forth. The respective interleaved converters hereby comprise a respective number of cells that are controlled in an interleaved manner, wherein each cell comprises at least two semiconductor switches. Hereby, various implementations of the cell configuration is possible, such as a 2L-leg configuration, a 3L-NPC (neutral point clamped) configuration, a 3L-T-type configuration, whereas also other cell configurations are possible as known to the skilled person. This approach of interleaving helps distribute stress across semiconductor devices and helps in reducing the size of passive components, enhancing efficiency and component longevity of the converter. An aspect of interleaving lies in maintaining current balance between individual cells in normal steady-state and transient conditions, so that inductors avoid saturation under varying operating conditions. Achieving a balanced operation under normal steady-state and transient conditions is established. However, effective balancing during abnormal conditions, i.e. during a fault event (e.g. such as grid faults, overcurrent, overvoltage etc.), is currently not available with conventional interleaved converters.

[0081] In conventional interleaved converters the operation of overcurrent protection, OCP, systems are implemented to trigger a trip event, as soon as a respective measured current inside a respective cell of the interleaved converter exceeds a respective specified overcurrent, OC, threshold. The system then resets on the next timer cycle, provided that the current has dropped below the OC value.

[0082] Figure 1 schematically shows an interleaved converter 10 according to an exemplary embodiment of this disclosure. Here the interleaved converter 10 comprises at least two cells 110, 110-1, 110-2 ... 110-z, wherein each cell 110, 110-1, 110-2 ... 110-z comprises:

[0083] at least two semiconductor switches 110SW1, 110SW2, 110-1SW1, I I0-ISW2:

[0084] a measurement device 115 for measuring operation parameters of the respective cell 110, 110-1, 110-2 ... 110-z.

[0085] Furthermore, the interleaved converter 10 comprises a controller 1110 and a fault protection device 1140. The controller is hereby for controlling the at least two cells 110, 110-1, 110-2 ... 110-z by supplying respective control signals 1150. In thisregard the controller is configured to control each cell 110, 110-1, 110-2, ..., 110-z with a same switching period tsw and with a same duty cycle dsw, wherein the cells 110, 110-1, 110-2, ..., 110-z are hereby controlled in an interleaved manner.

[0086] Figure 2 illustrates an exemplary possible implementation of interconnection between respective cells 110 of an interleaved converter 10. Here an m-phase multiphase converter system is shown, whereas per phase a respective same number and same configuration of n cells 110 is provided. As shown the m-phase interleaved power converter is configured for interfacing DC source or load to AC load or source. In the exemplary implementation, an m-phase converter 10 is shown, wherein each phase comprises n cells 110. Consequently, the combined current la, lb ... Im of each phase is composite from the respective current flowing through the individual interleaved cells 110-1 to 110-n of the interleaved converter 10. Exemplary through the respective cells of phase a, the respective individual current Li, Ia2 ... Im is flowing through their respective cell 1 to n. The respective cells 110 of a respective phase a to n are consequently put in parallel to each other. As apparent to the skilled person the herein disclosed interleaved converter 10 and method for operation of an interleaved converter 10 is not limited to a single specific structure of an interleaved converter but is applicable to any interleaved converter 10 independent from its respective cell configuration. In this regard it is exemplary stated that the respective present (at least two) cells 110 of the interleaved converter 10 may have a 2L-leg configuration, a 3L-NPC configuration, a 3L-T-type configuration, or any other cell configuration. The respective semiconductor switches llOsw, llOswi, 110sw2, 110-lswi, 110-lsw2 ... may exemplary be Si-IGBT / MOSFETs, or SiC-MOSFETs, or any others.

[0087] Figure 3 exemplary illustrates an implementation of an interleaved converter 10 and its exemplary cell configuration. Here, the shown exemplary implementation comprises four cells 110, 110-1, 110-2, 110-3, 110-4 interfacing a DC source 101 or DC load 101 to an AC load 102 or AC source 102 (depending on the operation mode of the interleaved converter). A respective cell current Ii, I2, la, I4 flows through the respective cell 110, 110-1, 110-2, 110-3, 110-4, i.e. through the respective semiconductor switch llOsw, llOswi, llOsw?, 110-lswi, 110-lsw2, 110-2swi, 110-2sw2, 110-3swi, 110-3sw2, 110-4swi, 110-4SW2, depending on the switch state of the respective cell 110, 110-1, 110-2, 110-3, 110-4. The semiconductor switch llOsw, llOswi, 110sw2, 110-lswi, 110-lsw2, 110-2swi, 110-2sw2, 110-3swi, 110-3sw2, 110-4swi, 110-4sw2 are hereby controlled via a respective control signal, respectively via a PWM switch signal S, SI, S2, S3, S4. The control signals S, SI, S2, S3, S4 may in particular be part of control signals 1150 supplied via the controller 1110 towards the respective cells 110 of a respective interleaved converter 10, as exemplary indicated in Figure 4 and Figure 7. Figures 5 and 8 respectively focus on the generation of the respective PWM switch signals S, SI, S2, S3, S4 - here respectively with regard to the exemplary implementation of an interleaved converter 10 comprising four cells 110. Other configurations with less than four cells 110, or more than four cells 110, are also conceivable, whereas likewise various configurations concerning the interconnections of the cells 110 are conceivable, depending on the respective desired application scenario.

[0088] The PWM switch signal S, SI, S2, S3, S4 generation is hereby performed via comparison of a respective carrier signal Crl, Cr2, Cr3, Cr4 with a respective reference signal RS. The carrier signal Crl, Cr2, Cr3, Cr4 is typically a triangular or sawtooth waveform signal with a fixed frequency - in the shown exemplary implementation a triangular waveform signal is used for the respective carrier signals Crl , Cr2, Cr3, Cr4. The reference signal RS is generated by a respective control loop of the interleaved converter 10, such as a PI or PID controller. The PI or PID controller may hereby be integrated in the control unit 1000, and in particular in the controller 1110 as exemplary illustrated in Figures 4 and 7. The reference signal RS hereby may represent the desired output, usually a duty cycle proportional to the required voltage or current. The respective carrier signals Crl, Cr2, Cr3, Cr4 and reference signal RS are then fed into a comparator or PWM modulator, to generate the respective switch signals S, SI, S2, S3, S4. Hereby, the switching logic may be that when the reference signal RS is greater than the respective carrier signal Crl, Cr2, Cr3, Cr4, the output of the comparator, i.e. the respective corresponding switching signal S, SI, S2, S3, S4, is HIGH (logic 1), and when the reference signal RS is less than the respective carrier signal Crl, Cr2, Cr3, Cr4, the output, i.e. the respective corresponding switch signal S, SI, S2, S3, S4, is LOW (logic 0) - or vice versa, depending on the respectivelyimplemented logic. Hence, the output of the comparator, i.e. the respective switch signal S, SI, S2, S3, S4 is a PWM signal, and the duty cycle of this PWM signal is determined by the reference signal RS amplitude relative to the respective corresponding carrier signal Crl, Cr2, Cr3, Cr4. As indicated in Figures 5 and 8 the carrier signals Crl, Cr2, Cr3, Cr4 for different phases are offset in time to achieve interleaved operation.

[0089] Figures 4 and 7 show different implementations of the control unit 1000, whereas the implementation of Figure 7 is additionally equipped with a fault protection device 1140 according to this disclosure. In both implementations the interleaved converter 10, respectively each cell 110, comprises a measurement device 115 for measuring operation parameters of the respective cell 110. Moreover, the interleaved converter 10 in each implementation comprises a controller 1110 for controlling the respective cells 110 of the respective interleaved converter 10 by supplying respective control signals 1150 (such as the aforementioned and discussed switch signals S, SI, S2, S3, S4). Furthermore, the controller is configured to control each respective cell 110 with a same switching period tsw and with a same duty cycle dsw.

[0090] Figures 4, 5, 6A and 6B show connected illustrations of a first implementation of an interleaved converter 10 and its operation characteristics. Here the interleaved converter 10 may be exemplary implemented as the interleaved converter 10 known from Figure 3 for illustration purposes. The Figures 7, 8, 9A and 9B likewise show connected illustrations of a second implementation of an interleaved converter 10 and its operation characteristics. Here the interleaved converter 10 may also be exemplary implemented as the interleaved converter 10 known from Figure 3 for illustration purposes.

[0091] In the first implementation the interleaved converter 10 is exemplary implemented as current conventional interleaved converters with regard to the operation of the converter during a respective fault condition F. A fault condition F may hereby be (at least) one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like. In the herein discussed exemplary implementation of the first implementation an overcurrent protection, OP, shall be regarded as the fault condition F. As soon as a respective fault condition is observed, i.e. a respective operation parameter indicating a fault is measured by the measurement device 115 and a respective fault condition F is detected by the controller 1110 a respective fault operation is triggered, hereby - to protect the components of the interleaved converter 10, and to resolve the fault condition - a disable signal, i.e. a so called trip signal, is issued disabling the cells 110, respectively their semiconductor switches 1 lOsw, of the interleaved converter 10.

[0092] In the provided example of Figures 4, 5, 6A and 6B the interleaved converter 10 according to the first implementation the overcurrent protection comprises an overcurrent protection, OCP, system to protect the converter 10 from the fault condition F being an overcurrent. Here the OCP system may be implemented in the control unit 1000 - and hereby may be implemented in the controller 1110 and / or with the hardware protection device 1130. The trip signal is issued as soon as the current inside a respective cell 110 exceeds a predefined overcurrent, OC, threshold, so that the cells 110 (respectively the semiconductor switches llOsw) are deactivated. The OCP system then resets the converter 10, respectively the cells 110, and hereby in particular the semiconductor switches llOsw, on the next timer cycle, provided that the current has dropped below the OC threshold value - i.e. provided that the fault condition F is resolved. The waveforms of PWM generation during normal operation and during the fault operation is exemplary shown in Figure 5.

[0093] In Figure 5 the time point where the trip signal is issued is marked as TT, whereas the time point where the reset signal is issued, resetting the converter 10 after the fault condition F is resolved, is marked as TR. The individual carrier signals Crl, Cr2, Cr3, Cr4 for the respective exemplary four cells 110 of the converter 10, as exemplary shown in Figure 3, are likewise illustrated in Figure 5, with respective different full, dashed or dotted lines. The reference signal RS is also shown. Based on the respective carrier signal Crl, Cr2, Cr3, Cr4 curve and the reference signal RS curve the respective PWM switch signal S, SI, S2, S3, S4 is generated and supplied to the respective cells 110 in normal operation. Upon detection of a fault condition F however the

[0094]

[0095] For the second fault condition F, i.e. the second off-duration toFF the respectively present effective duty cycle deqcan thus be calculated in an analogous manner as:

[0096]

[0097] Overall in this first implementation it is thus to be stated that the dropped duty cycle portions Ad are unequal, as the off-duration toFF affects the respective duty cycle of the respective switch signal S, SI, S2, S3, S4 in an individual manner. In view of the exemplary embodiment of Figure 5 the following relations concerning the dropped duty cycle portions Ad are valid:

[0098] Adi,i > Ad4,i > Ad2,i > Ada, i;

[0099] whereas resulting therefrom, the following relations concerning the effective duty cycle deqof the individual switch signals S 1 , S2, S3, S4 is valid:

[0100]

[0101] Similar relations can be extracted concerning the second fault condition F shown in Figure 5, whereas here the following is valid:

[0102]

[0103] Due to the unequal dropped parts Ad of the duty cycles during the respective trip periods toFF toFFi and toFF2 and, consequently, the respective unequal effective duty cycles dequnbalance arises between the cell currents. This unbalance is cumulative when consecutive OCP trips happen, such as exemplary displayed in Figure 5 with the two consecutive fault conditions F leading to respective trip signals being issued at time points TT and a respective rest being performed at time points TR when the fault condition F is resolved. Such consecutive fault conditions F increase the risk of and in particular promote inductors saturation.

[0104] Figures 6A and 6B exemplary illustrate the result of such an imbalanced operation during a fault condition F event, whereas here the aggregated total current I is displayed, picturing the sum of the individual exemplary currents Ii, I2, la, I4 flowingthrough the exemplary four cells 110, 110-1, 110-2, 110-3, 110-4 of the exemplary implementation of the interleaved converter 10 shown in Figure 3. Figure 6B shows an enlarged section of the graph shown in Figure 6A. In Figures 6A and 6B it is shown that at the beginning of the graph the interleaved converter 10 is at first in normal operation N, with smooth current curves of currents I, Ii, I2, la, I4. However, at around time mark 0.105 a fault condition F occurs, in the present exemplary implementation: an overcurrent, OC, leading to an unbalanced, and instable operation of the interleaved converter 10.

[0105] Therefore, overall in the exemplary first implementation of the interleaved converter upon entering a fault operation, a trip is triggered when the trip condition is satisfied (e.g., a current in at least one of the cells exceeds a predetermined overcurrent, OC, threshold). This will disable all the semiconductor switches in the cells of the converter to safeguard the converter. Following the fault condition F disappears (e.g. the respective current has dropped back below the OC value), a reset takes place immediately - as exemplary illustrated in Figure 5. However, in interleaved converters, such consecutive fault trips can cause abrupt or severe imbalances in the interleaving operation. These imbalances are due to the duty cycles not being uniformly adjusted during the respective off-time duration topp.

[0106] With regard to the previously discussed first implementation the basic functioning of an interleaved converter 10 is described. As apparent this first implementation has operational flaws with regard to operation during a fault condition F. Hence, subsequently a second implementation of an interleaved converter 10, respectively of a method for operating the interleaved converter 10, is provided. Here, the basic functioning concerning the fault trigger (i.e., the detection of a fault event and initiation of a fault operation) remains, whereas improvements in the control of the resetting of the converter 10 (respectively its cells 110 and the semiconductor switches 1 lOsw) after a respective fault condition F is resolved are realized. Hence, with the second implementation the fault trigger may act and react as previously described with regard to the first implementation, i.e. the fault trigger reacts essentially immediately when a respective fault condition F is detected (e.g. a respective current exceeds the OC threshold), but resetting the fault state is now explicitly controlled with regard to its timing, so that the reset may only be permitted at predefined time points that ensure that all interleaved cells experience equally dropped duty cycle portions Ad.

[0107] The subsequent description focuses on various exemplary configurations of the second implementation. Each respective configuration is hereby compatible for combination with respective other configurations.

[0108] The Figures 7, 8, 9A and 9B show an exemplary second implementation of the interleaved converter 10. As apparent the interleaved converter 10 of the second implementation comprises a fault protection device 1140. The fault protection device 1140 is part of the control unit 1000. In Figure 7 this fault protection device 1140 is particularly illustrated as being part of the control entity 1100, that comprises the controller 1110 and the hardware protection device 1130. The here shown illustration is a mere example, whereas it is apparent that the fault protection device 1140 may be implemented as an entity besides the control entity 1100, may be implemented as a component inside the control entity 1100 besides the controller 1110 and the hardware protection device 1130 (as illustrated in Figure 7), may be at least partially part of the controller 1110, or may be at least partially part of the hardware protection device 1130.

[0109] In view of Figure 3 and Figure 7 the therein disclosed exemplary interleaved converter 10 comprises a number of cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z (four cells in the provided example), that are controlled in an interleaved manner, wherein eachcell llO, 110-1, 110-2, ..., 110-n, ..., 110-z comprises at least two semiconductor switches llOswi, 110sw2, 110-lswi, 110-1 sw2j and a measurement device 115 for measuring operation parameters of the respective cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z. The interleaved converter 10 further comprises a controller 1110 for controlling the respective number of cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z by supplying respective control signals 1150,wherein the controller is configured to control each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z with a same switching period tsw and with a same duty cycle dsw. Further, the converter 10 comprises a fault protection device 1140, wherein the fault protection device 1140 is configured:

[0110] to monitor the operation parameter signals from each measurement device 115, and hereby further configured to detect a fault condition F in the operation parameter signals;

[0111] when a fault condition F is detected, to disable the respective present cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z, wherein by disabling these cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z a respective portion A of the duty cycle dsw of each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z is lost, resulting in a respective individual lost duty cycle value Ad of each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z;

[0112] when the respective present cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z are disabled, determine a first reset condition for enabling the disabled at least two cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z, wherein the first reset condition is met when the individual lost duty cycle value Ad of each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z is equal; when the at least two cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z are disabled, to enable the disabled at least two cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z when the first reset condition is met and when a second reset condition is met, wherein the second reset condition is met when the fault condition F is resolved.

[0113] With this implementation it is achieved that the respective present interleaved cells 110 have an equal dropped duty cycle value Ad in their duty cycles dsw during the fault condition period, i.e. during the disabling duration torr, tom, torrs of the cells. Thus, the reset timing of the cells by the fault protection device is individually evaluated as per the trip instant. As a result abrupt and severe imbalances in the operation of the interleaved converter 10 are avoided. Further, with this second implementation the size and cost of coupled / uncoupled inductors may be reduced by achieving better current balancing, thereby further lowering the risk of saturation. Additionally, loss distribution between cells is further optimized, eliminating the need for oversized semiconductors and enhancing overall efficiency, power density and cost-effectiveness.

[0114] Hence, in view of Figure 8 corresponding to an exemplary PWM switch signal S generation for the respective cells 110 of the converter 10 according to the exemplary second implementation it is achieved that all interleaved cells 110 experience an equal reduction in their duty cycles dsw during the respective fault period, i.e. the disabling duration topp. Hence the following relations are valid with regard to the illustrated example:

[0115]

[0116] With regard to a respective second or Xthfault event the following is likewise valid:

[0117] Adi, 2=Ads, 2=Ads, 2=Ad4,2

[0118] (with Adi, 2 = Adla,2 + Adlb,2; Ad2,2 = Ad2a,2 + Ad2b,2; Ads, 2 = Adsa,2 + Adsb,2);

[0119] Adi,x= Ad2,x= Ads,x= Ad4,x; and thus:

[0120] deql,2 = deq2,2 = deq3,2 = deq4,2; and

[0121] deql,x—deq2,x—deq3,x—deq4,x.

[0122] More general, with the converter 10 according to an exemplary embodiment of a second implementation: for a number n of cells 110 present in a respective interleaved converter 10 the individual lost duty cycle value Ad of each cell 110 for a respective fault event thus fulfil the requirement of:

[0123] Adi = d2 = ... = Adn.

[0124]

[0125] Furthermore, the fault protection device 1140 may be configured to enable the respective disabled present cells 110 simultaneously, when the first reset condition and the second reset condition are met. This exemplary configuration is also exemplary illustrated in the example of the second implementation shown in Figure 8.

[0126] Also, it is conceivable that the fault protection device 1140 may be configured to enable the respective disabled present cells 110 individually per cell 110, when the first reset condition and the second reset condition are met. With this configuration, consistent volt-seconds may be further easily achieved across all cells by individually setting their reset timing at different instants, in particular aligned with their respective switching duty cycles. In a further example, depending on the fault scenario the fault protection device 1140 may be configured to perform the enabling of at least two of the respective disabled present cells 110 by the fault protection device 1140 in a staggered manner.

[0127] The initiation of the off-duration toFF, i.e. the sending of the trip signal at the respective time point TT may be performed by the fault protection device. Thus, the fault protection device 1140 may be configured to disable the at least two cells 110 when a fault condition F is detected by sending the trip signal. In this regard the fault protection device 1140 may in particular be configured to send the trip signal to the controller 1110 upon detection of the fault condition F, whereby the controller 1110 may be configured to disable the respective present cells 110 upon receival of the trip signal, whereas it is conceivable that this is performed by disabling the control signal supply 1150.

[0128] As previously described and as shown in particular in F igure 7 the interleaved converter 10 may comprise a hardware protection device 1130, wherein in such a configuration the fault protection device 1140 is configured to send the trip signal to the hardware protection device 1130 upon detection of the fault condition F, and the hardware protection device 1130 is configured to disable the respective present cells 110 of the converter 10 upon receival of the trip signal. In this regard it may be further conceivable that the hardware protection device 1130 is configured to disable the respective present cells 110 by disabling control signal supply 1150 of the controller 1110, so that in particular the respective switch signals S may not be supplied to the respective cells 110.

[0129] Furthermore, there are different exemplary options available on how the reset of the converter 10, respectively it cells 110 may be performed. One option may be that the fault protection device 1140 is configured to uphold the trip signal until the enabling of the disabled respective present cells 110 when the first reset condition and the second reset condition are met. Hence, the respective trip signal is present over the whole toFF period, so that no other control signals may be received by the respective cells 110, respectively their semiconductor switches 1 lOsw ensuring the disabling thereof. Hereby, the fault protection device1140 may be further configured to enable the respective disabled cells 110 when the first reset condition and the second reset condition are met, by terminating the uphold trip signal. Thus, the trip signal is terminated as soon as the first and second reset condition are met, so that the previously disabled cells 110 are activated, i.e. enabled again, so that normal operation of the converter 10 is performed. Here, the reset of the cells 110 is thus initiated by the removal of previously (uphold) issued signal. Also - additionally or alternatively - the fault protection device 1140 may be configured to enable the respective disabled cells 110 when the first reset condition and the second reset condition are met, by sending a reset signal. Hence, the reset of the cells 110 may be initiated by an active sending of a signal. Hereby, the fault protection device 1140 may be further configured to send the reset signal to the controller 1110 and / or to the hardware protection device 1130 (if present). Hereby it is moreover conceivable that the controller 1110 and / or the hardware protection device 1130 may be configured to enable the respective disabled cells 110 upon receival of the reset signal. This may be performed by enabling the control signal supply 1150.

[0130] In a further exemplary configuration, the fault protection device 1140 may be configured to detect a normal operation in the operation parameter signals, whereby the fault protection device 1140 is further configured to detect the resolve of the fault condition F by detecting the normal operation. It is also conceivable that a respective measurement device 115 issues a respective fault condition resolve signal to the fault protection device 1140 so that normal operation can be detected. Also, the fault protection device 1140 may be configured to control the control signal supply 1150 of the controller 1110 towards the respective cells 110.

[0131] As apparent from Figures 9A and 9B this interleaved converter 10 according to the second implementation, respectively the method for operation of the interleaved converter 10, achieves a balanced operation of the interleaved converter 10, and - in view of the provided example - a balanced current between the cells even during consecutive fault events (such as consecutive overcurrent protection, OCP), as indicated in particular in Figure 9B, showing the consecutive torr durations during the respective fault events. Here the current curves of the individual cell currents Ii, I2, la, I4 as well as the combined current I has an improved smoothness. This leads in general to an improved protection of the inductors of the interleaved converter 10 from saturation, and ensures a better loss distribution between the respective cells 110, respectively the semiconductor switches 1 lOsw during the fault / abnormal condition.

[0132] Possible fault conditions F may hereby be at least one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like; whereby the fault protection device 1140 is respectively configured for at least one of: an overcurrent protection, an undercurrent protection, an overvoltage protection, an undervoltage protection, an overtemperature protection, a short circuit protection, or the like.

[0133] The Figure 10 shows an exemplary implementation for a method M100 for operation of an interleaved converter 10, and in particular of an interleaved converter 10 according to any previously described exemplary configuration of the second implementation. The interleaved converter 10 may hereby comprise: a number of (at least two) cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z, wherein each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z comprises: at least two semiconductor switches llOsw, 1 lOswi, 110sw2, 110-lswi, 110-lsw2, ...; a measurement device 115 for measuring operation parameters of the respective cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z; a controller 1110 for controlling the respective present cells 110, 110-1, 110-2, ..., 110-n, ..., 110-z; and a fault protection device 1140.

[0134] The method Ml 00 starts with starting point M101, where a respective interleaved converter 10 is in a normal operation. The method M100 for operation of an interleaved converter 10 hereby comprises in particular the method steps of:

[0135] controlling Ml 10, by the controller 1110, in normal operation the respective present cells 110, 110-1, 110-2, ..., 110- n, ..., 110-z in an interleaved manner via respective control signals 1150, wherein each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z is controlled with a same switching period tsw and each cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z has a same duty cycle dsw;

[0136] measuring, by each measurement device 115, operation parameters of the respective cell 110, 110-1, 110-2, ..., 110-n, ..., 110-z;

[0137] monitoring M120, by the fault protection device 1140, the operation parameter signals from each measurement device 115.

[0138] Thus, method steps Ml 10 to M120 describe operation in the normal operation of the converter 10. In subsequent method step Ml 30 the fault protection device 1140 checks if the monitored operation parameter signals include a fault condition F. If no fault condition is detected Ml 31 normal operation N of the converter 10 is present and thus the normal operation mode of the converter 10 is maintained. If however a fault condition F is present with at least one of the respective present cells 110, the fault protection device 1140 detects M134 the respective fault condition F in the monitored operation parameter signals. Thus, a fault F is present so that the converter 10 may now operate in a fault operation.

[0139] Due to the detection Ml 34 of the fault condition F and the converter 10 thus being in a fault operation the fault protection device 1140 disables M140 the respective present cells 110 of the converter 10. This is performed to protect the components of the converter 10 from any damage, and to quickly resolve the fault condition F. Hereby, by disabling M140 the respective present cells 110 a respective portion of the duty cycle dsw of each cell 110 is lost, resulting in a respective individual lost duty cycle value Ad of each cell 110 (as illustrated and described in particular in view of Figure 8). The disabling Ml 40 may be performed in various conceivable manners, as previously described. Hereby in particular it may be conceivable that a trip signal is issued, whereas said trip signal may further be uphold for the duration of the fault operation, i.e. the duration of the disabling time toFF. Also, it is exemplary conceivable that the fault operation is resolved by issuing a respective resolve signal.

[0140] With the cells 110 being disabled the converter 10, respectively the fault protection device 1140 may proceed M145 with operations to identify conditions for resolving the fault operation. Hereby the fault protection device 1140 determines Ml 50 a first reset condition for enabling the respective disabled cells 110, wherein the first reset condition is met when the individual lost duty cycle value Ad of each cell 110 is equal. Thus, the above mentioned and described mathematical relation of the lost duty cycle value Ad of n cells of a respective converter 10 may be used for determination if the first reset condition is met: Adi = Ad? = ... = Adn.

[0141] Hence, with this configuration it is ensured, that all respective cells 110 of the converter 10 are in a balanced operation, as the individual lost duty cycle value Ad is monitored and control of the reset is based on the respective condition. If the first reset condition is met Ml 56 the fault protection device 1140 may check the resolving M160 of the fault condition F. The resolving M160 of the fault condition F hereby constitutes the second reset condition. If however the first reset condition is not met, the disabling of the cells 110, and thus the fault operation, may be uphold M154 continuing with method step M140. If however the second reset condition is not met, the disabling of the cells 110, and thus the fault operation, may be upholdM164 continuing with method step M140. Hence, only when the first and second reset condition are met M156, Ml 67 the fault protection device 1140 may continue with enabling M170 of the respective disabled cells 110.

[0142] With regard to an exemplary implementation the method Ml 00 the method may further comprise the method step of:

[0143] detecting Ml 60, by the fault protection device 1140, a normal operation in the operation parameter signals, whereby upon detecting the normal operation in the operation parameter signals the fault protection detects the resolve of the fault condition F.Here it is noted that the method steps of determining Ml 50 the first reset condition, and the monitoring / resolving Ml 60 the second reset condition (as well as the related method steps Ml 56, Ml 54, Ml 67, and Ml 64) may be performed simultaneous, or in another succession different from the above exemplary description.

[0144] With performing the enabling M170 the converter 10 is returned M171 to normal operation N, with the respective controlling Ml 10 of the cells 110 by the controller 1110.

[0145] With regard to an exemplary implementation the method M100 the first reset condition may be met when each respective cell 110 has a same effective duty cycle deq, wherein the effective duty cycle deqof a respective cell 110 is the difference of the duty cycle dsw and the respective individual lost duty cycle value Ad. Alternatively or additionally the first reset condition of each cell 110 having a same effective duty cycle deqmay be met when a disabling-duration torr, tom, torr? of the disabling of the respective present cells 110 is a positive integer multiple of the switching period tsw. Here in this regard the mathematical relations described with regard to Figures 7, 8, 9A, and 9B apply likewise.

[0146] With regard to an exemplary implementation the method M100 the method step of enabling M170, by the fault protection device 1140, the respective disabled cells 110 is performed simultaneously for the respective cells 110. It is also conceivable that the method step of enabling M170, by the fault protection device 1140, the respective disabled cells 110 is performed by the fault protection device 1140 individually per cell 110, and this may be in particular realized in a staggered manner.

[0147] With regard to an exemplary implementation the method M100 the method step of disabling M140, by the fault protection device 1140, the respective cells 110 comprises the additional method step of:

[0148] sending, by the fault protection device 1140, a trip signal.

[0149] In this regard the fault protection device 1140 may send the trip signal to the controller 1110 upon detecting the fault condition F, whereby the controller 1110 then performs the method step of disabling M140 the respective cells 110 upon receival of the trip signal. This may further be realized by the additional method step of:

[0150] disabling the controlling of the respective cells 110 via respective control signals 1150.

[0151] Hence, the controlling of the respective cells 110 via respective control signals 1150 is disabled by the fault protection device 1140.

[0152] Additionally or alternatively, the interleaved converter 10 may comprise a hardware protection device 1130, whereby the fault protection device 1140 then may send the trip signal to the hardware protection device 1130 upon detecting Ml 34 the fault condition F. Then, the hardware protection device 1130 may perform the method step of disabling M140 the respective cells 110 upon receival of the trip signal. This may further be realized by the additional method step of:

[0153] disabling the controlling of the respective cells 110 via respective control signals 1150.

[0154] Hence, the controlling of the respective cells 110 via respective control signals 1150 is disabled by the hardware protection device 1130 being controlled by the fault protection device 1140.

[0155] With regard to an exemplary implementation the method Ml 00 the method step of sending the trip signal is uphold, preferably continuously, by the fault protection device 1140 until the method step of enabling M170 of the respective disabled cells 110, when / if the first reset condition and the second reset condition are met, is performed. In this regard the method step of enabling M170 of the respective disabled cells 110 may comprise terminating the uphold sending of the trip signal.With regard to an exemplary implementation the method M100 the method step of enabling M170, by the fault protection device 1140, the respective disabled cells 110 comprises the method step of:

[0156] sending a reset signal, preferably to the controller 1110 and / or the hardware protection device 1130.

[0157] Here the controller 1110 and / or the hardware protection device 1130 may then perform the method step of enabling M170 the respective disabled cells 110 upon receival of the reset signal. This may further be realized by the additional method step of:

[0158] enabling the controlling of the respective cells 110 via respective control signals 1150.

[0159] Hence, the controlling of the respective cells 110 via respective control signals 1150 is enabled by the controller 1110 and / or the hardware protection device 1130 being controlled by the fault protection device 1140.

[0160] With regard to an exemplary implementation the method M100 the fault condition F may be at least one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like; whereby the fault protection device 1140 is respectively configured for at least one of: an overcurrent protection, an undercurrent protection, an overvoltage protection, an undervoltage protection, an overtemperature protection, a short circuit protection, or the like.

[0161] According to a respective implementation a computer program is provided. The computer program comprising instructions which, when the program is executed by a computer, cause the computer to perform the method steps of the fault protection device 1140 of the method Ml 00 according to any one of the presented exemplary implementations thereof.

[0162] Thus, an interleaved converter 10 and a method Ml 00 for operation thereof is described. The interleaved converter 10 hereby comprises at least two cells 110 that are controlled in an interleaved manner, wherein each cell 110 comprises: at least two semiconductor switches 110SW; and a measurement device 115 for measuring operation parameters of the respective cell 110. The interleaved converter 10 further comprises: a controller 1110 for controlling the at least two cells 110 by supplying respective control signals 1150, wherein the controller is configured to control each cell 110 with a same switching period tSW and with a same duty cycle dSW; and a fault protection device 1140. The fault protection device 1140 is configured to monitor the operation of the cells 110 and to detect a fault condition F, wherein when a fault condition F is detected, to fault protection device 1140 is configured to disable the cells 110. By disabling the at least two cells 110 a respective portion of the duty cycle dSW of each cell 110 is lost, resulting in a respective individual lost duty cycle value Ad of each cell 110. The disabled at least two cells 110 are enabled when the individual lost duty cycle value Ad of each cell 110 is equal and when the fault condition F is resolved.

[0163] It is apparent to the skilled person that the herein proposed beneficial second implementation that is exemplary displayed with Figures 3, 7, 8 and 9 (as well as the corresponding exemplary method shown in Figure 10) is not limited to the specific configuration of components of the converter 10. Configurations exemplary described with regard to the first implementation but not explicitly mentioned with regard to the second implementation may - if not described otherwise - also be applicable to the second implementation, as apparent for the skilled person.

[0164] The underlying concept exemplary described in view of the second implementation can be used in any n-cell interleaved converter (n = 1, 2, ... ). The proposed technique can also be used as bidirectional operation of the converter; rectification and inversion mode. As an example, the herein proposed interleaved converter 10 may be used in PV applications, energy storage systems, EV applications or any power conversion system that has a DC / AC conversion stage.

[0165] The converter 10, and in particular the control unit 1000 thereof, may comprise a processor or processing circuitry (not shown) configured to perform, conduct or initiate the various operations of the device described herein. The processing circuitry maycomprise hardware and / or the processing circuitry may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as applicationspecific integrated circuits (ASICs), field-programmable arrays (FPGAs), digital signal processors (DSPs), or multi-purpose processors. The device may further comprise memory circuitry, which stores one or more instruction(s) that can be executed by the processor or by the processing circuitry, in particular under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed by the processor or the processing circuitry, causes the various operations of the device to be performed. In one embodiment, the processing circuitry comprises one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code which, when executed by the one or more processors, causes the device to perform, conduct or initiate the operations or methods described herein.

[0166] The present disclosure has been described in conjunction with various configurations as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed matter, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

CLAIMS1. An interleaved converter (10) comprising:at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z), that are controlled in an interleaved manner, wherein each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) comprises:at least two semiconductor switches (110SW, 110SW1, 110SW2, 110-1SW1, 110-1SW2, ...); a measurement device (115) for measuring operation parameters of the respective cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z);a controller (1110) for controlling the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) by supplying respective control signals (1150),wherein the controller is configured to control each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) with a same switching period (tsw) and with a same duty cycle (dsw);a fault protection device (1140), wherein the fault protection device (1140) is configured:to monitor the operation parameter signals from each measurement device (115), and hereby further configured to detect a fault condition (F) in the operation parameter signals;when a fault condition (F) is detected, to disable the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z), wherein by disabling the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) a respective portion of the duty cycle (dsw) of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is lost, resulting in a respective individual lost duty cycle value (Ad) ofeach cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z);when the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) are disabled, determine a first reset condition for enabling the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z), wherein the first reset condition is met when the individual lost duty cycle value (Ad) of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is equal;when the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) are disabled, to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when the first reset condition is met and when a second reset condition is met, wherein the second reset condition is met when the fault condition (F) is resolved.

2. An interleaved converter (10) according to claim 1,wherein the first reset condition is met when each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) has a same effective duty cycle (deq), wherein the effective duty cycle (deq) of a respective cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is the difference of the duty cycle (dsw) and the respective individual lost duty cycle value (Ad); and / orwherein the first reset condition of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) having a same effective duty cycle (deq) is met when a disabling-duration (torr, tom, torr?) of the disabling of the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is a positive integer multiple of the switching period (tsw).

3. An interleaved converter (10) according to claims 1 or 2,wherein the fault protection device (1140) is configured to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) simultaneously, when the first reset condition and the second reset condition are met.

4. An interleaved converter (10) according to any one of the preceding claims,wherein the fault protection device (1140) is configured to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) individually per cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z), when the first reset condition and the second reset condition are met;wherein preferably the fault protection device (1140) is configured to perform the enabling of at least two of the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) by the fault protection device (1140) in a staggered manner.

5. An interleaved converter (10) according to any one of the preceding claims,wherein the fault protection device (1140) is configured to disable the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when a fault condition (F) is detected by sending a trip signal.

6. An interleaved converter (10) according to claim 5,wherein the fault protection device (1140) is configured to send the trip signal to the controller (1110) upon detection of the fault condition (F), whereby the controller (1110) is configured to disable the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) upon receival of the trip signal,wherein preferably the controller (1110) is configured to disable the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) by disabling the control signal supply (1150).

7. An interleaved converter (10) according to claim 5 or 6,wherein the interleaved converter (10) comprises a hardware protection device (1130),wherein the fault protection device (1140) is configured to send the trip signal to the hardware protection device (1130) upon detection of the fault condition (F),wherein the hardware protection device (1130) is configured to disable the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) upon receival of the trip signal,wherein preferably the hardware protection device (1130) is configured to disable the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) by disabling control signal supply (1150) of the controller (1110).

8. An interleaved converter (10) according to any one of the preceding claims 5 to 7,wherein the fault protection device (1140) is configured to uphold the trip signal until the enabling of the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when the first reset condition and the second reset condition are met; wherein preferably the fault protection device (1140) is configured to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when the first reset condition and the second reset condition are met, by terminating the uphold trip signal.

9. An interleaved converter (10) according to any one of the preceding claims,wherein the fault protection device (1140) is configured to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when the first reset condition and the second reset condition are met, by sending a reset signal, wherein preferably the fault protection device (1140) is further configured to send the reset signal to the controller (1110) and / or the hardware protection device (1130),wherein further preferably the controller (1110) and / or the hardware protection device (1130) is configured to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) upon receival ofthe reset signal,wherein further preferably the controller (1110) and / or the hardware protection device (1130) is configured to enable the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) by enabling the control signal supply (1150).

10. An interleaved converter (10) according to any one of the preceding claims,wherein the fault protection device (1140) is configured to detect a normal operation in the operation parameter signals, whereby the fault protection device (1140) is further configured to detect the resolve of the fault condition (F) by detecting the normal operation.

11. An interleaved converter (10) according to any one of the preceding claims,wherein the fault protection device (1140) is configured to control the control signal supply (1150) of the controller (1110) towards the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z).

12. An interleaved converter (10) according to any one of the preceding claims,wherein the fault protection device (1140) is at least partially part of the controller (1110); and / orwherein the fault protection device (1140) is at least partially an external component to the controller (1110); and / or wherein preferably the fault protection device (1140) is at least partially part of the hardware protection device (1130).

13. An interleaved converter (10) according to any one of the preceding claims,wherein the fault condition (F) is at least one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like; whereby the fault protection device (1140) is respectively configured for at least one of: an overcurrent protection, an undercurrent protection, an overvoltage protection, an undervoltage protection, an overtemperature protection, a short circuit protection, or the like.

14. A method (M100) for operation of an interleaved converter (10),the interleaved converter (10) comprising:at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z), wherein each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) comprises:at least two semiconductor switches (llOsw, llOswi, 110sw2, 110-lswi, 110-lsw2, ...);a measurement device (115) for measuring operation parameters of the respective cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z);a controller (1110) for controlling the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z); a fault protection device (1140);wherein the method (Ml 00) comprises the method steps of:controlling (Ml 10), by the controller (1110), in normal operation the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) in an interleaved manner via respective control signals (1150), wherein each cell(110, 110-1, 110-2, ..., 110- n, ..., 110-z) is controlled with a same switching period (tSW) and each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) has a same duty cycle (dSW);measuring, by each measurement device (115), operation parameters of the respective cell (110, 110-1, 110-2, ..., 110- n, ..., 110-z);monitoring (M120), by the fault protection device (1140), the operation parameter signals from each measurement device (115);wherein when a fault condition (F) is present with at least one of the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z), the method comprising:a. detecting (M134), by the fault protection device (1140), the fault condition (F) in the operation parameter signals;b. disabling (M140), by the fault protection device (1140), the at least two cells (110, 110-1, 110-2, ..., 110- n, ..., 110-z) wherein by disabling (M140) the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) a respective portion of the duty cycle (dsw) of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is lost, resulting in a respective individual lost duty cycle value (Ad) of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z);c. determining (Ml 50), by the fault protection device (1140), a first reset condition for enabling the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z), wherein the first reset condition is met when the individual lost duty cycle value (Ad) of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is equal; d. enabling (Ml 70), by the fault protection device (1140), the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when the first reset condition is met (Ml 56) and when a second reset condition is met (Ml 67), wherein the second reset condition is met when the fault condition (F) is resolved (Ml 60).

15. A method (M100) for operation of an interleaved converter (10) according to claim 14,wherein the first reset condition is met when each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) has a same effective duty cycle (deq), wherein the effective duty cycle (deq) of a respective cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is the difference of the duty cycle (dsw) and the respective individual lost duty cycle value (Ad); and / orwherein the first reset condition of each cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z) having a same effective duty cycle (deq) is met when a disabling-duration (torr, tom, lorn) of the disabling of the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is a positive integer multiple of the switching period (tsw).

16. A method (M100) for operation of an interleaved converter (10) according to any one of the claims 14 or 15, wherein the method step of enabling (M170), by the fault protection device (1140), the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is performed simultaneously for the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z).

17. A method (M100) for operation of an interleaved converter (10) according to any one of the claims 14 to 16, wherein the method step of enabling (M170), by the fault protection device (1140), the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is performed by the fault protection device (1140) individually per cell (110, 110-1, 110-2, ..., 110-n, ..., 110-z);wherein preferably the method step of enabling (M170), by the fault protection device (1140), the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) is performed by the fault protection device (1140) in a staggered manner.

18. A method (M100) for operation of an interleaved converter (10) according to any one of the claims 14 to 17, wherein the method step of disabling (M140), by the fault protection device (1140), the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) comprises the additional method step of:sending, by the fault protection device (1140), a trip signal;wherein preferably the fault protection device (1140) sends the trip signal to the controller (1110) upon detecting the fault condition (F), whereby the controller (1110) performs the method step of disabling (M140) the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) upon receival of the trip signal, further preferably by the additional method step of:disabling the controlling of the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) via respective control signals (1150);and / orwherein preferably the interleaved converter (10) comprises a hardware protection device (1130), whereby the fault protection device (1140) sends the trip signal to the hardware protection device (1130) upon detecting (M134) the fault condition (F), whereby the hardware protection device (1130) performs the method step of disabling (M140) the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) upon receival of the trip signal, further preferably by the additional method step of:disabling the controlling of the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) via respective control signals (1150).

19. A method (M100) for operation of an interleaved converter (10) according to claim 18,wherein the method step of sending the trip signal is uphold, preferably continuously, by the fault protection device (1140) until the method step of enabling (M170) of the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) when the first reset condition and the second reset condition are met is performed;wherein preferably the method step of enabling (M170) of the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) comprises terminating the uphold sending of the trip signal.

20. A method (M100) for operation of an interleaved converter (10) according to any one of the claims 14 to 19, wherein the method step of enabling (M170), by the fault protection device (1140), the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) comprises the method step of:sending a reset signal, preferably to the controller (1110) and / or the hardware protection device (1130); whereby further preferably the controller (1110) and / or the hardware protection device (1130) performs the method step of enabling (M170) the disabled at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) upon receival of the reset signal, preferably with the additional method step of:enabling the controlling of the at least two cells (110, 110-1, 110-2, ..., 110-n, ..., 110-z) via respective control signals (1150).

21. A method (M100) for operation of an interleaved converter (10) according to any one of the claims 14 to 20, wherein the method further comprises the method step of:detecting (M160), by the fault protection device (1140), a normal operation in the operation parameter signals, whereby upon detecting the normal operation in the operation parameter signals the fault protection detects the resolve of the fault condition (F).

22. A method (M100) for operation of an interleaved converter (10) according to any one of the claims 14 to 21, wherein the fault condition (F) is at least one of: an overcurrent, an undercurrent, an overvoltage, an undervoltage, an overtemperature, a short circuit, or the like; whereby the fault protection device (1140) is respectively configured for at least one of: an overcurrent protection, an undercurrent protection, an overvoltage protection, an undervoltage protection, an overtemperature protection, a short circuit protection, or the like.

23. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to perform the method steps of the fault protection device (1140) of the method according to any one of the preceding claims 14 to 22.

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