Semiconductor element and method for applying a buffer layer

Abstract

The invention relates to a semiconductor element (4) having a defined surface roughness on the front side (V), which is characterised by an average roughness depth (Rz) of 5 μm to 90 μm, in particular 30 μm to 90 μm, and an average groove width (RSm) of 2 μm to 80 μm. This special surface structure serves as an optimal base for applying a buffer layer (P) by means of thermal spraying. The method according to the invention for applying the buffer layer comprises selecting the particle diameter (d) on the basis of the surface roughness, wherein the diameter is selected such that the roughness corresponds approximately to 1.5 to 3 times the splat diameter (ds). This specific matching achieves optimal clamping and adhesion of the sprayed-on layer. The invention enables cost-effective production of semiconductor components with improved properties, in particular with regard to service life and electrical contacting.

Description

[0001] 202500098

[0002] 1

[0003] Description

[0004] Semiconductor element and method for applying a buffer layer

[0005] The present disclosure relates to semiconductor elements and buffer layers, and in particular to a semiconductor element with a specific surface roughness, a method for applying a buffer layer to a semiconductor element by means of a thermal spraying process and a semiconductor device containing such elements.

[0006] Semiconductor devices are widely used in various electronic applications, from consumer electronics to industrial equipment. These devices typically comprise a semiconductor element made from materials such as silicon, gallium arsenide, gallium nitride, or silicon carbide. The semiconductor element, or a resulting semiconductor component such as IGBTs or diodes, has a front and a back, with the front often containing active regions where electronic components are formed.

[0007] In the manufacturing process of semiconductor devices, it is common practice to apply various layers to the surface of the semiconductor element. These layers can serve different purposes, such as providing electrical connections, protecting the underlying semiconductor material, or improving the device's performance. One such layer, which has gained importance in recent years, is the buffer layer.

[0008] Buffer layers are typically applied to the front face of the semiconductor device and serve several purposes. They can help distribute forces during subsequent processing steps, improve thermal management, and enhance the electrical properties of the device. However, applying buffer layers to semiconductor devices presents several challenges.

[0009] A significant challenge lies in achieving proper adhesion between the buffer layer and the semiconductor surface. Poor adhesion can lead to delamination, reduced device reliability, and decreased performance.

[0010] 2

[0011] WO 2023 / 147972 A2 discloses a semiconductor arrangement comprising a semiconductor element with at least one terminal element, wherein a metallic contacting element is applied to the semiconductor element by a thermal spraying process. This contacting element consists of particles forming a textured layer. The aim is to increase the lifetime of the semiconductor arrangement by distributing compressive forces and preventing cracking in the semiconductor. The particles, such as copper and molybdenum, are applied by thermal spraying, creating a porous and resilient structure. This structure compensates for differences in thermal expansion between the semiconductor and the metal and reduces stress. The textured layer consists of larger, flat, deformed particles and smaller, molten particles that act as an adhesive.This layer acts as a buffer, distributing mechanical stresses evenly and thus extending the semiconductor's lifespan. Applications include power converters where the semiconductor assembly must withstand cyclic loads.

[0012] WO 2024 / 099822 A1 discloses a semiconductor arrangement with a switchable semiconductor element having at least one control contact and one load contact. To increase the lifetime of the semiconductor arrangement, an electrically insulating material is applied by additive manufacturing to an area of ​​the load contact adjacent to the control contact contact area to form an insulating layer. Subsequently, a metallic material is applied by thermal spraying to the control contact contact area and the insulating layer to form a metallic control contact element that partially overlaps the load contact contact area. This design distributes the forces occurring during contacting and minimizes thermomechanical stress, thus improving the lifetime of the semiconductor arrangement.The insulating layer can contain polymers with high glass transition temperatures and exhibit thixotropic properties to enhance adhesion and long-term strength. The metallic layer can have a porosity of 1% to 50% to accommodate tolerances. This innovative combination of materials and processes significantly increases the robustness and reliability of the semiconductor assembly.

[0013] The present invention relates to a semiconductor device or semiconductor component and a method for applying a buffer layer to a semiconductor device by means of a thermal spraying process. In particular, a semiconductor device with a specially adapted surface roughness is described, which enables improved adhesion of the sprayed-on buffer layer.

[0014] 3

[0015] The semiconductor element according to the invention has a defined surface roughness on at least some areas of its front surface. This roughness is characterized by an average roughness depth in the range of 5 pm to 90 pm, particularly 30 pm to 90 pm, and an average groove width in the range of 2 pm to 80 pm. The special surface structure serves as an ideal basis for applying a buffer layer by thermal spraying. The ratio between roughness and particle diameter is crucial here.

[0016] The inventive method for applying the buffer layer first comprises setting or determining the surface roughness of the semiconductor element. Based on this roughness, the diameter of the particles of the layer material to be used is then selected. The particle diameter is chosen such that the surface roughness in pm corresponds approximately to 1.5 to 3 times the diameter of a flattened spray particle (splat).

[0017] This targeted matching of particle size to surface roughness achieves optimal interlocking and adhesion of the sprayed layer. The invention thus enables the cost-effective production of semiconductor components with improved properties, particularly with regard to service life and electrical contact.

[0018] The surface roughness of the semiconductor element plays a crucial role in determining adhesion quality. However, controlling and optimizing this roughness while simultaneously maintaining the integrity of the underlying semiconductor structure has proven difficult.

[0019] Another challenge lies in the method for depositing the buffer layer. Conventional deposition techniques may not always deliver the desired layer properties or may subject the semiconductor device to excessive thermal or mechanical stress. This can potentially damage the delicate structures within the semiconductor device.

[0020] Furthermore, the increasing demand for smaller and more efficient semiconductor devices has put additional pressure on manufacturers to develop buffer layer application techniques that are compatible with advanced semiconductor designs and materials.

[0021] Copper wire bonds promise a significantly longer lifespan due to their material properties (higher modulus of elasticity, higher electrical conductivity). 202500098

[0022] 4

[0023] However, copper wire bonding technology has the crucial disadvantage that higher pressure forces are required for bonding compared to aluminum wire bonding, and therefore there is a risk of damaging the semiconductor component.

[0024] It was recognized that a plasma buffer deposition process is needed that overcomes one or more of these problems.

[0025] In a first aspect, a semiconductor element made of semiconductor material is provided, configured for the fabrication of semiconductor components. The semiconductor element comprises a front and a back surface, with at least some areas of the front surface exhibiting a mean roughness depth (Rz) in the range of 30 pm to 90 pm and a mean groove width (RSm) in the range of 2 pm to 80 pm.

[0026] This specific surface roughness profile on the front face of the semiconductor device enables improved adhesion for subsequently applied buffer layers, especially those applied by thermal spraying processes. The defined roughness parameters provide an optimal surface for the mechanical interlocking of sprayed particles, thus improving the overall reliability and performance of the semiconductor device.

[0027] The sub-areas of the semiconductor element can have a total roughness profile height Rt in the range of 3 pm to 540 pm.

[0028] Particle diameter d = 1 - 30 pm = particle size

[0029]

[0030] The diameter of the splat can be 2-6 times the particle diameter, resulting in a range of 2 to 180 µm.

[0031] The roughness should be approximately Rt = 1.5-3*ds (ds = diameter of the splat, which is 2-6 times the particle diameter). This allows for a higher bond strength (better interlocking or cross-linking) during layer deposition due to the uniform deformation of the particle into a splat, resulting in a firm bond with the semiconductor chip. Note: In spraying processes where the splat bursts, adhesion tends to be reduced due to a lack of cohesion within the particle. This occurs more frequently with rougher surfaces, which is why the process window is quite narrow. Ideally, the particle should be completely deformed without complete spattering, and the ratio of roughness to particle size or diameter is crucial for this.

[0032] 5

[0033] This overall height range further optimizes the surface topography for the adhesion of thermally sprayed coatings and allows a balance between sufficient roughness for mechanical interlocking and maintaining the structural integrity of the semiconductor element.

[0034] In a second aspect, a method for applying a buffer layer to a semiconductor device using a thermal spraying process is provided. The method comprises: heating a layer material in particle form, preferably a spherical particle, by a heat source and subsequently applying it at high speed to a surface of a front face of the semiconductor device; setting and / or determining a surface roughness at least in or of partial regions of the front face surface; selecting a particle diameter of the particles of the layer material to be used based on the set and / or determined surface roughness;wherein the particle diameter is selected such that the surface roughness in pm corresponds approximately to 1.5 to 3 times the diameter of a flattened spray particle, wherein the particle is deformed into a splat after impact with the front surface and the surface roughness corresponds approximately to 1.5 to 3 times a splat diameter; and depositing the selected particles onto the front surface of the semiconductor element to form the buffer layer.

[0035] This process enables the creation of a buffer layer with optimal adhesion to the semiconductor device by adapting the particle size to the surface roughness. The specific relationship between particle size, splat formation, and surface roughness ensures effective mechanical interlocking, resulting in a more durable and reliable buffer layer.

[0036] Adjusting the surface roughness of the semiconductor element can be achieved by at least one of the following methods: prior metallization application by thermal metal spraying; macroscopic roughness increase through geometric chip design adjustments; adaptation of additive deposition processes in chip production; generation of rough metallizations through subtractive processes; laser roughening; paste application followed by baking; or galvanic growth of rough metal layers.

[0037] These various methods for adjusting surface roughness offer flexibility in achieving the desired surface profile and enable optimization based on specific semiconductor device properties and manufacturing constraints.

[0038] 6

[0039] The particle diameter can range from 1 pm to 100 pm, in particular from 5 pm to 25 pm.

[0040] This particle size range ensures effective splat formation and optimal mechanical interlocking with the roughened semiconductor surface, which contributes to improved adhesion of the buffer layer.

[0041] The particles can be sprayed at a speed of 50 to 800 m / s, especially less than 300 m / s.

[0042] Controlling the particle velocity within this area enables effective particle deformation upon impact without damaging the underlying semiconductor element, thus promoting optimal buffer layer formation.

[0043] When applying the selected particles to the surface, in a first step only a few particles can be applied, but at a higher temperature, and in a second step the actual buffer layer can then be applied at a normal temperature, whereby the higher temperature refers to the temperature of the particles and is aimed at greater than 1400 degrees Celsius, while the normal temperature is in the range of 1000 degrees to 1400 degrees Celsius.

[0044] This two-stage deposition process with temperature variation improves the initial adhesion of the buffer layer by promoting better bonding of the first particles, followed by the main layer deposition under normal conditions, resulting in a more robust and better-adhering buffer layer.

[0045] According to the invention, an ideally adhesive buffer layer deposited by thermal metal spraying is proposed, wherein the adhesion is determined by one of two decisive parameters of the starting materials.

[0046] These parameters are the surface roughness and the particle size or its diameter d.

[0047] Contrary to the invention, such roughness values ​​are not common in semiconductor or wafer manufacturing, since layers are deposited on smooth silicon surfaces and the applied layers are even leveled by means of CMP (chemical mechanical polishing). To increase the roughness, it is therefore proposed that the semiconductor chips be deliberately roughened before the copper buffer layer is applied at the chip manufacturer or also at the chip manufacturer.

[0048] to roughen the surface in between, thus utilizing the inherently rougher properties of IGBTs and MOS-FETS due to their cell structure.

[0049] Examples of current surface roughness of building components.

[0050] >

[0051]

[0052] <

[0053] The invention will now be described and explained in more detail with reference to the exemplary embodiments shown in the figures. The figures show:

[0054] FIG 1 shows a schematic representation of a thermal spraying process onto a semiconductor element,

[0055] FIG 2 shows a schematic representation of a typical deformation of a metallic particle upon impact with the surface of a semiconductor element.

[0056] FIG 3 a roughness profile and

[0057] FIG 4 shows a principle for optimal coverage of a splat on a peak.

[0058] Semiconductor element 4 is exemplified as an insulated-gate bipolar transistor (IGBT). Other examples of such semiconductor devices made from semiconductor element 4 include other transistor types such as field-effect transistors and bipolar transistors, as well as triacs, thyristors, and diodes. Semiconductor element 4 can be designed using silicon or a wide-bandgap semiconductor, e.g., silicon carbide (SiC) or gallium nitride (GaN), as a semiconductor substrate. An IGBT comprises terminal elements configured as a gate terminal, collector terminal, and emitter terminal. Each terminal element includes a contact pad with a chip metallization, which may, for example, contain AlSiCu. The contact pads are provided for contacting the semiconductor element 4, including via bonding agents.

[0059] A metallic contacting element 10 is produced by a thermal spraying process, wherein particles PI, P2, which202500098

[0060] 8

[0061] For example, particles containing copper and / or molybdenum are sprayed onto the semiconductor element 4. The particles PI, P2 form a textured buffer layer P or a metallic layer 12, which, for example, has a thickness in the range of 1 pm to 250 pm, particularly 5 pm to 100 pm. Such a buffer layer P consists of particles PI, P2, which are at least partially deformed into a splat-like shape. For example, the buffer layer P comprises splat-like deformed and melted second particles P2, where the diameter of the second particle P2, or splat diameter ds, corresponds to 2 to 6 times the diameter of a particle d. Thus, d = 1–30 pm becomes ds = 2–180 pm.

[0062] Such buffer layers P compensate for compressive forces. If pressure is applied, for example during contacting, especially during bonding, the resulting compressive forces are leveled by the textured layers 12 and transferred homogeneously to the semiconductor element 4. During subsequent operation of the semiconductor element 4, for example when switching a power semiconductor on and off, the different coefficients of thermal expansion of the semiconductor (Si, GaN, SiC 3-7 ppm) and the metals (copper 17-18 ppm, aluminum 24 ppm) are largely compensated for by their spring effect. Thus, the metallic contacting element 10 acts as a buffer layer.

[0063] As shown in FIG. 2, the impacting particles PI form a flat, slab-like particle P2, for example a copper particle and / or molybdenum particle, which is transformed into a so-called splat S upon impact. A thermal and / or kinetic energy source 14 is used to apply the particles PI, P2; this source can be a plasma, a combustion flame, an electric arc, a laser, an explosion, or a heated gas. The spray additives are available, among other forms, as rods, wires, suspensions, or powders.

[0064] FIG. 2 shows a typical deformation of a metallic particle P1 upon impact with a surface 16 of a semiconductor element 4. Due to its velocity, which is, for example, in the range of 50 m / s to 800 m / s, and its softened state, the particle P1 is strongly deformed, resulting in a flat, splatter-like shape. This effect is called the splattering effect and leads to high adhesion due to the wetting of a large surface area.

[0065] Figure 3 shows a surface roughness profile, a representation of the surface's microstructure, which consists of numerous small irregularities and depressions. It describes the deviations of a real surface from its ideal, smooth form. These deviations can be caused by various manufacturing processes, material properties, or environmental influences.

[0066] 9

[0067] The roughness profile is typically acquired by measuring the surface with specialized instruments, such as stylus instruments or optical profilometers. The resulting profile can then be displayed graphically to show the differences in height and depth along a defined measurement path.

[0068] Some important parameters that can be derived from the roughness profile are:

[0069] 1. Average roughness value R: The arithmetic mean of the absolute deviations of the roughness profile from the mean line over a measuring distance.

[0070] 2. Quadratic mean roughness value Rq or RMS: The quadratic averaging of the deviations of the roughness profile from the mean line.

[0071] 3. Maximum roughness depth Rz: The difference between the highest and lowest points of the roughness profile over a measuring distance.

[0072] 4. Height of the largest profile peak Rp: The highest point of the profile above the central line.

[0073] 5. Depth of the largest profile valley Rv: The lowest point of the profile below the central line.

[0074] These parameters provide information about surface quality and can be specified for various applications and requirements. Particularly in semiconductor manufacturing and plasma coating, precise roughness values ​​are crucial to ensure the adhesion of coatings and the functionality of the manufactured components.

[0075] The following procedure can be used to determine surface roughness:

[0076] Capturing the roughness profile:

[0077] Use an optical profilometer to record the surface roughness profile. The profile is displayed as a graphical representation of the height and depth differences along a defined measurement path.

[0078] Identifying the profile peaks:

[0079] Analyze the recorded profile to identify the positions of the profile peaks (highest points) and the valleys (lowest points). A profile peak can be defined as the point where the profile height reaches a local maximum.

[0080] Calculation of the side length of a profile tip:

[0081] A profile peak in roughness measurement can be approximated as triangular or trapezoidal. The side length of such a profile peak can be calculated from the horizontal distance between the two points where the peak reaches the mean line or an adjacent valley.

[0082] 10

[0083] According to FIG 4, if the profile peak is assumed to be approximated as an isosceles triangle, then the side length I of a profile peak is the distance between the highest point (vertex) of the profile peak and the base of the peak (where it intersects the mean line or an adjacent valley).

[0084] If the profile tip is assumed to be a simple geometric triangle, then the side length I can be calculated as follows:

[0085] I = square root (h 2 +(b / 2) 2 ) Rsm is used for b.

[0086] Here, h is the height of the profile tip, namely the roughness depth Rz (the vertical distance from the mean line to the highest point of the tip) and b is the width of the base of the profile tip (the horizontal distance between the two points where the profile tip intersects the mean line).

[0087] In summary, calculating the side length of a profile tip consists of determining the exact geometry of the tip from the measured roughness profile and then calculating the side length using suitable geometric relationships.

[0088] 1. Average roughness depth (Rz): 5 pm to 90 pm, especially 30 pm to 90 pm

[0089] This describes the average vertical distance between the highest elevations and lowest valleys of the surface profile.

[0090] 2. Average groove width (RSm): 2 pm to 80 pm

[0091] This represents the average horizontal distance between the irregularities of the surface.

[0092] 3. Total height of the roughness profile (Rt): 3 pm to 540 pm

[0093] This indicates the maximum vertical distance between the highest point and the lowest valley of the entire surface profile.

[0094] These roughness parameters are carefully coordinated to provide an optimal basis for the adhesion of the thermally sprayed buffer layer. The special surface structure enables effective mechanical interlocking of the sprayed particles.

[0095] If the side length I is given, then half the splat diameter ds can be deduced, ds = 2*l, and an optimal surface roughness results from 1.5 to 3 times the splat diameter ds. From this, an optimal particle size or optimal particle diameter d can then be determined.

Claims

202500098 11 Patent claims 1. Semiconductor element (4) designed from semiconductor material for the manufacture of semiconductor components comprising: a front (V) and a reverse side (R), characterized in that a surface (16) of the front side (V) has at least in partial areas (T) a mean roughness depth (Rz) in the range of 5 pm to 90 pm, in particular 30 pm to 90 pm, and a mean groove width (RSm) in the range of 2 pm to 80 pm.

2. Semiconductor element (4) according to claim 1, wherein the sub-areas (T) have a total height (Rt) of the roughness profile in the range of 3 pm to 540 pm.

3. Method for applying a buffer layer (P) to a semiconductor element (4) by means of a thermal spraying process in which a layer material in particle form is heated by a heat source (14) and then applied at high speed to a surface (16) of a front face (V) of the semiconductor element (4), comprising: - Setting and / or determining a surface roughness at least in or of partial areas (T) of the surface (16) of the front side (V), characterized by the fact that - a particle diameter (d) of the particles (P1,P2) of the layer material to be used is selected based on the set and / or determined surface roughness; and wherein the particle diameter (d) is selected such that the surface roughness in pm is approximately 1.5 to 3 times the diameter of a flattened spray particle, wherein the particle (P1,P2) is deformed into a splat (S) upon impact with the surface (4) of the front (V) and the surface roughness is approximately 1.5 to 3 times a splat diameter (ds), - Application of the selected particles (P1,P2) to the surface (16) of the front (V) of the semiconductor element (4) to form the buffer layer (P).

4. The method of claim 3, wherein the adjustment of the surface roughness of the semiconductor element (4) is carried out by at least one of the following methods: - Previous metallization application using thermal metal spraying; - Macroscopic roughness increase through geometric chip design adjustments; - Adaptation of additive manufacturing processes in chip production; 202500098 12 - Production of rough metallizations by subtractive processes; - Laser roughening; - Paste application followed by baking; or - Galvanic growth of rough metal layers.

5. Method according to claim 3 or 4, wherein the particle diameter (d) has a size of 1 pm to 100 pm, in particular 5 pm to 25 pm.

6. Method according to any one of claims 3 to 5, wherein the particles (P1,P2) are sprayed at a speed of 50 to 800 m / s, in particular less than 300 m / s.

7. Method according to any one of claims 3 to 6, wherein, in the first step of applying the selected particles (P1,P2) to the surface (16), only a few particles (P1,P2) are applied, but at a higher temperature, and in a second step the actual buffer layer (P) is applied at a normal temperature, wherein the higher temperature refers to the temperature of the particles (P1,P2) and is greater than 1400 degrees Celsius, and the normal temperature is in the range of 1000 degrees to 1400 degrees.

8. Method according to any one of claims 3 to 7, wherein a bond wire or bond ribbon is applied to the buffer layer (P).

9. Method according to any one of claims 3 to 7, wherein a pressure contact is applied to the buffer layer (P).

10. Method according to any one of claims 3 to 7, wherein a laser bond is applied to the buffer layer (P).

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