Common-mode voltage stabilization in loop-unrolled SAR ADC

Abstract

A loop-unrolled SAR ADC achieves decreased total analog to digital conversion time, with low noise, by stabilizing the common mode voltage between differential nodes of a capacitive DAC VCM is heavily influenced by state-dependent input capacitance of the latching comparators that successively perform comparisons and latch output bits in the SAR ADC. In a first aspect, each latching comparator includes both an operative pre-amplifier and a replica pre- amplifier, the outputs of which are not used, and which is clocked in anti-phase to the operative pre-amplifier. The two pre-amplifiers are hence always in opposite states. In a second aspect, a clock scheduler circuit generates individual clock signals to the latching comparators under the constraint that a constant number of the latching comparators are in the reset state upon latching any one latching comparator.

Description

[0001] COMMON-MODE VOLTAGE STABILIZATION IN LOOP-UNROLLED SAR ADC

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic circuits, and in particular to an improved Successive Approximation Register Analog to Digital Converter having a stable common mode voltage between the inputs of a differential capacitive Digital to Analog circuit.

[0004] BACKGROUND

[0005] Many modern electronic devices receive or acquire information in the form of analog signals (e.g., optical signals, acoustic signals, electro-magnetic (EM) waves, and the like), and transform the information to the digital domain for processing by digital circuitry, such as Digital Signal Processors (DSP) and microprocessors. Fast, accurate, low-power (particularly for battery operated devices) Analog to Digital Converters (ADC) are thus critical circuits in many devices.

[0006] One non-limiting example of ADC use is in User Equipment (UE) and corresponding base station circuitry in the Radio Access Network (RAN) of a wireless communication network. These network nodes exchange control- and user-plane data across an air interface by transmitting and receiving modulated Radio Frequency (RF) carrier waves. In particular, the most recent technical standards defining such networks, such as the Fifth Generation (5G) standard promulgated by the 3rd Generation Partnership Project, define two bands of frequencies: FR1 (410 MHz to 7.125 GHz) and FR2 (24.25 GHz to 52.6 GHz). In addition to higher frequencies, modern wireless communication networks also operate using wider bandwidth RF carriers. High speed, high resolution ADC operation is a requirement in network node operation. Furthermore, particularly for battery-powered mobile devices, low power consumption is desirable.

[0007] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

[0008] SUMMARY

[0009] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present someconcepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0010] According to aspects of the present disclosure described and claimed herein, a loop-unrolled SAR ADC achieves decreased total analog to digital conversion time, with low noise, by stabilizing the common mode voltage VCM between differential nodes of a capacitive DAC. The VCM is stabilized by ensuring a low difference in input capacitance between the reset and latched states, ACjn= |Creset - Ciatchedl, of all bit conversion stages. In a first aspect, a latching comparator in each bit decision comprises close or identical first and second input stages in parallel. The first input stage is enabled by a per-stage individual clock controlling operation of the latching comparator. The second input stage is enabled by the inverse of this clock, and the outputs of the second input stage are not used. In a second aspect, a clock scheduling circuit generates the per-stage individual clocks, under the constraint that, throughout an N-bit decision cycle, prior to clocking a latching comparator in any bit decision stage from reset to latched state, a constant number M of the N latching comparators of the SAR ADC are in the reset state.

[0011] One aspect relates to a loop-unrolled, N-bit, Successive Approximation Register (SAR) Analog to Digital Converter (ADC) configured to convert an analog input voltage to an N-bit digital representation. The SAR ADC includes N bit decision stages. Each bit decision stage includes a latching comparator. The latching comparator is controlled by an individual clock signal between a reset state, where the comparator prepares to make a bit decision, and a latched state where the comparator makes the bit decision and stores a bit value representing a comparison between the analog input voltage and the bit position’s digital value. The latching comparator includes parallel first and second input stages. For all but the last, each bit decision stage also includes control circuitry configured to generate an individual clock signal for a successive bit decision stage. The latching comparator makes a bit decision based on an output of the first input stage. The second input stage is clocked in anti-phase to the first input stage, and the output of the second input stage is not used by the latching comparator.

[0012] Another aspect relates to a method of converting an analog input voltage to an N-bit digital representation using a loop-unrolled, N-bit, SAR ADC. At each of N bit decision stages: in a reset state, making a bit decision is prepared, and in a latched state, the bit decision is made and a bit representing a comparison between the analog input voltage and the bit position’s digital value is stored. The reset and latched states are controlled by the states of an individual clock signal for that bit decision stage. Also, at each bit decision stage, a first input stage is enabled with the individual clock signal and an output of the first input stage is used in the bit decision, and a second input stage, parallel to the first input stage, is enabled with the inverse of the individual clock signal and the output of the second input stage is ignored.

[0013] Yet another aspect relates to a loop-unrolled, N-bit, SAR ADC configured to convert an analog input voltage to an N-bit digital representation. The SAR ADC includes N bit decisionstages. Each bit decision stage includes a latching comparator controlled by an individual clock signal between a reset state, where the comparator prepares to make a bit decision, and a latched state where the comparator makes the bit decision and stores a bit representing a comparison between the analog input voltage and the bit position’s digital value. The SAR ADC further includes control circuitry including a clock scheduler. The clock scheduler is configured to generate the N individual clock signals so as to mutually exclusively transition each latching comparator from reset to latched state. Throughout an N-bit decision cycle, prior to the latching comparator in any bit decision stage transitioning from reset to latched states, clock signals to the N latching comparators are controlled such that a constant number M of them are in the reset state.

[0014] Still another aspect relates to a method of converting an analog input voltage to an N-bit digital representation using a loop-unrolled, N-bit, SAR ADC. A latching comparator in each of N bit decision stages is independently clocked between a reset state, where the latching comparator prepares to make a bit decision, and a latched state, where the latching comparator makes the bit decision and stores a bit representing a comparison between the analog input voltage and the bit position’s digital value. The N independent clock signals are generated so as to mutually exclusively transition each latching comparator from reset to latched state.

[0015] Throughout an N-bit decision cycle, prior to the latching comparator in any bit decision stage transitioning from reset to latched states, a constant number M of the clock signals to the N latching comparators control their respective latching comparators to be in the reset state.

[0016] Still another aspect relates to an Integrated Circuit (IC). The IC includes at least one of the loop-unrolled SAR ADCs described above.

[0017] Still another aspect relates to a Radio Frequency (RF) transceiver. The RF transceiver includes at least one of the loop-unrolled SAR ADCs described above.

[0018] Still another aspect relates to a User Equipment (UE) operative in a wireless communication network. The UE includes a transceiver including at least one of the loop-unrolled SAR ADCs described above.

[0019] Still another aspect relates to a base station operative in a wireless communication network. The base station includes a transceiver including at least one of the loop-unrolled SAR ADCs described above.

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0022] FIG. 1 is a block diagram of a basic conventional SAR ADC.FIG. 2 is a graph showing conversion of an analog voltage to a digital value in a SAR ADC.

[0023] FIG. 3A is a graph of integrated input-referred noise vs. common mode voltage in a SAR ADC comparator.

[0024] FIG. 3B is a graph of bit decision time vs. common mode voltage in a SAR ADC comparator.

[0025] FIG. 4 is a schematic diagram of a loop-unrolled SAR ADC using a CDAC.

[0026] FIG. 5 is a schematic diagram of a conventional latching comparator having a preamplifier.

[0027] FIG. 6 shows graphs of clock signals for bit decision stages, and growth of the common mode voltage.

[0028] FIG. 7 shows graphs depicting the increasing delay from one bit decision stage clock to the next.

[0029] FIG. 8 is a schematic diagram of a latching comparator comprising first and second input stages in parallel and clocked in anti-phase.

[0030] FIG. 9 shows graphs of clock signals for latching comparators, and stability of the common mode voltage, for a SAR ADC using the latching comparator of FIG. 8.

[0031] FIG. 10 shows graphs of clock signals for latching comparators, and stability of the common mode voltage, for the SAR ADC of FIG. 11.

[0032] FIG. 11 is a schematic diagram of a loop-unrolled SAR ADC with a clock scheduling control circuit.

[0033] FIG. 12 is a flow diagram of a method of operating the loop-unrolled SAR ADC of FIGs. 4 and 8, according to a first aspect.

[0034] FIG. 13 is a flow diagram of a method of operating the loop-unrolled SAR ADC of FIG. 11, using the latching comparator of FIG. 5, according to a second aspect.

[0035] FIG. 14A is a diagram of wireless communication in a wireless communication network. FIG. 14B is a hardware block diagram of a User Equipment operative in a wireless communication network.

[0036] FIG. 14C is a hardware block diagram of a base station operative in a wireless communication network.

[0037] DETAILED DESCRIPTION

[0038] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well known methods andstructures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0039] At high sample rates, e.g., above 100 Mega Samples per second (MSps), the most power-efficient ADCs architecture is the successive-approximation register (SAR) technique, often in combination with other techniques like pipelining and time-interleaving to improve sampling rates. FIG. 1 depicts the basic components of a conventional N-bit SAR ADC. A Sample-and-Hold (S / H) circuit acquires an analog input voltage vm and maintains it at a stable value. An analog voltage comparator compares the analog input voltage vm with the output Vd of a Digital to Analog Converter (DAC), and outputs the binary result to an approximation register -that is, an indication of whether the DAC voltage Vd is above or below the input voltage. In each successive decision cycle, the approximation register changes its digital output, converging on a digital representation of the analog input voltage. Although many conversion strategies are known, for a digital SAR ADC, a common one is to initially set the Most Significant Bit (MSB) of the approximation register to 1 , and all other bits to zero. This outputs a voltage from the DAC that is half of the ADC’s range, or VREF / 2. The comparator output indicates whether the analog input voltage is above or below this midpoint. If it is above, for the next decision cycle, the approximation register maintains the MSB at 1, and switches only the next-least-significant bit to 1 , which divides the upper half of the voltage range in half, and again compares this value to the input voltage. This process continues through N decision cycles for an N-bit SAR ADC stage.

[0040] FIG. 2 depicts the process for a simple, 4-bit SAR ADC. The bold line represents the DAC output voltage Vd, the (constant) thin line is the input voltage vm, and the SAR ADC output is the digital code below the abscissa. Initially, the 4-bit approximation register is set to 1000, and vm is compared to VREF / 2. Since vm < REF / 2, the MSB is cleared to “0”. The approximation register is then set to 0100, and vm is compared to VREF / 4 (the center of the subrange O-VREF / 2 selected in the preceding decision cycle). Because vm > VREF / 4, the “1” is retained for this bit position, and the next lower bit is set to one, yielding 0110, which compares the input voltage to Vd = 3VREF / 8. The input voltage vm is below this value, so this bit value is cleared, and the last bit is tested with the approximation register being set to 0101 , for Vd = 7VREF / 16. Because VIN exceeds this value, the “1” is retained for the LSB, and the SAR ADC output is 0101 for this value of v^.

[0041] Another way to perform the comparison between vm and Vd, which can be performed in a capacitive DAC (CDAC), is to subtract the DAC output from the analog input voltage in each decision cycle, generating a series of residual voltages. The input voltage is initially sampled and retained. During subsequent cycles, parts of the capacitor bank are connected to a positive reference voltage VREFP or a negative reference voltage VREFM, in response to the approximation register output d<N-1:0>. The DAC then outputs the residual voltage vm - Vd. In this case, the comparator only determines whether the residual voltage is positive or negative, which yieldsthe same information for the approximation register to make a more accurate digital approximation in the next decision cycle. In a differential implementation, Vd = 0 initially and thus for the first decision cycle, the comparator determines the polarity of the analog input voltage vm. To summarize, the CDAC acts simultaneously as sample-and-hold, DAC, and subtractor. In other words, the DAC capacitors are also used as sampling capacitors, so a superposition of the input voltage and the DAC voltage is generated by the DAC, and the polarity of this value is detected to yield a bit decision. In a conventional CDAC, the capacitors in the network are binary weighted, and the CDAC only consumes energy during charging and discharging of the capacitive network.

[0042] Most of the switching schemes of the CDAC are developed to reduce the power consumption due to capacitor charging and discharging. Some CDAC switching schemes have stable common-mode voltage (VCM) whereas others do not. For example, the monotonic switching scheme shows excellent energy efficiency, but suffers from shifting (or drifting) VCM during successive bit decisions. On the other hand, the merged capacitor switching (MCS) scheme is even more energy efficient and provides a constant CM during bit decisons. See, e.g., the paper by Hariprasath, J. Guerber, S.-H. Lee, and ll.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” published in Electronics Letters, vol. 46, pp. 620-621, April 2010, the disclosure of which is incorporated herein by reference in its entirety.

[0043] Many SAR architectures and algorithms are known in the art, some of which exhibit significant energy savings, compared to a conventional CDAC switching technique. Examples include the split-capacitor, monotonic switching, MCS, and set-and-down. The primary objective of these switching techniques is to reduce the average energy dissipation, whereas only a subset of the variants exhibit a stable VCM during bit decisons. The MCS scheme has many attractive properties, including stable VCM during bit decisions, simple digital switch logic, only half the capacitor CDAC area, and 87.5% energy savings compared with the conventional switching technique. Aspects of the present disclosure are described herein in the context of the MCS scheme; however, those of skill in the art will readily recognize that other switching schemes could be used within the scope of the claims.

[0044] In addition to reducing power consumption, numerous techniques are known for increasing the speed of a SAR ADC, including asynchronous clocking, pipelining, multi-bit per decision, and alternate or loop-unrolled comparators. Papers describing the latter include the following, all of which are incorporated herein by reference in their entireties:

[0045] • L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi, M. Braendli, M. Kossel, T. Morf, T. M. Anderson, and Y. Leblebici, “A 3.1 mW 8b 1.2GS / S Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS,” ISSCC Dig. Tech. Papers, pp. 468-470, Feb. 2013.• Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel Kossel, Hazar Yueksel, Alessandro Cevrero, liter Ozkaya, Thomas Toif, “A 10b 1.5GS / S Pipelined-SAR ADC with Background Second-Stage Common- Mode Regulation and Offset Calibration in 14nm CMOS FinFET”, ISSCC 2017.

[0046] • Tao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Kangmin Hu, Patrick Yin Chiang, "A Single-Channel, 1.25-GS / s, 6-bit, 6.08-mW Asynchronous Successive- Approximation ADC With Improved Feedback Delay in 40-nm CMOS", IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 10, October 2012.

[0047] • Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun, "A 0.95-mW6-b 700-MS / s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS", Transactions on Circuits and Systems II: Express Briefs, 2016.

[0048] • Kareem Ragab, Nan Sun, "A 1.4mW8b 350MS / S Loop-Unrolled SAR ADC with Background Offset Calibration in 40nm CMOS", ESSC / RC Conference 2016.

[0049] • Xiyuan Tang, Long Chen, Jeonggoo Song, Nan Sun, "A 10-b 750pW200MS / s Fully Dynamic Single-Channel SAR ADC in 40nm CMOS", ESSC / RC Conference 2016. • Chao Chen, Jie Sun, Chenghua Wang, Weiqiang Liu, "A 10-b 500MS / S Partially Loop- unrolled SAR ADC with a Comparator Offset Calibration Technique", 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

[0050] • Chao Wu, Jie Yuan, "A 12-Bit, 300-MS / s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC", IEEE Journal of Solid-State Circuits Vol.: 54, Issue: 5, May 2019. In an asynchronous SAR algorithm, the triggering of the internal comparisons from MSB to LSB occur in a ripple-like fashion, such that the quantization time allocated to each bit is not limited by the slowest bit decision, but rather the average quantization time. This improves throughput, as compared to a synchronous architecture. See, in particular, Jiang, et al., cited above.

[0051] A loop-unrolled architecture works asynchronously and uses one comparator per bit decision. The comparator decision is directly stored by a latch at the comparator output. This greatly simplifies the SAR logic. The small logic depth leads to short delay, high speed, and low power consumption. See, in particular, L. Chen, et al., cited above.

[0052] A loop-unrolled architecture removes the dedicated reset phase from the time-critical path. Consequently, the bit decision time is no longer limited by the comparator reset time. See, in particular, Ragab, et al., and C. Chen, et al., both of which are cited above.

[0053] A known drawback to the loop-unrolled architecture is that mismatch between the comparators can limit the linearity, and a comparator offset calibration is necessary to reach the target spurious-free dynamic range (SFDR) number. This is discussed by Tang, et al., cited above. Comparator offset calibration is well understood by those of skill in the art.

[0054] The comparator used in a data converter is typically implemented using one or more pre-amplifiers, or input stages, followed by a latch stage. As used herein, the term “latchingcomparator” refers to the combination of an input stage and regenerative latch, which performs the comparison. As known in the art, in various implementations, these elements may be integrated in various ways. For example, the input stage may be incorporated into the latch structure, or may be separate.

[0055] In implementations including a pre-amplifier as an input stage, the pre-amplifier amplifies the input signal upstream of the comparator / latch, which reduces the input-referred noise and enables detection of relatively smaller signals present in high-resolution data converters.

[0056] Another advantage when using pre-amplifiers is the reduction of kickback. When the latching comparator takes a decision, a full-swing output may be generated, which capacitively couples back to the comparator input, affecting the charge stored on the CDAC.

[0057] A dynamic pre-amplifier is presently preferred as the input stage for its low noise, low power consumption, and input noise filtering properties, relative to a static pre-amplifier with essentially constant power consumption. In Kull, Toifl, et al., the comparator is a Strong-Arm latch chosen for its good balance between speed, noise, and power. The Strong-Arm dynamic comparator decision time is simulated versus input VCM in L. Chen, et al., where the shortest decision time is seen for VCM « 0.8 V (ca 0.67*VDD). Even though the decision time versus input CM level may be different depending on comparator architecture and chosen input stage transistor type (e.g., n- or p-type), they share the property that the decision time is lowest at a specific VCM level.

[0058] FIG. 3A graphs the simulated characteristic of the input-referred integrated noise of a comparator. That is, a hypothetical noise source that, when connected to the input, would give rise to the actual noise at the output of the comparator. FIG. 3B graphs the decision time of the comparator, both plotted versus VCM level. It is clear from these graphs that selecting a proper VCM is a tradeoff between comparator noise and decision time. A balanced approach is to minimize the noise*decision time product, which here indicates a preferred VCM « 0.4 V in the typical corner case, with some margin for Process, Voltage, and Temperature (PVT) variation to the region where the decision time grows superlinear (approx. VCM S 0.5 V).

[0059] FIG. 4 shows a 5-bit loop-unrolled SAR ADC based on MCS. The final bit (d<0>) is not required in the CDAC and thus a 4-bit CDAC is sufficient. The capacitors are binary weighted. A logic block at each comparator output latches the digital bit, controls the CDAC switches, and generates a clock signal to the next bit decision stage when one bit decision stage has taken a decision. In the MCS scheme, the comparator is a polarity detector, as the CDAC capacitors hold a superposition of the analog input and the DAC output - the decision at each bit is whether the analog value at the comparator is positive or negative.

[0060] The differential input signal is connected to the CDAC top plate nodes o_sdac_p, o_sdac_m when the sampling switch sar_smp is closed. The MSB decision is triggered at the falling edge of the clock, clk<4>, of the first latching comparator in the loop-unrolled array. The next bit decision is triggered at the falling edge of clk<3>, which is asynchronously generated bythe distributed control circuitry at the output of the bit 4 latching comparator. The process repeats until all the bits are converted, and the sample data is stored in d<4:0>. Thereafter, all latching comparators are forced to the reset state at the rising edge of the clocks, clk<4:0>. This clocking scheme is well known to persons skilled in the art of SAR ADC design and is not further described. Those of skill in the art understand that either the falling or rising edge can be used to clock or reset a latching comparator.

[0061] FIG. 5 shows a latching comparator comprising a dynamic pre-amplifier as an input stage and a regenerative latch, which performs the comparison and latches the result when clocked. The pre-amplifier presents a small, but state-dependent, input capacitance ( / .e., reset or latched states). A small input capacitance is preferred, as it reduces the total capacitive load seen by the sample-and-hold (S / H) circuit. When the latching comparator having a dynamic preamplifier as an input stage, as shown in FIG. 5, is used in a loop-unrolled SAR ADC architecture, in combination with the standard clocking scheme described above, it results in a significant drawback shown as varying VCM = (o_sdac_p + o_sdac_m) / 2 level at the inputs of the comparators connected to the CDAC nodes o_sdac_p, o_sdac_m.

[0062] FIG. 6 shows the five latching comparator clock signals clk<4:0> in the lower five graphs, where in this implementation, high is reset and low is latched. Above those is the sar_smp pulse that samples the input voltage to o_sdac_p and o_sdac_m. The voltage value of these nodes is graphed in the second graph from the top, and uppermost graph shows the common mode voltage VCM, which increases throughout the ADC conversion cycle. The dots on the CM graph indicate the latching times of the latching comparators in the bit decision stages.

[0063] FIG. 7 shows the clk-to-clk bit decision times for each of the bit decision stages. This decision time increases with each successive bit from MSB to LSB, with a pronounced jump in the delay at the LSB. These increasing bit decision times correspond to the increasing value of VCM, as shown in FIG. 6.

[0064] For simplicity, the latching comparator is assumed to be in either the reset or the latched state. The VCM shift per bit decision is an undesired effect of state-dependent input capacitance of the input stage (dynamic pre-amplifier) of the latching comparator. Simulations indicate this capacitance, in one implementation, is Creset = 3.1 fF and Cached = 1.8 fF.

[0065] The magnitude of the VCM shift ACjnduring each bit decision depends on the absolute value |Creset - Ciatche | and the number of latching comparators in the loop-unrolled architecture, in relation to the total CDAC capacitance plus any parasitic capacitance connected to the topplate of the CDAC. During bit decisions, the VCM level can decrease or increase depending on to which node the parasitic capacitor is connected, and which capacitor value is larger (Creset or Ciatche ). Since the latter factors identified above are the same throughout the SAR ADC, for convenience and ease of explanation, the difference in input capacitance causing the shift in VCM is simplified herein to ACin= |Creset - Ciatched|.The most significant part of the injected charge is caused by the capacitive coupling of the clock signal in the input stage (dynamic pre-amplifier) of each latched comparator.

[0066] According to a first aspect of the present disclosure, the injected charge is cancelled or significantly reduced by providing two input stages in parallel, only one of which is used, with the “replica” input stage clocked in anti-phase to the operative one.

[0067] FIG. 8 shows a schematic diagram of this circuit 40, with first and second input stages in parallel. The first input stage 42 operates conventionally, and the regenerative latch 46 makes a bit decision based on its output. A second input stage 44 is configured in parallel to the first input stage 42, and clocked by an inverted version clk_n of the clock signal elk provided to the first input stage 42. In the second input stage 44, the transistor type and size are identical to those in the first input stage 42. The outputs of the second input stage 44 are not used. That is, they are not connected to the regenerative latch 46. Because the second input stage 44 is clocked on the opposite phase of the first input stage 42, the two are always activated in opposite states of the latching comparator 40 - that is, one is active in the reset state and the other is active in the latched state. This yields the result that, across the SAR ADC, the same number of latching comparator 40-n input stages 42, 44 are active as are inactive.

[0068] Table 1 shows the latching comparator input capacitance in the reset and the latched states for the circuits of FIGs. 5 and 8. The conventional latching comparator, with one (operative) input stage and no second (replica) input stage (FIG. 5), presents a large Cjndifference between the two states. However, the latching comparator 40 with both an operative first input stage 42 and a replica second input stage 44 clocked in anti-phase (FIG. 8) presents an insignificant difference in Cjnbetween the two states. This state-independent Cjnof the latter circuit 40 (FIG. 8) results in a state-independent, and hence constant, VCM level.

[0069]

[0070] Table 1: Difference in input capacitance for latching comparators

[0071] without and with a replica pre-amplifier

[0072] As Table 1 shows, the difference in input capacitance between the reset and latched states, ACin = |Creset - Ciatchedl is 1.3 fF for the conventional case, but only 0.24 fF for the case of both first and second input stages 42, 44. The latter is 18.5% of the former. Although the improvement will vary depending on implementation details ( / .e., total capacitance of the DAC and other (parasitic) capacitance in the node to which the latching comparator 40 is connected),this example shows that a significant improvement is achieved with the two-stage latching comparator, with anti-phase input stages.

[0073] FIG. 9 shows the graphs for this aspect of the loop-unrolled SAR ADC, similar to the graphs of FIG. 7 for the conventional case. The upper graph shows that the common mode voltage VCM shows an insignificant variation over the course of the entire N-bit conversion cycle. Here again, dots on the VCM curve indicate the individual latching comparator 40 latching times.

[0074] One way to view the effect of the SAR ADC of the first aspect is that, as each latching comparator 40 is transitioned from the reset to the latched state, a same number M of the input stages of the N latching comparators are in the reset state (M=N, since every latching comparator 40 has one input stage in the reset state and one input stage in the latched state). Hence, the state-dependent input capacitances are equalized, reducing variations in CM.

[0075] Considering again the graph of FIG. 6, showing conventional SAR ADC operation, one sees that initially, all latching comparators are in the reset state. The latching comparators then successively transition to the latched state one by one, in MSB-to-LSB order, and at the end of the SAR ADC conversion cycle, all latching comparators are in the latched state. In this clocking sequence, the small but state-dependent input capacitances of the input stages of the latching comparators successively add up, resulting in the increase in VCM shown in the uppermost graph in FIG. 6.

[0076] According to a second aspect of the present disclosure, the timing of transitions between reset and latched states of conventional latching comparators (e.g., FIG. 5) is altered from this successive pattern, such that prior to the latching comparator in any bit decision stage clocking from the reset state to the latched state, a constant number M of all N latching comparators in the SAR ADC are in the reset state.

[0077] FIG. 10 shows one representative example of such a clocking pattern. In this particular example of a 5-bit SAR ADC, each latching comparator comprises the conventional single, operative input stage (FIG. 5). At the falling edge of each clock signal, clocking a latching comparator from the reset state to the latched state, exactly two latching comparators are in the reset state. This sequence is also shown in Table 2.

[0078]

[0079] Table 2: Comparator states prior to transition from reset to latched stateFIG. 10 also shows, in the uppermost graph, that VCM remains stable throughout the SAR ADC bit conversion cycle. Here again, the dots indicate the individual latching comparator latching times.

[0080] The clock transition pattern depicted in FIG. 10 is one example of many possible implementations. In the general case, let ncmpdenote the total number of latching comparators in the SAR ADC. nreset denotes the number of latching comparators in the reset state, and niched denotes the number of latching comparators in the latched state.

[0081] ncmp = N, for an N-bit SAR ADC.

[0082] ncmp—nreset + notched

[0083] nreset can be any number in the range {1, ncm-1}

[0084] FIG. 11 shows a schematic diagram of the SAR ADC 50 according to this second aspect of the present disclosure. While some of the control circuitry remains distributed - the logic blocks at the output of each bit decision stage controlling the voltage switches - another block of control circuitry is centrally located, labeled CLOCK SCHEDULER 52 in FIG. 11. In this aspect of the SAR ADC, rather than the logic at the output of each bit decision stage directly generating the clock for the succeeding state, the logic at the output of each bit decision stage generates a “ready” signal rdy<n>, indicating the completion of a bit decision operation. The clock scheduler 52 receives the rdy<4:0> indicators, and asserts a clock signal to a latching comparator in the next bit decision stage (in this example, asserted low). The clock scheduler 52 additionally controls the timing of transitions from latched to reset states for each stage, conforming to the constraint that of the N latching comparators, the same number M of them are in the reset state prior to any one of them transitioning to the latched state. As FIG. 11 indicates, the SAR ADC 50 (as well as the SAR ADC including regenerative latches 40 having dual input stages 42, 44) may be implemented on an integrated circuit 54, optionally (as indicated by the dashed lines) along with other circuitry 56.

[0085] Returning to FIG. 10, note that, in this example, to comply with the constraint, the latching comparator for bit 4, after latching its decision value, is clocked to the reset state prior to the latching comparator for bit 0 being clocked to the latched state. Accordingly, additional storage is required to maintain the value of the bit 4 decision prior to outputting the digital value. In general, providing additional storage for each bit decision stage enables any clocking scheme that complies with the constraint of a constant number M of the N latching comparators being in the reset state upon transitioning any one of them to the latched state. This additional hardware will add a small delay per bit, but by maintaining a stable VCM, the clocking scheme significantly speeds up the overall SAR ADC 50 conversion cycle (see FIG. 7). The clock scheduling circuitry 52 also adds some hardware and additional complexity, but does not impact the SAR ADC 50 conversion speed.Compared to the first aspect of the present disclosure, with the first and second input stages 42, 44, the total input capacitance of the latching comparator array in the second aspect is approximately halved, while still maintaining a stable VCM.

[0086] FIG. 12 is a flow diagram of a method 100 of converting an analog input voltage to an N-bit digital representation in a loop-unrolled, N-bit, SAR ADC, according to a first aspect of the present disclosure. The method comprises, at each of N bit decision stages: in a reset state, preparing (block 102) to make a bit decision and in a latched state, making (block 104) the bit decision and storing a bit representing a comparison between the analog input voltage and the bit position’s digital value. The reset and latched states are controlled by the states of an individual clock signal for that bit decision stage. At the same time ( / .e., as a simultaneous, ongoing operation), the method further comprises, at each of the N bit decision stages: enabling (block 106) a first input stage 42 with the individual clock signal and using the output of the first input stage 42 in the bit decision, and enabling (block 108) a second input stage 44, parallel to the first input stage 42, with the inverse of the individual clock signal and ignoring the output of the second input stage 44. If all N bits have not been resolved (block 110), the method 100 repeats for each remaining bit.

[0087] FIG. 13 is a flow diagram of a method 200 of converting an analog input voltage to an N-bit digital representation in a loop-unrolled, N-bit, SAR ADC 50, according to a second aspect of the present disclosure. A latching comparator in each of N bit decision stages is independently clocked between a reset state, where the latching comparator prepares to make a bit decision, and a latched state where the latching comparator makes the bit decision and stores a bit representing a comparison between the analog input voltage and the bit position’s digital value (block 202). The N independent clock signals are generated so as to mutually exclusively transition each latching comparator from reset to latched state, and wherein, throughout an N-bit decision cycle, prior to the latching comparator in any bit decision stage transitioning from reset to latched states, a constant number M of the clock signals to the N latching comparators control their respective latching comparators to be in the reset state (block 204). If all N bits have not been resolved (block 206), the method 200 repeats for each remaining bit.

[0088] In both methods 100 and 200, at the latching comparator in each of N bit decision stages, ACjn= |Creset - Ciatchedl is very small, due to a constant number M of the N latching comparators presenting the input capacitance of the reset state. In the first aspect, with each latching comparator 40 having first and second input stages 42, 44 clocked in anti-phase, M=N. This is because, at all times, all of the N latching comparators 40-n are either in the reset state, with the first input stage 42 enabled, or are in the latched state, with the second input stage 44 enabled. Since the first and second input stages 42, 44 are close or identical in component size and value, each latching comparator 40 presents the same input configuration, and hence capacitance, regardless of its state (reset or latched). In the second aspect, the latching comparators have only a first input stage, and hence the input capacitance differs between thereset and latched states. However, the individual clocks to the N latching comparators are explicitly controlled in the second aspect to conform to the constraint that a constant number M of the N latching comparators are in the reset state upon latching any one of them. In this second aspect, M is in the range {1, N-1}. As shown in FIGs. 9 and 10, a very low value of ACjn(ideally approaching zero) yields a near-constant common mode voltage VCM throughout the overall ADC conversion operation, eliminating the divergent bit decision times shown in FIG. 7. The result is a significant increase in the overall ADC conversion speed.

[0089] FIG. 14A is a diagram of transmissions over the air interface of Radio Access Network (RAN) of a wireless communication network 10, such as a 3GPP 4G (Long Term Evolution, or LTE) or 5G (New Radio, or NR) network. A User Equipment (UE) 20, such as a smartphone, receives and transmits modulated Radio Frequency (RF) signals, over one or more antennas, from and to a base station 30, such as an LTE eNB or an NR gNB.

[0090] At each of the UE 20 and base station 30, at least one transceiver receives and transmits RF signals. At least the receiving function of these transceivers requires high-speed ADC. Low power consumption is always a requirement of a battery-powered UE 20, and is preferred at the base station 30 to reduce heat dissipation. Accordingly, one or both of the UE 20 and base station 30 may employ a SAR ADC according to the first or second aspect of the present disclosure.

[0091] FIG. 14B is a block diagram of the UE 20 of FIG. 14A. As used herein, the term UE may refer to a user-operated telephony terminal, a machine-to-machine (M2M) device, a machinetype communications (MTC) device, a Narrowband Internet of Things (NB-loT) device (in particular a UE implementing the 3GPP standard for NB-loT), etc. A UE 20 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smartphones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), and the like.

[0092] The UE 20 transmits and receives RF signals on at least one antenna 24, which may be internal or external, as indicated by dashed lines. The RF signals are generated, and received, by one or more transceiver circuits 22, which include one or more VcM-stabilized, loop-unrolled SAR ADCs as described herein. The transceiver circuits 22, as well as other components of the UE 20, are controlled by processing circuitry 26. Memory 28 operatively connected to the processing circuitry 26 stores software in the form of computer instructions executed by the processing circuitry 26. A user interface 29 may include output devices such as a display and speakers (and / or a wired or wireless connection to audio devices such as ear buds), and / or input devices such as buttons, a keypad, a touchscreen, and the like. As indicated by thedashed lines, the user interface 29 may not be present in all UEs 20; for example, UEs 20 designed for Machine Type Communications (MTC) such as Internet of Things (loT) devices, may perform dedicated functions such as sensing / measuring, monitoring, meter reading, and the like, and may not have any user interface 29 features.

[0093] FIG. 14C is a block diagram of the base station 30 of FIG. 14A. A base station 30 -known in various network implementations as a Radio Base Station (RBS), Base Transceiver Station (BTS), Node B (NB), enhanced Node B (eNB), Next Generation Node B (gNB), or the like - is a node of a wireless communication network that implements a Radio Access Network (RAN) in a defined geographic area called a cell, by providing radio transceivers to communicate wirelessly with a plurality of UEs 20.

[0094] The base station 30 transmits and receives RF signals on a plurality of antennas 34. As indicated by the broken line, the antennas 34 may be located remotely from the base station 30, such as on a tower or building. The RF signals are generated, and received, by one or more transceiver circuits 32. The transceiver circuits 32 include one or more VcM-stabilized, loop-unrolled SAR ADCs according to the first or second aspect of the present disclosure. The transceiver circuits 32, as well as other components of the base station 30, are controlled by processing circuitry 36. Memory 38 operatively connected to the processing circuitry 36 stores instructions executed by the processing circuitry 36. Although the memory 38 is depicted as being separate from the processing circuitry 36, those of skill in the art understand that the processing circuitry 36 includes internal memory, such as a cache memory or register file.

[0095] Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 36 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). Communication circuitry 39 provides one or more communication links to one or more other network nodes, propagating communications to and from UEs 20, from and to other network nodes or other networks, such as telephony networks or the Internet.

[0096] In all aspects, the processing circuitry 26, 36 may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in memory 28, 38, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.)-, programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above.

[0097] In all aspects, the memory 28, 38 may comprise any non-transitory machine- readable media known in the art or that may be developed, including but not limited to magnetic media (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like.In all aspects, the transceiver circuits 22, 32 are operative to communicate with one or more other transceivers via a Radio Access Network (RAN) according to one or more communication protocols known in the art or that may be developed, such as IEEE 802. xx, CDMA, WCDMA, GSM, LTE, UTRAN, WiMax, NB-loT, or the like. The transceiver 22, 32 implements transmitter and receiver functionality appropriate to the RAN links (e.g., frequency allocations and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately.

[0098] In all aspects, the communication circuitry 39 may comprise a receiver and transmitter interface used to communicate with one or more other nodes over a communication network according to one or more communication protocols known in the art or that may be developed, such as Ethernet, TCP / IP, SONET, ATM, IMS, SIP, or the like. The communication circuits 39 implement receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately. Although not shown in FIG. 14C, the communication circuitry 39 may also include one or more VcM-stabilized, loop-unrolled SAR ADCs according to the first or second aspect of the present disclosure.

[0099] Aspects of the present disclosure provide numerous advantages over the prior art, and may also provide one or more of the following technical advantage(s). The VCM at the input of the latching comparators in a loop-unrolled SAR ADC should be carefully selected to find the best compromise between decision time ( / .e., inversely related to the maximum conversion rate) and the input referred noise ( / .e., inversely related to the SNR). Applying the desired (or optimum) VCM guarantees the highest conversion rate whilst fulfilling the SNR requirement. Furthermore, once selected, maintaining the CM at a stable value throughout an ADC conversion cycle dramatically speed up the conversion process, by eliminating the cumulative state-dependent differences in input capacitance and concomitant increasing bit decision times experienced when using conventional SAR ADC circuitry and conventional latching comparator clocking pattern. The combination of VCM selection, and VCM stabilization according to the first or second aspect of the present disclosure, results in an optimized SAR ADC with high speed and low noise.

[0100] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc., are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise,any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0101] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0102] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0103] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

CLAIMS1. A loop-unrolled, N-bit, Successive Approximation Register, SAR, Analog to Digital Converter, ADC, configured to convert an analog input voltage to an N-bit digital representation, comprising:N bit decision stages, each comprisinga latching comparator (40), controlled by an individual clock signal between a reset state, where the comparator prepares to make a bit decision, and a latched state where the comparator makes the bit decision and stores a bit representing a comparison between the analog input voltage and the bit position’s digital value, the latching comparator (40) including parallel first and second input stages (42, 44); andfor all but the last bit decision stage, control circuitry configured to generate an individual clock signal for a successive bit decision stage;wherein the latching comparator makes the bit decision based on an output of the first input stage (42); andwherein the second input stage (44) is clocked in anti-phase to the first input stage (42), and the output of the second input stage (44) is not used by the latching comparator (40).

2. The SAR ADC of claim 1 whereinthe SAR ADC has a differential input;the SAR ADC further comprises a differential capacitive digital to analog converter, CDAC; anda common mode voltage, VCM, defined as an average of the positive and negative outputs of the differential CDAC, is substantially constant throughout a conversion cycle of the SAR ADC.

3. The SAR ADC of claim 2, wherein a bit decision time is substantially equal for all of the N bit decision stages.

4. The SAR ADC of any preceding claim wherein a difference in input capacitances between the reset and latched states, ACjn= |Creset - Ciatchedl, of each latching comparator (40) is less than the ACjnof a comparable latching comparator without the second input stage (44).

5. A method (100) of converting an analog input voltage to an N-bit digital representation in a loop-unrolled, N-bit, Successive Approximation Register, SAR, Analog to Digital Converter, ADC, comprising, at each of N bit decision stages:in a reset state, preparing to make a bit decision; andin a latched state, making the bit decision and storing a bit representing a comparison between the analog input voltage and the bit position’s digital value; wherein the reset and latched states are controlled by the states of an individual clock signal for that bit decision stage;enabling a first input stage (42) with the individual clock signal and using an output of the first input stage (42) in the bit decision; andenabling a second input stage (44), parallel to the first input stage (44), with the inverse of the individual clock signal and ignoring the output of the second input stage (44).

6. The method of claim 5 whereinthe SAR ADC has a differential input;the SAR ADC further comprises a differential capacitive digital to analog converter, CDAC; anda common mode voltage, VCM, defined as an average of the positive and negative outputs of the differential CDAC, is substantially constant throughout a conversion cycle of the SAR ADC.

7. The method of claim 5, wherein a bit decision time is substantially equal for all of the N bit decision stages.

8. The method of any of claims 5-7 wherein a difference in input capacitances between the reset and latched states, ACjn= |Creset - Ciatchedl, of each bit decision stage is less than the ACjnof a comparable bit decision stage without the second input stage (44).

9. An N-bit Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) configured to convert an analog input voltage to an N-bit digital representation, comprising:N bit decision stages, each comprising a latching comparator controlled by an individual clock signal between a reset state, where the comparator prepares to make a bit decision, and a latched state where the comparator makes the bit decision and stores a bit representing a comparison between the analog input voltage and the bit position’s digital value; andcontrol circuitry comprising a clock scheduler (52) configured to generate the N individual clock signals so as to mutually exclusively transition each latching comparator from reset to latched state, and wherein, throughout an N-bit decision cycle, prior to the latching comparator in any bit decision stage transitioning fromreset to latched states, clock signals to the N latching comparators are controlled such that a constant number M of them are in the reset state.

10. The SAR ADC of claim 9, wherein M is in the range {1, N-1}.

11. The SAR ADC of claim 9 whereinthe clock scheduler (52) is centralized; andother control circuitry is distributed such that logic at an output of each latching comparator outputs to the clock scheduler (52) a signal indicating completion of a bit decision.

12. A method (200) of converting an analog input voltage to an N-bit digital representation in a loop-unrolled, N-bit, Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) comprising:independently clocking (202) a latching comparator in each of N bit decision stages between a reset state, where the latching comparator prepares to make a bit decision, and a latched state where the latching comparator makes the bit decision and stores a bit representing a comparison between the analog input voltage and the bit position’s digital value; andgenerating (204) the N independent clock signals so as to mutually exclusively transition each latching comparator from reset to latched state, and wherein, throughout an N-bit decision cycle, prior to the latching comparator in any bit decision stage transitioning from reset to latched states, a constant number M of the clock signals to the N latching comparators control their respective latching comparators to be in the reset state.

13. The method of claim 12, wherein M is in the range {1, N-1}.

14. The method of any of claims 12-13 whereinthe clock scheduler (52) is centralized; andother control circuitry is distributed such that logic at an output of each latching comparator outputs to the clock scheduler (52) a signal indicating completion of a bit decision.

15. An Integrated Circuit, IC, comprising the loop-unrolled, N-bit SAR ADC of any of claims 1-4 or 9-11.

16. A Radio Frequency, RF, transceiver circuit (22, 32), the RF transceiver circuit (22, 32) comprising the loop-unrolled, N-bit SAR ADC of any of claims 1-4 or 9-11.

17. A User Equipment, UE (20), operative in a wireless communication network (10), the UE (20) comprising a RF transceiver circuit (22) comprising the loop-unrolled, N-bit SAR ADC of any of claims 1-4 or 9-11.

18. A base station (30), operative in a wireless communication network (10), the base station (30) comprising a RF transceiver circuit (32) comprising the loop-unrolled, N-bit SAR ADC of any of claims 1-4 or 9-11.

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