A converter arrangement

Abstract

A mechanism for controlling the operation of a converter arrangement comprising a full bridge switching arraignment and an output bridge switching arrangement connected by an inductor arrangement. A phase shift (a first phase shift) between a first leg and a second leg of the full bridge switching arrangement is controlled responsive to a voltage of a DC supply to the converter arrangement and a voltage of an AC mains connected to the converter arrangement. A phase shift between the output of the full bridge switching arrangement and a switching of the output bridge switching arrangement is controlled responsive to an integrated error between a measured time delay and a predefined time delay. The measured time delay is a time delay between a current through the inductor arrangement and the switching of the output bridge switching arrangement.

Description

[0001] 2024PF80520

[0002] 1

[0003] A CONVERTER ARRANGEMENT

[0004] FIELD OF THE INVENTION

[0005] The present invention relates to the field of power conversion, and in particular to bidirectional conversion of a DC input to an AC output.

[0006] BACKGROUND OF THE INVENTION

[0007] There is an increasing demand for environmentally friendly, sustainable and renewable power sources. One known power source is a photovoltaic installation, which may comprise a large number of individual photovoltaic elements (e.g., solar panels).

[0008] A challenge with using a photovoltaic installation is a need to efficiently convert a generated DC power into an AC power, for supplying an AC mains power. One recent development is a so-called solar microinverter. Each photovoltaic element is equipped with its own microinverter for connection to the AC mains power.

[0009] There is a demand for more efficient and compact DC-AC power converter, particularly one suitable for use in converting a DC power generated by a photovoltaic installation into an AC power for an AC mains supply.

[0010] Further, DC-AC converter needs to provide a reactive AC power at the AC power terminal to contribute to a control of the AC mains voltage. Reactive AC power is characterized by a 90-degree phase margin between a sinusoidal voltage and current. This requires the power converter to allow a bidirectional power flow.

[0011] SUMMARY OF THE INVENTION

[0012] The invention is defined by the claims.

[0013] There is herein proposed a converter arrangement for bidirectional conversion of a DC input to an AC output. The converter arrangement comprises an input interface configured to receive the DC input; an output interface configured to provide the AC output to an AC mains; a full bridge switching arrangement connected to the DC input, the full bridge switching arrangement having a first leg and a second leg for providing a bipolar square wave output; an inductance arrangement connected to receive the bipolar square wave output and produce an intermediate output; an output bridge switching arrangement2024PF80520

[0014] 2

[0015] connected between the inductive arrangement and the output interface; a sensing arrangement configured to monitor a voltage of the DC input; a voltage of the AC mains and a current through the inductance arrangement; and a controller configured to control an operation of the full bridge switching arrangement and the output bridge switching arrangement.

[0016] The controller is configured to: determine a first phase shift by performing a first determination process comprising processing at least the voltage of the DC input and the voltage of the AC mains; and control a phase shift between the left leg and the right leg of the full bridge switching arrangement to match the determined first phase shift.

[0017] The controller is also configured to determine a second phase shift by performing a second determination process. The second determination process comprises monitoring a time delay between a zero crossing of the current through the inductance arrangement and a switching of the output bridge switching arrangement; integrating an error between the monitored time delay and a predefined time delay; and determining the second phase shift using the integrated error.

[0018] The controller is also configured to control a phase angle between the bipolar square wave output and the switching of the output bridge switching arrangement to match the determined second phase shift.

[0019] The present disclosure proposes a converter arrangement having a full bridge switching arrangement and an output bridge switching arrangement connected by an inductance arrangement (e.g., a transformer arrangement). The full bridge switching arrangement selectively connects a DC supply to the inductance arrangement. The output bridge switching arrangement selectively connects the inductance arrangement to an AC mains.

[0020] A controller controls the full bridge switching arrangement to supply a bipolar square wave to one side of the inductance arrangement. A duty cycle of the bipolar square wave is controlled by controlled a first phase shift between a left and right leg of the full bridge switching arrangement. This effectively controls an amount of instantaneous power available for transfer to the AC mains.

[0021] The controller also controls the output bridge switching arrangement to define a square wave (intermediate output) at the other side of the inductance arrangement. It will be appreciated that the square wave may contain ripples, and may therefore be an effective square wave. The phase shift (a second phase shift) between the bipolar square wave at one side of the inductor arrangement and the square wave at the other side of the inductor arrangement controls an amount of power flow across the inductor arrangement (i.e., from2024PF80520

[0022] 3

[0023] the DC supply to the AC mains or vice versa). Power flows from the DC supply to the AC mains when the second phase shift is greater than 0.

[0024] The present invention recognizes that soft commutation of any switches in the switching arrangements can be facilitated through appropriate control of the first phase shift and the second phase shift. In particular, by controlling the value of the second phase shift responsive to an integrated error between the time delay of the switching of the output bridge switching arrangement and the current through the inductance arrangement and a predefined (desired) time delay, zero-voltage switching can be achieved.

[0025] In particular, it has been recognized that zero-voltage switching can be achieved by controlling the second phase shift such that the inductance current IR leads the switching of the output bridge switching arrangement by a certain phase angle or time delay. This goal is achieved by the herein proposed second determination process.

[0026] In some examples, the first determination process comprises: receiving first phase shift information identifying a minimum phase shift for the first phase shift; processing the voltage of the DC input and the voltage of the AC mains to determine a potential first phase shift; and responsive to the potential first phase shift falling below the minimum phase shift identified by the first phase shift information, setting the minimum phase shift as the first phase shift.

[0027] This approach ensures that the full bridge switching arrangement maintains a minimum phase shift, which helps robustness of the phase shift determination process against voltage transients at the DC input and AC mains output.

[0028] In some examples, the first determination process comprises: receiving first phase shift information identifying a maximum phase shift for the first phase shift; processing the voltage of the DC input VDC and the voltage of the AC mains VAC to determine a potential first phase shift; responsive to the potential first phase shift being above the maximum phase shift identified by the first phase shift information, setting the maximum phase shift as the first phase shift.

[0029] Use of a maximum phase shift for the first phase shift ensures that there is sufficient current flow to the inductance arrangement that facilitates soft commutation (e.g. zero voltage switching) of the full bridge switching arrangement.

[0030] In some examples, the first determination process comprises: determining a first ratio between the absolute value of the voltage of the AC mains VAC and the voltage of the DC input VDC; and processing the determined first ratio to determine the first phase shift. This provides a control technique that automatically adjusts to varying voltage levels at the2024PF80520

[0031] 4

[0032] DC input and the AC mains output, facilitating improved efficiency provided by reducing circulating or reactive power in the inductance arrangement, thereby provide a more efficient converter arrangement. The first determination process also helps realizing a sinusoidal waveform of the current injected to the AC mains.

[0033] In some examples, the first determination process comprises determining an intermediate first phase shift, IFPS, using the following equation:

[0034] ( abs(Vo)

[0035] IFPS = 180 1 - * K

[0036] \ ”DC

[0037] wherein abs(V0) is the absolute value of the voltage of the AC mains VAC, voltage of the AC mains VAC, VDC is the voltage of the DC input VDC, and K is a predefined constant value, which is related to the transformer turns ratio.

[0038] In some examples, the output interface comprises a first output node and a second output node, wherein the AC output is provided between the first output node and the second output node; the inductive arrangement comprises a first intermediate output node; and the output bridge switching arrangement comprises: a first bidirectional switch connected between the first output node and the first intermediate output node; and a second bidirectional switch connected between the first intermediate output node and the second output node.

[0039] This configuration of the output interface and bridge switching arrangement allows for efficient bidirectional power flow between the AC and DC sides. The use of bidirectional switches enables the converter arrangement to handle both positive and negative half-cycles of the AC waveform.

[0040] In some examples, the first bidirectional switch comprises a first MOSFET and a second MOSFET connected in a common source or common drain configuration; and / or the second bidirectional switch comprises a third MOSFET and a fourth MOSFET connected in a common source or common drain configuration. The use of MOSFETs in a common source configuration for bidirectional switches is advantageous as it allows for convenience in defining any gate driving circuitry because the two MOSFETs share a common ground and thus can be supplied via a single gate power supply circuit. The MOSFETs provide low on-state resistance and fast switching capabilities, reducing switching losses to improve the efficiency of the converter arrangement.2024PF80520

[0041] 5

[0042] In some examples, the second phase determination process comprises monitoring, as the monitored time delay, a time delay between a zero crossing of the current through the inductance arrangement and a raising edge of the first MOSFET or the fourth MOSFET or a falling edge of the second MOSFET or the third MOSFET.

[0043] In some examples, the second phase determination process comprises monitoring, as the monitored time delay, a time delay between a zero crossing of the current through the inductance arrangement and an activation of the first MOSFET or the fourth MOSFET.

[0044] In some examples, the inductive arrangement further comprises a second intermediate output node, wherein the intermediate output is provided between the first intermediate output node and the second intermediate output node; and the output interface comprises: a first output capacitor connected between the first output node and the second intermediate output node; and a second output capacitor connected between the second intermediate output node and the second output node.

[0045] This arrangement with dual intermediate output nodes and output capacitors forms an effective voltage doubler and output filter stage. The capacitors help smooth the output voltage waveform, reducing harmonic content and improving the quality of the AC output. This configuration functions to effectively double voltage of the AC output, thus reducing transformer turns ratio by half, assuming that the inductance arrangement comprises a transformer. The output capacitors also function as or contribute to the EMI filter. In some embodiment, the output capacitors form a part of a resonant tank together with the leakage inductance of the transformer.

[0046] In some examples, the predefined time delay is between 0.2 to 2 microseconds, e.g., 0.5 microseconds. This has been identified as being a suitable time delay to achieve zero-voltage switching of all switches in the output bridge switching arrangement at a typical operating frequency of 100 kHz using common semiconductor switching devices (MOFET, GaN FET, etc.). The given preferred time delay value depends on the actual circuit and switching device parasitic capacitances (i.e., Coss of the MOSFET) - a parameter to be fine adjusted in an actual hardware design to identify a minimum required time delay for zero voltage switching.

[0047] In some examples, in the second determination process, determining the second phase shift using the integrated error comprises: defining a maximum error value; and, if a maximum error is defined, responsive to the integrated error being above the maximum error value, determining the second phase shift using the maximum error value.2024PF80520

[0048] 6

[0049] In some examples, in the second determination process, determining the second phase shift using the integrated error comprises: defining a minimum error value; and, if a minimum time delay is defined, responsive to the integrated error being below the minimum error value, determining the second phase shift using the minimum error value.

[0050] In some examples, the input interface comprises a power input node and a return line, wherein the DC input is defined between the power input node and the return line; the first leg comprises a first switch connected between the power input node and the input node of the inductive arrangement and a second switch connected between the input node of the inductive arrangement and the return line; and the second leg comprises a third switch connected between the power input node and the return node of the inductive arrangement and a fourth switch connected between the return node of the inductive arrangement and the return line.

[0051] In some examples, the input interface further comprises an input capacitor connected between the power input node and the return line, optionally wherein the input capacitor functions as an energy storage to process reactive power from the AC mains. The addition of an input capacitor helps stabilize the DC input voltage and reduces high-frequency ripple as well as the double-line-frequency ripple drawn by the converter, e.g., functioning as a ripple smoother and / or power factor compensation component to allow for reactive power to be processed by the converter arrangement. More particularly, reactive power from the AC mains will be buffered by the input capacitor.

[0052] In some examples, the sensing arrangement is configured to monitor a current of the DC input; and the controller is further configured to: process the voltage of the DC input and the current of the DC input to determine a switching frequency for the full bridge switching arrangement and the output bridge switching arrangement; and control the switching of the full bridge switching arrangement and the output bridge switching arrangement at the switching frequency.

[0053] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment s) described hereinafter.

[0054] BRIEF DESCRIPTION OF THE DRAWINGS

[0055] For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0056] Fig. 1 illustrates a proposed converter arrangement;2024PF80520

[0057] 7

[0058] Fig. 2 illustrates waveforms of the converter arrangement in operation;

[0059] Fig. 3 is a flowchart illustrating an approach for determining a first phase shift; Fig. 4 illustrates values for the first phase shift in different use case scenarios; Fig. 5 illustrates an approach for determining a second phase shift;

[0060] Fig. 6 is a flowchart illustrating an approach for determining the second phase shift; and

[0061] Fig. 7 is a flowchart for a step usable in a proposed approach for determining the second phase shift.

[0062] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0063] The invention will be described with reference to the Figures.

[0064] It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the apparatus, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. These and other features, aspects, and advantages of the apparatus, systems and methods of the present invention will become better understood from the following description, appended claims, and accompanying drawings. It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

[0065] The invention provides a mechanism for controlling the operation of a converter arrangement comprising a full bridge switching arraignment and an output bridge switching arrangement connected by an inductor arrangement. A phase shift (a first phase shift) between a first leg and a second leg of the full bridge switching arrangement is controlled responsive to a voltage of a DC supply to the converter arrangement and a voltage of an AC mains connected to the converter arrangement. A phase shift between the output of the full bridge switching arrangement and a switching of the output bridge switching arrangement is controlled responsive to an integrated error between a measured time delay and a predefined time delay. The measured time delay is a time delay between a current through the inductor arrangement and the switching of the output bridge switching arrangement. The switching frequency will remain substantially constant over an AC mains period.

[0066] Figure 1 illustrates a proposed converter arrangement 100. The converter arrangement is designed for converting a DC input into an AC output, and vice versa.2024PF80520

[0067] 8

[0068] The converter arrangement 100 comprises an input interface 110, an output interface 120, a full bridge switching arrangement 130, an inductive arrangement 140, an output bridge switching arrangement 150, a sensing arrangement 160 and a controller 170.

[0069] The input interface 110 is configured to receive the DC input SDC. The DC input is produced or provided by a DC supply DC, such as a battery, (hydrogen) fuel cell or photovoltaic installation (i.e., a solar cell).

[0070] In particular, the input interface 110 may comprise a power input node NINI (i.e., a positive terminal) and a return line NIN2 (i.e., a negative or ground terminal). The DC input SDC is defined between the power input node and the return line.

[0071] The input interface 110 may further comprise an input capacitor CIN connected between the power input node and the return line.

[0072] This input capacitor CIN functions to smooth variations in the DC input voltage. The input capacitor may (also) act as a low-pass filter, reducing high-frequency noise or ripple that could be present in the DC input. The input capacitor also buffers the double-line-frequency ripple drawn by the converter since the converter injects a sinusoidal current into the AC mains. In some embodiments, the input capacitor serves also as the energy buffer for reactive power processed by the converter from the AC mains side.

[0073] The output interface 120 is configured to provide the AC output to an AC mains AC. Thus, the AC output may be designed for connection to an AC mains. This configuration allows the converter arrangement to interface directly with standard electrical grids, which typically operate on alternating current, particularly to feed or supply power into the grid.

[0074] The full bridge switching arrangement 130 is configured to receive the DC input and generate a bipolar square wave output SBSW. In particular, the full bridge switching arrangement 130 may include multiple switches that are controlled to alternately connect the DC input to output nodes in opposite polarities, thereby producing the bipolar square wave. It will be appreciated that the bipolar square wave output may take three values. More particularly, the bipolar square wave may alternate between a positive voltage value (e.g., approximately the value of the DC input SDC, discounting any switching losses), a negative voltage value (approximately the same magnitude as the value of the DC input SDC but of opposite polarity), and zero.

[0075] More specifically, the full bridge switching arrangement 130 comprises a first leg 131 (which can be labelled a left leg) and a second leg 132 (which can be labelled a right leg).2024PF80520

[0076] 9

[0077] Each leg 131, 132 of the full bridge switching arrangement 130 typically consists of two switches connected in series between the power input node NINI and the return line NIN2 of the input interface. Each leg 131, 132 may include a respective high-side switch and a low-side switch. Thus, the first leg 131 may comprise a first high-side switch 131 A and a first low-side switch 13 IB. Similarly, the second leg 132 may comprise a second high-side switch 132A and a second low-side switch 132B. These switches may be implemented using semiconductor devices such as MOSFETs (Metal -Oxi de- Semi conductor Field-Effect Transistors), wide bandgap device (such as GaN (Gallium Nitride) devices, SiC (Silicon Carbide) devices), or IGBTs (Insulated-Gate Bipolar Transistors). In some embodiments, multiple devices can be connected in parallel to handle high currents.

[0078] The switches in each leg are controlled to alternately connect the DC input SDC to the output of the full bridge switching arrangement 130 in opposite polarities. This switching action generates the bipolar square wave output SBSW.

[0079] The inductive arrangement 140 is configured to receive the bipolar square wave output and produce an intermediate output, e.g., between a first intermediate output node NINTI and a second intermediate output node NINT2. In particular, the inductive arrangement 140 comprises at least one inductive element (such as an inductor and / or transformer T1 wherein the leakage inductance of the transformer serves as the inductor). The inductive arrangement 140 effectively functions to determine the amount of power flow in the converter together with the switching frequency and the second phase shift. In a preferred embodiment where a resonant tank is formed with the inductive arrangement, it functions also to filter and shape the bipolar square wave to provide a sinusoidal current (forming the intermediate output SINT).

[0080] The inductive arrangement 140 may be preferably embodied as a resonant tank, as illustrated. The resonant tank comprises at least one capacitor Cr and at least one inductor Lr connected in series. Here, the resonant tank is embodied using a transformer T1 connected to a resonant inductor Lr and the resonant capacitance Cr. These are illustrated as separate elements to the transformer T1 for illustrative clarity but, in some examples, the transformer T1 contributes at least partially to the resonant inductor Lr and the resonant capacitor Cr (i.e., non-ideal features of the transformer may define at least part of the resonant inductor Lr and / or resonant capacitor Cr).

[0081] The inductive arrangement may comprise one or more further capacitors Cl, Coi, C02 (e.g., for performing additional filtering). In particular, the inductive arrangement2024PF80520

[0082] 10

[0083] may comprise a DC blocking capacitor Cl that functions to prevent saturation of any inductive element(s) of the inductive arrangement, e.g., the transformer Tl.

[0084] The inductive arrangement 140 may comprise or define an input node NINDI and a return node NIND2. The first leg 131 of the full bridge switching arrangement here: comprises a first switch (i.e., first high-side switch) connected between the power input node NINI and the input node NINDI of the inductive arrangement 140 and a second switch 13 IB (i.e., the first low-side switch) connected between the input node NINDI of the inductive arrangement 140 and the return line NIN2. Similarly, the second leg 132 here comprises a third switch 132A (i.e., the second high-side switch) connected between the power input node NINI and the return node NIND2 of the inductive arrangement 130 and a fourth switch 132B (i.e., the second low-side switch) connected between the return node NIND2 of the inductive arrangement 130 and the return line NIN2.

[0085] The output bridge switching arrangement 150 is connected between the inductive arrangement 140 and the output interface 120. The output bridge switching arrangement is configured to receive the intermediate output SINT and controllably connect the inductive arrangement 140 to the output interface 120 to provide the AC output SAC.

[0086] In particular, the output bridge switching arrangement is able to control the power flow across the inductive arrangement, which facilitates control over whether power flows from the full bridge switching arrangement to the output interface or vice versa.

[0087] The operation or switching of the output bridge switching arrangement may be controlled by an output bridge switching signal. The output bridge switching signal controls which switches of the output bridge switching arrangement are activated and deactivated.

[0088] In some examples, as illustrated, the output interface comprises a first output node Noi and a second output node N02. The AC output SAC is provided or defined between the first output node and the second output node.

[0089] The inductive arrangement may comprise a first intermediate output node NINTI and a second intermediate output node NINT2.

[0090] The output bridge switching arrangement 150 may comprise a first bidirectional switch SBDI and a second bidirectional switch SBD2. The bidirectional switches are connected between the inductive arrangement and the output interface. Specifically, the first bidirectional switch SBDI is connected between the first intermediate output node NINTI of the inductive arrangement and the first output node Noi of the output interface. The second bidirectional switch SBD2 is connected between the first intermediate output node NINTI and the second output node N02 of the output interface.2024PF80520

[0091] 11

[0092] As a working example, the first bidirectional switch may comprise a first MOSFET Ml and a second MOSFET M2 connected in a common source configuration. Similarly, the second bidirectional switch may comprise a third MOSFET M3 and a fourth MOSFET M4 connected in a common source configuration.

[0093] As an alternative example, the first bidirectional switch may comprise a first MOSFET and a second MOSFET connected in a common drain configuration. Similarly, the second bidirectional switch may comprise a third MOSFET and a fourth MOSFET connected in a common drain configuration.

[0094] Other suitable examples will be well known to the skilled person.

[0095] In some examples, the output interface 120 comprises a first output capacitor Coi connected between the first output node Noi and the second intermediate output node NINT2, and a second output capacitor C02 connected between the second intermediate output node NINT2 and the second output node N02.

[0096] In this configuration, the first output capacitor and the second output capacitor hold a DC voltage, each being 50% of the instantaneous AC mains voltage. In some embodiments, the first output capacitor and the second output capacitor have a relatively low capacitance such that they become part of the resonant capacitor. In that case the voltage over the capacitors will have significant ripple over one switching frequency period. However, their mean value still holds 50% of the instantaneous AC mains voltage. The output bridge switching arrangement thereby doubles the output voltage from the inductance arrangement, thus reducing transformer turns ratio (if used) by half. The first and second output capacitors also contribute to performing EMI filtering of the output signal.

[0097] In some cases, Coi and C02 are able to totally replace the resonant capacitor Cr becoming the resonant capacitor themselves. Thus, in some examples, the resonant capacitor Cr can be omitted, with the output capacitors Coi, C02 functioning as a capacitance for the inductor arrangement 140. The output capacitors Coi and C02 may thereby serve as both the resonant capacitor and the voltage doubler.

[0098] In some examples, the output interface comprises an output inductor L2, which connects between the output bridge switching arrangement 150 and the output interface 120. In particular, the output inductor L2 may be connected between the first output capacitor Coi and the first output node Noi. The output inductor L2 contributes to performing EMI filtering of the output signal.

[0099] The controller 170 controls the operation of the full bridge switching arrangement 130 and the output bridge switching arrangement 150. In particular, the2024PF80520

[0100] 12

[0101] controller is configured to control a switching (i.e., the timing of any switching) performed by any switch or transistor of both switching arrangements 130, 150 using appropriate switching signals.

[0102] The controller 170 may control the operation of the full bridge switching arrangement 130 using a phase-shifted full bridge (PSFB) technique. In this technique, the first leg 131 and the second leg 132 may each be operated with a fixed duty cycle (typically around 50%). Put another way, the duty cycle of each individual leg may be fixed. More particularly, the controller provides switching signals to the high-side 131 A, 132A and low-side 13 IB, 132B switches of each leg to control their on and off states. The high-side and low-side switches in each leg are switched complimentary.

[0103] The switching signal(s) may be generated by a switching signal generator 175 of the controller 170 (e.g., internal times of a microcontroller). The switching signal(s) may be provided to the switches of the full bridge switching arrangement 130 by a first drive arrangement 191 configured to drive the switches using the switching signals.

[0104] The duty cycle of a leg is determined by the proportion of time the high-side switch of the respective switch is on compared to the total switching period for the respective leg. The switching frequency of both legs is the same.

[0105] The control signals for the first and second legs are phase shifted by a first phase shift phil. The range of phil is from 0° to 180°, and the value of phil is defined or controlled by the controller 170, e.g., by a first phase shift determination unit 171.

[0106] The value of the first phase shift effectively defines or controls the average magnitude of the power within one high frequency switching cycle provided to the inductance arrangement 140, which in turn affects the power available for transfer to the output. When the phase shift is 0°, both legs switch simultaneously (but with opposite polarity), resulting in maximum power transfer to the inductance arrangement. As the phase shift increases towards 180°, there are periods where switches in opposite legs are conducting simultaneously, effectively creating a short circuit across the input of the inductive arrangement, resulting in the effective voltage and power transfer decreasing.

[0107] Thus, the first phase shift phil effectively defines the duty cycle of the bipolar square wave output SBSW. This must be distinguished from the (preferably fixed) duty cycle of the control of each individual leg.

[0108] The controller 170 controls the output bridge switching arrangement 150, using an output bridge switching signal, such that the intermediate output SINT takes the shape of a square wave. The value of the intermediate output SINT thereby follows the2024PF80520

[0109] 13

[0110] switching of the output bridge switching arrangement, i.e., and therefore the output bridge switching signal. The switching frequency of the output bridge switching arrangement is the same as the switching frequency of the full bridge switching arrangement 130.

[0111] The intermediate output SINT is controlled by the controller 170 to be phased shifted from the bipolar square wave SBSW defined by the full bridge switching arrangement by a second phase shift phi2.

[0112] More particularly, the controller 170 provides switching signals to switches of the output bridge switching arrangement 150 to control their on and off states. The switching signal(s) may be generated by the switching signal generator 175 of the controller 170. The switching signal(s) may be provided to the switches of the output bridge switching arrangement 150 by a second drive arrangement 192 (e.g., gate driver) configured to drive the switches using the switching signals. Preferably, the controller 170 is placed on the primary side of the circuit. Thus, the drive arrangement 192 may comprise a galvanic isolation element to the controller 170, e.g., comprising one or more optocouplers or similar.

[0113] The value of the second phase shift phi2 is also defined or controlled by the controller, e.g., by a second phase shift determination unit 172.

[0114] This second phase shift phi2 is defined as the phase shift between the fundamental component of the (voltage component of the) bipolar square wave SBSW and the fundamental component (voltage component of the) intermediate output SINT. In this context, the fundamental component is the lowest frequency (i.e., the switching frequency) sinusoidal wave that forms the basis of a complex waveform. In particular, for periodic signals such as a square wave or bipolar square wave, the fundamental component is the sinusoidal (sine) wave with the same frequency as said periodic signal. Power flows from the DC supply to the AC mains when phi2 is greater than 0. The proposed topology also supports bidirectional power flow, as power will flow from the AC mains to the DC supply when phi2 is less than 0.

[0115] The skilled person will readily appreciate how the controller can be configured to generate switching or control signals (e.g., gate signals) for appropriately controlling the operation of the switches of each switching arrangement to function or operate with the defined parameters, e.g., at the defined first phase shift, second phase shift and / or switching frequency.

[0116] Nonetheless, one approach for generating the control signals for the converter arrangement 100 (Figure 1) is hereafter described for the sake of completeness. This approach may be employed by the switching signal generator 175.2024PF80520

[0117] 14

[0118] A first timer is used to generate a first switching signal which defines a switching of the switches in the first leg (left leg) of the full bridge switching arrangement. The first switching signal operates at the switching frequency defined by the controller, e.g., using a previously described approach. As previously explained, the switches in the first leg are controlled to have a 50% duty cycle. The switches are complementarily controlled such that the first high-side switch is activated (i.e., made conductive) when the first low-side switch is deactivated (and vice versa).

[0119] In general, in a first control approach, when the first switching signal is high, then the first high-side switch is activated and the first low-side switch is deactivated and when the first switching signal is low, then the first high-side switch is deactivated, and the first low-side switch is activated. In a second control approach, when the first switching signal is low, then the first high-side switch is activated and the first low-side switch is deactivated and when the first switching signal is high, then the first high-side switch is deactivated, and the first low-side switch is activated.

[0120] A second timer is used to generate a second switching signal that is phase shifted (i.e., delayed) from the first switching signal. The second switching signal defines a switching of the switches in the second leg (right leg) of the full bridge switching arrangement. As previously explained, the switches in the second leg are controlled to have a 50% duty cycle. The switches are complimentary controlled such that the first high-side switch is activated (i.e., made conductive) when the first low-side switch is deactivated (and vice versa).

[0121] In general, in the first control approach, when the second switching signal is high, then the second high-side switch is activated and the second low-side switch is deactivated and when the second switching signal is low, then the second high-side switch is deactivated, and the second low-side switch is activated. In the second control approach, when the second switching signal is low, then the second high-side switch is activated and the second low-side switch is deactivated and when the second switching signal is high, then the second high-side switch is deactivated, and the second low-side switch is activated.

[0122] The second timer is configured to generate the second switching signal to have a phase angle of 180° - phil, where phil is the first phase shift. This configures the phase shift between the first leg and the second leg to be equal to the first phase shift.

[0123] A third timer generates the output bridge switching signal that controls or defines the switching of the output bridge switching arrangement and is shifted from the first2024PF80520

[0124] 15

[0125] switching signal by a third switching phase shift phi3, which may be defined by the first phase shift phil and the second phase shift phi2 using the following equation:

[0126]

[0127] In an alternative embodiment, the determination of the third phase shift phi3 may be skipped and integrated into the determination process of phi2. The modified version of this error integrator, later described, will directly generate phi3 (i.e., phi2 actually becomes phi3) because of this offset. Put another way, -phi 1 / 2, may be automatically generated by the integrator.

[0128] This configures the phase shift between the intermediate output SINT and the bipolar square wave SBSW defined by the full bridge switching arrangement to be the second phase shift phi2.

[0129] The output bridge switching signal defines a high side switch signal H and a low side switch signal L. These control signals are used together with the polarity of the AC mains to define the gate signals for each MOSFET Ml, M2, M3, M4 of the output bridge switching arrangement.

[0130] More specifically, when the voltage magnitude of the AC mains is positive, then M2 and M4 are activated, and Ml and M3 are switched in a complimentary manner according to the output bridge switching signal. More particularly, Ml may be controlled by the high side switch signal and M3 may be controlled by the low side switch signal.

[0131] Similarly, when the voltage magnitude of the AC mains is negative, then Ml and M3 are activated, and M2 and M4 are switched complimentary according to the output bridge switching signal. More particularly, M4 may be controlled by the high side switch signal and M2 may be controlled by the low side switch signal.

[0132] Of course, although not mentioned in detail, for each leg of the full bridge switching arrangement, the switching between any activation and deactivation of any high-and low-side switches may be controlled during a commutation period such that they are simultaneously deactivated for a small period (deadtime) during the switch between activation of the first high-side switch and activation of the first low-side switch.

[0133] In the above-described embodiment, all the three timers are exemplarily implemented as an up and down counter (triangle wave). The counter value is compared to a fixed setpoint being halfway of the maximum counter value (for the 50% fixed duty cycle of2024PF80520

[0134] 16

[0135] the switching legs). The logic output is that the high side MOSFET (131 A, 132A, Ml, M4) gate signal goes low when counter value exceeds halfway of the maximum counter value. Deadtime blocks are used within the timer units for generating deadtime between high and low side MOSFETs. This is known to the skilled in the art. Other timer implementations are also possible.

[0136] Figure 2 illustrates waveforms demonstrating the operation of the converter arrangement 100 (Figure 1). Continued reference is made to elements illustrated in Figure 1 where appropriate.

[0137] Figure 2 illustrates a first waveform 210 representing the bipolar square wave output SBSW produced by the full bridge switching arrangement 130, a second waveform 220 representing the (square wave shaped) intermediate output SINT at the output of the inductance arrangement 140 (and defined / controlled by the output bridge switching arrangement) and a third waveform 230 representing an inductance current IR in the inductance arrangement. An alternative label for the inductance current his a resonant current.

[0138] The waveshape of the IR current to the inductance arrangement depends upon the voltage of the bipolar square wave output SBSW, the voltage of the intermediate output SINT, the inductance arrangement and the switching frequency fs of the switches of both switching arrangements.

[0139] The present disclosure recognizes that appropriate control of the switching performed by the full bridge switching arrangement 130 and the output bridge switching arrangement 150 can improve the efficiency and reduce the EMI noise of the power conversion.

[0140] It is recognized that with proper control by the controller 170, zero voltage switching can be achieved for all switches of both switching arrangements.

[0141] In general, to achieve zero voltage switching of the full bridge switching arrangement 130, the inductance current IR should be positive during negative-going transition of the bipolar square wave output SBSW and vice versa. To achieve zero-voltage switching of the output bridge switching arrangement 150, the inductance current IR should be negative during negative-going transition of the intermediate output SINT and vice versa.

[0142] In particular, it is recognized that to achieve zero voltage switching of the switching converters, a proper balance between the volt-seconds of the bipolar square wave output SBSW and the intermediate output SINT should be maintained. More particularly, when the voltage difference between the two outputs SBSW, SINT is high, the active time (duty cycle)2024PF80520

[0143] 17

[0144] of the outputs should be reduced to maintain the voltage-second balance. This balance reduces the circulating power in the tank, thus helping improve efficiency. It is recognized that the voltage of the intermediate output SINT will not have a constant amplitude, rather it is variable along the cycle of the AC mains. As such, the effective duty cycle of the bipolar square wave output SBSW should be controlled to limit the amount of reactive power and allow the output bridge switching arrangement to perform zero voltage switching. As previously explained, the effective duty cycle of the bipolar square wave output SBSW is controlled by the first phase shift phil. It should also be noted that the wave shape of SINT is for illustration only, showing an ideal case with very large capacitance for Coi and C02. In practice Coi and C02 may have limited value and often becomes part of the resonance tank, thus there can be significant variation of the voltage in each half cycle (i.e., it will manifest as a signal with such a flat shape as shown in Figure 2).

[0145] Thus, to facilitate zero voltage switching of at least the output bridge switching arrangement it is herein proposed to configure the controller 170 to determine a first phase shift by performing a first determination process comprising processing at least the voltage of the DC input VDC and the voltage of the AC mains VAC and control a phase shift between the left leg and the right leg of the full bridge switching arrangement to match the determined first phase shift.

[0146] The first phase determination process may be performed by a first phase determination unit 171 of the controller 170. The control of the phase shift between the left leg 131 and right leg 132 of the full bridge switching arrangement 130 may be performed by the switching signal generator 175 of the controller 170.

[0147] This approach facilitates determination of a first phase shift that is able to define a duty cycle for the bipolar square wave output SBSW that limits the amount of reactive power.

[0148] Accordingly, the sensing arrangement 160 is configured to monitor a voltage of the DC input VDC and a voltage of the AC mains VAC. In particular, the sensing arrangement may comprise a first voltage sensor 161 for monitoring a voltage of the DC input VDC and a second voltage sensor 163 for monitoring a (e.g., instantaneous) voltage of the AC mains VAC. This information is provided to the controller 170, specifically a first phase determination unit 171, to enable it to perform the first determination process.

[0149] Components for performing voltage monitoring (for forming a portion of the sensing arrangement) are well known to the skilled person. In particular, the sensing arrangement may comprise one or more voltage sensors connected to the input interface and2024PF80520

[0150] 18

[0151] output interface respectively. These voltage sensors may provide analog voltage signals that are proportional to the DC input voltage and AC mains voltage.

[0152] The controller 170 is also configured to determine a second phase shift phi2 by performing a second determination process.

[0153] The proposed second determination process recognizes that for improved efficiency, it would be advantageous to operate the switches of the output bridge switching arrangement (e.g., the bidirectional switches of the switching arrangement) with zero-voltage switching (ZVS) or near-zero voltage switching. The value of the second phase shift phi2 define the switching condition of the output bridge switching arrangement.

[0154] It has been recognized that to achieve ZVS, the switching of the output bridge switching arrangement should be controlled to lag the inductance current IR by a particular angle (e.g., 10°) or time delay. In this way, the switches are turned off with a positive current and then the current is diverted to the body diode of the opposite switch thus creates a ZVS condition for that switch.

[0155] The second phase determination process may be performed by a / the second phase determination unit 172 of the controller 170. The switching signal generator 175 may control the switching of the full bridge switching arrangement 130 and the output bridge switching arrangement 150 such that the phase angle between the bipolar square wave SBSW and the switching of the output bridge switching arrangement (i.e., the intermediate signal SINT) matches the second phase phi2. One example approach for performing this control has been previously described.

[0156] The proposed approach monitors a time delay between the zero crossing of the inductance current IR (i.e., the current through the inductance arrangement) and the switching of the output bridge switching arrangement.

[0157] With reference to Figure 2, this time delay Td is representable by a time delay between the zero crossing of the inductance current IR and a rising edge of the intermediate output SINT, which occurs upon a switching of the output bridge switching arrangement.

[0158] By way of example, the switching of the output bridge switching arrangement may be defined by the high side switch signal H previously described. When the voltage magnitude of the AC mains is positive, then M2 and M4 are (held) activated, and Ml and M2 are switched in a complimentary manner according to the output bridge switching signal. Similarly, when the voltage magnitude of the AC mains is negative, then Ml and M3 are (held) activated, and M2 and M4 are switched complimentary according to the output bridge switching signal.2024PF80520

[0159] 19

[0160] The switching of the output bridge switching arrangement may therefore be defined by the value of the high side switch signal H. More particularly, a switching of the output bridge switching arrangement may be represented by a rising edge of the high side switch signal.

[0161] In this context, for the illustrated output bridge switching arrangement (Figure 1), a rising edge of the high side switch signal represents an activation of the MOSFET Ml (when the volage magnitude of the AC mains is positive) or an activation of the MOSFET M4 (when the voltage magnitude of the AC mains is negative). Other suitable examples for a switching of the output bridge switching arrangement will be apparent to the skilled person familiar with such switching arrangements.

[0162] Example approaches that may be employed by the controller for performing the first determination process are hereafter described.

[0163] In a first variant, the first determination process may comprise processing the voltage of the DC input VDC and the voltage of the AC mains VAC using a look-up table to identify a value for the first phase shift.

[0164] The values in the look-up table may be defined through an iterative trial and error process. For example, different combinations of DC input voltage and AC mains voltage may be tested experimentally or in simulation to determine optimal or appropriate first phase shift values that achieve desired performance characteristics such as zero-voltage switching. These empirically determined optimal values may then be stored in the look-up table for use during operation of the converter arrangement. The trial and error process allows the look-up table to be populated with values that are tailored to the specific converter design and operating conditions.

[0165] Figure 3 is a flowchart illustrating a second variant for the first determination process that may be employed by the controller.

[0166] In particular, the first determination process may comprise determining 310 an intermediate first phase shift (IFPS), also known as a potential first phase shift, and setting the first phase shift responsive to the intermediate first phase shift.

[0167] One approach to determining the intermediate first phase shift is to perform a sub-step 311 of determining a first ratio between the absolute value of the voltage of the AC mains VAC and the voltage of the DC input VDC; and perform a sub-step 312 of processing the determined first ratio to determine the intermediate first phase shift.

[0168] In a simple example, a look-up table or similar is used to map the determined first ratio to a corresponding value for the intermediate first phase shift. The value(s) in the2024PF80520

[0169] 20

[0170] lookup table may be defined using equation (1) detailed below, or by trial-and-error by experimentation with a simulation or real-life version of the converter arrangement (e.g., with a target property, such as zero-voltage switching), an example of which has been previously described.

[0171] In a more complex example, the first determination process may comprise processing the first ratio to determine the intermediate phase shift using the following equation:

[0172] IFPS = 180

[0173]

[0174] wherein abs(V0) is the absolute value of the voltage of the AC mains VAC, VDC is the voltage of the DC input, and K is a predefined constant value related to the transformer turns ratio.

[0175] The value of K may also, for instance, be defined as a ratio between a maximum or minimum expected voltage of the DC input VDC MAX or VDC MIN and a maximum expected voltage of the AC mains VAC MAX. The values of such maximum or minimum expected voltages can be readily established, e.g., from known properties of the AC mains supply and / or DC supply.

[0176] In a simple example, the intermediate first phase shift, IFPS, is simply defined as the first phase shift.

[0177] In more complex examples, a minimum and / or maximum phase shift is defined for the first phase shift.

[0178] Thus, the first determination process 300 may comprise a step 330 of receiving first phase shift information identifying a minimum phase shift and / or a maximum phase shift for the first phase shift.

[0179] If a maximum phase shift is defined, and if the IFPS exceeds the maximum phase shift, the controller may limit the first phase shift to the defined maximum value. Thus, responsive to the IFPS being above the maximum phase shift FPSMAX, e.g., determined in a first determination process 341, the first determination process may comprise setting 342 the maximum phase shift as the first phase shift.

[0180] Applying a maximum phase shift for the first phase shift will extend the zero voltage switching region for the full bridge switching arrangement when the magnitude of the AC mains is near zero. In particular, when the AC mains is near zero, then the value of the2024PF80520

[0181] 21

[0182] intermediate first phase shift (if calculated according to equation (1)) would be close to 180°. This would result in a very small duty ratio for the bipolar square wave output SBSW, meaning that the ZVS condition may be lost for at least the high-side switches of the full bridge switching arrangement.

[0183] The maximum phase shift may, for instance, be no more than 120° (e.g., around 120°. This limits the minimum duty cycle for the bipolar square wave output SBSW to about 33%. This provides a minimum current flow to the inductance arrangement for facilitating soft commutation of at least the left-leg of the full bridge switching arrangement. The desired range for maximum phase shift can be 100° to 170°.

[0184] Similarly, if a minimum phase shift is defined, and if the IFPS falls below the minimum phase shift, the controller may set the first phase shift to the defined minimum value. Thus, responsive to the intermediate first phase shift IFPS falling below the minimum phase shift FPSMIN (identified by the first phase shift information), e.g., determined in a second determination process 351, the first determination process may comprise setting 352 the minimum phase shift as the first phase shift.

[0185] The minimum phase shift may, for instance, be 0°. Setting the minimum phase shift (most preferred value 0°) functions to prevent a (temporary) negative phase shift resulting from for instance some transients on the voltage VDC and / or Vo(IFPS can in principle be negative, see equation (1)).

[0186] Of course, if the IFPS does not fall below the minimum phase shift and / or above the maximum phase shift, then the IFPS may be set (in step 360) as the first phase shift.

[0187] Figure 4 is a graph illustrating example values for the first phase shift phil as determined using the second variant for the first determination process outlined above, and using equation (1). For the purposes of this demonstration, the minimum phase shift is 0° and the maximum phase shift is 120°.

[0188] A first waveform 410 illustrates the absolute value of the voltage of the AC mains VAC. A second waveform 420 illustrates the value of the first phase shift where the voltage of the DC input VDC is held at 40V. A third waveform 430 illustrates the value of the first phase shift where the voltage of the DC input VDC is held at 60V. A fourth waveform 440 illustrates the value of the first phase shift where the voltage of the DC input VDC is held at 20V.

[0189] In a third variant, the first determination process may comprise using a machine learning model to predict an appropriate value for the first phase shift.2024PF80520

[0190] 22

[0191] In this variant, a neural network or other machine learning algorithm may have been trained using historical data of voltages of the AC mains, voltages of the DC input and corresponding first phase shifts (e.g., user-defined first phase shifts). Example approaches for training a machine-learning algorithm (e.g., using backpropagation techniques, gradient descent techniques and the like) are well known and established in the art, and are not described in detail for the sake of conciseness.

[0192] In such approaches, the first determination process may comprise processing the voltage of the AC mains VAC and voltage of the DC input VDC (as provided by the sensing arrangement) using the machine learning algorithm to produce a value for the first phase shift.

[0193] Example approaches that may be employed by the controller for performing the second determination process are hereafter described.

[0194] Figure 5 is a diagram illustrating a proposed approach for performing the second phase determination process using the inductance current IR and the switching of the output bridge switching arrangement, represented by the high side switch signal H (i.e., the output bridge switching signal previously described). Continued reference will be made to elements of the converter arrangement 100, where appropriate.

[0195] It is noted that the frequency of the inductance current and the switching of the output bridge switching arrangement is the same and known (as this is defined by the switching frequency of the full bridge switching arrangement and the output bridge switching arrangement). As such, it is trivial to express a time delay between the two signals in the time domain (e.g., as a unit of time) or in a phase domain (e.g., as a unit of phase). The two mechanisms are therefore considered to be interchangeable.

[0196] However, it may be advantageous in a variable switching frequency system to control the time delay instead of phase angle for achieving ZVS conditions since the time required for soft commutation stays the same when the switching frequency changes. That is, at a higher frequency, a larger phase angle is required, while using time delay control, this parameter can remain constant over frequency.

[0197] The inductance current is sensed by an inductance current sensing arrangement 181. This may take the form, for instance, of a current transformer or a sensing resistor connected in series with the inductance arrangement 140, where a voltage across the sensing resistor represents the sensed inductance current. Although illustrated as a separate component, in practice, the inductance current sensing arrangement 181 forms part of the sensing arrangement 160.2024PF80520

[0198] 23

[0199] Thus, the converter arrangement 100 (and specifically, the sensing arrangement 160) may comprise an inductance current sensing arrangement 181 configured to monitor the inductance current IR.

[0200] The inductance current is processed, by a zero-crossing detection arrangement 182, to monitor or identify zero crossings of the monitored inductance current IR. Thus, the converter arrangement 100 may comprise a zero-crossing detection arrangement 182 configured to monitor or track real zero crossings (using proper filters if need to avoid multiple zero crossings near each other) of the inductance current IR. A wide variety of zerocrossing detection arrangements are known in the art, and are common in the field of electrical signal processing.

[0201] In particular, the zero-cross detection arrangement may be configured to monitor or identify only a negative-positive zero crossings of the monitored inductance current.

[0202] The zero-crossing detection arrangement 182 thereby produces a ZCD signal IR ZCD that identifies any zero crossings of the monitored inductance current IR.

[0203] The second phase shift determination unit 172 is configured to process the ZCD signal and the output bridge switching signal H to determine the second phase shift.

[0204] In particular, the second phase shift determination unit is configured to monitor a time delay between a zero crossing of the current through the inductance arrangement and a switching of the output bridge switching arrangement (i.e., the output bridge switching signal H). As previously mentioned, this time delay may be expressed in units of time or in units of phase, as the two are readily interchangeable for proposed systems. However, it may be advantageous to employ a time delay expressed in units of time, for use in a variable switching frequency approach as explained before.

[0205] More specifically, the second phase shift determination unit 172 may comprise a time delay measurement unit 520 configured to monitor (as a monitored time delay Td) a time delay between a zero crossing of the current through the inductance arrangement and a switching of the output bridge switching arrangement. As the switching of the output bridge switching arrangement is controlled by the controller, the switching of the output bridge switching arrangement is readily available.

[0206] In particular, the time delay measurement unit 520 may monitor, as the monitored time delay, a time delay between a zero crossing of the current through the inductance arrangement and a switching moment (e.g., an activation or switching ON) of the2024PF80520

[0207] 24

[0208] first MOSFET Ml (e.g., when the volage magnitude of the AC mains is positive) or the fourth MOSFET M4 (e.g., when the volage magnitude of the AC mains is negative).

[0209] The second phase shift determination unit is then configured to integrate an error between the monitored time delay and a predefined time delay Td*. This may be performed using an integration unit 530, e.g., formed from an operation amplifier integrator Ul, CIO, RIO. This produces an integrated error phi2x.

[0210] Thus, the second phase shift determination unit 172 may comprise an integration unit 530 configured to integrate the error (i.e., difference) between the monitored time delay Td and a predefined time delay Td*.

[0211] The second phase shift determination unit is then configured to determine the second phase shift using the integrated error phi2x.

[0212] In a simple example, the second phase shift is set to the value of the integrated error phi2x.

[0213] In other examples, the value of the second phase shift is clipped or limited to a maximum and / or minimum time delay, e.g., using a limitation unit 540.

[0214] Figure 6 illustrates an example method 600 performed by the second phase determination unit 172. Thus, method 600 provides an example approach for performing the second determination process.

[0215] The method 600 comprises a step 610 of calculating the integrated error phi2x. This is performed using a previously described approach.

[0216] The method 600 also comprises a step 611 of defining a maximum error value and / or a minimum error value (i.e., second phase information).

[0217] If a maximum error value is defined, and if the integrated error phi2x exceeds the maximum error value shift, the controller may set the second phase shift to the defined maximum error value. Thus, responsive to the integrated error being above the maximum error value SPSMAX, e.g., determined in a determination process 621, the second determination process 600 may comprise setting 622 the maximum error value as the second phase shift.

[0218] Applying a maximum error value for the second phase shift will result in a reduced amount of reactive power in the converter. This is because maximum (active / true) power transfer taking place at 90° and above 90° (active / true) power transfer starts to decrease while reactive power further increases. Thus it is desirable to limit the maximum value of phi2 to 90°. The maximum error value may, for instance, be a value representing a2024PF80520

[0219] 25

[0220] phase of no more than 90° (e.g., around 90°). The range for the maximum error value maximum phase shift may be between 60° and 90°.

[0221] Similarly, if a minimum error value is defined, and if the integrated error phi2x falls below the minimum error value, the controller may set the second phase shift to the defined minimum error value. Thus, responsive to the integrated error phi2x falling below the minimum error value SPSMIN (identified by the second phase shift information), e.g., determined in a determination process 631, the second determination process 600 may comprise setting 632 the minimum phase shift as the second phase shift.

[0222] The minimum error value shall not fall below 0° in case a positive power flow from the DC source to the AC mains is desired. At phase angle below 0° the power flow reverses. The minimum error value may, for instance, be 10°. Setting the minimum error value (e.g., to this preferred value of 10°) achieves a better switching condition for the full bridge switching arrangement 130 and output bridge switching arrangement 150 since when the second phase shift phi2 approaches 0° the amplitude of IR gets much smaller.

[0223] Of course, if the integrated error does not fall below the minimum phase shift and / or above the maximum phase shift, then the integrated error phi2x may be set (in step 640) as the second phase shift.

[0224] Figure 7 is a flowchart illustrating an approach for performing step 610 of calculating or generating the integrated error phi2x.

[0225] In this approach, step 610 comprises sensing 710 the inductance current and generating the ZCD signal. This can be performed using a current sensing system and a zerocrossing detection system, as previously described.

[0226] Step 610 may further comprise measuring 720 the time delay Td between the inductance current and the switching of the output bridge switching arrangement (e.g., as represented by the output bridge switching signal, specifically the high side switch signal H).

[0227] Step 610 may further comprise determining 730 an error between the measured time delay Td and a predefined time delay Td* (i.e., a setpoint). This can be trivially performed by determining a difference between the measured time delay Td and the predefined time delay Td*.

[0228] It will be appreciated, steps 710, 720 and 730 are iteratively repeated. This produces an error signal that changes with (i.e., represents) the error between the measured time delay Td and a predefined time delay Td*.2024PF80520

[0229] 26

[0230] Step 610 further comprises integrating 740 the error signal produced by step 730. This integrated error function as an intermediate phase shift suited for controlling or defining the second phase shift.

[0231] In some examples, the predefined time delay is between 0.2 to 2 microseconds, e.g., 0.5 microseconds.

[0232] In some examples, step 610 further comprises defining 750 the predefined time delay Td*. Step 750 may be performed, for instance, by processing the amplitude of the voltage of the AC mains VAC and / or the amplitude of the inductance current IR.

[0233] It is recognized that the higher the momentary value of the AC mains (voltage) VAC and / or the lower the inductance current IR, the larger time delay Td is required for ZVS. Thus, in some examples, step 750 comprise increasing the value of the predefined time delay Td* responsive to the voltage magnitude of the AC mains VAC increasing and / or increasing the value of the predefined time delay Td* response to the inductance current IR reducing. The amplitude IR is determined by the amount of power flowing in the system, which may be determined by a Maximum Power Point Tracking (MPPT) algorithm or similar.

[0234] Turning back to Figure 1, in some examples, the sensing arrangement 160 may be configured to monitor a current IDC of the DC input. This may be performed by a first current sensing unit 162.

[0235] In such examples, the controller 170 may be configured to process the voltage of the DC input VDC and the current of the DC input IDC to determine a switching frequency for the full bridge switching arrangement and the output bridge switching arrangement; and control the switching of the full bridge switching arrangement and the output bridge switching arrangement at the switching frequency.

[0236] The determination of the switching frequency fs may be performed by a switching frequency determination unit 173 of the controller 170.

[0237] To improve efficiency of power extraction from the DC source, particularly in the case of a photovoltaic input, the controller may employ a Maximum Power Point Tracking (MPPT) algorithm. One common MPPT technique mentioned is the perturbation method, also known as the "perturb and observe" method. This algorithm works by making small adjustments to the switching frequency and observing the resulting changes in power output. By iteratively perturbing the system and moving towards the point of maximum power, the MPPT algorithm is able to configure the converter arrangement to operate closer to an optimal point for power extraction from the DC source.2024PF80520

[0238] 27

[0239] The relationship between switching frequency and power conversion is inverse in the converter arrangement. As the switching frequency increases, so the amount of power converted from the DC input to the AC output generally decreases. This characteristic provides the controller with a means to regulate the power flow through the converter by adjusting the switching frequency alone.

[0240] It is important to note that the MPPT adjusts the switching frequency at a much lower rate than the mains frequency. Thus, the switching frequency remains fairly constant over an AC mains period. This control scheme has the advantage of ease of implementation using timers in a microprocessor.

[0241] In some further examples, the sensing arrangement is configured to monitor a current of the AC mains IAC in and amplitude and phase with respect to the sinusoidal AC output voltage. This may be performed using a second current sensor 164.

[0242] In such examples, the controller may be further configured to process the voltage of the AC mains, the voltage of the DC input VDC, the current of the AC mains IAC and the current of the DC input to determine a switching frequency for the full bridge switching arrangement and the output bridge switching arrangement.

[0243] In such examples, the controller may be further configured to process the AC mains IAC through a feedback control loop that regulates IAC to a desired sinusoidal waveshape by changing the first and / or the second phase shift together with the described the first and the second determination process. This can further reduce the THD in IAC and / or achieve bidirectional power flow control.

[0244] Of course, the controller is further configured to control the switching of the full bridge switching arrangement and the output bridge switching arrangement at the switching frequency.

[0245] Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality.

[0246] Functions implemented by a controller may be implemented by a single processor or by multiple separate processing units which may together be considered to constitute a "processor". Such processing units may in some cases be remote from each other and communicate with each other in a wired or wireless manner.

[0247] The controller may be embodied as a microprocessor or in programmable logic, like an FPGA. In some examples, the microprocessor may be a general-purpose2024PF80520

[0248] 28

[0249] processor programmed with software to perform the control functions described.

[0250] Alternatively, the microprocessor may be a specialized digital signal processor (DSP) designed for performing power control applications. The microprocessor may include internal memory for storing program instructions and data, as well as various peripheral interfaces for communicating with the sensing arrangement, switching arrangements (e.g., via one or more drive arrangements), and other components of the converter.

[0251] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0252] If the term "adapted to" is used in the claims or description, it is noted the term "adapted to" is intended to be equivalent to the term "configured to". If the term "arrangement" is used in the claims or description, it is noted the term "arrangement" is intended to be equivalent to the term "system", and vice versa.

[0253] Ordinal numbers (e.g. “first”, “second” and so on) have been used purely to distinguish different elements from one another for the sake of clarity, and does not necessarily imply a specific order, importance, relationship, or presence of all numbered elements. Reference to a non-“firsf ’ (e.g. “second” or “third”) element does not necessitate that a “first” element be present. The skilled person would be capable of relabeling any such elements as appropriate (e.g. relabeling a “second” element as a “first” element if only the second element is present).

[0254] Any reference signs in the claims should not be construed as limiting the scope.

Claims

2024PF8052029CLAIMS:

1. A converter arrangement (100) for bidirectional conversion of a DC input (SDC) to an AC output (SAC), the converter arrangement comprising:an input interface (110) configured to receive the DC input;an output interface (120) configured to provide the AC output to an AC mains (AC);a full bridge switching arrangement (130) connected to the DC input, the full bridge switching arrangement having a first leg (131) and a second leg (132) for providing a bipolar square wave output (SBSW);an inductance arrangement (140) connected to receive the bipolar square wave output and produce an intermediate output (SINT);an output bridge switching arrangement (150) connected between the inductive arrangement and the output interface;a sensing arrangement (160) configured to monitor a voltage of the DC input (VDC); a voltage of the AC mains (VAC) and a current (IR) through the inductance arrangement;a controller (170) configured to control an operation of the full bridge switching arrangement and the output bridge switching arrangement, wherein the controller is configured to:determine a first phase shift (phi 1) by performing a first determination process (300) comprising processing at least the voltage of the DC input and the voltage of the AC mains;control a phase shift between the left leg and the right leg of the full bridge switching arrangement to match the determined first phase shift;determine a second phase shift (phi2) by performing a second determination process (500) comprising:monitoring a time delay between a zero crossing of the current through the inductance arrangement and a switching of the output bridge switching arrangement;2024PF8052030integrating an error between the monitored time delay and a predefined time delay; anddetermining the second phase shift using the integrated error; andcontrol a phase angle between the bipolar square wave output and the switching of the output bridge switching arrangement to match the determined second phase shift,such that the phase angle is arranged to remain constant over frequency while achieving zero voltage switching.

2. The converter arrangement of claim 1, wherein the first determination process comprises:receiving first phase shift information identifying a minimum phase shift for the first phase shift;processing the voltage of the DC input VDC and the voltage of the AC mains VAC to determine a potential first phase shift;responsive to the potential first phase shift falling below the minimum phase shift identified by the first phase shift information, setting the minimum phase shift as the first phase shift.

3. The converter arrangement of claim 1 or 2, wherein the first determination process comprises:receiving first phase shift information identifying a maximum phase shift for the first phase shift;processing the voltage of the DC input VDC and the voltage of the AC mains VAC to determine a potential first phase shift;responsive to the potential first phase shift being above the maximum phase shift identified by the first phase shift information, setting the maximum phase shift as the first phase shift.

4. The converter arrangement of any one of claims 1 to 3, wherein the first determination process comprises:determining a first ratio between the absolute value of the voltage of the AC mains VAC and the voltage of the DC input VDC; and2024PF8052031processing the determined first ratio to determine the first phase shift.

5. The converter arrangement of claim 4, wherein the first determination process comprises determining an intermediate first phase shift, IFPS, using the following equation:IFPS = 180wherein abs(V0) is the absolute value of the voltage of the AC mains VAC, voltage of the AC mains VAC, VDC is the voltage of the DC input VDC, and K is a predefined constant value.

6. The converter arrangement of any one of claims 1 to 5, wherein:the output interface comprises a first output node and a second output node, wherein the AC output is provided between the first output node and the second output node;the inductive arrangement comprises a first intermediate output node; and the output bridge switching arrangement comprises:a first bidirectional switch connected between the first output node and the first intermediate output node; anda second bidirectional switch connected between the first intermediate output node and the second output node.

7. The converter arrangement of claim 6, wherein:the first bidirectional switch comprises a first MOSFET and a second MOSFET connected in a common source or common drain configuration; and / orthe second bidirectional switch comprises a third MOSFET and a fourth MOSFET connected in a common source or common drain configuration.

8. The converter arrangement of claim 7, wherein the second phase determination process comprises monitoring, as the monitored time delay, a time delay between a zero crossing of the current through the inductance arrangement and a switching-of the output bridge switching arrangement.2024PF80520329. The converter arrangement of claim 8, wherein the second phase determination process comprises monitoring, as the monitored time delay, a time delay between a zero crossing of the current through the inductance arrangement and an activation of the first MOSFET or the fourth MOSFET.

10. The converter arrangement of any one of claims 6 to 9, wherein:the inductive arrangement further comprises a second intermediate output node, wherein the intermediate output is provided between the first intermediate output node and the second intermediate output node; andthe output interface comprises:a first output capacitor connected between the first output node and the second intermediate output node; anda second output capacitor connected between the second intermediate output node and the second output node.

11. The converter arrangement of any one of claims 1 to 10, wherein the predefined time delay is between 0.2 to 2 microseconds.

12. The converter arrangement of any one of claims 1 to 11, wherein, in the second determination process, determining the second phase shift using the integrated error comprises:defining a maximum error value and / or a minimum error value; if a maximum error is defined, responsive to the integrated error being above the maximum error value, determining the second phase shift using the maximum error value; andif a minimum time delay is defined, responsive to the integrated error being below the minimum error value, determining the second phase shift using the minimum error value.

13. The converter arrangement of any one of claims 1 to 9, wherein:the inductive arrangement comprises an input node and a return node; the input interface comprises a power input node and a return line, wherein the DC input is defined between the power input node and the return line;2024PF8052033the first leg comprises a first switch connected between the power input node and the input node of the inductive arrangement and a second switch connected between the input node of the inductive arrangement and the return line; andthe second leg comprises a third switch connected between the power input node and the return node of the inductive arrangement and a fourth switch connected between the return node of the inductive arrangement and the return line.

14. The converter arrangement of claim 13, wherein the input interface further comprises an input capacitor connected between the power input node and the return line, optionally wherein the input capacitor functions as an energy storage to process reactive power from the AC mains.

15. The converter arrangement of any one of claims 1 to 14, wherein:the sensing arrangement is configured to monitor a current of the DC input; andthe controller is further configured to:process the voltage of the DC input and the current of the DC input to determine a switching frequency for the full bridge switching arrangement and the output bridge switching arrangement; andcontrol the switching of the full bridge switching arrangement and the output bridge switching arrangement at the switching frequency.

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