Electronic arrangement for integration into a power component

Abstract

The invention relates to an electronic arrangement for integration into a power component. The invention also relates to a method for detecting a short-circuit event in a power component.

Description

[0001] R.415298

[0002] - 1 -

[0003] Description

[0004] title

[0005] Electronic

[0006]

[0007] to

[0008]

[0009] The invention relates to an electronic arrangement for integration into a power component. Furthermore, the invention relates to methods for detecting a short-circuit event in a power component.

[0010] State of the art

[0011] Wide-bandgap power semiconductors, or components, are currently available in sufficient quality to be used in relevant market sectors such as the automotive industry, power distribution networks, and rail transport, to name just a few. Given the harsh operating conditions prevalent in such applications, these power components can be exposed to a wide range of abnormal operating conditions, such as short circuits (SCs). A short circuit occurs when the entire DC link voltage drops across the power component without a load limiting the current. The current is therefore limited only by the internal resistance of the power component. Knowing the resistance time of the power component in such situations is essential for developing a detection and protection circuit that prevents catastrophic system damage.Although short-circuit testing is listed in the JDEC and AEC standards as part of the standard qualification tests for power components, there is no IEEE standard that defines the detection and protection speed in the event of a short-circuit event.

[0012] This time is typically set to less than half the resistance time of the power component. The longer the resistance time, the better it is in terms of reliability aspects, such as robustness against extreme operating conditions. Another important reason for R.415298

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[0014] Short-circuit detection and protection in power components requires creating sufficient design margin. However, this can be achieved at the cost of a higher saturation current and thus reduced short-circuit withstand capability. Fast detection allows the saturation current to be limited from a high, but still safe, value to near zero, preventing device damage. This allows for optimization of the active area, resulting in significant cost savings. Literature reviews on solutions for short-circuit detection and protection show that the most time-consuming component is the short-circuit detection block. Fast short-circuit detection can only be achieved with a high-speed detection block and is a prerequisite for improving the robustness of power components.

[0015] Numerous solutions for detecting, processing, and ultimately safely shutting down a device in the event of a short circuit can be found in the literature. All methods aim to detect and shut down the device within half of its short-circuit withstand time. In most cases, short-circuit detection is performed externally, while signal conditioning, along with the safe shutdown mechanism, is integrated into the driver itself.

[0016] Normally, the drivers provide a standard on / off path and a separate path for safe / soft shutdown in the event of a fault. Most methods are designed for the detection of Type 1 short circuits (also known as hard switch faults); few are effective against both fault types (Type 1 short circuit and Type 2 short circuit (fault under load)). In terms of complexity, the blocks to be designed for the required functionality are limited by a finite number of components: passive elements such as resistors and capacitors, and active elements such as low-voltage MOS-type and silicon-like PN junctions. Therefore, the first constraint in the design space arises from this limited number of elements, and only simple architectures can be integrated. Since short circuits are characterized by fast transients that must be detected, the signal conditioning blocks require a large RS.415298

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[0018] Frequency bandwidth in the range of several tens of MHz. Furthermore, these blocks require integrators or comparators that are robust against process, voltage, and temperature variations (PVT) and exhibit low offset values. Since it is not possible to achieve such large bandwidths in a potentially low-voltage range within the active area of ​​a power device, additional circuitry must be added to handle these offsets and improve PVT robustness.

[0019] Standard short-circuit detection methods can be divided into two main categories: contact-based and non-contact. The latter indirectly monitor the current / voltage behavior of the power component during normal and faulty operation. However, because they rely on expensive external components, such as a Rogowski coil for continuous measurement of the device current, they also have the disadvantage of requiring considerable space. Non-contact solutions use an intrinsic marker of the device, such as drain or gate current, or drain-source voltage, gate charge, or gate voltage, and use this information to differentiate between normal and exceptional operating conditions.

[0020] Some of the solutions offer the possibility of being integrated into the main power supply unit.

[0021] Disclosure of the invention

[0022] The invention relates to an electronic arrangement with the features of claim 1 and a method with the features of claim 8.

[0023] Further features and details of the invention will become apparent from the respective dependent claims, the description, and the drawings. Features and details described in connection with the electronic arrangement according to the invention naturally also apply in connection with the method according to the invention, and vice versa, so that a reciprocal reference is always possible with regard to the disclosure of the invention. R.415298

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[0025] The invention relates in particular to an electronic arrangement, preferably an electronic circuit, for integration into a power component. The power component comprises in particular a first transistor element, in particular a transistor, which is also referred to as a "force" transistor within the scope of the present invention, and a second transistor element, in particular a transistor, which is also referred to as a "sense" transistor within the scope of the present invention, each of which is connected, preferably via a drain terminal, to an input (of the electronic arrangement) and, preferably via a source terminal, to an output of the electronic arrangement, and, preferably via a gate terminal, to a driver, in particular a gate driver, of the power component.The first and second transistor elements are connected in parallel. The second transistor element preferably has a smaller active area than the first transistor element. Furthermore, a current-sensing resistor (shunt) is preferably arranged between the second transistor element and the output of the electronic arrangement, in particular between the source terminal of the second transistor element and the output of the electronic arrangement.

[0026] Furthermore, the electronic arrangement includes, in particular, a gate clamp circuit connected to the driver of the power component and comprising a low-voltage transistor. The low-voltage transistor is preferably connected to the driver of the power component, to the second transistor element, to the current-sensing resistor, and to the output of the electronic arrangement. Preferably, a drain terminal of the low-voltage transistor is connected to the driver of the power component, a gate terminal of the low-voltage transistor is connected to the source terminal of the second transistor element and to the current-sensing resistor, and a source terminal of the low-voltage transistor is connected to the output of the electronic arrangement.

[0027] The electronic arrangement according to the invention advantageously enables short-circuit detection based on a KSENSE-based method, in which a smaller ("Sense") replica of the R.415298

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[0029] The power component is used to measure its current and transfer this information to a low-current circuit responsible for clamping or reducing the power voltage to a safe level to prevent damage to the power component. For this purpose, the second transistor element, which is a smaller replica of the first transistor element, and the gate clamping circuit according to the invention are used. An increase in the drain current of the second transistor element (C, Sense) specifically increases the voltage drop across the current-sensing resistor, thereby activating the gate clamping circuit, which includes the low-voltage transistor.

[0030] Preferably, the low-voltage transistor can be a temperature-controlled and / or a field-effect or a bipolar low-voltage transistor, wherein in the case of a bipolar low-voltage transistor the drain terminal corresponds to a collector terminal, the gate terminal to a base terminal and the source terminal to an emitter terminal.

[0031] It is advantageous for the gate clamping circuit to further comprise at least one resistor and / or at least one diode. The at least one resistor and / or the at least one diode can advantageously block a reverse current that would flow back into the driver at a negative voltage and could damage it. The at least one resistor and / or the at least one diode can be arranged at various locations within the electronic arrangement according to the invention.

[0032] It can be provided that at least one resistor and / or at least one diode is arranged between the driver of the power component and the low-voltage transistor, in particular the drain terminal of the low-voltage transistor.

[0033] Alternatively or additionally, it is conceivable that at least one resistor and / or at least one diode is placed between the low-voltage transistor, R.415298

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[0035] in particular the source terminal of the low-voltage transistor, and the output of the electronic arrangement.

[0036] The invention may provide for a further connection between the driver of the power component and the low-voltage transistor, in particular the gate terminal of the low-voltage transistor. At least one diode and / or at least one resistor may be arranged in this further connection between the driver of the power component and the low-voltage transistor, or the gate terminal of the low-voltage transistor.

[0037] Furthermore, the gate clamping circuit can also include a PMOS transistor, wherein the PMOS transistor is connected to the low-voltage transistor, the second transistor element, the current-sensing resistor, and the output of the electronic arrangement. Preferably, a source terminal of the PMOS transistor is connected to the gate terminal of the low-voltage transistor, a gate terminal of the PMOS transistor is connected to the source terminal of the second transistor element and to the current-sensing resistor, and a drain terminal of the PMOS transistor is connected to the output of the electronic arrangement. The PMOS transistor is, in particular, a reverse-polarity MOSFET transistor.

[0038] The invention also relates to a method for detecting a short-circuit event in a power component, comprising:

[0039] Providing an electronic arrangement according to the invention, wherein the electronic arrangement is integrated into the power component, in particular into an active area of ​​the power component,

[0040] Use the provided electronic arrangement to detect the short-circuit event.

[0041] The method according to the invention thus offers the same advantages as those described in detail with reference to the electronic arrangement according to the invention.

[0042] It may be provided that the procedure further includes: R.415298

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[0044] Initiating voltage limiting in the power component when the short-circuit event is detected.

[0045] Upon detection of the short-circuit event, the gate voltage of the power component's driver can initially be limited to a safe value, preferably below a maximum voltage provided by the gate driver. This limits the drain current of the power component, allowing the short-circuit event to be survived without damage.

[0046] Furthermore, within the scope of the invention, it is conceivable that the method also includes:

[0047] Initiating a shutdown of the power component when the short-circuit event has been detected.

[0048] This effectively protects the power component from damage. The shutdown can be performed, for example, by the driver.

[0049] The invention can also relate to a computer program, in particular a computer program product, comprising instructions that, when executed by a computer, cause it to execute the method according to the invention. Thus, the computer program according to the invention offers the same advantages as those described in detail with reference to a method according to the invention.

[0050] The invention may also include a data processing device configured to execute the method according to the invention. For example, the device may be a computer that executes the computer program according to the invention. The computer may have at least one processor for executing the computer program. Alternatively, a non-volatile data storage device may be provided in which the computer program is stored and from which the computer program can be read by the processor for execution. R.415298

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[0052] The invention may also relate to a computer-readable storage medium which contains the computer program according to the invention and / or includes instructions which, when executed by a computer, cause the computer to execute the method according to the invention. The storage medium is, for example, designed as a data storage device such as a hard drive and / or non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0053] Furthermore, the method according to the invention can also be implemented as a computer-implemented method. Alternatively or additionally, at least one of the disclosed method steps can be computer-implemented and / or carried out automatically.

[0054] Further advantages, features, and details of the invention will become apparent from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description can each be essential to the invention individually or in any combination. The drawings show:

[0055] Fig. 1 shows a schematic visualization of a method and a power component with an integrated electronic arrangement according to exemplary embodiments of the invention.

[0056] Fig. 2 shows a schematic representation of an embodiment of an electronic arrangement according to embodiments of the invention.

[0057] Fig. 3 shows a schematic representation of a further embodiment of an electronic arrangement according to embodiments of the invention.

[0058] Fig. 4 shows a schematic representation of a further embodiment of an electronic arrangement according to embodiments of the invention, R.415298

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[0060] Fig. 5 shows a schematic representation of a further embodiment of an electronic arrangement according to embodiments of the invention.

[0061] Fig. 6 shows a schematic representation of a further embodiment of an electronic arrangement according to embodiments of the invention.

[0062] Fig. 7 shows a schematic representation of a further embodiment of an electronic arrangement according to embodiments of the invention.

[0063] Fig. 8 shows a schematic representation of a further embodiment of an electronic arrangement according to embodiments of the invention.

[0064] Fig. 1 shows a schematic visualization of a method 100 and a power component 1 with an integrated electronic arrangement 2 according to exemplary embodiments of the invention.

[0065] Fig. 1 shows in particular an embodiment of a method 100 for detecting a short-circuit event in a power component 1. In a first step 101, an electronic arrangement 2 according to the invention is provided, wherein the electronic arrangement 2 is integrated into the power component 1, in particular into an active area of ​​the power component 1. In a second step, the provided electronic arrangement 2 is used to detect the short-circuit event.

[0066] One objective of the present invention is, in particular, to provide a framework for solutions that improve short-circuit detection speed, achieving low architectural complexity and short detection time. The proposed solution is characterized, in particular, by short-circuit detection occurring directly downstream of the gate clamping mechanism of the power component 1. The short-circuit detection according to embodiments of the invention is based on R.415298

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[0068] Preferably based on a KSENSE-based method, where a smaller “SENSE” replica of the power component 1 is used to measure its current and transfer this information to a low-current region responsible for clamping or pulling down the power voltage to a safe level to prevent destruction of the power component 1. However, the KSENSE solution can be susceptible to electrical and process-related variations between the power component 1 and its smaller replica.

[0069] According to exemplary embodiments of the invention, a solution space is provided to mitigate the negative effects that such a mismatch could have on the correct functionality of the gate clamping / pulling action during a short-circuit event. Due to their simplicity, requiring fewer passive and active components, the additional circuitry, i.e., the electronic arrangement 2 according to exemplary embodiments of the invention, can be monolithically integrated into the active area of ​​the power device 1, thus paving the way, in particular, for the development of smart power FETs. Therefore, parasitic elements such as inductances and capacitances associated with standard on-PCB solutions can be drastically minimized, which can have a positive impact on operating speed.

[0070] Since the architecture, according to the exemplary embodiments, is based on a 1- or 2-stage architecture, the bandwidth can be increased, which can have a further positive effect on the operating speed and eliminate the risk of potential gate voltage fluctuations. The solutions are preferably purely analog, which offers an advantage in terms of simplicity compared to most modern detection and protection methods: Signal conditioning is primarily performed in the analog domain; however, digital circuits may be required for timing, control, and communication synchronization between the fault detection signal generation blocks and the driver 5.

[0071] Exemplary embodiments of the invention provide robust solutions that can correctly detect a short-circuit event even when an R.415298

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[0073] A discrepancy exists between "Force," i.e., the first transistor element 3, and "Sense," i.e., the second transistor element 4. Furthermore, preferably after the detection of such a short-circuit event, a fast internal loop is activated, which immediately takes measures to limit the gate voltage of the power component 1 and thus its saturation current, before the driver 5 can safely switch off the power component 1. The proposed solutions according to the exemplary embodiments are preferably effective against both types of short-circuit events. Due to their low complexity, requiring only a small number of active and passive components, they can be integrated into the active area of ​​the power component 1.

[0074] The circuit diagram of a first embodiment of the electronic arrangement 2 is shown in Fig. 2. The short-circuit detection is based in particular on a force-sense power component pair, i.e., the first transistor element 3 and the second transistor element 4, while a gate clamping circuit 11 is based on a low-voltage transistor 12 and a diode D, in particular a PN diode, and can be integrated into an active region of the power component 1. A short-circuit event, either of type one or two, is in particular detected, and a gate voltage of the first transistor element 3 is preferably limited to a safe value until the external driver 5, in particular a gate driver, detects that a fault has occurred and switches off the power component 1. During such an undesired state, a drain current of the power component 1 can immediately rise towards a high saturation value.A fraction of the drain current flows, in particular, through the second transistor element 4, which is preferably a smaller copy of the first transistor element 3, i.e., the same process, but a different, or smaller, active area. It is also conceivable that the second transistor element 4 is integrated into the first transistor element 3; for example, the second transistor element 4 could constitute or encompass a portion of the gate fingers of the first transistor element 3. The ratio of their drain currents is, in particular, proportional to the ratio of their active areas, with both transistor elements 3, 4 being, in particular, biased in a common drain configuration. This configuration is, in particular, a classical approach for monitoring the drain current. R.415298.

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[0076] Current through the second transistor element 4 can generate a voltage drop across a current-sensing resistor 6 of the electronic arrangement 2. The current-sensing resistor can be integrated into the active area of ​​the first transistor element 3. If this current is large enough, caused, for example, by a high short-circuit current, and exceeds the threshold voltage of the low-voltage transistor 12, this low-voltage transistor 12 will switch on, particularly either in saturation or in the linear region. In both cases, if the low-voltage transistor 12 is large enough to draw a current greater than that supplied by the driver 5, it will preferably pull down the internal gate voltages of the transistor elements 3 and 4.This action can directly affect the gate currents of transistor elements 3 and 4, which eventually reach lower negative values, thereby maintaining the internal gate voltages at an intermediate value below that set by the driver 5 itself. Depending on the sinking capabilities of the driver 5, a PN junction in series with the low-voltage transistor 12 may be required to block the current caused by a negative driver voltage. Therefore, the additional gate clamping circuit 11 according to the invention does not interfere with the driver 5, for example, during an active clamping operation. In particular, during normal power-on of the power component 1, the drain current does not reach a sufficient magnitude to generate a voltage drop across the current-sense resistor 6 that is greater than the threshold voltage of the low-voltage transistor 12.Therefore, the low-voltage transistor 12, in particular when switched off, and the branch of the gate clamping circuit 11, which includes the low-voltage transistor 12 and the diode D, have no interference during a normal switching operation.

[0077] Regarding the stability of a current detection and amplification loop of the power component 1, the gate clamping circuit 11 is in a current-to-current negative feedback configuration, wherein a Q

[0078] closed loop equals - — with G m and gm,Treg of a

[0079] i+ — gm, STr —eg

[0080] The transconductance of the power component 1 or the low-voltage transistor 12 is when the low-voltage transistor 12 operates in the saturation region. Since, in particular, G m > gm.Treg is, the amplification of the closed loop R.415298

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[0082] below 0 dB, so that the loop is stable and there is no risk of unwanted vibrations.

[0083] The gain of the open-loop control system is defined in particular as the ratio between the controlled (clamped) current iiout and the control current (iin):

[0084]

[0085] In the preceding equation, the transconductance of the sense FET, i.e., in particular of the second transistor element 4, is related to the transconductance of the main power FET, i.e., in particular of the first transistor element 3, which can be changed by the KSENSE ratio:

[0086] gm, Force FET

[0087] gm, Sense FET = — — — - - - - —

[0088] KSENSE — Rshuntxgm, Force FET

[0089] The current amplification in the open control loop thus becomes, in particular:

[0090] gm, Force FET

[0091] A j

[0092] l 'n

[0093] o „

[0094] pe „„

[0095] n = -RshuntxRg

[0096] a atexg

[0097] a m.LDMOS Treg

[0098] a x———— — — - - - — — KSENSE — Rshuntxgm, Force FET

[0099] The minus sign in the open-loop gain in the equation specifically indicates the negative feedback of the closed-loop system. In a design loop using silicon carbide-based technology, the phase span can be greater than 45 degrees, and the open-loop gain may be greater than 50, indicating that the feedback loop is stable and strong enough to counteract large process variations. The estimated bandwidth of the closed-loop system is in the MHz range, meaning the loop is also fast enough to respond to rapid transients that can occur during Type 1 and Type 2 short-circuit events.

[0100] Depending on the initial operating conditions of the power component 1 during a short-circuit event, short-circuit events for large bandgap power components 1 can generally be classified into two types (R.415298).

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[0102] These events are referred to, in particular within the scope of the present invention, as SC1 or Hard Switching Fault (HSF) and SC2 or Fault Under Load (FUL). HSF occurs, for example, when a switch is turned on with a permanent full bus voltage across itself, which is caused, for example, by faulty control signals. An FUL event can occur after the power device 1 is turned on in the resistive region and is characterized by an increase in drain current up to high saturation values. For both fault scenarios, simulation test benches can be defined based on industry-standard power device models and voltage / current transient rise rates. In an SC1 event, the power device 1 is turned on, particularly with a voltage-based driver 5, under a very high drain-source voltage, for example, hundreds of volts.

[0103] While the driver 5 has reached its steady-state value, the internal gate voltage of the power component 1 can be limited to half the driver value due to the action of the auxiliary circuit, i.e., the electronic arrangement 2 according to the invention. This corresponds in particular to the detection of the short-circuit event by the increase in the drain current of the second transistor element 4, which increases the voltage drop across the shunt, i.e., the current-sensing resistor 6, and switches on the branch comprising the low-voltage transistor 12. The pull-down action of the low-voltage transistor 12 allows the internal gate of the power component 1 to be clamped at a constant value, for example, below 18 V.

[0104] An SC2 event is forced, for example, after a normal switch-on of the power component 1. The power component 1 is normally switched on, in particular via a voltage-controlled driver 5, where the driver continuous voltage is, for example, 18 V and the drain-source voltage is low. After a delay, the drain-source voltage can rise to a very high value, corresponding to a power bus, with a very high voltage rise rate of, for example, -50 kV / ps. The internal gate voltage of the power component 1 follows, in particular, the driver voltage. This means that the additional electronic arrangement 2 according to the invention, under normal conditions,

[0105] - 15 -

[0106] The power component 1 is not disturbed during the switch-on process. When the SC2 fault occurs, the voltage driver 5 is in a "high" state, but the internal gate voltage of the power component 1 is limited to approximately half the driver voltage. This corresponds in particular to the detection of the short-circuit event via the increase in the drain current of the second transistor element 4, i.e., the increase in the voltage drop across the current-sensing resistor 6, and thus the switch-on of the branch that includes the low-voltage transistor 12.

[0107] Assuming that, in a standard power component 1, the saturated drain current rises to 20 times the rated current during a short-circuit event without gate voltage limiting, and should be limited to 4 times the rated current when the gate limiting circuit is in operation, the resulting limited current would be, in particular, -600 A. By specifying a limited saturated drain current value IDS,sat_lim, the VGS for which this value is obtained can be calculated from the transconductance curve IDS,sat_lim=f(VGS) at the bus power supply. The results can be obtained, for example, assuming a low-voltage normally off (LVA) transistor 12, as a low-voltage transistor 12 with a large threshold voltage VTH-5V. Therefore, the minimum VGS mismatch between the first transistor element 3 and the second transistor element 4 corresponds, in particular, to the VTH value.Since the gate clamping circuit 11 is designed specifically as an analog negative feedback loop, the low-voltage transistor 12 must preferably be operated in the saturation region, which is why its gate voltage must preferably be above the threshold voltage with a VDS,sat value. Therefore, the VGS mismatch between the first transistor element 3 and the second transistor element 4 increases, in particular. At the moment the low-voltage transistor 12 switches on in the saturation region, the drain current of the first transistor element 3 increases, in particular, to a high value, and the driver 5 charges the gate to a maximum value, provided an SC1 event has occurred. When the low-voltage transistor 12 is switched on, the gate clamping circuit 11 is preferably activated and opposes the driver 5, thereby increasing the gate voltage of the first transistor element.

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[0109] 3 is pulled downwards. Depending on the transconductance of low-voltage transistor 12, the charging current of the gate of the first transistor element 3, and the actual gate value of the first transistor element 3 at the time the low-voltage transistor 12 is switched on, the gate voltage of the first transistor element 3 may not be limited to a sufficiently low value to limit the drain current of the first transistor element 3 to a safe level until the driver 5 safely switches off the power component 1. Different technologies have different current limiting requirements. For example, the saturated drain current during a short-circuit event can rise to ten times the rated current without gate voltage limiting and should preferably be limited to five times the rated current when the gate clamping circuit 11 is in operation.Therefore, a small VGS mismatch between the first transistor element 3 and the second transistor element 4 may be necessary to limit the gate voltage of the power component 1 to a sufficiently safe value, directly affecting the permissible value of the saturated drain current. This prevents the power component 1 from being destroyed before the driver 5 intervenes and safely shuts it down. Consequently, during a short-circuit event, the loop based on the low-voltage transistor 12 acts in opposition to the driver 5: the driver 5 continues to increase the gate voltage before detecting the short-circuit event, but the negative feedback loop intervenes and pulls this node downwards. The strength of this loop depends, for example, on the transconductance value of the low-voltage transistor 12 and its gate-source voltage VGS and threshold voltage VTH.

[0110] Further embodiments of the electronic arrangement according to the invention are described below, which are particularly robust against mismatches between the first transistor element 3 and the second transistor element 4.

[0111] Within the framework of the electronic arrangement 2 according to the embodiment in Fig. 3, whose functionality is similar to that described above, the low-voltage transistor 12 is in particular replaced by a normally R.415298

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[0113] The normally on device is replaced. At a negative threshold voltage, a mismatch of 0 V between the first transistor element and the second transistor element 4 can be achieved. Another difference from the electronic arrangement 2 according to Fig. 2 lies particularly in the connection of the low-voltage transistor 12. Its drain is preferably directly connected to the driver 5 of the power component 1, so that the low-voltage transistor 12 can be switched on directly in saturation. Since the loop is designed specifically as an analog negative feedback loop and not as a switch, this operating condition for the low-voltage transistor 12 may be mandatory. An analytical analysis is provided below as an example to prove that the normally on controller switches directly into saturation, based on the following technological assumptions.

[0114] Vth,Treg = -1 V and Vbody_diode = 2 V, lmax = 1500 A, Rs = 1 ohm. The loop is particularly active for VShunt = 1 V = Rs * lsense = 10 ohm * 1 A. Ksense = Active Area Force / Active Area Sense = 1500. Vshunt = VGS,Treg + 1 * Vbody_diode => VGS,Treg = -1 V >= VTH and opens directly in saturation. This can be verified by considering the voltage drop VDS,Treg and comparing it to VDS,sat. VDS,Treg = VDRIVE - 1 * Vbody_diode >= VGS,Treg - VTH,Treg = -1 V - (-2 V) = 1 V, therefore true, and low-voltage transistor 12 opens directly in saturation. The diode D in series with the low-voltage transistor 12 blocks, in particular, the reverse current flow into the driver 5 when the pull-down voltage of the driver 5 is negative. However, it can also be used to adjust the low-voltage transistor threshold voltage (in this case, the voltage increases, in particular, by the forward voltage drop of the diode D).

[0115] With reference to Fig. 4, a further embodiment of the electronic arrangement 2 according to the invention is described below. A high VDS,sat and threshold voltage from the low-voltage transistor 12 is, in particular, a limiting factor in the matching between the first transistor element 3 and the second transistor element 4. Small overdrive voltages can remain available to prevent the R.415298

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[0117] The low-voltage transistor 12 and the second transistor element 4 are kept switched on and in saturation, even when the driver 5, for which the loop detects a short circuit and begins regulation, is set to a high value (which can lead to a load on the power component 1). Therefore, according to this embodiment, the low-voltage transistor 12 can be configured as a bipolar transistor. This can have the advantage of a lower Vth (for example, -0.7 V). Thus, the electrical mismatch between the first transistor element 3 and the second transistor element 4 can be reduced, for example, to 0.7 V.

[0118] With reference to Fig. 5, another possible embodiment of the electronic arrangement 2 according to the invention is described below. The gate-source mismatch between the first transistor element 3 and the second transistor element 4 is fixed at 0 V, particularly by the choice of architecture, since the two transistor elements 3 and 4 are in a current mirror configuration with VGS,Sense = VGS,Force. As soon as a short-circuit event occurs, a Zener diode Z collapses due to the high voltage drop across the drain-source terminals of the first transistor element 3, and the voltage across its cathode is clamped to a relatively low value compared to VDS,Force, which can reach the value of the bus power supply. Therefore, a high-value resistor R must preferably be connected in series with the Zener diode Z to allow most of the VDS,Force voltage to pass through.As soon as the Zener diode Z breaks down, its cathode voltage is particularly high enough to turn on the low-voltage Tlim transistor 12, allowing the gate current forced by the external driver 5 to flow through it. The second transistor element 4 is also turned on due to a VGS voltage equal to VGS, Force, and large.

[0119] VGS, Force=VGS, Sense is clamped at this moment to a sufficiently safe value that is smaller than the voltage forced by the driver 5 itself. This value depends on the strength of the driver 5, i.e., the current supplied to the gate terminal of the first transistor element 3, and on the strength of the gate clamping circuit 11, which R.415298

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[0121] The low-voltage transistor 12 and the second transistor element 4 are included, which divert the gate current of the first transistor element 3. Therefore, the limiting loop can counteract the driver 5 and divert the current imposed by the driver 5 via the second transistor element 4 away from the gate of the first transistor element 3. Thus, the gate voltage of the first transistor element 3 is brought to a safe value. Due to the current mirror between the first transistor element 3 and the second transistor element 4, the saturated drain current of the first transistor element 3 can be a factor larger than the gate current, specifically by a factor determined by the active area ratios between the first transistor element 3 and the second transistor element 4, which typically have values ​​between, for example, 100 and 1000.

[0122] For an operating mode as described above, the low-voltage transistor 12 and the second transistor 4 must operate in saturation. Therefore, it may be essential to define an optimal DC operating point and to design the low-voltage transistor 12 accordingly with respect to its width and length. The following analysis of the DC operating point demonstrates that the Zener diode Z, which is intended to bias the gate of the low-voltage transistor 12 in the event of a failure during a short-circuit event, is large enough to enable such an operating mode. VZener = VGS, Tlim + VDS, Sense. For the second transistor 4 to be saturated, its VGS voltage should preferably be a threshold voltage above its VDS saturation value. This results, in particular, in a minimum VZener breakdown voltage for correct loop operation and minimal voltage headroom consumption.VZener = VGS, Tlim + VDS, sat, Sense = VGS, Tlim + VGS, Sense - VTH, Sense = VGS, Tlim + VGS, Force - VGS, Sense. The diode D in series with the drain of the low-voltage transistor 12 blocks the reverse current, in particular, in the case that the driver 5 reduces negative currents (with a bipolar +- driver supply). Typically, this diode D can be a standard PN-Si diode with a forward voltage drop of less than 1 V up to a current of 2 A flowing through it, and for this analysis, the voltage drop across this diode is neglected (< <R.415298.

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[0124] VGS, Force). Therefore, the following must hold in particular for the low-voltage transistor 12 to operate in saturation: VGS, Sense = VDS, sat, Tlim + VDS, sat, Sense = VGS, Sense - VTH, Sense + VGS, Tlim - VTH, Tlim Since VZener = VGS, Tlim + VGS, Sense - VTH, Sense

[0125] The low-voltage transistor 12 must preferably be designed such that the following is true, i.e., its saturated drain-source voltage should be equal to the threshold voltage of the second transistor element 4:

[0126] VDS, sat, Tlim = VGS, Tlim - VTH, Tlim = VTH, Sense

[0127] With reference to Fig. 6, a further embodiment of the electronic arrangement 2 according to the invention is described. Here, a PMOS transistor 13 is further used to increase VGS,Treg without increasing VShunt, the voltage drop across the current-sense resistor 6. Therefore, the electrical mismatch between VGS,Sense and VGS,Force due to the voltage drop across the current-sense resistor 6 can be minimized to values ​​close to 0 V. In the original solution according to Fig. 2, the loop is particularly active when VGS,Treg = Vshunt equals VDS,sat above the low-voltage transistor threshold voltage. VGS,Treg original design = VShunt = VDS,sat + VTH,Treg = large. This can lead to a mismatch between the first transistor element 3 and the second transistor element 4. By adding the PMOS transistor 13, the gate potential of the low-voltage transistor 12 can be increased.VGS, Treg = Vshunt + VSG, pMOS = VDRIVE - VLoad and VGS, Sense = VLoad + VSG, pMOS => VLoad = VGS, Sense - VSG, pMOS. VGS, Treg = VDRIVE - VGS, Sense + VSG, pMOS. The loop does not require a high Vshunt value, so the mismatch between the first transistor element 3 and the second transistor element 4 can be improved. The threshold voltages of the PMOS transistor 13 and the low-voltage transistor 12 can be adjusted via a resistor R and the current-sense resistor 6. The threshold voltages of the low-voltage transistor 12 and the PMOS transistor 13 are particularly important for this topology. If the threshold voltage of the PMOS transistor 13 is greater than the threshold voltage of the low-voltage transistor 12, the low-voltage transistor 12 is in particular always switched on, although no R.415298.

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[0129] Current flows. One requirement may therefore be that the threshold voltage of the PMOS transistor 13 is always slightly lower than the threshold voltage of the low-voltage transistor 12. In this case, the regulation can begin with Vth,nmos - Vth,pmos, thereby reducing the voltage applied to the current-sensing resistor 6 and thus decreasing the deviation between the first transistor element 3 and the second transistor element 4. Furthermore, two diodes D1, D2 can be placed before the low-voltage transistor 12 and before the resistor R.

[0130] In another embodiment, shown in Fig. 7, the threshold of the low-voltage transistor 12 is shifted forward, in particular by the voltage drop across diode D1. This could be a solution to keep the threshold voltage of the low-voltage transistor 12 always higher than that of the PMOS transistor 13.

[0131] Another alternative to achieve the same effect of increasing the threshold voltage of the low-voltage transistor 12 is shown in Fig. 8. In this case, one of the source terminals of the low-voltage transistor 12 is modified by adding a small resistor Rs in series with the source terminal, which can cause an additional voltage drop. For the low-voltage transistor 12 to switch on, its gate voltage must be above the threshold voltage at this voltage drop. In a driver 5 with a bipolar power supply, diodes D1 and D2 can be added in series with the low-voltage transistor 12 and the PMOS transistor 13, respectively, to block the reverse current that could flow back into the driver 5.The diode D1 performs two tasks simultaneously: It protects the driver 5 from negative voltages applied to the gate of the power component 1 and increases the threshold voltage of the low-voltage transistor 12.

[0132] The preceding explanation of the embodiments describes the present invention exclusively by way of examples.

[0133] Of course, individual features of the embodiments may be included, provided that R.415298

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[0135] They can be combined freely in a technically meaningful way without leaving the scope of the present invention.

Claims

R.415298 - 23 - Claims 1. Electronic arrangement (2) for integration into a power component (1), comprising: A first transistor element (3) and a second transistor element (4), each connected to an input and an output of the electronic arrangement (2) and to a driver (5) of the power component (1), wherein the first transistor element (3) and the second transistor element (4) are connected in parallel to each other, wherein the second transistor element (4) has a smaller active area than the first transistor element (3), wherein a current-sensing resistor (6) is arranged between the second transistor element (4) and the output of the electronic arrangement (2), a gate clamping circuit (11) connected to the driver (5) of the power device (1) and comprising a low-voltage transistor (12), wherein the low-voltage transistor (12) is connected to the driver (5) of the power device (1), to the second transistor element (4), to the current-sense resistor (6) and to the output of the electronic arrangement (2). R.415298 - 24 - 2. Electronic arrangement (2) according to claim 1 , characterized by that the low-voltage transistor (12) is a temperature-controlled and / or a field-effect or a bipolar low-voltage transistor, wherein in the case of a bipolar low-voltage transistor the drain terminal corresponds to a collector terminal, the gate terminal to a base terminal and the source terminal to an emitter terminal 3. Electronic arrangement (2) according to claim 1 or 2 , characterized by that the gate clamping circuit (11) further comprises at least one resistor and / or at least one diode.

4. Electronic arrangement (2) according to claim 3, characterized by that at least one resistor and / or at least one diode is arranged between the driver (5) of the power component (1) and the low-voltage transistor (12).

5. Electronic arrangement (2) according to claim 3 or 4, characterized by that at least one resistor and / or at least one diode is arranged between the low-voltage transistor (12) and the output of the electronic arrangement (2). R.415298 - 25 - 6. Electronic arrangement (2) according to any one of the preceding claims, characterized by that a further connection is provided which runs between the driver (5) of the power component (1) and the low-voltage transistor (12), wherein the gate clamping circuit (11) further comprises a PMOS transistor (13), wherein the PMOS transistor (13) is connected to the low voltage transistor (12), the second transistor element (4), the current sensing resistor (6) and the output of the electronic arrangement (2).

7. Electronic arrangement (2) according to claim 6, characterized by that in the further connection between the driver (5) of the power component (1) and the low-voltage transistor (12) at least one diode and / or at least one resistor is arranged.

8. Method (100) for detecting a short-circuit event in a power component (1), comprising: Providing (101) an electronic arrangement (2) according to one of the preceding claims, wherein the electronic arrangement (2) is integrated into the power component (1), Use (102) of the provided electronic arrangement (2) to detect the short-circuit event.

9. Method (100) according to claim 8, characterized by that the procedure (100) further includes: Initiating voltage limiting in the power component (1) when the short-circuit event has been detected.

10. Method (100) according to claim 8 or 9, characterized by that the procedure (100) further includes: R.415298 - 26 - Initiating a shutdown of the power component (1) when the short-circuit event has been detected.

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