An inverter

Abstract

An inverter that has two or more phase legs, each for generating a respective phase AC output voltage of the multi-phase voltage and each of the two or more phase legs being coupled between first and second DC inputs and a respective phase AC output. Each of the respective phase legs has an Upper bank of switches coupled between the first input and a respective output, and a Lower bank of switches coupled between the respective output and the second input. The Upper bank of switches has first and second switches connected in parallel; the Lower bank of switches comprising first and second switches connected in parallel. The inverter further has a controller coupled to each of the switches and configured to control the switches using Pulse Width Modulation (PWM) over a plurality of PWM periods to generate the multi-phase AC output voltages. The controller is configured to control one or both of the first and second switches in a respective bank of switches for each phase leg to generate the multi-phase AC output voltage based on one or more operating parameters of the inverter.

Description

[0001] An Inverter

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to an enhanced inverter design for driving an electric machine, in particular an inverter that advantageously reduces the probability of a common mode fault that would cause more than one inverter to fail at a time.

[0004] BACKGROUND OF THE INVENTION

[0005] In recent years, advances in technology have led to substantial changes in the design and configuration of air transport vehicles. Many electrical components used in electric and hybrid vehicles, receive electrical power from direct current (DC) power supplies (e.g., batteries). Devices known as power inverters are used to convert the DC power to a multiphase AC power format required by the AC electric motors used in the vehicle propulsion systems.

[0006] Power inverters use multiple switches that are controlled through gate drivers. Individual switches can be made up of several power semiconductor devices to achieve a required power rating. In standard applications, all such parallel power semiconductor devices that make up one switch are switched simultaneously.

[0007] A standard topology for a power inverter is the 2-level type which has two switches per AC phase output which is often referred to as a phase leg. These switches are arranged with one switch, called the upper switch, connecting between the positive DC supply and the AC phase output, and the second switch, called the lower switch, connecting between the negative DC supply and the AC phase output. This format is usually referred to as a half-bridge topology.

[0008] When one switch is conducting, the other is isolating. Either the upper switch is conducting or the lower switch, but never both at the same time. If both switches were to switch to conducting at the same time this would result in a shoot-through of current from the positive to negative of the DC supply, effectively a short-circuit.

[0009] 15286718-1A DC supply is converted into an AC voltage through the action of quickly changing between the upper switch conducting and the lower switch conducting. The ratio between the time that the upper switch conducts versus the time that the lower switch is conducting sets the voltage at the AC phase output. The inductance of the motor, filters the pulses to provide a smooth current waveform. This method is called Pulse Width Modulation, PWM.

[0010] The transition between switch isolation to conduction (and vice versa) is kept quick because during this transition the power devices are in a high loss mode (called the linear mode). I2R and other losses occur in this region which causes switches to heat up. The circuit will also have transient (switching) loop inductance and this in turn may cause a transient overvoltage where the DC voltage locally increases to a peak and then returns to the average of the DC supply. This transient overvoltage can stress the power devices and may decrease their life expectancy.

[0011] High voltage batteries or battery packs are typically used to provide electric power storage for electric traction systems in most electric and hybrid electric vehicles. Such a high voltage battery may have a nominal voltage of 100 volts or more.

[0012] A system that includes a power inverter and an associated motor are often referred to as a propulsion electric drive or an electric propulsion unit (EPU). For many electric aircraft propulsion systems, failure of multiple propulsion electric drives (where electric drive is the combination of an inverter and electric motor or EPU) can lead to loss of the aircraft. To mitigate this, such propulsion systems have multiple electric drives with sufficient redundancy that the loss of at least one electric drive would not cause a safety issue.

[0013] Using multiple propulsion electric drives increase the robustness of the overall system as it provides multiple redundant elements. However, each of these multiple propulsion electric drives may be of the same design and use the same type of components. This may in turn lead to common-mode failures, by which a common attribute, for example design or choice of component, may simultaneously lead to the failure of all or several of the multiple redundant elements.

[0014] 15286718-1There is a small risk of a common mode error in the power electronic circuit of each power inverter, either due to incorrect design, common mode build error, or operating outside the specified envelope, that could lead to a common mode failure with more than one power inverter failing in a single mission.

[0015] A commonly used approach to overcoming such common mode failure is taught by US2015 / 0291279 which addresses the problem of common mode failure in motor controllers for electro-mechanical brake actuators for aircraft. An electromechanical actuator controller includes a first motor controller for generating a first drive signal for the EMAbrake and a second motor controller for generating a second drive signal for the EMAbrake wherein the first motor controller and the second motor controller are dissimilar so as to provide protection against common mode failure of the first and second motor controllers.

[0016] A similar approach is taught by US20240126259 and is more broadly applied to reducing common mode failures by using dissimilar components found in flight control systems for aircraft which may include sensors, effectors command processors and monitor processors.

[0017] Whereas mitigation approaches to common mode failure as described above, is generally useful, of particular concern are common mode environmental factors, where the supply voltage, temperature or load current command seen by multiple inverters is outside the designed and tested range. Such ‘corner cases’ could lead to many inverters and so propulsion electric drives, which have successfully operated for significant lifetimes of use under ‘normal’ operating conditions, failing within a single flight mission as a result of for example over-heating of multiple parallel gate switches of the same type.

[0018] CN 104283199 teaches a plurality of independent control circuits for controlling a plurality of MOSFETs. This control approach allows multiple MOSFETs to operate simultaneously in parallel or in stages with a time delay between each stage. This allows the heating pressure on the MOSFETs to be spread over multiple MOSFETs simultaneously or separated in time.

[0019] 15286718-1CN110034685 teaches an alternative approach to reducing stress on gate switches, by using different switch technologies in parallel each having different optimised switch characteristics. In the case taught by CN110034685, fast low noise switching is effected by SiC- MOSFETs whilst large current passes through parallel Si-IGBTs.

[0020] Whilst these different approaches to reducing common mode failure in Inverter gate control switch components are useful, they do not address lifetime ‘corner case’ common mode failure of such components particularly in mission and life critical operational environments and we have seen there is value in proposing alternative solutions.

[0021] We have therefore appreciated the need for an improved inverter and method of controlling the switches in an inverter.

[0022] SUMMARY OF THE INVENTION

[0023] The present invention is defined by the independent claims appended hereto. Further advantageous embodiments are also defined by the dependent claims, also appended hereto.

[0024] The present invention provides a multi-phase inverter for supplying a multi-phase AC voltage and current to an electric machine, the inverter comprising: first and second inputs for receiving respectively first and second DC input voltages; two or more outputs, each output for outputting a respective phase AC output voltage of the multi-phase AC output voltage; and two or more phase legs, each for generating a respective phase AC output voltage of the multi-phase voltage and each of the two or more phase legs being coupled between the first and second inputs and a respective output of the two or more outputs, each of the respective phase legs comprising: an Upper bank of switches coupled between the first input and a respective output, the Upper bank of switches comprising first and second switches connected in parallel; and a Lower bank of switches coupled between the respective output and the second input, the Lower bank of switches comprising first and second switches connected in parallel; and a controller coupled to each of the switches and configured to control the switches using Pulse Width Modulation (PWM) over a plurality of PWM periods to generate the multi-phase AC output voltages, wherein the controller is configured, for each PWM period, to: control

[0025] 15286718-1one or both of the first and second switches in a respective bank of switches for each phase leg to generate the multi-phase AC output voltage based on one or more operating parameters of the inverter.

[0026] The one or more operating parameters may comprise one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of the respective first and second switches, or a lifetime threshold for each of the respective first and second switches.

[0027] As such, the present invention provides an inverter that, on a PWM period-by PWM period basis, can control one or both of each of the first and second switches in a respective Upper and Lower switch bank depending on the required operating parameters of the inverter. Over the lifetime of the switches, therefore, and based on the desired operating parameters of the inverter, the switches can be controlled in as such a way that the risk of common mode failures can be reduced without the need for significant additional components in the system.

[0028] The controller may be configured to control the switches in a first mode in which the controller only switches the respective first or second switches in each of the banks of switches for a respective phase leg to generate the multi-phase AC output voltage.

[0029] In the first mode, the controller may be configured to only switch the respective first switches in each of the banks of switches for a respective phase leg to generate the multi-phase AC output voltage. Alternatively, in the first mode, the controller may be configured to only switch the respective second switches in each of the banks of switches for a respective phase leg to generate the multi-phase AC output voltage. Alternatively, in the first mode, the controller may be configured to only switch the first switch in the Upper bank and the second switch in the Lower bank for a respective phase leg to generate the multi-phase AC output voltage. Alternatively, in the first mode, the controller is configured to only switch the second switch in the Upper bank and the first switch in the Lower bank for a respective phase leg to generate the multi-phase AC output voltage.

[0030] 15286718-1In any of the above first modes, the one or more operating parameters may comprise a power output demand of the inverter and wherein the controller is configured to control the switches in the first mode when the power output demand for the inverter is below a threshold power demand.

[0031] In an alternative to the first mode, the controller may be configured to control the switches in a second mode in which the controller switches both respective first and second switches in a respective banks of switches for a respective phase leg to generate the multi-phase AC output voltage.

[0032] In the second mode, the controller may be configured to switch each of the first and second switches in a respective switch bank substantially at the same time.

[0033] Alternatively, in the second move, the controller may be configured to switch each of the first and second switches in a respective switch bank at different times.

[0034] When the controller is configured to switch each of the first and second switches in a respective switch bank at different times, the controller may be configured to apply a turn on delay between the first and second switch being turned on such that only one of the first or second switches is on during the turn on delay, and after the turn on delay both of the first and second switches are on.

[0035] When the controller is configured to switch each of the first and second switches in a respective switch bank at different times, the controller may be configured to apply a turn off delay between the first and second switch being turned off such that only one of the first or second switches is off during the turn off delay, and after the turn off delay both of the first and second switches are off.

[0036] In the second mode, the one or more operating parameters may comprise a power output demand of the inverter and wherein the controller may be configured to control the switches in the second mode when the output power demand for the inverter is above a threshold power demand.

[0037] We also describe an Electrical Propulsion Unit (EPU) comprising: an electrical machine; and a multi-phase inverter according to the above, wherein the multi-phase inverter is

[0038] 15286718-1electrically connected to the electrical machine and configured to drive the electrical machine using the multi-phase AC output voltages.

[0039] In the EPU the electrical machine may be an axial flux electrical machine. The electrical machine may be a motor or generator.

[0040] We also describe a method of generating a multi-phase AC voltage and current to an electric machine using an inverter, the inverter comprising: two or more phase legs, each for generating a respective phase AC output voltage of the multi-phase voltage and each of the two or more phase legs being coupled between first and second DC inputs and a respective phase AC output, each of the respective phase legs comprising: an Upper bank of switches coupled between the first input and a respective output, the Upper bank of switches comprising first and second switches connected in parallel; and a Lower bank of switches coupled between the respective output and the second input, the Lower bank of switches comprising first and second switches connected in parallel, the method comprising: controlling the switches using Pulse Width Modulation (PWM) over a plurality of PWM periods to generate the multi-phase AC output voltages; and for each PWM period, controlling one or both of the first and second switches in a respective bank of switches for each phase leg to generate the multi-phase AC output voltage based on one or more operating parameters of the inverter.

[0041] The one or more operating parameters may comprise one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of the respective first and second switches, or a lifetime threshold for each of the respective first and second switches.

[0042] As such, the present invention provides method that, on a PWM period-by PWM period basis, controls one or both of each of the first and second switches in a respective Upper and Lower switch bank in an inverter depending on the required operating parameters of the inverter. Over the lifetime of the switches, therefore, and based on the desired operating parameters of the inverter, the switches can be controlled in as such a way that the risk of common mode failures can be reduced without the need for significant additional components in the system.

[0043] 15286718-1The switches may be controlled in a first mode in which only the respective first or second switches in each of the banks of switches for a respective phase leg are switched to generate the multi-phase AC output voltage.

[0044] In the first mode, the only the respective first switches in each of the banks of switches for a respective phase leg may be switched to generate the multi-phase AC output voltage. Alternatively, the only the respective second switches in each of the banks of switches for a respective phase leg may be switched to generate the multi-phase AC output voltage. Alternatively, only the first switch in the Upper bank and the second switch in the Lower bank for a respective phase leg may be switched to generate the multi-phase AC output voltage. Alternatively, only the second switch in the Upper bank and the first switch in the Lower bank for a respective phase leg may be switched to generate the multi-phase AC output voltage.

[0045] In the first mode, the one or more operating parameters may comprise a power output demand of the inverter and wherein the method may comprise switching the switches in the first mode when the power output demand for the inverter is below a threshold power demand.

[0046] In an alternative to the first mode, the switches may be controlled in a second mode in which both respective first and second switches in a respective banks of switches for a respective phase leg are switched to generate the multi-phase AC output voltage.

[0047] In the second mode, each of the first and second switches in a respective switch bank may be switched substantially at the same time.

[0048] Alternatively, in the second mode, each of the first and second switches in a respective switch bank may be switched at different times.

[0049] In the second mode, a turn on delay may be applied between the first and second switch being turned on such that only one of the first or second switches is on during the turn on delay, and after the turn on delay both of the first and second switches are on.

[0050] 15286718-1In the second mode, a turn off delay may be applied between the first and second switch being turned off such that only one of the first or second switches is off during the turn off delay, and after the turn off delay both of the first and second switches are off.

[0051] In the second mode, the one or more operating parameters may comprise a power output demand of the inverter and wherein the method may comprise controlling the switches in the second mode when the output power demand for the inverter is above a threshold power demand.

[0052] In any of the above methods, the one or more operating parameters may comprise one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of the respective first and second switches, or a lifetime threshold for each of the respective first and second switches.

[0053] LIST OF FIGURES

[0054] The present invention will now be described by way of example only and with reference to the accompanying figures, in which:

[0055] Figure 1 shows a schematic diagram of a half bridge showing of banks of upper and lower switches;

[0056] Figure 2 shows a schematic diagram of a half bridge being controlled in a first mode in which the upper and lower A banks are switched and holding the upper and lower B banks in the off state;

[0057] Figure 3 shows a schematic diagram of a half bridge being controlled in a first mode in which the upper and lower B banks are switched and holding the upper and lower A banks in the off state;

[0058] 15286718-1Figure 4 shows a schematic diagram of a half bridge being controlled in a first mode in which the upper A bank and the lower B bank is switched and holding the lower A bank and upper B bank in the off state; and

[0059] Figure 5 shows a schematic diagram of a half bridge being controlled in a second mode in which the upper and lower A and B banks are switched;

[0060] Figure 6 shows a schematic timing diagram showing switch interlock delays on primary and secondary switch blocks used in the second mode of switching; and

[0061] Figure 7 shows a simplified example of an Electric Propulsion Unit.

[0062] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0063] In brief the present invention provides an inverter that has two or more phase legs, each for generating a respective phase AC output voltage of the multi-phase voltage and each of the two or more phase legs being coupled between first and second DC inputs and a respective phase AC output. Each of the respective phase legs has an Upper bank of switches coupled between the first input and a respective output, and a Lower bank of switches coupled between the respective output and the second input. The Upper bank of switches has first and second switches connected in parallel; the Lower bank of switches comprising first and second switches connected in parallel. The inverter further has a controller coupled to each of the switches and configured to control the switches using Pulse Width Modulation (PWM) over a plurality of PWM periods to generate the multi-phase AC output voltages. The controller is configured to control one or both of the first and second switches in a respective bank of switches for each phase leg to generate the multi-phase AC output voltage based on one or more operating parameters of the inverter.

[0064] The one or more operating parameters may comprise one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of

[0065] 15286718-1the respective first and second switches, or a lifetime threshold for each of the respective first and second switches.

[0066] As such, the present invention provides an inverter that, on a PWM period-by PWM period basis, can control one or both of each of the first and second switches in a respective Upper and Lower switch bank depending on the required operating parameters of the inverter. Over the lifetime of the switches, therefore, and based on the desired operating parameters of the inverter, the switches can be controlled in as such a way that the risk of common mode failures can be reduced without the need for significant additional components in the system.

[0067] With reference to Figure 1 which shows a basic phase of a 2-level inverter powered from a de link (positive 105 and negative 106) with a capacitor (107) to smooth the de voltage.

[0068] The inverter is of the half-bridge configuration where the upper and lower switches i.e., those attached to the positive DC link (105) and those connected to the negative DC link (106) respectively, are each divided into two banks. The upper consists of an “A” or first bank (101) and a “B” or second bank (103). Likewise, the lower consists of an “A” or first bank (102) and a “B” or second bank (104). The upper switches 101, 103 and lower switches 102, 104 are connected to an output “phase” connection (108). The action of switching the upper and lower switches between the conducting and isolating state (often via a Pulse Width Modulation, PWM, control) provides the demanded voltage at the phase connection (108). Whilst not shown, in practice the switches are controlled by a controller that is coupled to each of the switches. The controller may be a micro-controller or micro-processor or the like.

[0069] Those skilled in the art will appreciate that the simple switch and diode symbol shown in Figure 1 and subsequently could be any form of switch device e.g., SiC- MOSFET, Si-IGBT and similar, and may also denote many devices in parallel with a common control command.

[0070] In the simplest normal operation, for example where the power demand is low, the controller may control the switches in a first mode in which only one bank of switches may be used for the duration of the mission (or on a PWM period by PWM period basis). That is, either the bank “A” or first switches are operated, or the bank “B” or second

[0071] 15286718-1switches are operated. In other scenarios, first example when the power demand on the inverter is higher, the controller may control the switches in a second mode in which both bank “A” and bank “B” switches are operated together. In the present invention, the selection of which bank is the primary bank could be changed every mission, such that the lifetime stress on the devices is shared across the power switches. Furthermore, decisions of which bank of switches that should be used can be made on a PWM period by PWM period basis.

[0072] The secondary, or non-operated, banks for a mission, or PWM period, will see a much lower thermal and electrical stress through that mission, so that the probability of the secondary bank failing during that mission is lower than the primary bank.

[0073] With reference to Figure 2 which shows the inverter being controlled in a first mode in which the first, or bank “A” switches are operated and the bank “B” or second switches are held open. The invention is based on a 2-level inverter powered from a de link (positive 105 and negative 106) with capacitor (107) to smooth the de voltage, in this instance as described above, only one bank 101, 102 is switching, and the other bank 103, 104 is held in the non-conducting (isolating) state. The inverter is of the half-bridge configuration where the upper and lower switches, that is those attached to the positive DC link (105) and those connected to the negative DC link (106) respectively, are each divided into two banks. The upper consists of an “A” bank (101) and a “B” bank (103). Likewise, the lower consists of an “A” bank (102) and a “B” bank (104). The upper switches 101, 103 and lower switches 102, 104 are connected to an output “phase” connection (108). Only bank “A”, i.e., switches 101 and 102 are switched between the conducting and isolating state via PWM and bank “B” switches (103 and 104) are held in the isolating state.

[0074] The switching configuration shown in Figure 2 may be used during ‘normal operating conditions’ which may be set at e.g., less than half peak load, and thus permit the B banks to remain cooler than the A banks. This decision may be based on the mission as a whole or on a PWM period by PWM period basis. The B banks thus see a different mission profile to that seen by the A banks. This changes the probability of failure due to common life experiences. We define peak loading in these examples as the peak that can be provided if all banks are utilised.

[0075] 15286718-1The alternate situation to that described for Figure 2 is shown with reference to Figure 3. The inverter is controlled in a first mode in which the second, or bank “B” switches are operated and the bank “A” or first switches are held open. In more detail, figure 3 shows a 2-level inverter powered from a de link, comprising a positive 105 and negative 106 DC source, and with a capacitor (107) to smooth the de voltage when only one bank 103, 104 is switching, and the other 101, 102 is held in the non-conducting (isolating) state.

[0076] As before the inverter is of the half-bridge configuration where the upper and lower switches i.e., those attached to the positive DC link (105) and those connected to the negative DC link (106) respectively, are each divided into two banks. The upper consists of an “A” bank (101) and a “B” bank (103). Likewise, the lower consists of an “A” bank (102) and a “B” bank (104).

[0077] The upper and lower switches are connected to an output “phase” connection (108). Only bank “B”, bank switches 103 and 104 are switched between the conducting and isolating state via PWM and the bank “A” switches (101 and 102) are held in the isolating state.

[0078] Alternatively, the B bank could take over from the A bank during less than half peak load to share the lifetime reduction due to use, but they will see a different mission profile. For example, the A bank could be used for take-off and the B bank for landing, while they could alternate during cruising. As discussed above, the decisions may be made on a PWM period by PWM period basis.

[0079] With reference to Figure 4 which shows the inverter being controlled in a first mode in which the bank “A” switches in one bank is being controlled with the bank “B” switches in the other bank. Figure 4 shows a basic phase of a 2-level inverter powered from a de link comprising a positive 105 and negative 106 DC supply terminal with a capacitor (107) to smooth the de voltage when upper bank “A” and lower bank “B” are switching. In this instance lower bank “A” and upper bank “B” are held in the non-conducting state.

[0080] The inverter, as before, is of the half-bridge configuration where the upper and lower switches, that is those attached to the positive DC link (105) and those connected to the negative DC link (106) respectively, are each divided into two banks. The upper consists

[0081] 15286718-1of an “A” bank (101) and a “B” bank (103). Likewise, the lower consists of an “A” bank (102) and a “B” bank (104).

[0082] The upper and lower switches are connected to an output “phase” connection (108). Bank “A”, bank upper switch 101 and bank “B” lower switch 104 are switched between the conducting and isolating state via PWM while bank “A”, bank lower switch 102 and bank “B” upper switch 103 are held in the non-conducting state.

[0083] The switch configuration shown schematically in Figure 4 is an alternative to switching only A banks or only B banks when, for example, the load is below half the peak loading. The diagram shows A upper and B lower banks, although, the converse i.e. , A lower and B upper could also be used in this “diagonal” switching configuration. This diagonal switching configuration is an alternate way of sharing mission profile sections within i.e. inter A and B banks and not just between i.e., intra A and B banks. As discussed above, the decisions may be made on a PWM period by PWM period basis

[0084] Following usual component layout for maximum electrical efficiency, any potential switching efficiency penalty due to increased transient (switching) loop inductance because of diagonal configuration switching, is minimised if the switching banks are located close to each other.

[0085] Figure 5 shows the inverter being controller in a second mode in which bank “A” and bank “B” switches are both controlled. Figure 5 again shows a basic phase of a 2-level inverter powered from a de link comprising a positive 105 and negative 106 DC supply with a capacitor (107) to smooth the de voltage. In this instance, which as alluded to previously, may be a rare event, both banks ‘A’ and ‘B’ are switching.

[0086] With reference to Figure 5 which shows a condition where, for example, power demand is above a threshold which in this instance is set at half the peak rating, the gate control logic sets a requirement for both sets of switch banks to be activated. This configuration could also be used at lower than half the peak rating, however, this would mean that both sets of banks would experience the same mission profile and thereby introduce common life experiences and hence common failure times. The switches in a respective upper or lower bank may be switched substantially at the same time, or at a different time.

[0087] 15286718-1The technique of switching the switches at a different time may be used to further aid reliability and de-stress switch devices there is advantage in pre-warming switches which under normal operating conditions for a mission profile are held in the off state. Cold switching large voltages and currents unduly stresses devices and packaging and can lead to rapid failures. Such normal operating conditions would be those exemplified by switch configurations shown in Figures 2, 3 and 4. An abnormal high stress, i.e., high power demand state would be that exemplified by the switch configuration shown in Figure 5. Switching from switch configurations shown in Figures 2, 3 and 4 to that shown in Figure 5 would bring switches which had been in the non-conducting state, immediately online, and potentially at high-power demand.

[0088] In the instance shown in Figure 5, when switching in ‘cold’ switches, either bank A or bank B or diagonal AB switches as shown in Figure 4, i.e., the secondary (cold) bank power switches may be switched on slightly later than the primary switches and turned off slightly earlier than the primary switches. That is, the controller may implement a turn-on delay between the first and second switch being turned on in which only one of the first or second switches is on during the turn on delay, and after the turn on delay both of the first and second switches are on. The controller may also implement a turnoff delay between the first and second switch being turned off in which only one of the first or second switches is off during the turn off delay, and after the turn off delay both of the first and second switches are off.

[0089] With this time delayed configuration of switching, the secondary bank power switches are not cold when they are required to switch and avoid the temperature differential between their diodes which are always active.

[0090] This warm start approach has advantages. Firstly, it means that the secondary bank does not experience any switching losses as it does not try to switch voltage and current at the same time. This means the junction temperature of the secondary switches will be lower than the primary switches, and so less likely to be subject to damage. Advantageously primary and secondary banks under this switching regime, do not share life experiences, which assists in avoiding common mode device failure.

[0091] Secondly, the secondary bank is less likely to see damage caused by shoot-through, where the top and bottom switches try to switch at the same time. Shoot-through

[0092] 15286718-1damage could occur in a situation where, due to certain abnormal conditions, the there is a period of time where both upper and lower switches are switching. This damage, if it were to occur, is much less likely to occur in the secondary bank than the primary bank because there is a longer interlock delay between upper and lower switches switching in the secondary switches than the primary switches.

[0093] With reference to Figure 6 and Figure 1, Figure 6 is a schematic timing diagram of this delayed start embodiment of the invention based on switching control signals for “A” bank and “B” bank switches.

[0094] Plot 601 shows the switching control of bank “A” upper switch (101 in Figure 1). Plot 602 shows the switching control of the bank “B” upper switch (103 in Figure 1). Plot 603 shows the switching control of the bank “A” lower switch (102 in Figure 1). Plot 604 shows the switching control of the bank “B” lower switch (104 in Figure 1).

[0095] The “Primary interlock delay” (606) is a ‘deadtime’ switch timing delay placed between a change in conduction state of the upper and lower switches. Switches take time to change state and often there is also a delay in the interfacing (gate driver) circuitry. The “Primary interlock delay” (606) deadtime is set to a period that guarantees the conducting switch has transitioned to the non-conducting state before the next switch begins to change state. If an upper switch and a lower switch is on at the same time it would lead to a short circuit across the DC link (105 and 106 in Figure 1) and across the DC link capacitor (107 in Figure 1), potentially causing permanent component failures. Switch delays proposed in the present invention do not interfere with good ‘sinusoidal’ delivery of power to motor loads, but does enable non-switching banks to be pre-warmed and securely ensures freedom from risk of catastrophic switch induced power link shorts.

[0096] The “Secondary interlock delay”, or turn on delay, (607) is a delay between the “A” bank lower changing state and the “B” bank lower changing state. This is to allow the “A” bank lower to absorb the switching energy before the “B” bank lower joins to share the conduction losses. In this way the “B” bank sees different losses to the “A” bank. Similarly, the turn-off delay (608) is provided such that bank “B” does not experience the same switching losses as bank “A”.

[0097] 15286718-1Figure 6 shows similar delays between other switch transitions. As discussed earlier, although secondary switches might be configured with respect to power switching only to be used in emergency conditions, they could also be used in peak load conditions during normal operation when power demand is greater than the capability of the primary power switches alone. For instance, when the peak load requirement exceeds 50% for a reasonably small portion e.g., <20% of the total mission, so that the secondary switches are kept at a much lower thermal and electrical stress than the primary switches. Applying Interlock delays on the secondary switches further helps to maintain a significant difference in the stress seen by the primary and secondary switches. Advantageously applying both switching configurations i.e., switching switch blocks between primary and secondary and applying interlock delays e.g., on secondary switch blocks, acts to effectively separate lifetime experiences of common device types, based on operational time, and so mitigates against common mode lifetime stress failures

[0098] Interlock delays and use of primary switches for power switching for <50% power demands, also means secondary switches would not be active during transient overvolt instances which occur when primary switches transition from ‘on’ to ‘off’ and vice-versa. This too reduces stress on secondary switches and further differentiates same device topologies by way of their lifetime experiences of stress.

[0099] With switch configurations taught in the present invention in which 100% power may be provided by combined primary and secondary switches and either bank can supply nominal power of <50% for e.g., cruising, the primary and secondary switches may be sized to carry as little as 50% of the peak power capability, so that the total installed inverter power capability is the same or only a little higher than would be the case for a more conventional inverter design with only one set of switches.

[0100] For double stator motors it is possible that each switch bank, bank A and bank B can be connected to different stator windings. Seldom are stators clones and there are often differences in reactive I passive load impedances. This leads to different stresses on inverter supplies choosing how inverter switches allocate their lifetime operation can also mitigate against common-mode failure. Furthermore, it is envisaged that each switch bank A / B may be applied within a single three phase stator to different windings. Though this introduces complexity, this may be sufficiently advantageous to mitigate against common mode failure.

[0101] 15286718-1As will be appreciated by those with ordinary skill in the art, there are many different switch modes that advantageously separate, by virtue of lifetime experience, switches in power inverters used to power electric propulsion units. All modes of switching leading to this outcome are included in the present invention. Table 1 provides a few examples of switching modes that satisfy this criterion.

[0102] TABLE 1

[0103]

[0104] As will also be appreciated by those with ordinary skill in the art, there are many possible criteria that can be used to control the selection of switch modes. For example, the one or more operating parameters discussed above may comprise one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of the respective first and second switches, or a lifetime threshold for each of the respective first and second switches. The parameter may also include using accumulated stress*time. For instance, ‘stress’ could be defined as the current being switched and ‘time’, the duration of the switch transition. However, ‘stress’ may also be defined in different terms including:

[0105] • the current being switched multiplied by a weighting

[0106] • the current being conducted (when the switch is fully conducting) multiplied by a different weighting

[0107] 15286718-1These parameters may be captured and / or monitored by sensors or timers in the system. The controller may also provide such monitoring and data recording. These parameters may be stored in memory for later use by the controller in its decision of which of modes 1 (where only the first or second switch being operative in a respective bank of switches) or modes 2 (where both the first and second switches are operated in a respective switch bank, either substantially at the same time or at different times) to operate in.

[0108] Semiconductor device lifetime predictions often include manufacturer’s statistical analysis based on testing and long-term use data. In the light of the present invention which predictably ‘chooses’ and differentiates lifetime use for specific at-risk components, such statistically valid predictive data based on e.g. stress*time index (and alternatives) may now be usefully used to predict differences in probable mortality of devices between two banks.

[0109] For applications such as vertical take-off and landing aircraft (VTOLs), the remaining life required from a second switch bank, if the first bank has failed, may only be 2 minutes (i.e. , the time required to land safely). In this case, the mode selection may evaluate the stress*time index for each separately controllable bank and make a choice that keeps the corresponding lifetime difference greater than, for example, 20 minutes (depending on the resolution of the models with a tolerance allowance), and less than 1hour.

[0110] It is proposed that a 1-hour maximum lifetime difference is used between two switch banks, so that the share of lifetime between the two banks is not so great as would result in one bank being the limiting factor for the whole vehicle.

[0111] The invention has been described with example embodiments, and we will reiterate some advantages to be gained:

[0112] • A secondary bank will experience statistically valid lower environmental stress during various missions.

[0113] • Junction temperatures of secondary power switches will be lower than their primary counterparts.

[0114] • If there are unusually high voltage transients on the DC supply during a mission, the secondary switches during that mission will not be switching and so are less likely to be damaged.

[0115] 15286718-1The invention does not change the probability of a common mode lifetime failure occurring in the primary switches, but it does significantly reduce the probability of a common mode failure of secondary switches. The secondary switches even though an integral and used part of what may be the prime and only propulsion power inverter device nevertheless, act as an additional fail-safe mechanism available in reserve.

[0116] Some prior art solutions have a secondary set of power switches ready on standby in the event of failure of the primary switches is advantageous. Some teach the use of dual redundant inverter controllers, which is an extreme though often utilised example. However, even the less extreme approach would normally require the inverter to carry twice the area of power switch dies, with a total installed inverter capability of twice the nominal load. This has disadvantages in terms of cost, size and weight which is obviated by the mode of switch use proposed by the present invention.

[0117] The present invention does not require a doubling of the inverter capacity. Instead, the total area of the power switch dies can be the same as if a conventional single switch inverter was used. Alternatively, it can be a little higher if required, but much lower than two-times the capacity.

[0118] It is proposed that the goal of an inverter design in the light of the present invention is to keep at least 50% power capability across all inverters in the system in a condition where there is a common-mode failure of the power electronics due to environmental stress, design or build errors. This is achieved by maintaining a high differential on thermal and electrical stresses between the primary and secondary switches. This differential is further maintained by enhancement of delays of switching of the secondary switches in situations where both primary and secondary switches are required to operate.

[0119] The inverter arrangement as described above may be used in Electrical Propulsion Units (EPU), for example in automotive or aerospace applications. In such an EPU, the multiphase inverter is couple to an electrical machine such as an electric motor, where the inverter is configured to drive the electrical machine using the multi-phase AC output voltages. The electrical machine may for example be an axial flux electrical machine, although it may be other types of electric machines such as radial flux machines.

[0120] 15286718-1M&C PC933975W0

[0121] 21

[0122] A simple example arrangement of an EPU is shown in Figure 7 with an inverter (100) coupled to controller (200), where the controller is configured to control the switches of the inverter as described above, and the multi-phase AC output of the inverter (100) is coupled to an electric machine (300) for driving the electric machine.

[0123] No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the scope of the claims appended hereto.

[0124] 15286718-1

Claims

22CLAIMS:

1. A multi-phase inverter for supplying a multi-phase AC voltage and current to an electric machine, the inverter comprising:first and second inputs for receiving respectively first and second DC input voltages;two or more outputs, each output for outputting a respective phase AC output voltage of the multi-phase AC output voltage; andtwo or more phase legs, each for generating a respective phase AC output voltage of the multi-phase voltage and each of the two or more phase legs being coupled between the first and second inputs and a respective output of the two or more outputs, each of the respective phase legs comprising:an Upper bank of switches coupled between the first input and a respective output, the Upper bank of switches comprising first and second switches connected in parallel; anda Lower bank of switches coupled between the respective output and the second input, the Lower bank of switches comprising first and second switches connected in parallel; anda controller coupled to each of the switches and configured to control the switches using Pulse Width Modulation (PWM) over a plurality of PWM periods to generate the multi-phase AC output voltages,wherein the controller is configured, for each PWM period, to:control one or both of the first and second switches in a respective bank of switches for each phase leg to generate the multi-phase AC output voltage based on one or more operating parameters of the inverter.

2. A multi-phase inverter according to claim 1, wherein the controller is configured to control the switches in a first mode in which the controller only switches the respective first or second switches in each of the banks of switches for a respective phase leg to generate the multi-phase AC output voltage.

3. A multi-phase inverter according to claim 2, wherein, in the first mode, the controller is configured to only switch the respective first switches in each of the banks of switches for a respective phase leg to generate the multi-phase AC output voltage.15286718-14. A multi-phase inverter according to claim 2, wherein, in the first mode, the controller is configured to only switch the respective second switches in each of the banks of switches for a respective phase leg to generate the multi-phase AC output voltage.

5. A multi-phase inverter according to claim 2, wherein, in the first mode, the controller is configured to only switch the first switch in the Upper bank and the second switch in the Lower bank for a respective phase leg to generate the multi-phase AC output voltage.

6. A multi-phase inverter according to claim 2, wherein, in the first mode, the controller is configured to only switch the second switch in the Upper bank and the first switch in the Lower bank for a respective phase leg to generate the multi-phase AC output voltage.

7. A multi-phase inverter according to any one of claims 2 to 6, wherein the one or more operating parameters comprises a power output demand of the inverter and wherein the controller is configured to control the switches in the first mode when the power output demand for the inverter is below a threshold power demand.

8. A multi-phase inverter according to claim 1, wherein the controller is configured to control the switches in a second mode in which the controller switches both respective first and second switches in a respective banks of switches for a respective phase leg to generate the multi-phase AC output voltage.

9. A multi-phase inverter according to claim 8, wherein, in the second mode, the controller is configured to switch each of the first and second switches in a respective switch bank substantially at the same time.

10. A multi-phase inverter according to claim 8, wherein, in the second mode, the controller is configured to switch each of the first and second switches in a respective switch bank at different times.

11. A multi-phase inverter according to claim 10, wherein the controller is configured to apply a turn on delay between the first and second switch being turned on such that15286718-1only one of the first or second switches is on during the turn on delay, and after the turn on delay both of the first and second switches are on.

12. A multi-phase inverter according to claim 10 or 11, wherein the controller is configured to apply a turn off delay between the first and second switch being turned off such that only one of the first or second switches is off during the turn off delay, and after the turn off delay both of the first and second switches are off.

13. A multi-phase inverter according to any one of claims 8 to 12, wherein the one or more operating parameters comprises a power output demand of the inverter and wherein the controller is configured to control the switches in the second mode when the output power demand for the inverter is above a threshold power demand.

14. A multi-phase inverter according to any preceding claim, wherein the one or more operating parameters comprises one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of the respective first and second switches, or a lifetime threshold for each of the respective first and second switches.

15. An Electrical Propulsion Unit (EPU) comprising:an electrical machine;a multi-phase inverter according to any one of claims 1 to 14,wherein the multi-phase inverter is electrically connected to the electrical machine and configured to drive the electrical machine using the multi-phase AC output voltages.

16. An Electrical Propulsion Unit according to claim 15, wherein the electrical machine is an axial flux electrical machine.

17. An Electrical Propulsion Unit according to claim 15 or 16, wherein the electrical machine is a motor or generator.

18. A method of generating a multi-phase AC voltage and current to an electric machine using an inverter, the inverter comprising:15286718-125two or more phase legs, each for generating a respective phase AC output voltage of the multi-phase voltage and each of the two or more phase legs being coupled between first and second DC inputs and a respective phase AC output, each of the respective phase legs comprising:an Upper bank of switches coupled between the first input and a respective output, the Upper bank of switches comprising first and second switches connected in parallel; anda Lower bank of switches coupled between the respective output and the second input, the Lower bank of switches comprising first and second switches connected in parallel,the method comprising:controlling the switches using Pulse Width Modulation (PWM) over a plurality of PWM periods to generate the multi-phase AC output voltages; andfor each PWM period, controlling one or both of the first and second switches in a respective bank of switches for each phase leg to generate the multi-phase AC output voltage based on one or more operating parameters of the inverter.

19. A method according to claim 18, wherein the switches are controlled in a first mode in which only the respective first or second switches in each of the banks of switches for a respective phase leg are switched to generate the multi-phase AC output voltage.

20. A method according to claim 19, wherein, in the first mode, the only the respective first switches in each of the banks of switches for a respective phase leg are switched to generate the multi-phase AC output voltage.

21. A method according to claim 19, wherein, in the first mode, the only the respective second switches in each of the banks of switches for a respective phase leg are switched to generate the multi-phase AC output voltage.

22. A method according to claim 19, wherein, in the first mode, only the first switch in the Upper bank and the second switch in the Lower bank for a respective phase leg are switched to generate the multi-phase AC output voltage.15286718-12623. A method according to claim 19, wherein, in the first mode, only the second switch in the Upper bank and the first switch in the Lower bank for a respective phase leg are switched to generate the multi-phase AC output voltage.

24. A method according to any one of claims 19 to 23, wherein the one or more operating parameters comprises a power output demand of the inverter and wherein the method comprises switching the switches in the first mode when the power output demand for the inverter is below a threshold power demand.

25. A method according to claim 18, wherein the switches are controlled in a second mode in which both respective first and second switches in a respective banks of switches for a respective phase leg are switched to generate the multi-phase AC output voltage.

26. A method according to claim 25, wherein each of the first and second switches in a respective switch bank are switched substantially at the same time.

27. A method according to claim 25, wherein each of the first and second switches in a respective switch bank are switched at different times.

28. A method according to claim 27, comprising applying a turn on delay between the first and second switch being turned on such that only one of the first or second switches is on during the turn on delay, and after the turn on delay both of the first and second switches are on.

29. A method according to claim 27 or 28, comprising applying a turn off delay between the first and second switch being turned off such that only one of the first or second switches is off during the turn off delay, and after the turn off delay both of the first and second switches are off.

30. A method according to any one of claims 25 to 29, wherein the one or more operating parameters comprises a power output demand of the inverter and wherein the method comprises controlling the switches in the second mode when the output power demand for the inverter is above a threshold power demand.15286718-1M&C PC933975W02731. A method according to any one of claims 18 to 30, wherein the one or more operating parameters comprises one or more of a power output demand of the inverter, or a respective desired mission profile for each respective first and second switches, or an accumulated switching duration for each of the respective first and second switches over a period of time, or an accumulated on time for each of the respective first and second switches, or a lifetime threshold for each of the respective first and second switches.15286718-1

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